JP4488847B2 - Plasma processing method and plasma processing apparatus for manufacturing semiconductor integrated device - Google Patents

Plasma processing method and plasma processing apparatus for manufacturing semiconductor integrated device Download PDF

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JP4488847B2
JP4488847B2 JP2004264168A JP2004264168A JP4488847B2 JP 4488847 B2 JP4488847 B2 JP 4488847B2 JP 2004264168 A JP2004264168 A JP 2004264168A JP 2004264168 A JP2004264168 A JP 2004264168A JP 4488847 B2 JP4488847 B2 JP 4488847B2
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大本　　豊
誠浩 角屋
茂 白米
主人 高橋
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Hitachi High Tech Corp
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本発明は、半導体集積装置の加工に用いられるプラズマ処理方法、特にプラズマエッチング装置およびプラズマエッチング方法に関する。   The present invention relates to a plasma processing method used for processing a semiconductor integrated device, and more particularly to a plasma etching apparatus and a plasma etching method.

半導体装置は、高機能化のため高密度で素子を集積する方向にあり、このため加工寸法がますます微細化されている。一方、その製造工程の一部であるプラズマエッチング加工においては加工精度の確保のために堆積性のガスを多く用いる傾向にある。堆積性のガスは、ウエハ表面以外のプラズマに接する加工処理室部材表面で膜を形成し、その一部がやがて剥離することにより半導体装置の加工寸法に近い大きさの微粒子となってプラズマ中を浮遊する。その微粒子の一部は、加工途中の半導体装置上に落下付着し、加工を阻害し所望の加工結果を得られなくしている。   Semiconductor devices are in a direction to integrate elements at high density for high functionality, and therefore, processing dimensions are becoming increasingly finer. On the other hand, in the plasma etching process which is a part of the manufacturing process, a large amount of depositing gas tends to be used in order to ensure the processing accuracy. The deposition gas forms a film on the surface of the processing chamber member that is in contact with the plasma other than the wafer surface, and a part of the film is peeled off to form fine particles close to the processing dimensions of the semiconductor device. Float. Some of the fine particles fall and adhere to the semiconductor device being processed, hindering the processing and making it impossible to obtain a desired processing result.

この問題を解決する従来の技術として、加工処理室内に副ポテンシャル分布形成手段を導入し、処理中の半導体装置を有するウエハ上の空間から異物（微粒子）を除去することによって半導体装置上への落下異物を低減するようにした半導体装置の製造方法が知られている（例えば、特許文献１参照）。
特開平５−４７７１２号公報 As a conventional technique for solving this problem, a sub-potential distribution forming means is introduced into the processing chamber, and foreign matter (fine particles) is removed from the space on the wafer having the semiconductor device being processed, thereby falling onto the semiconductor device. A method of manufacturing a semiconductor device in which foreign substances are reduced is known (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 5-47712

従来の技術で用いられている副ポテンシャル形成手段は反応排気ガス流路に設置する必要があるが、排気のポンプ抵抗となって微細加工性能の高い低圧力での処理を制約し、加工性能を高める上で支障となっていた。さらに、副ポテンシャル形成手段は電力導入のための給電路を必要とするが、その表面がプラズマにさらされて堆積性ガスによって膜を形成し、この膜の除去のためプラズマクリーニングや大気開放による手作業でのクリーニングが必要で、装置稼働率の低下を招いていた。   The sub-potential forming means used in the prior art needs to be installed in the reaction exhaust gas flow path, but it becomes a pump resistance of the exhaust and restricts processing at low pressure with high micromachining performance, thereby reducing machining performance. It was a hindrance in raising. Further, the sub-potential forming means requires a power supply path for introducing electric power, but its surface is exposed to plasma to form a film with a depositing gas, and this film is removed by plasma cleaning or opening to the atmosphere. Cleaning at work was necessary, leading to a reduction in the operating rate of the apparatus.

本発明では、ウエハ周辺部に載置されたリングに印加するバイアス電力を処理時間中に調整することによってウエハ上の空間に滞留する異物を該リング上に導き、該リング上に落下させる。該リング上に落下した異物は他の処理時間中に印加されるバイアスによって徐々にエッチング除去されるためクリーニングの必要がない。また、該リングは反応ガス排気路途上になく、排気を妨げることがないため低圧で高精度の加工処理が可能となる。   In the present invention, by adjusting the bias power applied to the ring placed on the periphery of the wafer during the processing time, foreign matter staying in the space on the wafer is guided onto the ring and dropped onto the ring. The foreign matter dropped on the ring is gradually etched away by a bias applied during another processing time, so that there is no need for cleaning. Further, since the ring is not in the reactive gas exhaust path and does not hinder exhaust, high-precision processing can be performed at low pressure.

すなわち、本発明は、真空処理室内に配置された電極の上面にウエハを載置し、そのウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材を配置し、前記真空処理室内にプラズマを形成して前記ウエハの処理を開始し、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させるようにした。 That is, in the present invention, a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of a portion on which the wafer is placed is placed on the upper surface of the electrode placed in the vacuum processing chamber. and, the ratio of the vacuum processing chamber to form a plasma to start the processing of the wafer, the bias voltage applied to the ring-shaped member via said conductor ring and the bias voltage applied to the electrode, the plasma is to reduce relatively the bias voltage of the ring-shaped member before being stopped.

さらに、本発明は、真空処理室内に配置された電極の上面にウエハを載置し、そのウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材を配置し、前記真空処理室内にプラズマを形成して前記ウエハの表面に配置され２種類以上の積層された膜に対して同じパターンを転写加工するプラズマ処理方法において、前記処理対象の膜が切り替わる際、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させるようにした。 Further, according to the present invention, a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of a portion on which the wafer is placed is placed on the upper surface of the electrode placed in the vacuum processing chamber. In the plasma processing method of forming plasma in the vacuum processing chamber and transferring the same pattern to two or more kinds of laminated films arranged on the surface of the wafer, when the film to be processed is switched, the ratio of the bias voltage applied to the ring-shaped member via a bias voltage and the conductor ring to be applied to the electrodes, relatively lower the bias voltage of the ring-shaped member before said plasma is stopped I tried to make it.

本発明は、真空処理室内に配置された電極の上面にウエハを載置し、そのウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材を配置し、前記真空処理室内にプラズマを形成して前記ウエハの表面に配置され２種類以上の積層形成するプラズマ処理方法において、前記積層される膜の種類が切り替わる際、前記電極に印加されるバイアス電圧と導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させるようにした。 In the present invention , a wafer is placed on the upper surface of an electrode disposed in a vacuum processing chamber, and a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of a portion on which the wafer is placed is disposed. In the plasma processing method in which plasma is formed in the vacuum processing chamber and disposed on the surface of the wafer to form two or more types of stacked layers, a bias voltage and a conductor applied to the electrodes when the types of the stacked films are switched The ratio of the bias voltage applied to the ring-shaped member via the ring is made to relatively reduce the bias voltage of the ring-shaped member before the plasma is stopped .

本発明は、内部に処理対象のウエハを処理するためのプラズマが形成される真空処理室と、この真空処理室内に配置されその上面に前記ウエハが載置される電極と、前記ウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材とを備え、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させる手段を備えるようにした。 The present invention includes a vacuum processing chamber in which plasma for processing a wafer to be processed is formed, an electrode disposed in the vacuum processing chamber and on which the wafer is mounted, and the wafer mounted A ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of a portion to be formed, and a bias voltage applied to the electrode and a bias voltage applied to the ring-shaped member via the conductor ring the ratios were in so that comprises a means for relatively reducing the bias voltage of the ring-shaped member before said plasma is stopped.

本発明は、内部に処理対象のウエハを処理するためのプラズマが形成される真空処理室と、この真空処理室内に配置されその上面に前記ウエハが載置される電極と、前記ウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材とを備え、前記プラズマを用いて前記ウエハ上の２種類以上の積層された膜に対して同じパターンを転写加工する処理中に前記処理対象の膜の種類が切り替わる際、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させる手段を備えるようにした。 The present invention includes a vacuum processing chamber in which plasma for processing a wafer to be processed is formed, an electrode disposed in the vacuum processing chamber and on which the wafer is mounted, and the wafer mounted And a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of the portion to be transferred, and using the plasma, the same pattern is transferred to two or more kinds of stacked films on the wafer when the type of the processing target film during processing is switched, the ratio of the bias voltage applied to the ring-shaped member via a bias voltage and the conductor ring to be applied to the electrode, the plasma is stopped It was so that with the means for relatively reducing the bias voltage of the ring-shaped member before.

本発明は、内部に処理対象のウエハを処理するためのプラズマが形成される真空処理室と、この真空処理室内に配置されその上面に前記ウエハが載置される電極と、前記ウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材とを備え、前記プラズマを用いて前記ウエハ上の２種類以上の膜を積層形成する処理中に、前記積層される膜の種類が切り替わる際、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させる手段を備えるようにした。 The present invention includes a vacuum processing chamber in which plasma for processing a wafer to be processed is formed, an electrode disposed in the vacuum processing chamber and on which the wafer is mounted, and the wafer mounted And a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of the portion to be stacked , and the stacking is performed during the process of stacking two or more types of films on the wafer using the plasma. When the type of film is switched, the ratio of the bias voltage applied to the electrode and the bias voltage applied to the ring-shaped member via the conductor ring is set to the ratio of the ring-shaped member before the plasma is stopped. was so that with the means for relatively lowering the bias voltage.

本発明によれば、半導体集積装置の生産歩留まりを向上できる。   According to the present invention, the production yield of a semiconductor integrated device can be improved.

本発明の一実施例を、図１および図２を使って説明する。図１は、ＵＨＦ−ＥＣＲを用いたプラズマエッチング装置の概略断面図である。プラズマエッチング装置は、真空処理室１０１と、ＵＨＦ電磁界を真空処理室１０１内に通過させるための石英窓１０２と、石英窓１０２に対向して真空処理室１０１内に配置され半導体集積装置が形成されるウエハ１０４を載置する電極１０３と、電極１０３にバイアス電圧を印加する高周波電源１０５と、石英窓１０２に連結され真空処理室１０１内にプラズマを発生させるための電磁界をＵＨＦ電源１１０から導入するアンテナ１０７と、真空処理室１０１内に磁場を形成するソレノイドコイル１０８と、エッチングレシピに従ってマスフローコントローラ１１１から供給されたガスを真空処理室内１０１に分散させ均一に導入するガス分散板１０９を有して構成される。   An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view of a plasma etching apparatus using UHF-ECR. The plasma etching apparatus is disposed in the vacuum processing chamber 101, the quartz window 102 for allowing the UHF electromagnetic field to pass through the vacuum processing chamber 101, and the quartz processing chamber 102 so as to face the quartz window 102, thereby forming a semiconductor integrated device. An electrode 103 on which the wafer 104 is mounted, a high-frequency power source 105 that applies a bias voltage to the electrode 103, and an electromagnetic field that is connected to the quartz window 102 and generates plasma in the vacuum processing chamber 101 is supplied from the UHF power source 110. An antenna 107 to be introduced, a solenoid coil 108 for forming a magnetic field in the vacuum processing chamber 101, and a gas dispersion plate 109 for dispersing and uniformly introducing the gas supplied from the mass flow controller 111 in accordance with the etching recipe into the vacuum processing chamber 101 are provided. Configured.

電極１０３のウエハ非載置部（周縁部）には絶縁リング１２３、導体リング１２２を介してシリコンリング１２１（フォーカスリング）が設置されている。導体リング１２２には真空処理室１０１外からインピーダンス調整回路１２４を介して高周波電源１０５が接続されている。   A silicon ring 121 (focus ring) is provided on the wafer non-mounting portion (peripheral portion) of the electrode 103 via an insulating ring 123 and a conductor ring 122. A high frequency power source 105 is connected to the conductor ring 122 from outside the vacuum processing chamber 101 via an impedance adjustment circuit 124.

図２を用いて、本実施例において、ウエハ上でエッチング加工される半導体集積装置の最表面の構造の一部を説明する。絶縁膜２０１はフォトレジストパターン２０３に従って配線パターンが上記エッチング装置により転写加工される。フォトレジスト２０３の露光時に絶縁膜２０１からの反射光による露光不良を避けるために絶縁膜２０１とフォトレジスト２０３との間に反射防止膜２０２が設けられている。本実施例では、絶縁膜２０１としてＯＳＧ（Ｏｒｇａｎｏ−Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）膜を、反射防止膜として有機系膜を用いた場合について説明する。   A part of the structure of the outermost surface of the semiconductor integrated device etched on the wafer in this embodiment will be described with reference to FIG. A wiring pattern of the insulating film 201 is transferred by the etching apparatus according to the photoresist pattern 203. An antireflection film 202 is provided between the insulating film 201 and the photoresist 203 in order to avoid exposure failure due to light reflected from the insulating film 201 during exposure of the photoresist 203. In this embodiment, an OSG (Organo-Silicate Glass) film is used as the insulating film 201 and an organic film is used as an antireflection film.

図３（ａ）を用いて、従来のエッチング加工の処理手順を説明する。まず、処理室１０１にウエハ１０４を搬入し（Ｓ１）、電極１０３の所定の位置に置いた後、マスフローコントローラ１１１から反射防止膜エッチング用に調整された流量でエッチングガスを導入し、所定の圧力に調整する（Ｓ２）。その後、ＵＨＦ電源１１０からアンテナ１０７、石英窓１０２を介して真空処理室１０１にＵＨＦ電磁界を導入し、プラズマを生成する（Ｓ３）。プラズマ生成の直後、高周波電源１０５により所定のバイアス電圧が印加され、反射防止膜のエッチングが開始される（Ｓ４）。被エッチング部の反射防止膜のエッチングの終了が検知され所定の時間経過後、絶縁膜エッチングステップに移行するためバイアス、プラズマ、ガスの供給が順に停止されて排気される（Ｓ５）。   A conventional etching process will be described with reference to FIG. First, the wafer 104 is loaded into the processing chamber 101 (S1), placed at a predetermined position of the electrode 103, an etching gas is introduced from the mass flow controller 111 at a flow rate adjusted for etching the antireflection film, and a predetermined pressure is applied. (S2). Thereafter, a UHF electromagnetic field is introduced from the UHF power source 110 into the vacuum processing chamber 101 through the antenna 107 and the quartz window 102 to generate plasma (S3). Immediately after plasma generation, a predetermined bias voltage is applied by the high frequency power source 105, and etching of the antireflection film is started (S4). After the end of the etching of the antireflection film in the etched portion is detected and a predetermined time elapses, the supply of bias, plasma, and gas is stopped in order to shift to the insulating film etching step and exhausted (S5).

次に、絶縁膜エッチング用ガスの導入が開始され（Ｓ６）、ＵＨＦ電源１１０からアンテナ１０７、石英窓１０２を介して真空処理室１０１にＵＨＦ電磁界を導入し、プラズマを生成する（Ｓ７）。次いで絶縁膜のエッチングが行われ（Ｓ８）、一連の処理を終了し、バイアス、プラズマ、ガスの供給が順に停止され、排気がなされ（Ｓ９）、処理室１０１からウエハ１０４が搬出された（Ｓ１０）後、次のウエハが搬入されて再び、図３（ａ）の処理がウエハ１枚毎に繰り返し行われる。   Next, the introduction of the insulating film etching gas is started (S6), and a UHF electromagnetic field is introduced from the UHF power supply 110 into the vacuum processing chamber 101 through the antenna 107 and the quartz window 102 to generate plasma (S7). Next, the insulating film is etched (S8), a series of processes is terminated, the supply of bias, plasma, and gas is stopped in order, the exhaust is performed (S9), and the wafer 104 is unloaded from the processing chamber 101 (S10). After that, the next wafer is loaded, and the process of FIG. 3A is repeated for each wafer.

図３（ｂ）を用いて、本発明による処理手順を説明する。本発明による処理手順は、従来の反射防止膜エッチングとステップ移行のための一連の手続きの間に異物をダンプする処理を設けた点が従来と異なる点である。   A processing procedure according to the present invention will be described with reference to FIG. The processing procedure according to the present invention is different from the conventional one in that a processing for dumping foreign matter is provided between a series of procedures for conventional antireflection film etching and step transition.

すなわち、本発明の処理手順では、まず、処理室１０１にウエハ１０４を搬入し（Ｓ１１）、電極１０３の所定の位置に置いた後、マスフローコントローラ１１１から反射防止膜エッチング用に調整された流量でエッチングガスを導入し、所定の圧力に調整する（Ｓ１２）。その後、ＵＨＦ電源１１０からアンテナ１０７、石英窓１０２を介して真空処理室１０１にＵＨＦ電磁界を導入し、プラズマを生成する（Ｓ１３）。プラズマ生成の直後、高周波電源１０５により所定のバイアス電圧が印加され、反射防止膜のエッチングが開始される（Ｓ１４）。被エッチング部の反射防止膜のエッチングの終了が検知され所定の時間経過後、シリコンリング（フォーカスリング）１２１に印加されている電圧を低下させ、プラズマシースの境界に滞留しており、例えば負に帯電した浮遊粒子を導体リング１２２上に移行させる（Ｓ１５）。その後、絶縁膜エッチングステップに移行するためバイアス、プラズマ、ガスの供給が順に停止されて排気される（Ｓ１６）。   That is, in the processing procedure of the present invention, first, the wafer 104 is loaded into the processing chamber 101 (S11), placed at a predetermined position of the electrode 103, and then at a flow rate adjusted for etching the antireflection film from the mass flow controller 111. An etching gas is introduced and adjusted to a predetermined pressure (S12). Thereafter, a UHF electromagnetic field is introduced from the UHF power source 110 into the vacuum processing chamber 101 through the antenna 107 and the quartz window 102 to generate plasma (S13). Immediately after plasma generation, a predetermined bias voltage is applied by the high frequency power source 105, and etching of the antireflection film is started (S14). After the end of the etching of the antireflection film of the etched portion is detected and a predetermined time has elapsed, the voltage applied to the silicon ring (focus ring) 121 is reduced and stays at the boundary of the plasma sheath, for example, negatively The charged suspended particles are transferred onto the conductor ring 122 (S15). Thereafter, the supply of bias, plasma, and gas is stopped and exhausted in order to shift to the insulating film etching step (S16).

次に、絶縁膜エッチング用ガスの導入が開始され（Ｓ１７）、ＵＨＦ電源１１０からアンテナ１０７、石英窓１０２を介して真空処理室１０１にＵＨＦ電磁界を導入し、プラズマを生成する（Ｓ１８）。次いで絶縁膜のエッチングが行われ（Ｓ１９）、一連の処理を終了し、バイアス、プラズマ、ガスの供給が順に停止され、排気がなされ（Ｓ２０）、処理室１０１からウエハ１０４が搬出された（Ｓ２１）後、次のウエハが搬入されて再び、図３（ｂ）の処理がウエハ１枚毎に繰り返し行われる。   Next, the introduction of the insulating film etching gas is started (S17), and a UHF electromagnetic field is introduced from the UHF power source 110 into the vacuum processing chamber 101 through the antenna 107 and the quartz window 102 to generate plasma (S18). Next, the insulating film is etched (S19), a series of processes is completed, the supply of bias, plasma, and gas is stopped in order, the exhaust is performed (S20), and the wafer 104 is unloaded from the processing chamber 101 (S21). After that, the next wafer is carried in, and the process of FIG. 3B is repeated for each wafer again.

次に、従来の方法と本発明による方法との違いを処理制御ダイアグラムによって説明する。図４、図５に示す処理制御ダイアグラムの横軸はエッチング処理開始からの経過時間を、縦軸はその処理経過時間に対応したフォーカスリングと電極に印加される電圧を示している。図４に示す従来の方法では、バイアス印加中は、高周波電源１０５とフォーカスリング、電極との間のそれぞれの伝送線路のインピーダンスによって印加電圧が決まり、バイアス電源の出力にかかわらずその比率は一定の値を取るようになっていた。   Next, the difference between the conventional method and the method according to the present invention will be described with reference to a process control diagram. The horizontal axis of the process control diagrams shown in FIGS. 4 and 5 represents the elapsed time from the start of the etching process, and the vertical axis represents the voltage applied to the focus ring and the electrode corresponding to the process elapsed time. In the conventional method shown in FIG. 4, during bias application, the applied voltage is determined by the impedance of each transmission line between the high-frequency power source 105 and the focus ring and electrode, and the ratio is constant regardless of the output of the bias power source. It was supposed to take a value.

一方、本発明の実施例では、図１のインピーダンス調整回路１２４により、反射防止膜エッチング終了時のバイアス停止前に、図５に示すようにインピーダンス調整回路１２４を用いてフォーカスリング側にかかるバイアス電圧を相対的に低下させるように調整した２秒間の異物ダンプステップを付加した。   On the other hand, in the embodiment of the present invention, the bias voltage applied to the focus ring side by using the impedance adjustment circuit 124 as shown in FIG. 5 by the impedance adjustment circuit 124 of FIG. A foreign matter dumping step of 2 seconds adjusted so as to lower the relative pressure was added.

本発明実施例の効果を確認するため、この方法を用いて処理したウエハと従来の方法で処理したウエハに、同じ配線用メタル材の埋め込み処理を行った後で配線の導通試験を行った。二つのエッチング処理方法の不良率の統計比較を行ったところ、本発明実施例を用いた場合に従来方法に比べ３．２％の不良率低減効果が得られることがわかった。   In order to confirm the effect of the embodiment of the present invention, the wiring continuity test was conducted after the wafer processed using this method and the wafer processed by the conventional method were embedded with the same wiring metal material. A statistical comparison of the defect rates of the two etching methods revealed that a defect rate reduction effect of 3.2% was obtained when the embodiment of the present invention was used compared to the conventional method.

この不良率低減効果が得られた原因について、図６および図７の模式図を用いて定性説明を行う。図６は従来の方法での、反射防止膜エッチング終了直前から、絶縁膜エッチング開始前のプラズマ停止時の様子を示したものである。反射防止膜エッチング中、浮遊してきた粒子は負に帯電しやすく、ウエハ上のプラズマシース境界に滞留している。この状態から絶縁膜エッチングステップに移行する際のプラズマ停止時に、この滞留していた粒子はウエハ上に落下する。この後に引き続いて行われる絶縁膜のエッチング時にこのウエハ上に落下した異物は、エッチングに対しマスクとなるので、これにより配線を断線させたことが不良発生の一因となっていたと考えられる。   The reason why this defective rate reduction effect is obtained will be described qualitatively using the schematic diagrams of FIGS. FIG. 6 shows a state in which plasma is stopped in the conventional method immediately before the end of the antireflection film etching and before the start of the insulating film etching. During the antireflection film etching, the floating particles are easily negatively charged and stay at the plasma sheath boundary on the wafer. At the time of stopping the plasma when shifting from this state to the insulating film etching step, the staying particles fall on the wafer. The foreign matter dropped on the wafer during the subsequent etching of the insulating film becomes a mask for the etching, and it is considered that the disconnection of the wiring caused a defect.

一方、本発明の場合は、図７に示すようにプラズマ停止前にフォーカスリングに印加される電圧を下げることにより、プラズマ境界面が図のように山型の形状となり滞留粒子をフォーカスリング上に移動させることができたと考えられる。このことによりプラズマ停止時、粒子はウエハではなくフォーカスリング上に落下する。この結果、異物がマスクとなって生じる加工不良を減少できたと考えられる。 On the other hand, in the case of the present invention, as shown in FIG. 7, by reducing the voltage applied to the focus ring before the plasma is stopped, the plasma boundary surface becomes a mountain shape as shown in the figure, and the staying particles are placed on the focus ring. It is thought that it was able to move. This causes the particles to fall on the focus ring, not the wafer, when the plasma is stopped. As a result, it is considered that processing defects caused by foreign matter as a mask could be reduced.

本発明は、高集積の半導体装置ではこのような加工を繰り返しながら積層配線を形成していくので、本発明の適用による歩留まり向上の効果は大きく、特にチップ収量の多いウエハエッジ部分で不良率を低減できることの寄与が大きい。   In the present invention, a highly integrated semiconductor device forms a multilayer wiring while repeating such processing. Therefore, the application of the present invention greatly improves the yield, and the defect rate is reduced particularly at the wafer edge portion where the chip yield is high. The contribution of what can be done is great.

なお、上記不良低減効果の考察から、処理を繰り返していくと、異物はフォーカスリング上に蓄積され、経時後に新たな異物発生源になることが懸念されるが、通常の処理室メンテナンス間でそのような不具合の発生は見られなかった。これはフォーカスリングにはエッチング時には高いバイアスが印加されているため付着した異物が徐々にエッチングされ消滅しているためと考えられる。   In addition, from the consideration of the above-described defect reduction effect, there is a concern that foreign matter accumulates on the focus ring and becomes a new foreign matter generation source after a lapse of time. The occurrence of such problems was not seen. This is considered because a high bias is applied to the focus ring at the time of etching, and the attached foreign matter is gradually etched and disappears.

また、本発明では、ガス排気路に対して抵抗となるものの設置を必要としないため、従来と比較して同じプロセスレシピを用いて加工形状、処理速度などまったく変化なかった。   Further, in the present invention, since there is no need to install anything that becomes a resistance to the gas exhaust passage, the machining shape and the processing speed are not changed at all using the same process recipe as compared with the conventional one.

以上、本発明により、半導体集積装置の生産歩留まりを高める効果を得ることができ、かつ他の特性に対してトレードオフを生じない技術を提供することができることが示めされた。   As described above, it has been shown that the present invention can provide a technique capable of improving the production yield of a semiconductor integrated device and not causing a trade-off with respect to other characteristics.

また、本発明はエッチングに限らずバイアスＣＶＤの連続成膜にも応用可能である。ＣＶＤの場合も膜間の条件切り替え時に本方式を応用することによって粒子のウエハへの落下を減少させることができ、異物によって生じる膜間のボイドを低減し、信頼性の高い半導体装置の生産を行うことができる。   Further, the present invention is not limited to etching and can be applied to continuous film formation by bias CVD. Even in the case of CVD, by applying this method when switching the conditions between films, it is possible to reduce the drop of particles to the wafer, reduce voids between films caused by foreign substances, and produce highly reliable semiconductor devices. It can be carried out.

本発明の実施例を説明するプラズマ処理装置の断面図。Sectional drawing of the plasma processing apparatus explaining the Example of this invention. 本発明実施例で加工対象とする半導体集積装置の最表面の一部の断面図。1 is a cross-sectional view of a part of the outermost surface of a semiconductor integrated device to be processed in an embodiment of the present invention. 従来及び本発明の加工手順を示すフロー図。The flowchart which shows the process sequence of the past and this invention. 本発明を用いない場合の処理制御ダイアグラム。The processing control diagram when not using this invention. 本発明を用いた場合の処理制御ダイアグラム。The processing control diagram at the time of using this invention. 本発明を用いない場合のプラズマ停止時の浮遊粒子の状況を説明する図。The figure explaining the condition of the floating particle at the time of the plasma stop at the time of not using this invention. 本発明を用いた場合のプラズマ停止時の浮遊粒子の状況を説明する図。The figure explaining the condition of the floating particle at the time of the plasma stop at the time of using this invention.

符号の説明Explanation of symbols

１０１…真空処理室、１０３…電極、１０４…ウエハ、１２１…シリコンリング（フォーカスリング）、１２２…導体リング、１２４…インピーダンス調整回路、２０１…ＯＳＧ（絶縁膜）、２０２…反射防止膜（有機膜）、２０３…レジストマスク。   DESCRIPTION OF SYMBOLS 101 ... Vacuum processing chamber, 103 ... Electrode, 104 ... Wafer, 121 ... Silicon ring (focus ring), 122 ... Conductor ring, 124 ... Impedance adjustment circuit, 201 ... OSG (insulating film), 202 ... Antireflection film (organic film) ), 203... Resist mask.

Claims (6)

真空処理室内に配置された電極の上面にウエハを載置し、そのウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材を配置し、前記真空処理室内にプラズマを形成して前記ウエハの処理を開始し、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させることを特徴とするプラズマ処理方法。 A wafer is mounted on the upper surface of the electrode disposed in the vacuum processing chamber, and a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of the portion on which the wafer is mounted is disposed, and the vacuum processing chamber to form a plasma to start the processing of the wafer, the ratio of the bias voltage applied to the ring-shaped member via a bias voltage and the conductor ring to be applied to the electrode, the plasma is stopped A plasma processing method characterized by relatively lowering a bias voltage of the ring-shaped member before. 真空処理室内に配置された電極の上面にウエハを載置し、そのウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材を配置し、前記真空処理室内にプラズマを形成して前記ウエハの表面に配置され２種類以上の積層された膜に対して同じパターンを転写加工するプラズマ処理方法において、前記処理対象の膜が切り替わる際、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させることを特徴とするプラズマ処理方法。 A wafer is mounted on the upper surface of the electrode disposed in the vacuum processing chamber, and a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of the portion on which the wafer is mounted is disposed, and the vacuum processing chamber In the plasma processing method of forming a plasma on the surface of the wafer and transferring the same pattern to two or more kinds of stacked films, the plasma is applied to the electrode when the film to be processed is switched. the ratio of the bias voltage applied to the ring-shaped member via a bias voltage between the conductor rings, wherein the bias voltage of the ring-shaped member be relatively lowered before said plasma is stopped Plasma processing method. 真空処理室内に配置された電極の上面にウエハを載置し、そのウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材を配置し、前記真空処理室内にプラズマを形成して前記ウエハの表面に配置され２種類以上の積層形成するプラズマ処理方法において、前記積層される膜の種類が切り替わる際、前記電極に印加されるバイアス電圧と導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させることを特徴とするプラズマ処理方法。 A wafer is mounted on the upper surface of the electrode disposed in the vacuum processing chamber, and a ring-shaped member including a conductor ring disposed on the electrode on the outer periphery of the portion on which the wafer is mounted is disposed, and the vacuum processing chamber In the plasma processing method of forming plasma on the wafer surface and forming two or more types of stacked layers, when the types of the stacked films are switched , via a bias voltage applied to the electrodes and a conductor ring the plasma processing method characterized in that the ratio between the bias voltage applied to the ring-shaped member, the plasma reduces relatively bias voltage of the ring-shaped member before being stopped. 内部に処理対象のウエハを処理するためのプラズマが形成される真空処理室と、この真空処理室内に配置されその上面に前記ウエハが載置される電極と、前記ウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材とを備え、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させる手段を備えたことを特徴とするプラズマ処理装置。A vacuum processing chamber in which plasma for processing a wafer to be processed is formed; an electrode disposed in the vacuum processing chamber on which the wafer is placed; and a portion on which the wafer is placed A ring-shaped member including a conductor ring disposed on the outer peripheral electrode, and a ratio of a bias voltage applied to the electrode and a bias voltage applied to the ring-shaped member via the conductor ring, A plasma processing apparatus comprising means for relatively reducing the bias voltage of the ring-shaped member before the plasma is stopped. 内部に処理対象のウエハを処理するためのプラズマが形成される真空処理室と、この真空処理室内に配置されその上面に前記ウエハが載置される電極と、前記ウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材とを備え、前記プラズマを用いて前記ウエハ上の２種類以上の積層された膜に対して同じパターンを転写加工する処理中に前記処理対象の膜の種類が切り替わる際、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させる手段を備えたことを特徴とするプラズマ処理装置。 A vacuum processing chamber in which plasma for processing a wafer to be processed is formed; an electrode disposed in the vacuum processing chamber on which the wafer is placed; and a portion on which the wafer is placed A ring-shaped member including a conductor ring disposed on the outer peripheral electrode, and during the process of transferring the same pattern to two or more kinds of laminated films on the wafer using the plasma when the type of film to be processed is switched, the ratio of the bias voltage applied to the ring-shaped member via a bias voltage and the conductor ring to be applied to the electrode, the ring before the plasma is stopped A plasma processing apparatus comprising means for relatively reducing the bias voltage of the member. 内部に処理対象のウエハを処理するためのプラズマが形成される真空処理室と、この真空処理室内に配置されその上面に前記ウエハが載置される電極と、前記ウエハが載置される部分の外周の前記電極上に配置された導体リングを含むリング状部材とを備え、前記プラズマを用いて前記ウエハ上の２種類以上の膜を積層形成する処理中に、前記積層される膜の種類が切り替わる際、前記電極に印加されるバイアス電圧と前記導体リングを介して前記リング状部材に印加されるバイアス電圧との比率を、前記プラズマが停止される前に前記リング状部材のバイアス電圧を相対的に低下させる手段を備えたことを特徴とするプラズマ処理装置。 A vacuum processing chamber in which plasma for processing a wafer to be processed is formed; an electrode disposed in the vacuum processing chamber on which the wafer is placed; and a portion on which the wafer is placed A ring-shaped member including a conductor ring disposed on the electrode on the outer periphery, and during the process of laminating and forming two or more types of films on the wafer using the plasma, When switching, the ratio between the bias voltage applied to the electrode and the bias voltage applied to the ring-shaped member via the conductor ring is compared with the bias voltage of the ring-shaped member before the plasma is stopped. A plasma processing apparatus comprising means for reducing the temperature of the plasma processing apparatus.
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