JP4470507B2 - Display device - Google Patents

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JP4470507B2
JP4470507B2 JP2004028822A JP2004028822A JP4470507B2 JP 4470507 B2 JP4470507 B2 JP 4470507B2 JP 2004028822 A JP2004028822 A JP 2004028822A JP 2004028822 A JP2004028822 A JP 2004028822A JP 4470507 B2 JP4470507 B2 JP 4470507B2
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pixel
display
display area
sequentially
signal
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JP2005221695A (en
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奈津美 市来
順一 後野
佳代子 鬼塚
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Sony Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0442—Handling or displaying different aspect ratios, or changing the aspect ratio

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Shift Register Type Memory (AREA)

Description

本発明は表示装置に関する。詳しくは、第２の表示領域の各画素に複数行ずつ順次所定の輝度レベル信号を書き込むことによって、寄生容量によるノイズを抑制しようとした表示装置に係るものである。 The present invention relates to a display device . Specifically, the present invention relates to a display device that attempts to suppress noise due to parasitic capacitance by sequentially writing a predetermined luminance level signal to each pixel of the second display region in a plurality of rows.

近年、アスペクト比が４：３の標準のテレビジョン方式（ＮＴＳＣ方式など）に対して、アスペクト比が１６：９のいわゆるワイドビジョン（ハイビジョン）が開発され、これに伴ってワイドビジョン用の撮影モードを持ったビデオカメラ装置も発売されている。従って、標準のテレビジョン方式に対応したアスペクト比が４：３の画面を有する表示装置において、１６：９のワイドビジョン対応の表示が行えることが望まれている。   In recent years, so-called wide vision (high vision) with an aspect ratio of 16: 9 has been developed for standard television systems (NTSC, etc.) with an aspect ratio of 4: 3. A video camera device with a camera is also on sale. Accordingly, it is desired that a display device having a 4: 3 aspect ratio screen corresponding to a standard television system can perform 16: 9 wide vision compatible display.

上記した様に、アスペクト比が異なるテレビジョン方式に対応できる様にするためには、テレビジョン方式に応じてアスペクト比を切り替える必要がある。   As described above, in order to be able to cope with television systems having different aspect ratios, it is necessary to switch the aspect ratio according to the television system.

ここで、アスペクト比を切り替える方法として、画素部の上端部及び下端部の所定数の走査線に黒色情報を書き込む処理を行う表示装置の駆動方法が提案されていた（例えば、特許文献１参照。）。   Here, as a method for switching the aspect ratio, there has been proposed a driving method of a display device that performs processing of writing black information to a predetermined number of scanning lines at the upper end portion and the lower end portion of the pixel portion (see, for example, Patent Document 1). ).

ところが、特許文献１に記載の方法により異なるアスペクト比での表示を行うには、その駆動をなす駆動系にメモリやスキャンコンバータなどの回路が必要となるため、その分高価なものになるという問題があった。特に、ビデオカメラ装置のＥＶＦ（Electronic View Finder）などに用いられる液晶表示装置では、装置の簡易化、低消費電力化が強く望まれていることから、異なったアスペクト比での表示を、できるだけ簡単な構成で廉価に実現したいという要求がある。   However, in order to perform display with a different aspect ratio by the method described in Patent Document 1, a circuit such as a memory or a scan converter is required for a drive system for driving the display, and thus the cost is increased accordingly. was there. In particular, in liquid crystal display devices used for EVF (Electronic View Finder) of video camera devices, it is strongly desired to simplify the device and reduce power consumption. Therefore, display with different aspect ratios is as simple as possible. There is a demand to realize a low price with a simple structure.

この様な要求に応じて、アスペクト比を切り替えるための制御信号が与えられた時に画素部の上下の所定領域の各画素を強制的にアクティブ状態にし黒レベル信号を一括して書き込むとともに、それ以外の領域の画素に対しては行単位で順にアクティブ状態にしつつ各行毎に表示信号を書き込む表示装置の駆動方法が提案されている（例えば、特許文献２参照。）。   In response to such a request, when a control signal for switching the aspect ratio is given, each pixel in a predetermined area above and below the pixel portion is forcibly activated to write a black level signal all at once, and otherwise There has been proposed a driving method of a display device that writes a display signal for each row while sequentially activating the pixels in the region in units of rows (see, for example, Patent Document 2).

特開平８−３１４４２１号公報JP-A-8-314421

特開２００１−５１６４３号公報JP 2001-51643 A

しかしながら、上記した従来の表示装置の駆動方法では、一括して黒レベル信号を書き込むために、寄生容量によるノイズの影響を受けやすく、黒表示領域に充分に黒信号が書き込めない等の問題がある。   However, the conventional driving method of the display device described above has a problem that, since the black level signal is written in a lump, it is easily influenced by noise due to parasitic capacitance, and the black signal cannot be sufficiently written in the black display region. .

本発明は、以上の点に鑑みて創案されたものであって、所定の輝度レベル信号を書き込む際の寄生容量によるノイズの影響を抑制することができる表示装置を提供することを目的とする。 The present invention has been made in view of the above points, and an object of the present invention is to provide a display device that can suppress the influence of noise due to parasitic capacitance when a predetermined luminance level signal is written.

上記の目的を達成するために、本発明に係る表示装置は、画素が行列状に配列され、第１の表示領域と第２の表示領域を有する画素部と、第１の駆動モード時に第１の表示領域及び第２の表示領域の各画素を一行ずつ順次選択し、第２の駆動モード時に第１の表示領域の各画素を一行ずつ順次選択すると共に、第２の駆動モード時に第２の表示領域の各画素を複数行ずつ順次選択する様に構成された垂直駆動系と、第１の駆動モード時に前記垂直駆動系によって選択した第１の表示領域及び第２の表示領域の各画素に表示信号を順次書き込み、第２の駆動モード時に前記垂直駆動系によって選択した第１の表示領域の各画素に表示信号を順次書き込むと共に、第２の駆動モード時に前記垂直駆動系によって選択した第２の表示領域の各画素に所定の輝度レベル信号を順次書き込む様に構成された水平駆動系を備える。   In order to achieve the above object, a display device according to the present invention includes a pixel unit in which pixels are arranged in a matrix, a first display region and a second display region, and a first driving mode. The pixels in the display area and the second display area are sequentially selected one line at a time, each pixel in the first display area is sequentially selected one line at a time in the second drive mode, and the second display mode is selected in the second drive mode. A vertical drive system configured to sequentially select each pixel in the display area in a plurality of rows, and each pixel in the first display area and the second display area selected by the vertical drive system in the first drive mode. The display signal is sequentially written, the display signal is sequentially written to each pixel in the first display area selected by the vertical drive system in the second drive mode, and the second signal selected by the vertical drive system in the second drive mode. For each pixel in the display area Comprising a horizontal driving system configured as sequentially writes the constant luminance level signal.

また、上記の目的を達成するために、本発明に係る表示装置の製造方法は、画素が行列状に配列され、第１の表示領域と第２の表示領域を有する画素部と、該画素部の各画素を行単位で選択する垂直駆動系と、該垂直駆動系により選択した画素に信号を書き込む水平駆動系を有し、前記第１の表示領域及び第２の表示領域の各画素に表示信号を書き込む第１の駆動モードと、前記第１の表示領域の各画素に表示信号を書き込み、前記第２の表示領域の各画素に所定の輝度レベル信号を書き込む第２の駆動モードを備える表示装置の駆動方法において、前記第１の駆動モード時は、前記垂直駆動系により前記第１の表示領域及び前記第２の表示領域の各画素を一行ずつ順次選択すると共に、選択した第１の表示領域及び第２の表示領域の各画素に表示信号を順次書き込み、前記第２の駆動モード時は、前記垂直駆動系により前記第１の表示領域の各画素は一行ずつ順次選択し、前記第２の表示領域の各画素は複数行ずつ順次選択すると共に、選択した第１の表示領域の各画素に表示信号を順次書き込み、選択した第２の表示領域の各画素に所定の輝度レベル信号を順次書き込む。   In order to achieve the above object, a method for manufacturing a display device according to the present invention includes a pixel unit in which pixels are arranged in a matrix, a first display region and a second display region, and the pixel unit. A vertical drive system that selects each pixel in a row unit, and a horizontal drive system that writes a signal to the pixel selected by the vertical drive system, and displays on each pixel in the first display area and the second display area A display having a first drive mode for writing a signal and a second drive mode for writing a display signal to each pixel in the first display region and writing a predetermined luminance level signal to each pixel in the second display region. In the driving method of the apparatus, in the first driving mode, each pixel of the first display area and the second display area is sequentially selected by the vertical driving system one row at a time, and the selected first display Each pixel in the region and the second display region Display signals are sequentially written, and in the second drive mode, each pixel in the first display area is sequentially selected by one line by the vertical drive system, and each pixel in the second display area is sequentially selected by a plurality of lines. In addition to selection, a display signal is sequentially written to each pixel of the selected first display area, and a predetermined luminance level signal is sequentially written to each pixel of the selected second display area.

上記した表示装置では、例えばアスペクト比が４：３の表示画面の場合における駆動モードである第１の駆動モード時には、垂直駆動系により第１の表示領域及び第２の表示領域の各画素を一行ずつ順次選択すると共に、第１の表示領域及び第２の表示領域の一行ずつ順次選択された各画素に表示信号を書き込むことによって、第１の表示領域及び第２の表示領域の各画素に対して一行ずつ表示信号を書き込むことができる。   In the display device described above, for example, in the first drive mode which is a drive mode in the case of a display screen having an aspect ratio of 4: 3, each pixel in the first display region and the second display region is arranged in one row by the vertical drive system. By sequentially selecting and writing a display signal to each pixel that is sequentially selected row by row in the first display region and the second display region, for each pixel in the first display region and the second display region The display signal can be written line by line.

一方、例えばアスペクト比が１６：９の表示画面の場合における駆動モードである第２の駆動モード時には、垂直駆動系により第１の表示領域の各画素を一行ずつ順次選択すると共に、第１の表示領域の一行ずつ順次選択された各画素に表示信号を書き込むことによって、第１の表示領域の各画素に対して一行ずつ表示信号を書き込むことができる。また、第２の駆動モード時には、垂直駆動系により第２の表示領域の各画素を複数行ずつ順次選択すると共に、第２の表示領域の複数行ずつ順次選択された各画素に所定の輝度レベル信号を書き込むことによって、第２の表示領域の各画素に対して複数行ずつ所定の輝度レベル信号を書き込むことができる。   On the other hand, for example, in the second drive mode that is a drive mode in the case of a display screen with an aspect ratio of 16: 9, each pixel in the first display region is sequentially selected by the vertical drive system one row at a time. By writing a display signal to each pixel that is sequentially selected for each row in the region, it is possible to write a display signal for each row in each pixel in the first display region. In the second drive mode, each pixel in the second display region is sequentially selected by a plurality of rows by the vertical drive system, and a predetermined luminance level is applied to each pixel sequentially selected by the plurality of rows in the second display region. By writing the signal, a predetermined luminance level signal can be written in a plurality of rows for each pixel in the second display area.

上記した本発明の表示装置では、第２の表示領域の各画素に所定の輝度レベル信号を書き込む際に、一括して書き込みを行わず、複数行ずつ書き込みを行うために、画素部が寄生容量によるノイズの影響を受け難く、充分に所定の輝度レベル信号の書き込みを行うことができる。 In the display device of the present invention described above, when a predetermined luminance level signal is written to each pixel in the second display region, the pixel portion has a parasitic capacitance in order to perform writing for a plurality of rows without performing batch writing. Therefore, it is possible to write a predetermined luminance level signal sufficiently.

また、本発明の表示装置では、外部に特別な回路を設けることなく簡単な回路構成を付加し、単にアスペクト比を切り替えるための制御信号を与えるだけで異なったアスペクト比での表示を簡単な構成にて廉価でかつ消費電力で実現することができる。 In the display device of the present invention, a simple circuit configuration is added without providing a special circuit outside, and a display with a different aspect ratio is simply configured simply by providing a control signal for switching the aspect ratio. Can be realized at low cost and with low power consumption.

以下、本発明の実施の形態について図面を参照しながら説明し、本発明の理解に供する。
図１は本発明を適用したアクティブマトリクス型液晶表示装置の一例における液晶駆動回路の構成を説明するための図であり、ここで示す液晶駆動回路は、画素が行列状（マトリクス状）に配置されてなる画素部１と、画素部の例えば上側に配置され、各画素への表示データ若しくは黒レベル信号の書き込みを点順次で行う水平駆動系２と、画素部の例えば左側に配置され、各画素を行単位で選択する垂直駆動系３を備えている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a diagram for explaining a configuration of a liquid crystal driving circuit in an example of an active matrix liquid crystal display device to which the present invention is applied. In the liquid crystal driving circuit shown here, pixels are arranged in a matrix (matrix). A pixel unit 1, a horizontal drive system 2 disposed on, for example, the pixel unit and performing dot-sequential writing of display data or a black level signal to each pixel, and disposed on, for example, the left side of the pixel unit. Is provided in a vertical drive system 3.

画素部１は、２枚のガラス基板間に液晶材料が封入されることによって作製され、マトリクス状に配置された各画素は、スイッチング素子であるポリシリコンＴＦＴ４と、このＴＦＴのドレイン電極に画素電極が接続された液晶セル５と、ＴＦＴのドレイン電極に一方の電極が接続された補助キャパシタ６から構成されている。   The pixel portion 1 is manufactured by enclosing a liquid crystal material between two glass substrates, and each pixel arranged in a matrix includes a polysilicon TFT 4 as a switching element and a pixel electrode on the drain electrode of the TFT. Is connected to the liquid crystal cell 5 and the auxiliary capacitor 6 having one electrode connected to the drain electrode of the TFT.

この画素構造において、各画素のＴＦＴは、そのゲート電極が垂直方向（行方向）の画素数２２０（以下、垂直画素数２２０と称する）に対応した２２０行分のゲートライン７−１，７−２，・・・７−２１９，７−２２０の各々にそれぞれ接続され、かつそのソース電極が水平方向（列方向）の画素数５６０（以下、水平画素数５６０と称する）に対応した５６０列分の信号ライン８−１，８−２・・・８−５５９，８−５６０の各々にそれぞれ接続されている。また、液晶セルの対向電極及び補助キャパシタの他方の電極は、コモン電圧Ｖｃｏｍが与えられるコモンライン１０に接続されている。 In this pixel structure, the TFT of each pixel has 220 gate lines 7 −1 and 7 − whose gate electrodes correspond to the number of pixels 220 in the vertical direction (row direction) (hereinafter referred to as the number of vertical pixels 220). 2 ,..., 7 -219 , 7 -220 and 560 columns corresponding to the number of pixels 560 in the horizontal direction (column direction) (hereinafter referred to as the number of horizontal pixels 560). Are connected to the signal lines 8 −1 , 8 −2 ... 8 −559 , and 8 −560 , respectively. The counter electrode of the liquid crystal cell and the other electrode of the auxiliary capacitor are connected to a common line 10 to which a common voltage Vcom is applied.

ここで、画素部は、図２に示す様に第１の表示領域１１と第２の表示領域１２を有し、第１の表示領域にはアスペクト比が４：３の標準のテレビジョン信号に対応した標準モード及びアスペクト比が１６：９のワイドビジョンに対応したワイドモードの両モードで表示データが供給される。一方、第２の表示領域には標準モードでは表示データが供給されるものの、ワイドモードでは表示データは供給されずに黒レベル信号が供給される。   Here, the pixel portion has a first display area 11 and a second display area 12 as shown in FIG. 2, and the first display area is a standard television signal having an aspect ratio of 4: 3. Display data is supplied in both the corresponding standard mode and the wide mode corresponding to the wide vision with an aspect ratio of 16: 9. On the other hand, although the display data is supplied to the second display area in the standard mode, the black level signal is supplied without supplying the display data in the wide mode.

なお、本実施例では、２９行から１９２行を第１の表示領域とし、１行から２８行及び１９３行から２２０行までを第２の表示領域（以下、便宜上１行から２８行を上部表示領域、１９３行から２２０行を下部表示領域と言う）とする場合を例に挙げて説明を行う。即ち、ワイドモードの際に１行から２８行及び１９３行から２２０行の各画素について黒色表示を行う場合を例に挙げて説明を行う。   In this embodiment, lines 29 to 192 are set as the first display area, lines 1 to 28 and lines 193 to 220 are set as the second display area (hereinafter, lines 1 to 28 are displayed in the upper part for convenience. The case where the area is designated as the lower display area is described as an example. That is, the case where black display is performed for each pixel from the first line to the 28th line and from the 193th line to the 220th line in the wide mode will be described as an example.

水平駆動系２は、水平画素数５６０に対応した５６０段のＨシフトレジスタ（図示せず）からなるＨスキャナ１３と、水平画素数５６０に対応して設けられた５６０個の水平スイッチ１４−１，１４−２・・・１４−５５９，１４−５６０を有する。Ｈスキャナは、水平スタートパルスＨＳＴを水平クロックＨＣＫに同期して順に転送することによって得られる各段の転送パルスを水平走査パルスとして順に出力する。水平スイッチは例えばＭＯＳトランジスタからなり、Ｈスキャナから順に出力される水平走査パルスに応答して順次オン状態となることで、表示データを画素部の信号ラインに供給する。 The horizontal drive system 2 includes an H scanner 13 composed of a 560-stage H shift register (not shown) corresponding to the number of horizontal pixels 560, and 560 horizontal switches 14 −1 provided corresponding to the number of horizontal pixels 560. , 14 -2 ... 14 -559 , 14 -560 . The H scanner sequentially outputs the transfer pulses of each stage obtained by sequentially transferring the horizontal start pulse HST in synchronization with the horizontal clock HCK as a horizontal scanning pulse. The horizontal switch is composed of, for example, a MOS transistor, and sequentially turns on in response to horizontal scanning pulses sequentially output from the H scanner, thereby supplying display data to the signal line of the pixel portion.

垂直駆動系３は、図３で示す様に、垂直画素数２２０に対応した段数のＶシフトレジスタ１５−１，１５−２・・・１５−２１９，１５−２２０と、７段目のＶシフトレジスタ１５−７に対応した垂直スイッチ１６−７、１１段目のＶシフトレジスタ１５−１１に対応した垂直スイッチ１６−１１、１５段目のＶシフトレジスタ１５−１５に対応した垂直スイッチ１６−１５、１９段目のＶシフトレジスタ１５−１９に対応した垂直スイッチ１６−１９、２３段目のＶシフトレジスタ１５−２３に対応した垂直スイッチ１６−２３、１９９段目のＶシフトレジスタ１５−１９９に対応した垂直スイッチ１６−１９９、２０３段目のＶシフトレジスタ１５−２０３に対応した垂直スイッチ１６−２０３、２０７段目のＶシフトレジスタ１５−２０７に対応した垂直スイッチ１６−２０７、２１１段目のＶシフトレジスタ１５−２１１に対応した垂直スイッチ１６−２１１、２１５段目のＶシフトレジスタ１５−２１５に対応した垂直スイッチ１６−２１５からなるＶスキャナ１７を有する。 As shown in FIG. 3, the vertical drive system 3 includes V shift registers 15 −1 , 15 −2 ... 15 −219 , 15 −220 corresponding to the number of vertical pixels 220, and the V shift of the seventh stage. register 15 vertical switch 16 -7 corresponding to -7, vertical switch 16 -11 corresponding to the V shift register 15 -11 11 stage, the vertical switch 16 -15 corresponding to the V shift register 15 -15 15 stage vertical switch 16 -19 corresponding to 19-stage V shift register 15 -19, vertical switch 16 -23 corresponding to the V shift register 15 -23 23 stage, the V shift register 15 -199 199 stage the corresponding vertical switch 16 -199, 203-stage V shift register 15 -203 vertical switch 16 -203 corresponding to, 207 stage V Schiff Vertical switch 16 corresponding to the register 15 -207 -207, 211-stage V shift register 15 -211 vertical switch 16 -211 corresponding to a vertical switch 16 corresponding to the 215-stage V shift register 15 -215 -215 The V scanner 17 consisting of

ここで、上部表示領域に形成された垂直スイッチ１６−７，１６−１１，１６−１５，１６−１９，１６−２３は、第1のＣＭＯＳスイッチ１８及び第２のＣＭＯＳスイッチ１９を有し、第１のＣＭＯＳスイッチのＰチャネル側のゲート電極と第２のＣＭＯＳスイッチのＮチャネル側のゲート電極はアスペクト比切り替え制御パルスＷＩＤＥラインに接続し、第１のＣＭＯＳスイッチのＮチャネル側のゲート電極と第２のＣＭＯＳスイッチのＰチャネル側のゲート電極はインバータ２０を介してＷＩＤＥラインに接続し、第１のＣＭＯＳスイッチのソース電極は対応するＶシフトレジスタの前段のＶシフトレジスタに接続し、第２のＣＭＯＳスイッチのソース電極は２段目のＶシフトレジスタに接続し、第１のＣＭＯＳスイッチのドレイン電極及び第２のＣＭＯＳスイッチのドレイン電極は対応するＶシフトレジスタに接続している。 Here, the vertical switches 16 −7 , 16 −11 , 16 −15 , 16 −19 , and 16 −23 formed in the upper display area include the first CMOS switch 18 and the second CMOS switch 19, The gate electrode on the P channel side of the first CMOS switch and the gate electrode on the N channel side of the second CMOS switch are connected to the aspect ratio switching control pulse WIDE line, and the gate electrode on the N channel side of the first CMOS switch The gate electrode on the P channel side of the second CMOS switch is connected to the WIDE line via the inverter 20, the source electrode of the first CMOS switch is connected to the V shift register in the preceding stage of the corresponding V shift register, and the second The source electrode of the CMOS switch is connected to the second stage V shift register, and the drain of the first CMOS switch is connected. And the drain electrode of the second CMOS switch are connected to the corresponding V shift register.

また、下部表示領域に形成された垂直スイッチ１６−１９９，１６−２０３，１６−２０７，１６−２１１，１６−２１５は、第１のＣＭＯＳスイッチ及び第２のＣＭＯＳスイッチを有し、第１のＣＭＯＳスイッチのＰチャネル側のゲート電極と第２のＣＭＯＳスイッチのＮチャネル側のゲート電極はＷＩＤＥラインに接続し、第１のＣＭＯＳスイッチのＮチャネル側のゲート電極と第２のＣＭＯＳスイッチのＰチャネル側のゲート電極はインバータを介してＷＩＤＥラインに接続し、第１のＣＭＯＳスイッチのソース電極は対応するＶシフトレジスタの前段のＶシフトレジスタに接続し、第２のＣＭＯＳスイッチのソース電極は１９４段目のＶシフトレジスタに接続し、第１のＣＭＯＳスイッチのドレイン電極及び第２のＣＭＯＳスイッチのドレイン電極は対応するＶシフトレジスタに接続している。 The lower display vertical switch 16 formed in the region -199, 16 -203, 16 -207, 16 -211, 16 -215 has a first CMOS switch and the second CMOS switch, the first The gate electrode on the P channel side of the CMOS switch and the gate electrode on the N channel side of the second CMOS switch are connected to the WIDE line, and the gate electrode on the N channel side of the first CMOS switch and the P channel of the second CMOS switch The gate electrode on the side is connected to the WIDE line via an inverter, the source electrode of the first CMOS switch is connected to the V shift register in the previous stage of the corresponding V shift register, and the source electrode of the second CMOS switch is 194 stages Connected to the second V shift register, the drain electrode of the first CMOS switch and the second CMOS switch A drain electrode of the pitch is connected to the corresponding V shift register.

なお、ＷＩＤＥはハイレベル（以下、Ｈレベルと言う）とローレベル（以下、Ｌレベルと言う）の２値をとり、第１のＣＭＯＳスイッチ及び第２のＣＭＯＳスイッチは、Ｐチャネル側のゲート電極にＬレベルのＷＩＤＥが供給された際にオンの状態となる様に設計されている。   Note that WIDE has a binary value of high level (hereinafter referred to as H level) and low level (hereinafter referred to as L level), and the first and second CMOS switches are gate electrodes on the P channel side. It is designed to be turned on when L level WIDE is supplied.

以下、垂直スタートパルスＶＳＴ、垂直クロックＶＣＫ、ＷＩＤＥの動作タイミング及びｎ段目のＶシフトレジスタの出力パルス＃ｎを示す図４、図５及び図６を参照して上記した液晶駆動回路の動作について説明する。なお、図中符号ｃは表示データの書き込みが行われる領域である画像表示部を示している。   Hereinafter, the operation of the liquid crystal driving circuit described above with reference to FIGS. 4, 5, and 6 showing the operation timing of the vertical start pulse VST, the vertical clocks VCK, and WIDE and the output pulse #n of the n-th stage V shift register. explain. In the figure, the symbol c indicates an image display unit which is an area where display data is written.

先ず、標準モード時は、図４に示す様にＷＩＤＥを常にＬレベルとして、図７で示す様に第１のＣＭＯＳスイッチをオンの状態とし、第２のＣＭＯＳスイッチをオフの状態とする。   First, in the standard mode, WIDE is always set to the L level as shown in FIG. 4, the first CMOS switch is turned on, and the second CMOS switch is turned off as shown in FIG.

この状態で、ＶＳＴをＶＣＫに同期して順に転送することによって、垂直走査パルスを順に出力し、画素部（第１の表示領域及び第２の表示領域）の各画素を一行ずつ順に選択する。同時に水平駆動系で、垂直駆動系での垂直走査によって順に選択される行毎に、Ｈスキャナから順に出力される水平走査パルスに応答して水平スイッチが順次オン状態となることで、表示データを画素部の信号ラインに供給する。
この様にして、画素部の各画素に対して１行毎に点順次で表示データの書き込みが行われ、結果としてアスペクト比が４：３の表示画像を得ることができる。 In this state, VST is sequentially transferred in synchronization with VCK, whereby vertical scanning pulses are sequentially output, and each pixel of the pixel portion (first display region and second display region) is sequentially selected row by row. At the same time, the horizontal switch is sequentially turned on in response to horizontal scanning pulses sequentially output from the H scanner for each row sequentially selected in the horizontal driving system by vertical scanning in the vertical driving system. This is supplied to the signal line of the pixel portion.
In this manner, display data is written dot-sequentially for each pixel in the pixel portion, and as a result, a display image having an aspect ratio of 4: 3 can be obtained.

次に、ワイドモード時は、図５及び図６に示す様にＷＩＤＥを常にＨレベルとして、図８に示す様に第１のＣＭＯＳスイッチをオフの状態とし、第２のＣＭＯＳスイッチをオンの状態とする。   Next, in the wide mode, WIDE is always set to the H level as shown in FIGS. 5 and 6, the first CMOS switch is turned off as shown in FIG. 8, and the second CMOS switch is turned on. And

この状態で、ＶＳＴをＶＣＫに同期して転送することによって、Ｖシフトレジスタは１段目から転送をし始めるが、３段目のＶシフトレジスタに転送されると同時に７段目、１１段目、１５段目、１９段目及び２３段目のＶシフトレジスタにも転送し、各々次段のＶシフトレジスタに順に転送するために、垂直走査パルスが６段同時に出力し、画素部の３行目、７行目、１１行目、１５行目、１９行目及び２３行目の各画素が同時に選択され、画素部の４行目、８行目、１２行目、１６行目、２０行目及び２４行目の各画素が同時に選択され、画素部の５行目、９行目、１３行目、１７行目、２１行目及び２５行目の各画素が同時に選択され、画素部の６行目、１０行目、１４行目、１８行目、２２行目及び２６行目の各画素が同時に選択できる。同時に水平駆動系で、上部表示領域に対応する図５中符号ａで示す８Ｈ期間黒レベル信号を供給し、垂直駆動系での垂直走査によって選択される行毎に、Ｈスキャナから順に出力される水平走査パルスに応答して水平スイッチが順次オン状態となることで、黒レベル信号を上部表示領域の信号ラインに供給する。
この様に８Ｈ期間黒レベル信号を供給することで、上部表示領域の各画素に対して黒レベル信号の書き込みを行うことができる。 In this state, by transferring VST in synchronization with VCK, the V shift register starts to transfer from the first stage, but at the same time as it is transferred to the third stage V shift register, the seventh stage and the eleventh stage In order to transfer the data to the 15th, 19th and 23rd V shift registers, and sequentially to the next V shift register, 6 vertical scanning pulses are output simultaneously, and 3 rows of the pixel portion are output. The pixels on the 7th, 7th, 11th, 15th, 19th and 23rd rows are selected simultaneously, and the 4th, 8th, 12th, 16th and 20th rows of the pixel portion are selected. The pixels in the first and 24th rows are selected at the same time, and the pixels in the fifth, ninth, thirteenth, seventeenth, twenty-first, twenty-first and twenty-fifth rows of the pixel portion are selected simultaneously. The pixels on the 6th, 10th, 14th, 18th, 22nd and 26th rows can be selected simultaneously. That. At the same time, an 8H period black level signal indicated by symbol a in FIG. 5 corresponding to the upper display area is supplied by the horizontal drive system, and sequentially output from the H scanner for each row selected by vertical scanning in the vertical drive system. In response to the horizontal scanning pulse, the horizontal switch is sequentially turned on to supply a black level signal to the signal line of the upper display area.
By supplying the black level signal for the 8H period in this way, the black level signal can be written to each pixel in the upper display area.

次に、２９段目から１９２段目までのＶシフトレジスタは順次転送することによって、垂直走査パルスを順に出力し、第１の表示領域の各画素を一行ずつ順に選択する。同時に水平駆動系で、垂直駆動系での垂直走査によって順に選択される行毎に、Ｈスキャナから順に出力される水平走査パルスに応答して水平スイッチが順次オンとなることで、表示データを表示部の信号ラインに供給する。
この様にして、第１の表示領域の各画素に対して１行毎に点順次で表示データの書き込みが行われる。 Next, the V shift registers from the 29th stage to the 192nd stage sequentially transfer to sequentially output vertical scanning pulses, and sequentially select each pixel in the first display area line by line. At the same time, the horizontal switch is sequentially turned on in response to horizontal scanning pulses sequentially output from the H scanner for each row sequentially selected by vertical scanning in the vertical driving system, thereby displaying display data. To the signal line of the unit.
In this manner, display data is written dot-sequentially for each row in each pixel of the first display area.

続いて、Ｖシフトレジスタは１９３段目から転送をし始めるが、１９５段目のＶに転送されると同時に１９９段目、２０３段目、２０７段目、２１１段目及び２１５段目のＶシフトレジスタにも転送し、各々次段のＶシフトレジスタに順位転送するため、垂直走査パルスが６段同時に出力し、画素部の１９５行目、１９９行目、２０３行目、２０７行目、２１１行目及び２１５行目の各画素が同時に選択され、画素部の１９６行目、２００行目、２０４行目、２０８行目、２１２行目及び２１６行目の各画素が同時に選択され、画素部の１９７行目、２０１行目、２０５行目、２０９行目、２１３行目及び２１７行目の各画素が同時に選択され、画素部の１９８行目、２０２行目、２０６行目、２１０行目、２１４行目及び２１８行目の各画素が同時に選択できる。同時に水平駆動系で、下部表示領域に対応する図６中符号ｂで示す８Ｈ期間黒レベル信号を供給し、垂直駆動系での垂直走査によって選択される行毎に、Ｈスキャナから順に出力される水平走査パルスに応答して水平スイッチが順次オン状態となることで、黒レベル信号を下部表示領域の信号ラインに供給する。
この様にして下部表示領域の各画素に対して黒レベル信号の書き込みが行われ、結果としてアスペクト比が１６：９の表示画像を得ることができる。 Subsequently, the V shift register starts to transfer from the 193rd stage, but at the same time as being transferred to the 195th stage V, the 199th, 203rd, 207th, 211th and 215th stage V shifts Since it is also transferred to the register and transferred to the next V shift register in order, 6 vertical scanning pulses are output simultaneously, and the 195th line, 199th line, 203rd line, 207th line, 211th line of the pixel portion are output. The pixels in the first and 215th rows are simultaneously selected, and the pixels in the 196th, 200th, 204th, 208th, 212th and 216th rows of the pixel portion are simultaneously selected, Lines 197, 201, 205, 209, 213, and 217 are selected at the same time, and pixels 198, 202, 206, 210, Lines 214 and 218 There can be selected at the same time. At the same time, a black level signal indicated by symbol b in FIG. 6 corresponding to the lower display area is supplied in the horizontal drive system, and is output sequentially from the H scanner for each row selected by vertical scanning in the vertical drive system. In response to the horizontal scanning pulse, the horizontal switches are sequentially turned on to supply a black level signal to the signal line in the lower display area.
In this way, a black level signal is written to each pixel in the lower display area, and as a result, a display image having an aspect ratio of 16: 9 can be obtained.

上記した本発明を適用したアクティブマトリクス型液晶表示装置では、第２の表示領域への黒レベル信号の書き込みを一括して行わないために、ワイドモードの際に画素部が寄生容量によるノイズの影響を受け難く、充分に黒レベル信号の書き込みを行うことができる。   In the active matrix liquid crystal display device to which the present invention is applied, the black level signal is not written to the second display area all at once, so that the pixel portion is affected by noise due to parasitic capacitance in the wide mode. The black level signal can be sufficiently written.

なお、上記の実施例では、２個のＣＭＯＳスイッチを１組として構成され、ＷＩＤＥによりどちらか一方のスイッチがオンの状態となる垂直スイッチを、一方のＣＭＯＳスイッチのソース端子には前段のＶシフトレジスタ出力が供給され、もう一方のＣＭＯＳスイッチのソース端子には複数行の同時選択を開始する前段のＶシフトレジスタ出力を供給する様に第２の表示領域に付加しているが、標準モードで画素部の各画素を一行ずつ順に選択する様な垂直走査パルスを順に出力し、ワイドモードで第２の表示領域の各画素を複数行ずつ順に選択する様な垂直走査パルスを順に出力することができるのであれば、他の回路構成であっても良い。   In the above-described embodiment, two CMOS switches are configured as one set, and a vertical switch in which one of the switches is turned on by WIDE, and the V-shift of the previous stage is applied to the source terminal of one CMOS switch. A register output is supplied and the second display area is added to the source terminal of the other CMOS switch so as to supply the V shift register output of the previous stage which starts simultaneous selection of a plurality of rows. A vertical scanning pulse for sequentially selecting each pixel in the pixel portion one by one in order is output in order, and a vertical scanning pulse for sequentially selecting each pixel in the second display region in a plurality of rows in the wide mode is sequentially output. If possible, other circuit configurations may be used.

また、上記の実施例では、上部表示領域内の各画素を複数行ずつ選択して黒レベル信号の書き込みを行い、第１の表示領域の各画素を一行ずつ選択して表示データの書き込みを行った後に、下部表示領域内の各画素を複数行ずつ選択して黒レベル信号の書き込みを行っているが、上部表示領域内の各画素を少なくとも一行選択すると共に下部表示領域内の各画素を少なくとも一行選択して上部表示領域内及び下部表示領域内の各画素に同時に黒レベル信号の書き込みを行っても良い。   Further, in the above embodiment, each pixel in the upper display area is selected in a plurality of lines and black level signal is written, and each pixel in the first display area is selected in one line and display data is written. After that, each pixel in the lower display area is selected in a plurality of rows and the black level signal is written, but at least one row in each pixel in the upper display area is selected and at least each pixel in the lower display area is selected. One line may be selected and a black level signal may be simultaneously written to each pixel in the upper display area and the lower display area.

更に、上記の実施例では、ワイドモードの際に画面の上下に黒レベル信号を書き込み、黒枠表示を行うことによって異なるアスペクト比を実現するとしたが、ワイドモードの際に画面の上下に書き込む信号は必ずしも黒レベル信号に限定される必要は無く、他の輝度レベル信号を書き込むことによって異なるアスペクト比に対応するようにしても良い。   Furthermore, in the above embodiment, the black level signals are written at the top and bottom of the screen in the wide mode, and different aspect ratios are realized by displaying the black frame. However, the signals to be written at the top and bottom of the screen in the wide mode are as follows. It is not necessarily limited to the black level signal, and different aspect ratios may be supported by writing other luminance level signals.

また、上記の実施例では、画素の表示素子として液晶セルを用いた液晶表示装置を例に挙げて説明を行ったが、画素の表示素子として例えばエレクトロルミネセンス（ＥＬ）素子を用いたＥＬ表示装置などのアクティブマトリクス型表示装置全般に適用が可能である。   In the above embodiments, a liquid crystal display device using a liquid crystal cell as a pixel display element has been described as an example. However, for example, an EL display using an electroluminescence (EL) element as the pixel display element. The present invention can be applied to all active matrix display devices such as devices.

本発明を適用したアクティブマトリクス型液晶表示装置の一例における液晶駆動回路の構成を説明するための図である。It is a figure for demonstrating the structure of the liquid crystal drive circuit in an example of the active matrix type liquid crystal display device to which this invention is applied. 画素部を説明するための模式図である。It is a schematic diagram for demonstrating a pixel part. 垂直駆動系を説明するための模式図である。It is a schematic diagram for demonstrating a vertical drive system. 標準モードにおける各クロックパルスの動作タイミング及びシフトレジスタの出力パルスを説明するためのタイミングチャートである。It is a timing chart for demonstrating the operation timing of each clock pulse in a standard mode, and the output pulse of a shift register. ワイドモードにおける各クロックパルスの動作タイミング及び上部表示領域のシフトレジスタの出力パルスを説明するためのタイミングチャートである。It is a timing chart for explaining the operation timing of each clock pulse in the wide mode and the output pulse of the shift register in the upper display area. ワイドモードにおける各クロックパルスの動作タイミング及び下部表示領域のシフトレジスタの出力パルスを説明するためのタイミングチャートである。It is a timing chart for demonstrating the operation timing of each clock pulse in a wide mode, and the output pulse of the shift register of a lower display area. 標準モードにおける垂直駆動系の動作を説明するための模式図である。It is a schematic diagram for demonstrating operation | movement of the vertical drive system in standard mode. ワイドモードにおける垂直駆動系の動作を説明するための模式図である。It is a schematic diagram for demonstrating operation | movement of the vertical drive system in a wide mode.

符号の説明Explanation of symbols

１ 画素部
２ 水平駆動系
３ 垂直駆動系
４ ＴＦＴ
５ 液晶セル
６ 補助キャパシタ
７ ゲートライン
８ 信号ライン
１０ コモンライン
１１ 第１の表示領域
１２ 第２の表示領域
１３ Ｈスキャナ
１４ 水平スイッチ
１５ Ｖシフトレジスタ
１６ 垂直スイッチ
１７ Ｖスキャナ
１８ 第１のＣＭＯＳスイッチ
１９ 第２のＣＭＯＳスイッチ
２０ インバータ 1 Pixel part 2 Horizontal drive system 3 Vertical drive system 4 TFT
5 Liquid Crystal Cell 6 Auxiliary Capacitor 7 Gate Line 8 Signal Line 10 Common Line 11 First Display Area 12 Second Display Area 13 H Scanner 14 Horizontal Switch 15 V Shift Register 16 Vertical Switch 17 V Scanner 18 First CMOS Switch 19 Second CMOS switch 20 Inverter

Claims (1)

画素が行列状に配列され、第１の表示領域と第２の表示領域を有する画素部と、
該画素部の各行に対応して設けられ、制御信号が入力されると画素部の各画素を垂直方向に走査する垂直走査信号を出力すると共に、後段に制御信号を出力可能に構成されたシフトレジスタと、該シフトレジスタに順次制御信号が入力されることで第１の表示領域及び第２の表示領域の各画素を１行ずつ順次選択する第１の駆動モードと、第２の表示領域に対応する所定のシフトレジスタに略同時に制御信号が入力され、同所定のシフトレジスタは前段のシフトレジスタからの制御信号が遮断される一方、前記所定のシフトレジスタ以外のシフトレジスタは前段のシフトレジスタからの制御信号が入力されることで第１の表示領域の各画素を１行ずつ順次選択すると共に、第２の表示領域の各画素を複数行ずつ順次選択する第２の駆動モードとを、切り替えるスイッチ回路を有する垂直駆動系と、
第１の駆動モード時に前記垂直駆動系によって選択した第１の表示領域及び第２の表示領域の各画素に表示信号を順次書き込み、第２の駆動モード時に前記垂直駆動系によって選択した第１の表示領域の各画素に表示信号を順次書き込むと共に、第２の駆動モード時に前記垂直駆動系によって選択した第２の表示領域の各画素に所定の輝度レベル信号を順次書き込む様に構成された水平駆動系を備える
表示装置。 A pixel portion in which pixels are arranged in a matrix and having a first display area and a second display area;
Shift provided to correspond to each row of the pixel portion, and configured to output a vertical scanning signal for scanning each pixel of the pixel portion in the vertical direction when a control signal is input, and to output a control signal to the subsequent stage. A first drive mode in which each pixel in the first display region and the second display region is sequentially selected one by one by sequentially inputting a control signal to the shift register, and the second display region A control signal is input to the corresponding predetermined shift register substantially simultaneously, and the control signal from the previous shift register is cut off from the predetermined shift register, while shift registers other than the predetermined shift register are input from the previous shift register. thereby sequentially selecting one row of pixels in the first display area in the control that the signal is input, a second driving mode for sequentially selecting the pixels of the second display area by a plurality of rows And a vertical driving system having a switching circuit for switching,
A display signal is sequentially written to each pixel in the first display area and the second display area selected by the vertical drive system in the first drive mode, and the first signal selected by the vertical drive system in the second drive mode. A horizontal drive configured to sequentially write a display signal to each pixel in the display area and to sequentially write a predetermined luminance level signal to each pixel in the second display area selected by the vertical drive system in the second drive mode. A display device comprising the system.
JP2004028822A 2004-02-05 2004-02-05 Display device Expired - Fee Related JP4470507B2 (en)

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KR101048994B1 (en) 2009-01-29 2011-07-12 삼성모바일디스플레이주식회사 Organic electroluminescence display device and driving method thereof
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