JP4443324B2 - Flexible wiring board and manufacturing method thereof, semiconductor chip mounting flexible wiring board, electronic device - Google Patents

Flexible wiring board and manufacturing method thereof, semiconductor chip mounting flexible wiring board, electronic device Download PDF

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JP4443324B2
JP4443324B2 JP2004189980A JP2004189980A JP4443324B2 JP 4443324 B2 JP4443324 B2 JP 4443324B2 JP 2004189980 A JP2004189980 A JP 2004189980A JP 2004189980 A JP2004189980 A JP 2004189980A JP 4443324 B2 JP4443324 B2 JP 4443324B2
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wiring
semiconductor chip
input
conductive
thickness
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JP2006013230A (en
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秀隆 大峡
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Tohoku Pioneer Corp
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Priority to CN2005100811303A priority patent/CN1717147B/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

本発明は、フレキシブル配線基板及びその製造方法、半導体チップ実装フレキシブル配線基板、電子機器に関するものである。   The present invention relates to a flexible wiring board and a manufacturing method thereof, a semiconductor chip mounting flexible wiring board, and an electronic device.

携帯電話機やＰＤＡ（Personal Digital Assistant：携帯情報端末機器）等の小型，軽量，高性能化が要求される電子機器においては、プリント配線基板上への電子部品の実装密度向上が求められている。特に、このような電子機器に装備される薄型のフラットパネル表示装置は、表示画面を可能な限り大きくとりたいことから、その周辺に配備される駆動配線部品の実装密度向上が要求されており、これに対応するために、フレキシブル配線基板の配線と半導体チップの入出力端子とを直接接続してフレキシブル配線基板上に半導体チップを実装するＣＯＦ（Chip On Film）が近年多用されている。   In electronic devices such as mobile phones and PDAs (Personal Digital Assistants) that require small size, light weight, and high performance, it is required to improve the mounting density of electronic components on a printed circuit board. In particular, a thin flat panel display device equipped in such an electronic device is required to increase the mounting density of drive wiring components arranged in the periphery of the thin flat panel display device because it wants to take a display screen as large as possible. In order to cope with this, COF (Chip On Film) in which the wiring of the flexible wiring board and the input / output terminals of the semiconductor chip are directly connected and the semiconductor chip is mounted on the flexible wiring board has been frequently used in recent years.

このＣＯＦでは、フレキシブル配線基板上の配線パターンを、半導体チップにおける入出力端子（バンプ）のパターンに対応して形成する必要がある。この際のフレキシブル配線基板のパターン形成技術としては、下記特許文献１に記載されるようなセミアディティブ法又はフルアディティブ法と呼ばれる技術が採用されることが多い。   In this COF, it is necessary to form the wiring pattern on the flexible wiring board corresponding to the pattern of the input / output terminals (bumps) in the semiconductor chip. As a pattern forming technique for the flexible wiring board at this time, a technique called a semi-additive method or a full additive method as described in Patent Document 1 below is often employed.

この従来技術を図１によって説明すると、先ず、同図（ａ）に示すように、可撓性の絶縁基材１００の表面にメッキリードとなるシード層１０１を形成し、次いで、同図（ｂ）に示すように、所望の配線パターンを形成するために、シード層１０１の表面にフォトレジスト材等を用いたマスクパターン１０２を形成する。そして、同図（ｃ）に示すように、電解メッキ法によってシード層１０１の露出した領域にニッケル，銅等の導電性部材を被着して配線パターン１０３を形成し、また、必要に応じて、それらの配線パターン１０３の表面に、電解メッキ法又はスパッタリングや蒸着等の成膜法で金等の異種金属による表面導電層１０４を形成する。そして、同図（ｄ）に示すように、マスクパターン１０２及びその底部に位置するシード層１０１を除去することにより、絶縁基材１００の上にシード層部分１０１Ａ，配線パターン１０３，表面導電層１０４からなる所望パターンの導電配線を有するフレキシブル配線基板が形成される。   This prior art will be described with reference to FIG. 1. First, as shown in FIG. 1A, a seed layer 101 serving as a plating lead is formed on the surface of a flexible insulating base material 100, and then FIG. ), A mask pattern 102 using a photoresist material or the like is formed on the surface of the seed layer 101 in order to form a desired wiring pattern. Then, as shown in FIG. 5C, a conductive member such as nickel or copper is deposited on the exposed region of the seed layer 101 by an electrolytic plating method to form a wiring pattern 103, and if necessary, Then, a surface conductive layer 104 made of a different metal such as gold is formed on the surface of the wiring pattern 103 by an electrolytic plating method or a film forming method such as sputtering or vapor deposition. Then, as shown in FIG. 4D, the mask pattern 102 and the seed layer 101 located at the bottom of the mask pattern 102 are removed, so that the seed layer portion 101A, the wiring pattern 103, and the surface conductive layer 104 are formed on the insulating substrate 100. A flexible wiring board having a conductive pattern having a desired pattern is formed.

一方、半導体チップにおける入出力端子（バンプ）の配列パターンは、駆動対象の電子機器の端子配列や半導体チップ内部の回路ブロックの構成によって決まるものであるが、一般的には、一様なパターンの端子形態ではなく、大小異なる大きさのバンプが配列されていることが多い。   On the other hand, the arrangement pattern of the input / output terminals (bumps) in the semiconductor chip is determined by the terminal arrangement of the electronic device to be driven and the configuration of the circuit block inside the semiconductor chip. In many cases, bumps of different sizes are arranged instead of the terminal form.

特開２０００−２８６５３６号公報JP 2000-286536 A

前述したような、異なる大きさのバンプを有する半導体チップを実装するＣＯＦにおいて、一般には大きなバンプには大きな電流が流れるので、このようなバンプと接続するフレキシブル配線基板上の配線幅はバンプの大きさに応じて広くしており、バンプの大きさに対応させて配線幅の異なる導電配線のパターンが形成されている。特に、このようなバンプの大きさに応じた配線幅を有する導電配線のパターン形成は、駆動電流の大小が機器の性能に大きく影響する電子機器を対象とする場合に重要な設計事項になる。特に、自発光型のフラットパネルディスプレイとして近年注目されている有機ＥＬ表示装置においては、駆動電流の大小が直接表示性能に影響を及ぼすので、これに接続されるフレキシブル配線基板には前述したような配線パターンの設計が不可欠になっている。   In a COF for mounting a semiconductor chip having bumps of different sizes as described above, generally a large current flows through a large bump. Therefore, the wiring width on the flexible wiring board connected to such a bump is the size of the bump. The pattern of the conductive wiring having a different wiring width is formed corresponding to the size of the bump. In particular, the formation of a conductive wiring pattern having a wiring width corresponding to the size of the bump is an important design item when an electronic device whose driving current greatly affects the performance of the device is targeted. In particular, in an organic EL display device that has been attracting attention as a self-luminous flat panel display in recent years, the magnitude of the drive current directly affects the display performance. Wiring pattern design is indispensable.

しかしながら、従来技術で示したような配線パターン形成技術を採用して、このような異なる線幅の導電配線を形成した場合には、以下に示すような問題が顕在化することになる。   However, when the wiring pattern forming technique as shown in the prior art is adopted to form conductive wirings having such different line widths, the following problems become apparent.

つまり、線幅の異なる複数の導電配線を電解メッキによって形成すると、幅の広い配線では配線材料が厚く被着され、幅の狭い配線では配線材料が薄く被着される現象が生じる。これは、電解メッキの際に幅の広い配線は幅の狭い配線に比べて抵抗による電位降下が小さくなることに起因するものであるが、このような厚みの差が導電配線のパターンに応じて生じると、フレキシブル配線基板の導電配線と半導体チップのバンプとを異方性導電膜を介して熱圧着により接続する際に、隣接する配線に段差が形成される部分の周辺で圧着不良が生じやすくなるという問題が生じる。   That is, when a plurality of conductive wirings having different line widths are formed by electrolytic plating, a phenomenon occurs in which the wiring material is thickly attached to a wide wiring and the wiring material is thinly attached to a narrow wiring. This is due to the fact that the potential drop due to resistance is smaller in the wide wiring than in the narrow wiring during electrolytic plating, but such a thickness difference depends on the pattern of the conductive wiring. When this occurs, when the conductive wiring of the flexible wiring board and the bump of the semiconductor chip are connected by thermocompression bonding via the anisotropic conductive film, a crimping failure is likely to occur around the portion where the step is formed in the adjacent wiring. Problem arises.

これを図２に示す例によって更に具体的に説明する。フレキシブル配線基板１には、幅が広い配線１ａと同一形態の配線によって一つのパターンを形成した第１の配線領域１Ａが形成されており、また、幅が狭い配線１ｂと同一形態の配線によって一つのパターンを形成した第２の配線領域１Ｂが形成されている。一方、半導体チップ２には、幅が広いバンプ２ａと同一形態のバンプによって一つのパターンを形成した第１のバンプ領域２Ａが形成されると共に、幅が狭いバンプ２ｂと同一形態のバンプによって一つのパターンを形成した第２のバンプ領域２Ｂが形成されている。配線１ａとバンプ２ａ或いは配線１ｂとバンプ２ｂは、それぞれほぼ同じ幅を有し且つ同じパターンを有しており、異方性導電膜（ＡＣＦ；Anisotropic conductive film）３を介して互いに突き合わされ、加熱状態で圧力Ｐを加えられて熱圧着されている。   This will be described more specifically with reference to the example shown in FIG. The flexible wiring board 1 is formed with a first wiring region 1A in which one pattern is formed by the same type of wiring as the wide wiring 1a, and one by the same type of wiring as the narrow wiring 1b. A second wiring region 1B in which two patterns are formed is formed. On the other hand, the semiconductor chip 2 is formed with a first bump region 2A in which one pattern is formed by a bump having the same form as the wide bump 2a, and one bump is formed by a bump having the same form as the narrow bump 2b. A second bump region 2B in which a pattern is formed is formed. The wiring 1a and the bump 2a or the wiring 1b and the bump 2b have substantially the same width and the same pattern, and are brought into contact with each other via an anisotropic conductive film (ACF) 3 and heated. In this state, pressure P is applied and thermocompression bonding is performed.

ここで、第１の配線領域１Ａと第２の配線領域１Ｂとの隣接箇所においては、前述したように配線の幅に基づいて配線の厚みに差が生じ、配線の接触面に段差が形成された状態になっている。この状態で熱圧着がなされると、段差が形成される部分の周辺部分Ａでは、その段差が影響して充分な圧力が加えられず、その周辺部分Ａで圧着不良が生じて接続に不具合が生じる問題が起きることになる。   Here, in the adjacent portion between the first wiring region 1A and the second wiring region 1B, as described above, a difference occurs in the thickness of the wiring based on the width of the wiring, and a step is formed on the contact surface of the wiring. It is in the state. When thermocompression bonding is performed in this state, in the peripheral portion A of the portion where the step is formed, the step is affected, so that sufficient pressure is not applied, and in the peripheral portion A, bonding failure occurs, resulting in a connection failure. The problem that arises will occur.

この問題を解消するには、第１の配線領域１Ａにおける配線１ａと第２の配線領域１Ｂにおける配線１ｂの厚みを同厚にすればよいが、このように異なる幅の配線における厚みを同厚にするためには、特殊な加工処理や電解メッキの処理時間を配線幅毎に変える特殊な製造方法が必要になり、煩雑な処理を要することでフレキシブル配線基板がコスト高になる。また、微細な配線パターンに対してこのような特殊な処理を施すことは極めて困難であるという問題もある。   In order to solve this problem, the thickness of the wiring 1a in the first wiring region 1A and the thickness of the wiring 1b in the second wiring region 1B may be made the same. In order to achieve this, a special manufacturing method that changes the processing time of special processing and electrolytic plating for each wiring width is required, and the cost of the flexible wiring board increases due to complicated processing. In addition, there is a problem that it is extremely difficult to perform such special processing on a fine wiring pattern.

本発明は、このような問題に対処することを課題の一例とするものである。すなわち、異なる大きさの端子に対応して線幅の異なる導電配線が複数形成されたフレキシブル配線基板において、特殊な加工や製法を採用することなく、端子接続部における配線厚さを均一化すること、そして、これによってフレキシブル配線基板の導電配線と接続対象の端子間に接続不良が生じないようにすること、更には、異なる大きさの入出力端子を有する半導体チップに対してそれに応じた配線パターンを形成することで精度の高いＣＯＦを得ること、また、これによって配線抵抗のばらつきによる駆動電流の不均一を解消し、電子機器、特に駆動電流の大小が直接表示性能に影響を及ぼす有機ＥＬ表示装置において、良好な表示性能を確保すること等が本発明の目的である。   This invention makes it an example of a subject to cope with such a problem. That is, in a flexible wiring board in which a plurality of conductive wirings with different line widths corresponding to terminals of different sizes are formed, the wiring thickness at the terminal connection part can be made uniform without employing special processing or manufacturing methods. In addition, this prevents a defective connection between the conductive wiring of the flexible wiring board and the terminal to be connected, and furthermore, a wiring pattern corresponding to a semiconductor chip having input / output terminals of different sizes. To obtain high-precision COF, and to solve the non-uniformity of the drive current due to the variation in wiring resistance, and the electronic EL display, in particular, the magnitude of the drive current directly affects the display performance It is an object of the present invention to ensure good display performance in the apparatus.

なお、ここでは、異方性導電膜（ＡＣＦ）を介した端子と配線を例にして説明したが、これに限らず、非導電性フィルム（ＮＣＦ；Non-Conductive Film），異方性導電ペースト（ＡＣＰ；Anisotropic Conductive Paste），非導電性ペースト（ＮＣＰ；Non-Conductive Paste）等の接合方法を異方性導電膜（ＡＣＦ）に換えて採用した場合にも同様の問題が生じる。   Here, the terminal and the wiring through the anisotropic conductive film (ACF) have been described as an example, but the present invention is not limited to this, but is not limited to this, a non-conductive film (NCF), an anisotropic conductive paste. The same problem occurs when a bonding method such as (ACP: Anisotropic Conductive Paste) or non-conductive paste (NCP) is used instead of the anisotropic conductive film (ACF).

このような目的を達成するために、本発明は、以下の各独立請求項に係る構成を少なくとも具備するものである。   In order to achieve such an object, the present invention comprises at least the configurations according to the following independent claims.

［請求項１］絶縁膜で覆われて線幅の異なる配線引き回し部と、半導体チップの入出力端子が電気的に接続され、絶縁膜で覆われていない端子接続部とを有する複数の導電配線を配線基板上に備えたフレキシブル配線基板であって、前記端子接続部における少なくとも前記入出力端子が接続される箇所で、少なくとも一つの半導体チップに接続される導電配線の線幅が均一化され、前記導電配線は、電解メッキを用いたアディティブ法によって形成されることにより配線の幅に基づいた厚さを有し、前記配線引き回し部の厚さと前記端子接続部の厚さが異なり、前記配線引き回し部の厚さから前記端子接続部の厚さに傾斜をもって変わる変移領域を有するものを含み、前記端子接続部における絶縁膜が施されていない範囲で前記入出力端子を接続するのに有効な範囲である有効範囲の長さは、前記入出力端子が異方性導電膜を介して熱圧着される熱圧着領域の幅より長いことを特徴とするフレキシブル配線基板。 [Claim 1] A plurality of conductive wirings having a wiring routing portion covered with an insulating film and having different line widths, and a terminal connecting portion where input / output terminals of the semiconductor chip are electrically connected and not covered with an insulating film Is a flexible wiring board provided on a wiring board, wherein at least the input / output terminals in the terminal connection portion are connected, the line width of the conductive wiring connected to at least one semiconductor chip is made uniform, The conductive wiring is formed by an additive method using electrolytic plating, and has a thickness based on the width of the wiring. The thickness of the wiring routing portion is different from the thickness of the terminal connection portion, and the wiring routing is performed. include those having a transition region changes from thick parts with inclined thickness of the terminal connection unit, the input and output terminals to the extent that the insulating film in the terminal connecting portion is not subjected to The length of the effective range is a valid range for connection is a flexible wiring board on which the input-output terminal is equal to or longer than the width of the thermocompression bonding areas are thermocompression-bonded to each other via the anisotropic conductive film.

［請求項２］配線基板上の導電配線に半導体チップの入出力端子を接続した半導体チップ実装フレキシブル配線基板であって、前記半導体チップは大きさの異なる入出力端子を備え、前記導電配線は、絶縁膜で覆われて前記入出力端子の大きさに応じた線幅の配線引き回し部を有すると共に、前記入出力端子が電気的に接続される絶縁膜で覆われていない端子接続部を有し、前記端子接続部における少なくとも前記入出力端子が電気的に接続された箇所で、少なくとも一つの半導体チップに接続される導電配線の線幅が均一化され、前記入出力端子と前記端子接続部は異方性導電膜を介して熱圧着することによって電気的に接続され、前記導電配線は、電解メッキを用いたアディティブ法によって形成されることにより配線の幅に基づいた厚さを有し、前記配線引き回し部の厚さと前記端子接続部の厚さが異なり、前記配線引き回し部の厚さから前記端子接続部の厚さに傾斜をもって変わる変移領域を有するものを含み、前記端子接続部において、前記異方性導電膜が固化している領域の幅より絶縁膜が施されていない範囲の幅が長いことを特徴とする半導体チップ実装フレキシブル配線基板。 [Claim 2 ] A semiconductor chip mounting flexible wiring board in which an input / output terminal of a semiconductor chip is connected to a conductive wiring on a wiring board, wherein the semiconductor chip includes input / output terminals of different sizes, The wiring connection portion is covered with an insulating film and has a line width corresponding to the size of the input / output terminal, and the terminal connection portion is not covered with an insulating film to which the input / output terminal is electrically connected. The line width of the conductive wiring connected to at least one semiconductor chip is made uniform at least at the input / output terminal in the terminal connection portion, and the input / output terminal and the terminal connection portion are It is electrically connected by thermocompression bonding through an anisotropic conductive film, and the conductive wiring is formed by an additive method using electrolytic plating, and has a thickness based on the width of the wiring. Has is different in thickness and the thickness of the terminal connecting portion of the wiring lead-out portion, include those having a transition region changing from the thickness of the wire routing portion with an inclination to the thickness of the terminal connecting portion, wherein A semiconductor chip mounting flexible wiring board, wherein a width of a region where an insulating film is not applied is longer than a width of a region where the anisotropic conductive film is solidified in a terminal connection portion.

以下、本発明の実施形態を図面を参照して説明する。図３は本発明の一実施形態に係るフレキシブル配線基板を説明する説明図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 3 is an explanatory view illustrating a flexible wiring board according to an embodiment of the present invention.

同図（ａ）において、フレキシブル配線基板１０は、絶縁フィルム等からなる配線基板１１上に複数の導電配線１２を備えたものであり、導電配線１２は、絶縁膜（絶縁レジスト）１３が施されていない端子接続部１２Ａと絶縁膜１３で覆われている配線引き回し部１２Ｂとを有し、導電配線１２の端子接続部１２Ａに半導体チップの入出力端子（バンプ）が接続されることで、半導体チップ実装フレキシブル配線基板（ＣＯＦ；Chip On Film）を形成するものである。   In FIG. 1A, a flexible wiring board 10 is provided with a plurality of conductive wirings 12 on a wiring board 11 made of an insulating film or the like, and the conductive wiring 12 is provided with an insulating film (insulating resist) 13. The terminal connection portion 12A that is not connected and the wiring routing portion 12B that is covered with the insulating film 13 are provided, and the input / output terminals (bumps) of the semiconductor chip are connected to the terminal connection portion 12A of the conductive wiring 12, so that the semiconductor A chip-mounted flexible wiring board (COF; Chip On Film) is formed.

半導体チップの実装に際しては、一般に、異方性導電膜（ＡＣＦ）を介してフレキシブル配線基板１０を半導体チップの入出力端子に熱圧着して、この入出力端子と導電配線１２を電気的に接続することがなされ、その際には、破線で示した熱圧着領域Ｈに異方性導電膜が固化して付着することになる。以下、異方性導電膜（ＡＣＦ）を介した接合を例にして説明するが、本発明の実施形態としては、これに限らず、非導電性フィルム（ＮＣＦ；Non-Conductive Film），異方性導電ペースト（ＡＣＰ；Anisotropic Conductive Paste），非導電性ペースト（ＮＣＰ；Non-Conductive Paste）等の接合方法を異方性導電膜（ＡＣＦ）と同様に採用することができる。   When mounting a semiconductor chip, generally, the flexible wiring board 10 is thermocompression bonded to an input / output terminal of the semiconductor chip via an anisotropic conductive film (ACF), and the input / output terminal and the conductive wiring 12 are electrically connected. In this case, the anisotropic conductive film is solidified and attached to the thermocompression bonding region H indicated by the broken line. In the following, description will be given by taking an example of joining via an anisotropic conductive film (ACF). However, the embodiment of the present invention is not limited to this, but is not limited to this, and is not a non-conductive film (NCF) or anisotropic. Bonding methods such as conductive conductive paste (ACP) and non-conductive paste (NCP) can be employed in the same manner as anisotropic conductive film (ACF).

このフレキシブル配線基板１０における導電配線１２の配線パターンは、導電配線１２の配線引き回し部１２Ｂが、半導体チップの入出力端子の大きさに応じて異なる線幅（図示の例ではＷ１，Ｗ２の２種類の線幅）を有しており、大きな入出力端子に対しては低抵抗で大きな電流を流すことができるようになっている。   The wiring pattern of the conductive wiring 12 in the flexible wiring board 10 is such that the wiring routing portion 12B of the conductive wiring 12 has different line widths according to the size of the input / output terminals of the semiconductor chip (in the example shown, two types W1 and W2). And a large current can be flowed with a low resistance to a large input / output terminal.

そして、導電配線１２の端子接続部１２Ａは、配線引き回し部１２Ｂの線幅の違いに拘わらず、少なくとも一つの半導体チップに接続される導電配線の線幅が、製造誤差を含む範囲で均一化されるようにパターン形成されている。すなわち、図示の実施形態では、線幅Ｗ１の配線引き回し部１２Ｂを有する導電配線１２１と線幅Ｗ２の配線引き回し部１２Ｂを有する導電配線１２２の２種類の導電配線１２が配線基板１１上に形成されており、一つの形態の導電配線１２１においては、比較的幅広の線幅Ｗ１を有する配線引き回し部１２Ｂに対して、この線幅Ｗ１より幅が狭い線幅Ｗ１ａの端子接続部１２Ａが形成され、もう一つの形態の導電配線１２２においては、導電配線１２１における端子接続部１２Ａの線幅Ｗ１ａと等しい線幅Ｗ２の端子接続部１２Ａと配線引き回し部１２Ｂが形成された配線パターンを有している。 The terminal connection portion 12A of the conductive wiring 12 is uniformized within a range including manufacturing errors, regardless of the line width of the wiring routing portion 12B. The pattern is formed as shown. That is, in the illustrated embodiment, two types of conductive wirings 12, that is, a conductive wiring 121 having a wiring routing portion 12 </ b > B having a line width W < b > 1 and a conductive wiring 122 having a wiring routing portion 12 </ b > B having a line width W < b > 2 are formed on the wiring substrate 11. are formed in the conductive wire 12 1 of one embodiment, relatively with respect to wire routing portion 12B having a wide line width W1, the width from the line width W1 of the terminal connecting portion 12A of the narrow line width W1a It is formed in the conductive wire 12 2 of another form, a wiring pattern to which the terminal connecting portion 12A and the wire routing portion 12B of the line width W1a equal line width W2 of the terminal connecting portion 12A of conductive trace 12 1 is formed Have.

前述の導電配線１２１の形状としては、図３（ａ）の形状（端子接続部１２Ａと配線引き回し部１２Ｂの中心が一致した形状）だけでなく、同図（ｂ）に示すように端子接続部１２Ａと配線引き回し部１２Ｂの中心がオフセットした形状等であってもよく、要するに、端子接続部１２Ａにおいて、少なくとも一つの半導体チップに接続される導電配線の線幅が製造誤差を含む範囲で均一化されるようにパターン形成されていればよい。 The aforementioned conductive wiring 12 1 shape, not only the shape (shape in which the center matches the terminal connecting portion 12A and the wiring routing portion 12B) of FIG. 3 (a), terminal connection as shown in FIG. (B) The center of the part 12A and the wiring routing part 12B may be offset, or the like. In short, in the terminal connection part 12A, the line width of the conductive wiring connected to at least one semiconductor chip is uniform within a range including manufacturing errors. It suffices if the pattern is formed so as to be realized.

また、図示の例では、一つの導電配線１２（１２１，１２２）においては、端子接続部１２Ａの全体で線幅（Ｗ１ａ，Ｗ２）を一様にしているが、本発明の実施形態では、端子接続部１２Ａにおける少なくとも半導体チップの入出力端子が接続される箇所で線幅がほぼ等しくなっていれば良く、例えば、前述の熱圧着領域Ｈ内のみで線幅がほぼ等しくなるような導電配線１２の形状であってもよい。 Further, in the illustrated example, in one conductive wiring 12 (12 1 , 12 2 ), the line width (W1a, W2) is made uniform throughout the terminal connection portion 12A, but in the embodiment of the present invention, In the terminal connection portion 12A, it is sufficient that the line widths are substantially equal at least at the portion where the input / output terminals of the semiconductor chip are connected. The shape of the wiring 12 may be sufficient.

このような実施形態によると、セミアディティブ法又はフルアディティブ法（以下、総称してアディティブ法という）によって導電配線１２の配線パターンを形成する場合であっても、導電配線１２の端子接続部１２Ａ或いは端子接続部１２Ａの少なくとも半導体チップの入出力端子が接続される箇所において、導電配線１２の厚さを均一にすることができる。すなわち、アディティブ法で導電配線１２1，１２2を形成した場合には、導電配線１２1において配線引き回し部１２Ｂの厚さと端子接続部１２Ａの厚さが異なることになり、端子接続部１２Ａにおいては導電配線１２1，１２2の厚さが等しくなる。これによって、フレキシブル配線基板１０の導電配線１２と半導体チップの入出力端子とを異方性導電膜を介して熱圧着により接続する際に、端子接続部１２において隣接する導電配線１２に問題となるような段差が形成されることがなくなり、段差による圧着不良が生じることがない。 According to such an embodiment, even when the wiring pattern of the conductive wiring 12 is formed by the semi-additive method or the full additive method (hereinafter collectively referred to as additive method), the terminal connection portion 12A of the conductive wiring 12 or The thickness of the conductive wiring 12 can be made uniform at least at the location where the input / output terminals of the semiconductor chip are connected in the terminal connection portion 12A. That is, when forming a conductive wiring 12 1, 12 2 in the additive method, the thickness and the thickness of the terminal connecting portion 12A of the wire routing portion 12B in the conductive wires 12 1 becomes different, the pin connection portion 12A The conductive wirings 12 1 and 12 2 are equal in thickness. As a result, when the conductive wiring 12 of the flexible wiring board 10 and the input / output terminals of the semiconductor chip are connected by thermocompression bonding via the anisotropic conductive film, there is a problem with the conductive wiring 12 adjacent in the terminal connection portion 12. Such a step is not formed, and a crimping failure due to the step does not occur.

また、端子接続部１２Ａにおける有効範囲（絶縁膜１３が施されていない範囲で半導体チップの入出力端子を接続するのに有効な範囲）の長さＬを熱圧着領域Ｈの幅ＬＨより長くして、熱圧着領域Ｈから絶縁膜１３の端までの間に余裕ができるようにすることで、導電配線１２１において配線引き回し部１２Ｂと端子接続部１２Ａの厚さが異なる場合にも、この厚さの差が熱圧着領域Ｈに影響することが無く、少なくとも熱圧着領域Ｈ内で導電配線１２の厚さを均一にすることができる。 The effective range in the terminal connecting portion 12A of the (valid range to connect the input and output terminals of the semiconductor chip to the extent that no insulating film 13 is subjected) a length L longer than the width L H of the heat crimping zone H to, by allowing a margin between the thermocompression bonding region H to the end of the insulating film 13, even if the thickness of the wire routing portion 12B and the terminal connecting portion 12A in the conductive wires 12 1 are different, the The difference in thickness does not affect the thermocompression bonding region H, and the thickness of the conductive wiring 12 can be made uniform at least in the thermocompression bonding region H.

本発明の実施形態に係るフレキシブル配線基板１０を製造するには、従来技術と同様に、配線基板１１上にアディティブ法によって導電配線１２を形成することができる。すなわち、例えば図１に示す各工程で、フォトレジスト材等を用いたマスクパターン１０２によって導電配線１２の配線パターンを形成する際に、端子接続部１２Ａにおける少なくとも半導体チップの入出力端子が接続される箇所で、少なくとも一つの半導体チップに接続される導電配線１２の線幅がほぼ等しくなるように配線パターンを形成する点が異なるだけで、その他の工程は従来技術と同様に製造することができる。   In order to manufacture the flexible wiring board 10 according to the embodiment of the present invention, the conductive wiring 12 can be formed on the wiring board 11 by the additive method, as in the prior art. That is, for example, at the time of forming the wiring pattern of the conductive wiring 12 by the mask pattern 102 using a photoresist material or the like in each step shown in FIG. 1, at least the input / output terminals of the semiconductor chip in the terminal connection portion 12A are connected. Other processes can be manufactured in the same manner as in the prior art, except that the wiring pattern is formed so that the line widths of the conductive wirings 12 connected to at least one semiconductor chip are substantially equal.

これによって、電解メッキ法によって被着されることで形成される導電配線１２の厚さを線幅が等しく形成された箇所で均一にすることができ、前述したように、半導体チップの入出力端子との圧着不良が生じないフレキシブル配線基板１０を得ることができる。   Thereby, the thickness of the conductive wiring 12 formed by being deposited by the electrolytic plating method can be made uniform at the portions where the line widths are equally formed. As described above, the input / output terminals of the semiconductor chip Thus, the flexible wiring board 10 that does not cause poor crimping can be obtained.

図４は本発明の実施形態に係るフレキシブル配線基板１０の他の例を示したものである。この例では、導電配線１２において３種類の線幅Ｗ１，Ｗ２，Ｗ３を有する配線引き回し部１２Ｂを備えた例である。この例においても、端子接続部１２Ａにおいては、少なくとも一つの半導体チップに接続される導電配線１２の線幅を等しく形成しており（Ｗ１ａ＝Ｗ３ａ＝Ｗ２）、図３の例と同様に、アディティブ法によって導電配線１２の配線パターンを形成する場合であっても、端子接続部１２Ａでは導電配線１２の厚さが均一になり、半導体チップとの接続に際して圧着不良のない接続を行うことができる。   FIG. 4 shows another example of the flexible wiring board 10 according to the embodiment of the present invention. In this example, the conductive wiring 12 is provided with a wiring routing portion 12B having three types of line widths W1, W2, and W3. Also in this example, in the terminal connection portion 12A, the conductive wirings 12 connected to at least one semiconductor chip have the same line width (W1a = W3a = W2), and as in the example of FIG. Even when the wiring pattern of the conductive wiring 12 is formed by the method, the thickness of the conductive wiring 12 becomes uniform in the terminal connection portion 12A, and a connection with no crimping failure can be performed when connecting to the semiconductor chip.

図５及び図６は、図３に示すフレキシブル配線基板１０に半導体チップを実装した半導体チップ実装フレキシブル配線基板（ＣＯＦ）及びこれを形成する半導体チップ実装方法を説明する説明図である（図５は、図３（ａ）に半導体チップを実装した場合のＸ１−Ｘ２断面図であり、図６は、同じく図３（ａ）に半導体チップを実装した場合のＹ１−Ｙ２断面図である）。図示の例では、半導体チップ２０の入出力端子２１ａ，２１ｂが異方性導電膜（ＡＣＦ）３０を介して導電配線１２の端子接続部１２Ａに熱圧着によって接続されている。   5 and 6 are explanatory views for explaining a semiconductor chip mounting flexible wiring board (COF) in which a semiconductor chip is mounted on the flexible wiring board 10 shown in FIG. 3 and a semiconductor chip mounting method for forming the same (FIG. 5). 3A is a cross-sectional view taken along the line X1-X2 when the semiconductor chip is mounted, and FIG. 6 is a cross-sectional view taken along the line Y1-Y2 when the semiconductor chip is also mounted in FIG. In the illustrated example, the input / output terminals 21a and 21b of the semiconductor chip 20 are connected to the terminal connection portion 12A of the conductive wiring 12 by thermocompression bonding via an anisotropic conductive film (ACF) 30.

図５に示すように、半導体チップ２０には、大きさ（幅）の異なる入出力端子２１ａ，２１ｂが設けられている。図示の例では、幅Ｂ１の入出力端子２１ａと幅Ｂ２（Ｂ１＞Ｂ２）の入出力端子２１ｂの２種類の入出力端子が設けられている。これに対して、幅広の入出力端子２１ａには幅広の線幅Ｗ１の配線引き回し部１２Ｂを有する導電配線１２１が対応し、比較的幅の狭い入出力端子２１ｂには狭い線幅Ｗ２の配線引き回し部１２Ｂの導電配線１２２が対応して、半導体チップ２０の入出力端子２１ａ，２１ｂと導電配線１２（１２１，１２２）の電気的な接続がなされている。 As shown in FIG. 5, the semiconductor chip 20 is provided with input / output terminals 21a and 21b having different sizes (widths). In the illustrated example, there are provided two types of input / output terminals, an input / output terminal 21a having a width B1 and an input / output terminal 21b having a width B2 (B1> B2). In contrast, the wide input and output terminals 21a corresponding conductive wire 121 having a wire routing portion 12B of the wide line width W1, wiring narrow line width W2 is relatively narrow width of the input and output terminals 21b corresponding conductive wire 12 and second lead portions 12B are input and output terminals 21a of the semiconductor chip 20, the electrical connection 21b and the conductive wires 12 (12 1, 12 2) have been made.

また、図６に示すように、配線基板１１に対して半導体チップ２０を実装する際には、前述したように、異方性導電膜３０が熱圧着によって固化している領域を絶縁膜１３の端からマージンＭだけ離しており、これによって、導電配線１２１の厚さが配線引き回し部１２Ａの厚さｔBから端子接続部１２Ｂの厚さｔAに変わる変移領域に熱圧着領域Ｈが関わらないようにしている。 Further, as illustrated in FIG 6, when mounting the semiconductor chip 20 to the wiring substrate 11, as described above, the insulating regions anisotropic conductive film 30 is solidified by thermocompression film 13 Thus, the thermocompression bonding region H is related to the transition region where the thickness of the conductive wiring 121 changes from the thickness t B of the wiring routing portion 12A to the thickness t A of the terminal connection portion 12B. I am trying not to.

そして、このような導電配線１２の端子接続部１２Ａに対して異方性導電膜３０を介して半導体チップ２０の入出力端子２１ａ，２１ｂを接続することで、段差のない均一な厚さを有する端子接続部１２Ａに対して入出力端子２１ａ，２１ｂを当接して圧力Ｐを印加した熱圧着を行うことができるようになり、圧着不良の生じない接続が可能になる。   Then, by connecting the input / output terminals 21a and 21b of the semiconductor chip 20 to the terminal connection portion 12A of the conductive wiring 12 via the anisotropic conductive film 30, it has a uniform thickness without a step. It becomes possible to perform thermocompression bonding in which the input / output terminals 21a and 21b are brought into contact with the terminal connection portion 12A and pressure P is applied, and connection without occurrence of defective crimping is possible.

なお、前述した実施形態では、導電配線１２と半導体チップ２０の入出力端子２１ａ，２１ｂとの電気的な接続を、異方性導電膜３０を介在させた熱圧着によって行う例を示したが、本発明の実施形態はこれに限らず、例えば、共晶接合エポキシダイボンディング，金属接合等の他の接合によって実施することも可能である。   In the above-described embodiment, an example in which the electrical connection between the conductive wiring 12 and the input / output terminals 21a and 21b of the semiconductor chip 20 is performed by thermocompression bonding with the anisotropic conductive film 30 is shown. The embodiment of the present invention is not limited to this, and can be implemented by other bonding such as eutectic bonding epoxy die bonding and metal bonding.

図７は、前述した実施形態に係る半導体チップ実装フレキシブル配線基板を搭載した電子機器の一例である表示装置を示す平面図である。ここでは、フレキシブル配線基板１０に半導体チップ２０を実装した半導体チップ実装フレキシブル配線基板（ＣＯＦ）を、有機ＥＬ表示装置、液晶表示装置（ＬＣＤ）、電界放射表示装置（ＦＥＤ）、プラズマディスプレイ装置（ＰＤＰ）等のフラットパネル型表示装置４０に接続した一例を示している。この半導体チップ実装フレキシブル配線基板は、表示装置４０の一辺に形成された引き出し電極４０Ａに接続することができるし、また、ＰＷＢ（硬質基板）５０等の他の回路部品に接続することができる。   FIG. 7 is a plan view showing a display device which is an example of an electronic device on which the semiconductor chip mounting flexible wiring board according to the above-described embodiment is mounted. Here, a semiconductor chip mounting flexible wiring substrate (COF) in which the semiconductor chip 20 is mounted on the flexible wiring substrate 10 is used as an organic EL display device, a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP). ) Etc., an example of connection to a flat panel type display device 40 is shown. This semiconductor chip mounting flexible wiring board can be connected to an extraction electrode 40A formed on one side of the display device 40, and can be connected to other circuit components such as a PWB (hard substrate) 50.

このような実施形態の半導体チップ実装フレキシブル配線基板を搭載した表示装置によると、ＣＯＦにおいて半導体チップの入出力端子の大きさに合致した配線引き回し部１２Ｂを有するフレキシブル配線基板の導電配線１２を採用して、各入出力端子と導電配線１２を高精度に接続することができるので、設定したばらつきのない駆動電流を表示装置に供給することが可能になる。これによると、特に、駆動電流の大小が直接表示性能に直接影響を及ぼす有機ＥＬ表示装置において良好な表示性能を得ることができる。   According to the display device on which the semiconductor chip mounting flexible wiring board of the embodiment is mounted, the conductive wiring 12 of the flexible wiring board having the wiring routing portion 12B that matches the size of the input / output terminals of the semiconductor chip in the COF is adopted. Thus, since each input / output terminal and the conductive wiring 12 can be connected with high accuracy, it is possible to supply a set drive current without variation to the display device. According to this, particularly in an organic EL display device in which the magnitude of the drive current directly affects the display performance, good display performance can be obtained.

以上説明したように、本発明の実施形態によると、半導体チップにおける異なる大きさの入出力端子に対応して、適正な線幅を有する配線引き回し部を有する導電配線が形成されたフレキシブル配線基板においても、特殊な加工や製法を採用することなく、単に導電配線のパターンを変更するだけで、端子接続部における導電配線の厚さを均一化することができ、これによって、フレキシブル配線基板の導電配線と接続対象の入出力端子間に生じる接続不良を解消することができる。   As described above, according to the embodiment of the present invention, in the flexible wiring board in which the conductive wiring having the wiring routing portion having the appropriate line width is formed corresponding to the input / output terminals of different sizes in the semiconductor chip. However, the thickness of the conductive wiring at the terminal connection can be made uniform by simply changing the pattern of the conductive wiring without adopting special processing or manufacturing methods. And poor connection between the input / output terminals to be connected can be eliminated.

すなわち、異なる大きさの入出力端子を有する半導体チップに対して、これに応じた導電配線の配線パターンを形成する際にも、接続不良が無く精度の高いＣＯＦを得ることができる。また、これによって、適正な配線抵抗を確保して駆動電流の適正化が可能になり、電子機器、特に駆動電流が直接表示性能に影響を及ぼす有機ＥＬ表示装置において、良好な表示性能を確保することができる。   That is, when a wiring pattern of conductive wiring corresponding to a semiconductor chip having input / output terminals of different sizes is formed, a highly accurate COF can be obtained without connection failure. In addition, this makes it possible to ensure appropriate wiring resistance and optimize drive current, and to ensure good display performance in electronic devices, particularly organic EL display devices in which drive current directly affects display performance. be able to.

従来技術（フレキシブル配線基板のパターン形成技術）の説明図である。It is explanatory drawing of a prior art (pattern formation technique of a flexible wiring board). 従来技術の課題を説明する説明図である。It is explanatory drawing explaining the subject of a prior art. 本発明の実施形態に係るフレキシブル配線基板を示す説明図である。It is explanatory drawing which shows the flexible wiring board which concerns on embodiment of this invention. 本発明の実施形態に係るフレキシブル配線基板の他の例を示す説明図である。It is explanatory drawing which shows the other example of the flexible wiring board which concerns on embodiment of this invention. 本発明の実施形態に係る半導体チップ実装フレキシブル配線基板、半導体チップ実装方法を示す説明図である。It is explanatory drawing which shows the semiconductor chip mounting flexible wiring board which concerns on embodiment of this invention, and a semiconductor chip mounting method. 本発明の実施形態に係る半導体チップ実装フレキシブル配線基板、半導体チップ実装方法を示す説明図である。It is explanatory drawing which shows the semiconductor chip mounting flexible wiring board which concerns on embodiment of this invention, and a semiconductor chip mounting method. 本発明の実施形態に係る半導体チップ実装フレキシブル配線基板を搭載した電子機器の一例である表示装置を示す平面図である。It is a top view which shows the display apparatus which is an example of the electronic device carrying the semiconductor chip mounting flexible wiring board which concerns on embodiment of this invention.

符号の説明Explanation of symbols

１０ フレキシブル配線基板
１１ 配線基板
１２，１２１，１２２ 導電配線
１２Ａ 端子接続部
１２Ｂ 配線引き回し部
１３ 絶縁膜
２０ 半導体チップ
２１ａ，２１ｂ 入出力端子
３０ 異方性導電膜
４０ 表示装置
４０Ａ 引き出し電極
５０ ＰＷＢ
Ｈ 熱圧着領域 10 flexible wiring board 11 wiring board 12, 12 1, 12 2 conductive wires 12A terminal connecting portion 12B wire routing unit 13 insulating film 20 semiconductor chips 21a, 21b output terminal 30 the anisotropic conductive film 40 display device 40A extraction electrode 50 PWB
H Thermocompression bonding area

Claims (3)

絶縁膜で覆われて線幅の異なる配線引き回し部と、半導体チップの入出力端子が電気的に接続され、絶縁膜で覆われていない端子接続部とを有する複数の導電配線を配線基板上に備えたフレキシブル配線基板であって、
前記端子接続部における少なくとも前記入出力端子が接続される箇所で、少なくとも一つの半導体チップに接続される導電配線の線幅が均一化され、
前記導電配線は、電解メッキを用いたアディティブ法によって形成されることにより配線の幅に基づいた厚さを有し、前記配線引き回し部の厚さと前記端子接続部の厚さが異なり、前記配線引き回し部の厚さから前記端子接続部の厚さに傾斜をもって変わる変移領域を有するものを含み、
前記端子接続部における絶縁膜が施されていない範囲で前記入出力端子を接続するのに有効な範囲である有効範囲の長さは、前記入出力端子が異方性導電膜を介して熱圧着される熱圧着領域の幅より長い
ことを特徴とするフレキシブル配線基板。 A plurality of conductive wirings having a wiring routing portion covered with an insulating film and having different line widths and a terminal connection portion where the input / output terminals of the semiconductor chip are electrically connected and not covered with the insulating film are formed on the wiring substrate. A flexible wiring board comprising:
The line width of the conductive wiring connected to at least one semiconductor chip is made uniform at a location where at least the input / output terminal is connected in the terminal connection portion,
The conductive wiring is formed by an additive method using electrolytic plating, and has a thickness based on the width of the wiring. The thickness of the wiring routing portion is different from the thickness of the terminal connection portion, and the wiring routing is performed. Including a transition region that changes with a slope from the thickness of the portion to the thickness of the terminal connection portion,
The length of the effective range, which is an effective range for connecting the input / output terminals in the range where the insulating film is not applied in the terminal connection portion, is that the input / output terminals are thermocompression-bonded via an anisotropic conductive film. A flexible wiring board characterized in that it is longer than the width of the thermocompression bonding area. 配線基板上の導電配線に半導体チップの入出力端子を接続した半導体チップ実装フレキシブル配線基板であって、
前記半導体チップは大きさの異なる入出力端子を備え、
前記導電配線は、絶縁膜で覆われて前記入出力端子の大きさに応じた線幅の配線引き回し部を有すると共に、前記入出力端子が電気的に接続される絶縁膜で覆われていない端子接続部を有し、
前記端子接続部における少なくとも前記入出力端子が電気的に接続された箇所で、少なくとも一つの半導体チップに接続される導電配線の線幅が均一化され、
前記入出力端子と前記端子接続部は異方性導電膜を介して熱圧着することによって電気的に接続され、
前記導電配線は、電解メッキを用いたアディティブ法によって形成されることにより配線の幅に基づいた厚さを有し、前記配線引き回し部の厚さと前記端子接続部の厚さが異なり、前記配線引き回し部の厚さから前記端子接続部の厚さに傾斜をもって変わる変移領域を有するものを含み、
前記端子接続部において、前記異方性導電膜が固化している領域の幅より絶縁膜が施されていない範囲の幅が長い
ことを特徴とする半導体チップ実装フレキシブル配線基板。 A semiconductor chip mounting flexible wiring board in which the input / output terminals of the semiconductor chip are connected to the conductive wiring on the wiring board,
The semiconductor chip includes input / output terminals of different sizes,
The conductive wiring is covered with an insulating film and has a wiring lead portion having a line width corresponding to the size of the input / output terminal, and is not covered with an insulating film to which the input / output terminal is electrically connected. Having a connection,
At the place where at least the input / output terminals are electrically connected in the terminal connection portion, the line width of the conductive wiring connected to at least one semiconductor chip is made uniform,
The input / output terminal and the terminal connection portion are electrically connected by thermocompression bonding through an anisotropic conductive film,
The conductive wiring is formed by an additive method using electrolytic plating, and has a thickness based on the width of the wiring. The thickness of the wiring routing portion is different from the thickness of the terminal connection portion, and the wiring routing is performed. Including a transition region that changes with a slope from the thickness of the portion to the thickness of the terminal connection portion,
In the terminal connection portion, the width of the area where the insulating film is not applied is longer than the width of the area where the anisotropic conductive film is solidified. 請求項２に記載された半導体チップ実装フレキシブル配線基板を搭載した電子機器。 An electronic device on which the semiconductor chip mounting flexible wiring board according to claim 2 is mounted.
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