JP4410188B2 - 半導体記憶装置のデータ書き込み方法 - Google Patents
半導体記憶装置のデータ書き込み方法 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
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Description
前記第2のメモリセルに書かれるべきデータが第1のしきい値電圧状態である場合に、前記第1のメモリセルのデータ書き込み時に、前記所望のしきい値電圧に等しい第1の書き込みベリファイ電圧を用い、
前記第2のメモリセルに書かれるべきデータが第1のしきい値電圧より高い第2のしきい値電圧状態である場合に、前記第1のメモリセルのデータ書き込み時に、前記所望のしきい値電圧より低い第2の書き込みベリファイ電圧を用いる。
第1のワード線に沿って配列された少なくとも第1及び第2のメモリセルに所望のしきい値電圧のデータを書き込むための書き込み電圧を印加し、
第1のワード線に続いて選択される隣接する第2のワード線により選択される、第1のメモリセルに隣接する第3のメモリセルに書き込まれるべきデータがそのしきい値電圧をシフトさせないものである場合、第1のメモリセルに対して前記所望のしきい値電圧に等しい第1のベリファイ電圧を用いた第1の書き込みベリファイを行い、
前記第2のワード線により選択される、第2のメモリセルに隣接する第4のメモリセルに書き込まれるべきデータがそのしきい値電圧をシフトさせるものである場合、第2のメモリセルに対して前記所望のしきい値電圧より低い第2のベリファイ電圧を用いた第2の書き込みベリファイを行う。
第1の書き込み方式では、第1のワード線に沿って配列された第1のメモリセル群に選択的に所望のしきい値電圧より低いしきい値電圧状態を書き込む第1のデータ書き込み(予備的書き込み)を行い、その第1のデータ書き込みの後、第1のワード線に隣接する第2のワード線に沿って配列された第2のメモリセル群に選択的にデータを書き込む第2のデータ書き込みを行い、その第2のデータ書き込みの後、第1のメモリセル群に選択的に、第1の書き込みと同じデータパターンをもって所望のしきい値電圧状態を書き込む第3のデータ書き込み(仕上げ書き込み)を行う。
第2の書き込み方式は、第1の書き込み方式の変形である。即ち第2の書き込み方式では、連続する複数のワード線からなる書き込み領域について順次ワード線を選択して、それぞれのメモリセル群に所定のデータパターンで所望のしきい値電圧より低い第1のベリファイ電圧を用いた書き込みベリファイを伴ってデータ書き込み(予備的書き込み)を行う。
第3の書き込み方式では、隣接する第1及び第2のメモリセルの第1のメモリセルにデータを書き込む際に、後に書かれるべき第2のメモリセルのデータに応じて、そのしきい値電圧制御を行う。
ここまでに説明した書き込み方式は、メモリセルの初期データ状態がデータ“A”であって、2つのワード線に沿ったメモリセルに選択的にデータ“B”を書く場合を想定している。このような書き込みは、4値記憶方式にも用いられるが、基本的には2値記憶方式に適用される。
第5の書き込み方式として、先の第3の書き込み方式を4値記憶方式の上位ページ書き込みに適用した例を次に説明する。
ここまで説明した第1乃至第5の書き込み方式は、いずれも隣接ワード線のセル間干渉の影響を低減するものであった。これに対してこの発明の書き込み方法は、隣接ビット線のセル間干渉の影響を低減する方法としても有効である。
第7の書き込み方式として、ある着目するメモリセルについて、これを取り囲むように隣接する複数のメモリセルの影響を考慮に入れて、仕上げ書き込みを行う例を説明する。
Claims (2)
- しきい値電圧により決まるデータを不揮発に記憶するメモリセルを有する半導体記憶装置において、互いに隣接する第1及び第2のメモリセルに順次書き込みが行われる場合に、第1のメモリセルに所望のしきい値電圧のデータを書き込む方法であって、
前記第2のメモリセルに書かれるべきデータが第1のしきい値電圧状態である場合に、前記第1のメモリセルのデータ書き込み時に、前記所望のしきい値電圧に等しい第1の書き込みベリファイ電圧を用い、
前記第2のメモリセルに書かれるべきデータが第1のしきい値電圧より高い第2のしきい値電圧状態である場合に、前記第1のメモリセルのデータ書き込み時に、前記所望のしきい値電圧より低い第2の書き込みベリファイ電圧を用いる
ことを特徴とする半導体記憶装置のデータ書き込み方法。 - 互いに交差して配列されたワード線とビット線、及びそれらの各交差部に配置された電気的書き換え可能な不揮発性メモリセルを有する半導体記憶装置のデータ書き込み方法であって、
第1のワード線に沿って配列された少なくとも第1及び第2のメモリセルに所望のしきい値電圧のデータを書き込むための書き込み電圧を印加し、
第1のワード線に続いて選択される隣接する第2のワード線により選択される、第1のメモリセルに隣接する第3のメモリセルに書き込まれるべきデータがそのしきい値電圧をシフトさせないものである場合、第1のメモリセルに対して前記所望のしきい値電圧に等しい第1のベリファイ電圧を用いた第1の書き込みベリファイを行い、
前記第2のワード線により選択される、第2のメモリセルに隣接する第4のメモリセルに書き込まれるべきデータがそのしきい値電圧をシフトさせるものである場合、第2のメモリセルに対して前記所望のしきい値電圧より低い第2のベリファイ電圧を用いた第2の書き込みベリファイを行う
ことを特徴とする半導体記憶装置のデータ書き込み方法。
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Families Citing this family (183)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4410188B2 (ja) | 2004-11-12 | 2010-02-03 | 株式会社東芝 | 半導体記憶装置のデータ書き込み方法 |
KR100669351B1 (ko) | 2005-07-29 | 2007-01-16 | 삼성전자주식회사 | 멀티 레벨 셀 플래시 메모리의 프로그램 방법 및 장치 |
JP4734110B2 (ja) | 2005-12-14 | 2011-07-27 | 株式会社東芝 | 不揮発性半導体記憶装置 |
WO2007079124A1 (en) * | 2005-12-29 | 2007-07-12 | Sandisk Corporation | Alternate row-based reading and writing for non-volatile memory |
KR100673025B1 (ko) * | 2006-01-24 | 2007-01-24 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
KR100673026B1 (ko) * | 2006-01-24 | 2007-01-24 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
KR100841336B1 (ko) * | 2006-01-24 | 2008-06-26 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리를 구비한 메모리 시스템 |
US7499326B2 (en) * | 2006-04-12 | 2009-03-03 | Sandisk Corporation | Apparatus for reducing the impact of program disturb |
US7426137B2 (en) * | 2006-04-12 | 2008-09-16 | Sandisk Corporation | Apparatus for reducing the impact of program disturb during read |
US7515463B2 (en) * | 2006-04-12 | 2009-04-07 | Sandisk Corporation | Reducing the impact of program disturb during read |
WO2007126665A1 (en) * | 2006-04-12 | 2007-11-08 | Sandisk Corporation | Reducing the impact of program disturb during read |
KR101012131B1 (ko) * | 2006-04-12 | 2011-02-07 | 샌디스크 코포레이션 | 프로그램 혼란의 영향을 감소시키는 방법 |
US7436713B2 (en) * | 2006-04-12 | 2008-10-14 | Sandisk Corporation | Reducing the impact of program disturb |
US7917685B2 (en) * | 2006-05-04 | 2011-03-29 | Micron Technology, Inc. | Method for reading a multilevel cell in a non-volatile memory device |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
WO2007132457A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
WO2007132452A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies | Reducing programming error in memory devices |
US7952922B2 (en) * | 2006-06-06 | 2011-05-31 | Micron Technology, Inc. | Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect |
KR100854970B1 (ko) | 2007-01-08 | 2008-08-28 | 삼성전자주식회사 | 멀티 레벨 셀 플래시 메모리 장치 및 그것의 프로그램 방법 |
EP2030205B1 (en) * | 2006-06-22 | 2011-07-06 | SanDisk Corporation | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
US7894269B2 (en) * | 2006-07-20 | 2011-02-22 | Sandisk Corporation | Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells |
US7885119B2 (en) * | 2006-07-20 | 2011-02-08 | Sandisk Corporation | Compensating for coupling during programming |
ATE472803T1 (de) * | 2006-07-20 | 2010-07-15 | Sandisk Corp | Floating-gate-speicher mit kopplungskompensation während der programmierung |
KR100919156B1 (ko) * | 2006-08-24 | 2009-09-28 | 삼성전자주식회사 | 멀티-비트 플래시 메모리 장치 및 그것의 프로그램 방법 |
WO2008026203A2 (en) | 2006-08-27 | 2008-03-06 | Anobit Technologies | Estimation of non-linear distortion in memory devices |
KR100805840B1 (ko) | 2006-09-01 | 2008-02-21 | 삼성전자주식회사 | 캐시를 이용한 플래시 메모리 장치 및 그것의 프로그램방법 |
JP2008103675A (ja) * | 2006-09-22 | 2008-05-01 | Toshiba Corp | 半導体集積回路 |
JP2008090451A (ja) | 2006-09-29 | 2008-04-17 | Toshiba Corp | 記憶装置 |
US7701770B2 (en) * | 2006-09-29 | 2010-04-20 | Hynix Semiconductor Inc. | Flash memory device and program method thereof |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
ITTO20060931A1 (it) * | 2006-12-29 | 2008-06-30 | Intel Corp | Sistemi e metodi per ridurre l'interferenza fra celle di memoria |
US7619919B2 (en) * | 2007-01-12 | 2009-11-17 | Marvell World Trade Ltd. | Multi-level memory |
KR100885783B1 (ko) * | 2007-01-23 | 2009-02-26 | 주식회사 하이닉스반도체 | 플래시 메모리 장치 및 동작 방법 |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
JP4498370B2 (ja) * | 2007-02-14 | 2010-07-07 | 株式会社東芝 | データ書き込み方法 |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
KR100816220B1 (ko) * | 2007-03-14 | 2008-03-21 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치의 언더 프로그램 셀 검출 방법 및그를 이용한 프로그램 방법 |
JP4435200B2 (ja) * | 2007-04-03 | 2010-03-17 | 株式会社東芝 | 半導体記憶装置のデータ書き込み方法 |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
US7719901B2 (en) * | 2007-06-05 | 2010-05-18 | Micron Technology, Inc. | Solid state memory utilizing analog communication of data values |
US8006166B2 (en) | 2007-06-12 | 2011-08-23 | Micron Technology, Inc. | Programming error correction code into a solid state memory device with varying bits per cell |
US7936599B2 (en) * | 2007-06-15 | 2011-05-03 | Micron Technology, Inc. | Coarse and fine programming in a solid state memory |
US7567455B2 (en) | 2007-06-19 | 2009-07-28 | Micron Technology, Inc. | Method and system for programming non-volatile memory cells based on programming of proximate memory cells |
KR101303177B1 (ko) * | 2007-06-22 | 2013-09-17 | 삼성전자주식회사 | 불휘발성 메모리 소자 및 그 동작 방법 |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
KR100908560B1 (ko) * | 2007-08-06 | 2009-07-21 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 프로그램 방법 |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
JP4660520B2 (ja) | 2007-09-03 | 2011-03-30 | 株式会社東芝 | 不揮発性半導体記憶装置およびその駆動方法 |
US7652929B2 (en) * | 2007-09-17 | 2010-01-26 | Sandisk Corporation | Non-volatile memory and method for biasing adjacent word line for verify during programming |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US7675772B2 (en) * | 2007-10-26 | 2010-03-09 | Micron Technology, Inc. | Multilevel memory cell operation |
JP5196965B2 (ja) | 2007-11-12 | 2013-05-15 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR101509836B1 (ko) | 2007-11-13 | 2015-04-06 | 애플 인크. | 멀티 유닛 메모리 디바이스에서의 메모리 유닛의 최적화된 선택 |
ITRM20070621A1 (it) * | 2007-11-28 | 2009-05-29 | Micron Technology Inc | Compensazione dell'effetto della configurazione a ritroso in un dispositivo di memorizzazione. |
JP5010444B2 (ja) * | 2007-11-29 | 2012-08-29 | 株式会社東芝 | 半導体記憶装置およびその駆動方法 |
JP2009134799A (ja) | 2007-11-29 | 2009-06-18 | Toshiba Corp | メモリシステム |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
JP5150245B2 (ja) | 2007-12-27 | 2013-02-20 | 株式会社東芝 | 半導体記憶装置 |
US7916544B2 (en) * | 2008-01-25 | 2011-03-29 | Micron Technology, Inc. | Random telegraph signal noise reduction scheme for semiconductor memories |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
KR101434403B1 (ko) * | 2008-05-15 | 2014-08-27 | 삼성전자주식회사 | 플래시 메모리 장치, 그것의 프로그램 방법, 그리고 그것을포함하는 메모리 시스템 |
WO2010002943A1 (en) * | 2008-07-01 | 2010-01-07 | Lsi Corporation | Methods and apparatus for interfacing between a flash memory controller and a flash memory array |
WO2010002945A1 (en) * | 2008-07-01 | 2010-01-07 | Lsi Corporation | Methods and apparatus for intercell interference mitigation using modulation coding |
JP5496198B2 (ja) * | 2008-07-22 | 2014-05-21 | エルエスアイ コーポレーション | フラッシュ・メモリにおいて信号レベルごとに複数のプログラム値をプログラミングするための方法および装置 |
KR101069004B1 (ko) * | 2008-08-01 | 2011-09-29 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 프로그램 방법 |
KR101528167B1 (ko) * | 2008-08-01 | 2015-06-12 | 삼성전자주식회사 | 메모리 장치 및 메모리 데이터 판정 방법 |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8130552B2 (en) * | 2008-09-11 | 2012-03-06 | Sandisk Technologies Inc. | Multi-pass programming for memory with reduced data storage requirement |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US7983078B2 (en) * | 2008-09-24 | 2011-07-19 | Sandisk Technologies Inc. | Data retention of last word line of non-volatile memory arrays |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
JP2010123210A (ja) * | 2008-11-20 | 2010-06-03 | Toshiba Corp | 半導体記憶装置 |
JP2010123211A (ja) | 2008-11-20 | 2010-06-03 | Toshiba Corp | 半導体記憶装置の書き込み方法 |
JP5410737B2 (ja) * | 2008-11-25 | 2014-02-05 | 三星電子株式会社 | 不揮発性半導体記憶装置 |
US8094495B2 (en) * | 2008-11-25 | 2012-01-10 | Samsung Electronics Co., Ltd. | Nonvolatile memory device |
KR101642465B1 (ko) * | 2008-12-12 | 2016-07-25 | 삼성전자주식회사 | 불휘발성 메모리 장치의 액세스 방법 |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8397131B1 (en) | 2008-12-31 | 2013-03-12 | Apple Inc. | Efficient readout schemes for analog memory cell devices |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
KR101534274B1 (ko) * | 2009-02-25 | 2015-07-06 | 삼성전자주식회사 | 메모리 시스템 및 그것의 프로그램 방법 |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
JP2010225220A (ja) * | 2009-03-23 | 2010-10-07 | Toshiba Corp | 不揮発性半導体記憶装置、及びそのデータ書き込み方法 |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
KR20100107609A (ko) * | 2009-03-26 | 2010-10-06 | 삼성전자주식회사 | 저항성 메모리 장치, 이를 포함하는 메모리 시스템 및 저항성 메모리 장치의 기입 방법 |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
JP5259481B2 (ja) * | 2009-04-14 | 2013-08-07 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR101572830B1 (ko) | 2009-06-22 | 2015-11-30 | 삼성전자주식회사 | 비휘발성 메모리 장치의 프로그램 방법, 비휘발성 메모리 장치 및 비휘발성 메모리 시스템 |
KR101530997B1 (ko) | 2009-06-23 | 2015-06-25 | 삼성전자주식회사 | 셀간 간섭을 집중시키는 불휘발성 메모리 장치의 프로그램 방법 |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8077515B2 (en) | 2009-08-25 | 2011-12-13 | Micron Technology, Inc. | Methods, devices, and systems for dealing with threshold voltage change in memory devices |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
US8248850B2 (en) * | 2010-01-28 | 2012-08-21 | Sandisk Technologies Inc. | Data recovery for non-volatile memory based on count of data state-specific fails |
JP2011159364A (ja) * | 2010-02-02 | 2011-08-18 | Toshiba Corp | 不揮発性半導体記憶装置および不揮発性半導体記憶装置の駆動方法 |
KR101620025B1 (ko) * | 2010-02-19 | 2016-05-24 | 삼성전자주식회사 | 데이터 저장 시스템 및 그것의 오픈 블록 관리 방법 |
US8355280B2 (en) | 2010-03-09 | 2013-01-15 | Samsung Electronics Co., Ltd. | Data storage system having multi-bit memory device and operating method thereof |
US8565020B2 (en) | 2010-04-14 | 2013-10-22 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8451664B2 (en) | 2010-05-12 | 2013-05-28 | Micron Technology, Inc. | Determining and using soft data in memory devices and systems |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8503233B2 (en) * | 2010-07-07 | 2013-08-06 | Skymedi Corporation | Method of twice programming a non-volatile flash memory with a sequence |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
JP2012027966A (ja) | 2010-07-20 | 2012-02-09 | Toshiba Corp | 不揮発性半導体記憶装置 |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8767459B1 (en) | 2010-07-31 | 2014-07-01 | Apple Inc. | Data storage in analog memory cells across word lines using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
JP5502773B2 (ja) * | 2011-02-01 | 2014-05-28 | 株式会社東芝 | 不揮発性半導体記憶装置 |
CN103119656A (zh) * | 2010-09-24 | 2013-05-22 | 株式会社东芝 | 非易失性半导体存储器件 |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
JP2012128816A (ja) * | 2010-12-17 | 2012-07-05 | Toshiba Corp | メモリシステム |
KR101734199B1 (ko) | 2010-12-29 | 2017-05-24 | 삼성전자주식회사 | 멀티-비트 메모리 장치를 포함한 데이터 저장 시스템 및 그것의 동작 방법 |
US9898361B2 (en) | 2011-01-04 | 2018-02-20 | Seagate Technology Llc | Multi-tier detection and decoding in flash memories |
JP5330421B2 (ja) * | 2011-02-01 | 2013-10-30 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US20120311262A1 (en) * | 2011-06-01 | 2012-12-06 | International Business Machines Corporation | Memory cell presetting for improved memory performance |
KR101785007B1 (ko) | 2011-06-14 | 2017-11-07 | 삼성전자주식회사 | 멀티-비트 메모리 장치를 포함한 데이터 저장 시스템 및 그것의 온-칩 버퍼 프로그램 방법 |
US8537623B2 (en) * | 2011-07-07 | 2013-09-17 | Micron Technology, Inc. | Devices and methods of programming memory cells |
US8775901B2 (en) | 2011-07-28 | 2014-07-08 | SanDisk Technologies, Inc. | Data recovery for defective word lines during programming of non-volatile memory arrays |
US8750042B2 (en) | 2011-07-28 | 2014-06-10 | Sandisk Technologies Inc. | Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures |
KR101818439B1 (ko) | 2011-09-22 | 2018-01-16 | 에스케이하이닉스 주식회사 | 메모리 및 메모리의 프로그램 방법 |
JP2012043530A (ja) * | 2011-10-24 | 2012-03-01 | Toshiba Corp | 不揮発性半導体記憶装置 |
TWI534810B (zh) | 2011-12-09 | 2016-05-21 | Toshiba Kk | Nonvolatile semiconductor memory device |
JP5674634B2 (ja) * | 2011-12-28 | 2015-02-25 | 株式会社東芝 | コントローラ、記憶装置およびプログラム |
US8730722B2 (en) * | 2012-03-02 | 2014-05-20 | Sandisk Technologies Inc. | Saving of data in cases of word-line to word-line short in memory arrays |
US9081664B2 (en) * | 2012-08-10 | 2015-07-14 | Kabushiki Kaisha Toshiba | Memory system capable of preventing data destruction |
KR102015906B1 (ko) * | 2012-11-12 | 2019-08-29 | 삼성전자주식회사 | 불휘발성 메모리 장치를 포함하는 메모리 시스템 및 그것의 읽기 방법 |
JP2014134843A (ja) | 2013-01-08 | 2014-07-24 | Toshiba Corp | メモリシステム |
JP2014175031A (ja) * | 2013-03-08 | 2014-09-22 | Toshiba Corp | 半導体記憶装置 |
CN110175088B (zh) | 2013-08-23 | 2022-11-11 | 慧荣科技股份有限公司 | 存取快闪存储器中储存单元的方法以及使用该方法的装置 |
CN107341071A (zh) * | 2013-08-23 | 2017-11-10 | 慧荣科技股份有限公司 | 存取快闪存储器中储存单元的方法以及使用该方法的装置 |
US9165683B2 (en) | 2013-09-23 | 2015-10-20 | Sandisk Technologies Inc. | Multi-word line erratic programming detection |
JP6151203B2 (ja) | 2014-03-04 | 2017-06-21 | 株式会社東芝 | 演算制御装置、それを備えたメモリシステム、および、情報処理装置 |
US9460809B2 (en) | 2014-07-10 | 2016-10-04 | Sandisk Technologies Llc | AC stress mode to screen out word line to word line shorts |
US9484086B2 (en) | 2014-07-10 | 2016-11-01 | Sandisk Technologies Llc | Determination of word line to local source line shorts |
US9443612B2 (en) | 2014-07-10 | 2016-09-13 | Sandisk Technologies Llc | Determination of bit line to low voltage signal shorts |
US9514835B2 (en) | 2014-07-10 | 2016-12-06 | Sandisk Technologies Llc | Determination of word line to word line shorts between adjacent blocks |
JP6240044B2 (ja) * | 2014-08-12 | 2017-11-29 | 東芝メモリ株式会社 | 不揮発性半導体記憶装置及びその動作方法 |
US9240249B1 (en) | 2014-09-02 | 2016-01-19 | Sandisk Technologies Inc. | AC stress methods to screen out bit line defects |
US9202593B1 (en) | 2014-09-02 | 2015-12-01 | Sandisk Technologies Inc. | Techniques for detecting broken word lines in non-volatile memories |
US9449694B2 (en) | 2014-09-04 | 2016-09-20 | Sandisk Technologies Llc | Non-volatile memory with multi-word line select for defect detection operations |
US9423961B2 (en) * | 2014-09-08 | 2016-08-23 | Apple Inc. | Method to enhance programming performance in multilevel NVM devices |
KR102246843B1 (ko) | 2015-01-15 | 2021-05-03 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 그것의 동작 방법 |
US9659666B2 (en) | 2015-08-31 | 2017-05-23 | Sandisk Technologies Llc | Dynamic memory recovery at the sub-block level |
KR102444238B1 (ko) * | 2016-02-26 | 2022-09-16 | 삼성전자주식회사 | 메모리 장치의 프로그램 방법 및 이를 적용하는 메모리 시스템 |
JP6502880B2 (ja) * | 2016-03-10 | 2019-04-17 | 東芝メモリ株式会社 | 半導体記憶装置 |
JP6684744B2 (ja) * | 2017-03-24 | 2020-04-22 | キオクシア株式会社 | メモリシステム、メモリコントローラ、およびメモリシステムの制御方法 |
US10734084B2 (en) | 2018-05-31 | 2020-08-04 | Western Digital Technologies, Inc. | Scheme to reduce read disturb for high read intensive blocks in non-volatile memory |
TWI690930B (zh) * | 2019-01-09 | 2020-04-11 | 力晶積成電子製造股份有限公司 | 補償非易失性記憶元件在編程時電荷流失與源極線偏置的方法 |
JP2020140747A (ja) * | 2019-02-27 | 2020-09-03 | キオクシア株式会社 | 半導体記憶装置 |
KR20210034274A (ko) | 2019-09-20 | 2021-03-30 | 삼성전자주식회사 | 비휘발성 메모리 장치의 구동 방법 및 이를 수행하는 비휘발성 메모리 장치 |
EP3891745B1 (en) * | 2019-10-12 | 2023-09-06 | Yangtze Memory Technologies Co., Ltd. | Method of programming memory device and related memory device |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
JP2023038769A (ja) * | 2021-09-07 | 2023-03-17 | キオクシア株式会社 | 半導体記憶装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6320785B1 (en) * | 1996-07-10 | 2001-11-20 | Hitachi, Ltd. | Nonvolatile semiconductor memory device and data writing method therefor |
JP3930074B2 (ja) | 1996-09-30 | 2007-06-13 | 株式会社ルネサステクノロジ | 半導体集積回路及びデータ処理システム |
JP4467815B2 (ja) * | 2001-02-26 | 2010-05-26 | 富士通マイクロエレクトロニクス株式会社 | 不揮発性半導体メモリの読み出し動作方法および不揮発性半導体メモリ |
JP2004023062A (ja) * | 2002-06-20 | 2004-01-22 | Nec Electronics Corp | 半導体装置とその製造方法 |
JP4181363B2 (ja) | 2002-08-29 | 2008-11-12 | スパンション エルエルシー | 不揮発性半導体記憶装置及びデータ書き込み方法 |
US6781877B2 (en) | 2002-09-06 | 2004-08-24 | Sandisk Corporation | Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells |
JP3935139B2 (ja) | 2002-11-29 | 2007-06-20 | 株式会社東芝 | 半導体記憶装置 |
US6657891B1 (en) * | 2002-11-29 | 2003-12-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device for storing multivalued data |
US6987695B2 (en) * | 2003-03-25 | 2006-01-17 | Promos Technologies Inc. | Writing data to nonvolatile memory |
JP3913704B2 (ja) | 2003-04-22 | 2007-05-09 | 株式会社東芝 | 不揮発性半導体記憶装置及びこれを用いた電子装置 |
JP2006031871A (ja) * | 2004-07-20 | 2006-02-02 | Toshiba Corp | 半導体記憶装置 |
JP4410188B2 (ja) | 2004-11-12 | 2010-02-03 | 株式会社東芝 | 半導体記憶装置のデータ書き込み方法 |
US7475187B2 (en) * | 2005-09-15 | 2009-01-06 | Infineon Technologies Ag | High-speed interface circuit for semiconductor memory chips and memory system including the same |
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2005
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Also Published As
Publication number | Publication date |
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US7593267B2 (en) | 2009-09-22 |
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US7257032B2 (en) | 2007-08-14 |
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