JP4305102B2 - COMPOSITE SUBSTRATE FOR SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - Google Patents

COMPOSITE SUBSTRATE FOR SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME Download PDF

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JP4305102B2
JP4305102B2 JP2003311910A JP2003311910A JP4305102B2 JP 4305102 B2 JP4305102 B2 JP 4305102B2 JP 2003311910 A JP2003311910 A JP 2003311910A JP 2003311910 A JP2003311910 A JP 2003311910A JP 4305102 B2 JP4305102 B2 JP 4305102B2
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wafer
light emitting
emitting element
forming
electrode
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JP2005079550A (en
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俊也 上村
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Toyoda Gosei Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Description

本発明は、半導体発光素子用複合基板及びその製造方法、並びに半導体発光素子の製造方法に関し、特に、フリップチップボンディング型半導体発光装置に適用される半導体発光素子の形成に好適な半導体発光素子用複合基板及びその製造方法、並びに半導体発光素子の製造方法に関する。   The present invention relates to a composite substrate for a semiconductor light-emitting element, a method for manufacturing the same, and a method for manufacturing a semiconductor light-emitting element. The present invention relates to a substrate, a manufacturing method thereof, and a manufacturing method of a semiconductor light emitting element.

ＧａＮ、ＡｌＧａＮ、ＧａＩｎＮ及びＡｌＧａＩｎＮ等のＧａＮ系化合物半導体を利用した青色発光の半導体発光装置において、一般に絶縁性のサファイアを基板とし、この基板に積層したＧａＮ系化合物半導体の表面側にｐ側及びｎ側の電極を形成し、これらの電極をマイクロバンプを介してサブマウント部材に接合する、フリップチップ型のものが知られている。   In a blue light emitting semiconductor light emitting device using a GaN compound semiconductor such as GaN, AlGaN, GaInN, and AlGaInN, an insulating sapphire is generally used as a substrate, and the p side and n are formed on the surface side of the GaN compound semiconductor laminated on the substrate. There is known a flip-chip type in which side electrodes are formed and these electrodes are joined to a submount member via micro bumps.

図８は、フリップチップボンディング型半導体発光装置に使用される半導体発光素子の従来例を示す図であり、（ａ）は半導体発光素子の断面説明図、（ｂ）は（ａ）のｂ−ｂ部における発光素子の底面説明図、（ｃ）はサブマウント部材の平面説明図である。半導体発光素子は、発光素子５０とサブマウント部材６０をバンプ５４、５５を介して接合されることにより構成されている。このバンプ５４、５５は、通常サブマウント側に予め形成され、スタッドバンプと呼ばれるワイヤーボンディング工法を応用した工法により形成される（例えば、特許文献１参照。）。   8A and 8B are diagrams showing a conventional example of a semiconductor light emitting element used in a flip-chip bonding type semiconductor light emitting device. FIG. 8A is a cross-sectional explanatory view of the semiconductor light emitting element, and FIG. The bottom explanatory drawing of the light emitting element in a part, (c) is a plane explanatory drawing of a submount member. The semiconductor light emitting element is configured by joining the light emitting element 50 and the submount member 60 via bumps 54 and 55. The bumps 54 and 55 are usually formed in advance on the submount side and formed by a method using a wire bonding method called a stud bump (see, for example, Patent Document 1).

発光ダイオード５１は、ＧａＮ系化合物半導体を利用した高輝度の青色発光のもので、サファイアを素材とした基板（図示せず）の表面に、たとえばＧａＮのｎ型層，ＧａＩｎＮの活性層及びＧａＮのｐ型層を積層したものである。そして、従来周知のように、ｐ型層の一部をエッチングしてｎ型層を露出させ、この露出したｎ型層の表面にｎ側電極５２を形成し、ｐ型層の表面にはｐ側電極５３を形成し、ｎ側電極５２をサブマウント部材６０の電極６２に、ｐ側電極５３をサブマウント部材６０の電極６３にそれぞれバンプ５４、５５を介して接合している。   The light-emitting diode 51 emits blue light with high brightness using a GaN-based compound semiconductor. For example, an n-type layer of GaN, an active layer of GaInN, and a GaN layer are formed on the surface of a substrate (not shown) made of sapphire. A p-type layer is laminated. Then, as is well known in the art, a part of the p-type layer is etched to expose the n-type layer, and the n-side electrode 52 is formed on the exposed surface of the n-type layer. The side electrode 53 is formed, and the n-side electrode 52 is joined to the electrode 62 of the submount member 60 and the p-side electrode 53 is joined to the electrode 63 of the submount member 60 via bumps 54 and 55, respectively.

サブマウント部材６０は、窒化アルミニウム基板（ＡｌＮ基板）６１に、Ｔｉ／Ｎｉ／Ａｕ（表面側）の３点からなる電極６２、６３を形成している。ＡｌＮ基板６１の底面には実装基板の電極に導通搭載される電極６４、６５を形成しており、電極６２と電極６４とはスルーホール６９を介して、また電極６３と電極６５とはスルーホール７０を介してそれぞれ電気的に導通させている。   In the submount member 60, electrodes 62 and 63 having three points of Ti / Ni / Au (surface side) are formed on an aluminum nitride substrate (AlN substrate) 61. Electrodes 64 and 65 are formed on the bottom surface of the AlN substrate 61 so as to be conductively mounted on the electrodes of the mounting substrate. The electrodes 62 and 64 are connected through the through holes 69, and the electrodes 63 and 65 are connected to the through holes. 70 are electrically connected to each other.

サブマウント部材６０は、底面の電極６４、６５を実装基板（図示せず）の配線パターン上に導通搭載される。このような導通構造によって、電源側と発光素子５０とが導通し、通電によって活性層からの青色発光が得られる。発光素子５０の活性層からの青色発光は透明のサファイアを利用した基板（図示せず）を抜けて上方に放出される。また、サブマウント部材６０は、サファイア基板とは反対方向に向かう光を効率よく反射し、発光素子の効率向上に寄与している。   In the submount member 60, electrodes 64 and 65 on the bottom surface are conductively mounted on a wiring pattern of a mounting substrate (not shown). With such a conduction structure, the power source side and the light emitting element 50 are conducted, and blue light emission from the active layer is obtained by energization. Blue light emission from the active layer of the light emitting element 50 is emitted upward through a substrate (not shown) using transparent sapphire. Further, the submount member 60 efficiently reflects light traveling in the opposite direction to the sapphire substrate, and contributes to improving the efficiency of the light emitting element.

上記のような半導体発光素子の製造に際しては、フリップチップ型発光素子とサブマウント部材を一個ずつ接合する方法が一般的であり、多量の素子について接合を行おうとすると位置決め等の手間が膨大なものとなって生産性の点で問題がある。一個ずつの接合に変えて、複数個をブロック化して接合する方法が提案されている（例えば、特許文献２参照）。
特開２００２−１１８１３７公報 特開平１１−３３０６２０号公報 In manufacturing the semiconductor light emitting device as described above, it is common to join the flip chip type light emitting device and the submount member one by one. There is a problem in terms of productivity. A method of joining a plurality of blocks in place of joining one by one has been proposed (for example, see Patent Document 2).
JP 2002-118137 A Japanese Patent Laid-Open No. 11-330620

しかし、特許文献２に記載された方法でも各ブロックを精度良く位置決めする必要があり、ブロックの数が大であると手間だけでなく複数のブロック間での均一な位置決め精度が要求されるため、依然として生産性の点で問題が残る。   However, even in the method described in Patent Document 2, it is necessary to position each block with high accuracy, and when the number of blocks is large, not only labor but also uniform positioning accuracy among a plurality of blocks is required. Problems still remain in terms of productivity.

従って、本発明の目的は、生産性を大幅に向上させることが可能な半導体発光素子用複合基板及びその製造方法、並びに半導体発光素子の製造方法を提供することにある。   Accordingly, an object of the present invention is to provide a composite substrate for a semiconductor light-emitting element, a method for manufacturing the same, and a method for manufacturing a semiconductor light-emitting element that can greatly improve productivity.

また、上記の目的を達成するため、本発明は、光透過性基板にＧａＮ系化合物半導体を成長させたウェハを形成する工程と、前記ウェハにｐ側電極及びｎ側電極を備え、前記ウェハのほぼ全面に亘り前記ｎ側電極及び前記ｐ側電極と電気的に導通した平面状の金属層を形成し、前記平面状の金属層の上にレジストを形成して選択的にバンプを形成し、前記レジスト及び表面に露出している部分の前記金属層を除去することにより、前記ｐ側電極と電気的に導通したバンプ及び前記ｎ側電極と電気的に導通したバンプを備えた複数の発光素子を前記ウェハのほぼ全面に亘り行列状に形成して発光素子側ウェハを得る工程と、前記ウェハの前記複数の発光素子に対応する複数のサブマウント部材を配置してサブマウント部材側ウェハを得る工程と、前記発光素子側ウェハと前記サブマウント部材側ウェハとを接合して前記サブマウント部材側ウェハの実装用電極と前記発光素子側ウェハの前記ｐ側電極及びｎ側電極とをスルーホールを介して導通させた複合基板を形成する工程と、前記複合基板を前記発光素子単位に分離する工程とを含むことを特徴とする半導体発光素子の製造方法を提供する。 In order to achieve the above object, the present invention includes a step of forming a wafer on which a GaN-based compound semiconductor is grown on a light-transmitting substrate, and the wafer includes a p-side electrode and an n-side electrode , Forming a planar metal layer electrically connected to the n-side electrode and the p-side electrode over substantially the entire surface, forming a resist on the planar metal layer and selectively forming bumps; A plurality of light emitting devices each including a bump electrically connected to the p-side electrode and a bump electrically connected to the n-side electrode by removing the resist and the metal layer exposed on the surface Forming a light emitting element side wafer by forming a plurality of submount members corresponding to the plurality of light emitting elements of the wafer to obtain a submount member side wafer. Process and The light emitting element side wafer and the submount member side wafer are joined, and the mounting electrode of the submount member side wafer is electrically connected to the p side electrode and the n side electrode of the light emitting element side wafer through a through hole. There is provided a method for manufacturing a semiconductor light emitting device, comprising a step of forming a composite substrate and a step of separating the composite substrate into light emitting device units.

さらに、上記の目的を達成するため、本発明は、光透過性基板にＧａＮ系化合物半導体を成長させたウェハを形成する工程と、前記ウェハにｐ側電極及びｎ側電極を備え、前記ウェハのほぼ全面に亘り前記ｎ側電極及び前記ｐ側電極と電気的に導通した平面状の金属層を形成し、前記平面状の金属層の上にレジストを形成して選択的にバンプを形成し、前記レジスト及び表面に露出している部分の前記金属層を除去することにより、前記ｐ側電極と電気的に導通したバンプ及び前記ｎ側電極と電気的に導通したバンプを備えた複数の発光素子を前記ウェハのほぼ全面に亘り行列状に形成して発光素子側ウェハを得る工程と、前記ウェハの前記複数の発光素子に対応する複数のサブマウント部材を配置してサブマウント部材側ウェハを得る工程と、前記発光素子側ウェハと前記サブマウント部材側ウェハとを接合して前記サブマウント部材側ウェハの実装用電極と前記発光素子側ウェハの前記ｐ側電極及びｎ側電極とをスルーホールを介して導通させた複合基板を形成する工程と、前記複合基板を前記発光素子単位に分離する工程とを含むことを特徴とする半導体発光素子の製造方法を提供する。 Furthermore, in order to achieve the above object, the present invention includes a step of forming a wafer on which a GaN-based compound semiconductor is grown on a light-transmitting substrate, and the wafer includes a p-side electrode and an n-side electrode , Forming a planar metal layer electrically connected to the n-side electrode and the p-side electrode over substantially the entire surface, forming a resist on the planar metal layer and selectively forming bumps; A plurality of light emitting devices each including a bump electrically connected to the p-side electrode and a bump electrically connected to the n-side electrode by removing the resist and the metal layer exposed on the surface Forming a light emitting element side wafer by forming a plurality of submount members corresponding to the plurality of light emitting elements of the wafer to obtain a submount member side wafer. Process The light emitting element side wafer and the submount member side wafer are bonded to each other, and the mounting electrode of the submount member side wafer and the p side electrode and the n side electrode of the light emitting element side wafer are connected through a through hole. There is provided a method for manufacturing a semiconductor light emitting device, comprising: forming a conductive composite substrate; and separating the composite substrate into light emitting device units.

本発明によれば、光透過性基板にＧａＮ系化合物半導体を成長させたウェハのほぼ全面に亘り発光素子単位が形成された発光素子側ウェハとサブマウント部材側ウェハを接合して半導体発光素子用複合基板を形成し、発光素子単位で切断するものであるため、発光素子の大量生産が可能となる。   According to the present invention, a light-emitting element side wafer in which a light-emitting element unit is formed over almost the entire surface of a wafer on which a GaN-based compound semiconductor is grown on a light-transmitting substrate is joined to a submount member side wafer. Since the composite substrate is formed and cut in units of light emitting elements, light emitting elements can be mass-produced.

本発明において、光透過性基板としてサファイア基板すると、優れた光透過性を実現できると共に、ＧａＮ系化合物半導体を容易に成長させることが可能となる。また、サブマウント部材側ウェハを窒化アルミニウム基板を用いて形成すると、優れた光の反射効率を実現でき、発光素子の発光効率を向上できる。   In the present invention, when a sapphire substrate is used as the light transmissive substrate, excellent light transmittance can be realized and a GaN-based compound semiconductor can be easily grown. Further, when the submount member side wafer is formed using an aluminum nitride substrate, excellent light reflection efficiency can be realized, and the light emission efficiency of the light emitting element can be improved.

以下に、本発明の実施の形態を図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は、本発明により得られる半導体発光素子の一実施の形態の説明図であり、（ａ）は半導体発光素子の断面説明図、（ｂ）は（ａ）のｂ−ｂ部における発光素子の底面説明図、（ｃ）はサブマウント部材の平面説明図である。半導体発光素子は、発光素子１とサブマウント部材１０とをバンプ６、７を介して接合することにより構成されているが、図８の従来例と異なる点は、バンプ６、７は金属層５を介してｎ側電極３及びｐ側電極４と接続されている点である。この金属層５が設けられていることにより、バンプ６、７を半導体発光素子側に電気めっきで一括して形成することができ、バンプ６、７の位置および形状を高い寸法精度とすることができる。   1A and 1B are explanatory views of an embodiment of a semiconductor light-emitting device obtained by the present invention, FIG. 1A is a cross-sectional explanatory view of the semiconductor light-emitting device, and FIG. (C) is a plane explanatory view of a submount member. The semiconductor light-emitting element is configured by joining the light-emitting element 1 and the submount member 10 via bumps 6 and 7, but the points different from the conventional example of FIG. It is a point connected to the n-side electrode 3 and the p-side electrode 4 through the. By providing the metal layer 5, the bumps 6 and 7 can be collectively formed on the semiconductor light emitting element side by electroplating, and the position and shape of the bumps 6 and 7 can have high dimensional accuracy. it can.

発光ダイオード２は、ＧａＮ系化合物半導体を利用した高輝度の青色発光のもので、この発光ダイオード２は、サファイアを素材とした基板（図示せず）の表面に、たとえばＧａＮのｎ型層，ＧａＩｎＮの活性層及びＧａＮのｐ型層を積層したものである。そして、ｐ型層の一部をエッチングしてｎ型層を露出させ、この露出したｎ型層の表面にｎ側電極３を形成し、ｐ型層の表面にはｐ側電極４を形成している。   The light emitting diode 2 emits blue light with high luminance using a GaN-based compound semiconductor. The light emitting diode 2 is formed on a surface of a substrate (not shown) made of sapphire, for example, an n-type layer of GaN, GaInN. The active layer and the p-type layer of GaN are stacked. Then, a part of the p-type layer is etched to expose the n-type layer, the n-side electrode 3 is formed on the surface of the exposed n-type layer, and the p-side electrode 4 is formed on the surface of the p-type layer. ing.

サブマウント部材１０は、窒化アルミニウム基板（ＡｌＮ基板）１１に、Ｔｉ／Ｎｉ／Ａｕ（表面側）からなる電極１４、１５を形成している。ＡｌＮ基板１１の底面には実装基板の電極に導通搭載される実装用電極としての電極１７、１８を形成しており、電極１４と電極１７とはスルーホール１９を介して、また電極１５と電極１８とはスルーホール２０を介してそれぞれ電気的に導通させている。   In the submount member 10, electrodes 14 and 15 made of Ti / Ni / Au (surface side) are formed on an aluminum nitride substrate (AlN substrate) 11. On the bottom surface of the AlN substrate 11, electrodes 17 and 18 are formed as mounting electrodes that are conductively mounted on the electrodes of the mounting substrate. The electrodes 14 and 17 are connected through the through holes 19 and the electrodes 15 and the electrodes. 18 are electrically connected to each other through a through hole 20.

上記のような半導体発光素子の製造方法を図２〜図７に基づいて説明する。図２は、半導体発光素子の製造方法のフローチャート、図３は、図２の各工程の断面説明図、図４は、複合基板の一実施の形態の説明図で、（ａ）は発光素子側ウェハの平面説明図、（ｂ）はサブマウント部材側ウェハの平面説明図、（ｃ）は発光素子側ウェハとサブマウント部材側ウェハを接合した複合基板の説明図、図５は、サブマウント部材側ウェハの断面説明図、図６は、発光素子側ウェハとサブマウント部材側ウェハの接合状態を示す断面説明図、図７は、発光素子側ウェハとサブマウント部材側ウェハとを接合した複合基板を分離して半導体発光素子を得る方法の説明図である。   A method for manufacturing the semiconductor light emitting device as described above will be described with reference to FIGS. 2 is a flowchart of a method for manufacturing a semiconductor light emitting device, FIG. 3 is a cross-sectional explanatory diagram of each step of FIG. 2, FIG. 4 is an explanatory diagram of an embodiment of a composite substrate, and FIG. FIG. 5B is an explanatory diagram of a wafer, FIG. 5B is an explanatory diagram of a composite substrate obtained by bonding a light emitting element side wafer and a submount member side wafer, and FIG. 5 is a submount member. FIG. 6 is a cross-sectional explanatory view showing a bonding state of the light emitting element side wafer and the submount member side wafer, and FIG. 7 is a composite substrate in which the light emitting element side wafer and the submount member side wafer are bonded. It is explanatory drawing of the method of isolate | separating and obtaining a semiconductor light-emitting device.

本発明の半導体発光素子の製造方法は、図２に示すように、（ａ）ＧａＮ系発光素子ウェハに電極形成、（ｂ）絶縁膜形成、（ｃ）全面金属層層形成、（ｄ）レジストパターニング、（ｅ）電気めっきによるバンプ形成、（ｆ）レジスト除去、（ｇ）金属層除去、そして（ｈ）サブマウント部材側ウェハとの接合、（ｉ）発光素子単位への分離、の各工程を含むものである。図２の各工程を図３及び図４に基づいて詳細に説明する。   As shown in FIG. 2, the method for manufacturing a semiconductor light emitting device of the present invention comprises: (a) forming an electrode on a GaN-based light emitting device wafer, (b) forming an insulating film, (c) forming an entire metal layer, and (d) resist. Each step of patterning, (e) bump formation by electroplating, (f) resist removal, (g) metal layer removal, (h) bonding to submount member side wafer, (i) separation into light emitting element units Is included. Each step in FIG. 2 will be described in detail with reference to FIGS.

まず、サファイア基板（図示せず）の表面にＧａＮ系化合物半導体を成長させたウェハ２０に、ｎ側電極３とｐ側電極４を備えた発光素子単位２１を、複数個、ウェハ２０のほぼ全面に亘り行列状に形成し（図３（ａ）、図４（ａ））、これら電極３と４のバンプを形成する部分以外にＳｉＯ2膜を形成する（図２（ｂ）、図３（ｂ））。 First, a plurality of light emitting element units 21 each including an n-side electrode 3 and a p-side electrode 4 are formed on a wafer 20 on which a GaN-based compound semiconductor is grown on the surface of a sapphire substrate (not shown). (FIG. 3 (a), FIG. 4 (a)), and an SiO 2 film is formed in addition to the portions where the bumps of these electrodes 3 and 4 are formed (FIG. 2 (b), FIG. b)).

次に、ウェハ２０のほぼ全面に亘りｎ側電極３及びｐ側電極４と電気的に導通した平面状の金属層５をウェハ全面に形成する（図２（ｃ））。金属層５は、Ｔｉ（下層）およびＡｕ（上層）からなり、蒸着やスパッタリング等によりＴｉ層は０．００１〜１μｍ、Ａｕ槽は０．５〜３μｍの厚さに形成する。   Next, a planar metal layer 5 that is electrically connected to the n-side electrode 3 and the p-side electrode 4 over almost the entire surface of the wafer 20 is formed on the entire surface of the wafer (FIG. 2C). The metal layer 5 is made of Ti (lower layer) and Au (upper layer), and the Ti layer is formed to a thickness of 0.001 to 1 μm and the Au tank is formed to a thickness of 0.5 to 3 μm by vapor deposition or sputtering.

次に、金属層５の上にレジスト２３を形成し（図３（ｄ））、電気めっきを施すことにより、金属層５の上にバンプ６、７を形成する。電気めっきは、最初に４０℃の０．１Ｎ塩酸に１分間浸漬し、次に、硫酸ニッケル、塩化ニッケル、ホウ酸と添加剤からなるｐＨ４．４に調整された５０℃のＮｉめっき水溶液に１５分投入して電解Ｎｉめっきを行う。このとき、ウェハの開口部（被めっき部）面積に対し、１０ｍＡ／ｃｍ２の電流密度で、カーボン電極を対向電極にして行う。次に、シアン化金カリウム、りん酸水素二カリウム、添加剤からなるｐＨ６．５に調整された６５℃のＡｕめっき水溶液に４５分投入して電解Ａｕめっきを行う。このとき、ウェハの開口部（被めっき部）面積に対し、１０ｍＡ／ｃｍ２の電流密度で、白金電極を対向電極にして行う（図３（ｅ））。 Next, a resist 23 is formed on the metal layer 5 (FIG. 3D), and bumps 6 and 7 are formed on the metal layer 5 by electroplating. The electroplating is first immersed in 0.1N hydrochloric acid at 40 ° C. for 1 minute, and then in a Ni plating aqueous solution at 50 ° C. adjusted to pH 4.4 consisting of nickel sulfate, nickel chloride, boric acid and additives. Electrolytic Ni plating is performed by adding a minute amount. At this time, the carbon electrode is used as a counter electrode at a current density of 10 mA / cm 2 with respect to the area of the opening (to-be-plated part) of the wafer. Next, electrolytic Au plating is performed by adding 45 minutes to a 65 ° C. Au plating solution adjusted to pH 6.5 consisting of potassium gold cyanide, dipotassium hydrogen phosphate, and additives. At this time, the platinum electrode is used as the counter electrode at a current density of 10 mA / cm 2 with respect to the area of the opening (plate portion) of the wafer (FIG. 3E).

次に、レジスト２３を除去し（図３（ｆ））、さらに、表面に露出している部分の金属層５を除去することによりｎ側電極３と電気的に導通したバンプ６及びｐ側電極４と電気的に導通したバンプ７を有する発光素子単位２１が行列状に形成された発光素子側ウェハ２４が得られる（図３（ｇ）、図４（ａ））。このように、平面状の金属層５の上にレジスト２３を形成して選択的に電気めっきを施すことにより、形状及び位置の寸法精度が高いバンプ６、７を形成することができる。なお、電気めっきにより、厚さ０．５μｍのＮｉ下地の上に厚さ１０μｍのＡｕを有するバンプ６、７を形成した。   Next, the resist 23 is removed (FIG. 3F), and further, the bump 6 and the p-side electrode that are electrically connected to the n-side electrode 3 by removing the portion of the metal layer 5 exposed on the surface. Thus, the light emitting element side wafer 24 in which the light emitting element units 21 having the bumps 7 electrically connected to 4 are formed in a matrix is obtained (FIG. 3G, FIG. 4A). As described above, by forming the resist 23 on the planar metal layer 5 and selectively performing electroplating, the bumps 6 and 7 having high dimensional accuracy in shape and position can be formed. Note that bumps 6 and 7 having Au of 10 μm thickness were formed on a Ni base of 0.5 μm thickness by electroplating.

一方、図４（ｂ）に示すように、発光素子側ウェハ２４の発光素子単位２１に対応するサブマウント部材単位２５がＡｌＮ基板１１上に複数個、行列状に形成されてなるサブマウント部材側ウェハ２６を用意する。サブマウント部材側ウェハ２６は、図１からも明らかな通り、窒化アルミニウム基板（ＡｌＮ基板）１１に、Ｔｉ／Ｎｉ／Ａｕ（表面側）の３層からなる電極１４、１５が行列状に形成されている。   On the other hand, as shown in FIG. 4B, the submount member side in which a plurality of submount member units 25 corresponding to the light emitting element units 21 of the light emitting element side wafer 24 are formed in a matrix on the AlN substrate 11. A wafer 26 is prepared. As is apparent from FIG. 1, the submount member side wafer 26 has electrodes 14 and 15 formed of three layers of Ti / Ni / Au (surface side) formed in a matrix on an aluminum nitride substrate (AlN substrate) 11. ing.

次に、図４（ａ）に示す発光素子側ウェハ２４の上下を反転させ、図４（ｂ）に示すサブマウント部材側ウェハ２６と重ね合わせ、バンプ６を電極１４に、また、バンプ７を電極１５に接合させることにより、図４（ｃ）に示すような半導体発光素子形成用複合基板２７が得られる。   Next, the light emitting element side wafer 24 shown in FIG. 4A is turned upside down and overlapped with the submount member side wafer 26 shown in FIG. 4B, and the bumps 6 are formed on the electrodes 14 and the bumps 7 are formed. By bonding to the electrode 15, a composite substrate 27 for forming a semiconductor light emitting element as shown in FIG. 4C is obtained.

半導体発光素子形成用複合基板２７は、図６に示すようにサブマウント部材側ウェハ２６に形成される電極１７、１８と、発光素子側ウェハ２４のｎ側電極３およびｐ側電極４とがスルーホール１９、２０を介して電気的に接続される。このことにより、図７に示すように、半導体発光素子形成用複合基板２７を破線に沿ってダイシングすることにより得られる個々の発光素子単位２１は、外部回路実装用の電極１７、１８をそれぞれ有したフリップチップ型半導体発光素子となる。   As shown in FIG. 6, the composite substrate 27 for forming a semiconductor light emitting element has electrodes 17 and 18 formed on the submount member side wafer 26, and the n side electrode 3 and the p side electrode 4 of the light emitting element side wafer 24 pass through. Electrical connection is made through holes 19 and 20. Accordingly, as shown in FIG. 7, each light emitting element unit 21 obtained by dicing the semiconductor light emitting element forming composite substrate 27 along the broken line has electrodes 17 and 18 for mounting external circuits, respectively. Thus, the flip chip type semiconductor light emitting device is obtained.

上記した実施の形態によると、以下の効果が得られる。
（１）平面状の金属層５の上にレジスト２３を形成して電気めっきを施すので、形状精度や質に優れるバンプ６、７を発光素子側ウェハ２４に大量、かつ容易に形成することができる。また、このバンプ６、７を介して発光素子側ウェハ２４と接合されるサブマウント部材側ウェハ２６がスルーホール１９、２０を介して外部回路実装用の電極１７、１８と電気的に接続されることにより、ワイヤ等の接続部材を必要としないサブマウント部材搭載型のフリップチップ型半導体発光素子を容易に、かつ多量に製造することができる。
（２）また、電気めっきによってバンプ６、７を形成することにより、バンプ６、７の厚さを通電時間によって制御でき、所望の厚さのバンプ６、７が容易に得られる。
（３）発光素子単位が複数個、行列状に形成された発光素子側ウェハと、発光素子側ウェハの複数の発光素子に対応する複数のサブマウント部材が配置されてなるサブマウント部材側ウェハを重ね合わせ接合してから分離するので、発光素子側ウェハとサブマウント部材側ウェハとを一度位置決めするだけで精度良く接合でき、製造工程を簡潔化できる。このため、複数の半導体発光素子を一挙に製造することが可能となる。
（４）発光素子側ウェハの電極形成時に用いるフォトリソグラフィーのためのマスクと、サブマウント部材側ウェハの電極形成時に用いるフォトリソグラフィー用のマスクとを共用することが可能になるので、効率の良い半導体発光素子の製造を可能にするとともに製造コストを低減することができる。 According to the above-described embodiment, the following effects can be obtained.
(1) Since the resist 23 is formed on the planar metal layer 5 and electroplating is performed, bumps 6 and 7 having excellent shape accuracy and quality can be easily formed in large quantities on the light emitting element side wafer 24. it can. Further, the submount member side wafer 26 bonded to the light emitting element side wafer 24 through the bumps 6 and 7 is electrically connected to the external circuit mounting electrodes 17 and 18 through the through holes 19 and 20. As a result, a submount member-mounted flip-chip type semiconductor light emitting element that does not require a connecting member such as a wire can be easily and in large quantities manufactured.
(2) Further, by forming the bumps 6 and 7 by electroplating, the thickness of the bumps 6 and 7 can be controlled by the energization time, and the bumps 6 and 7 having a desired thickness can be easily obtained.
(3) A light emitting element side wafer in which a plurality of light emitting element units are formed in a matrix, and a submount member side wafer in which a plurality of submount members corresponding to the light emitting elements of the light emitting element side wafer are arranged. Since the separation is performed after the overlap bonding, the light emitting element side wafer and the submount member side wafer can be bonded with high accuracy only by positioning once, and the manufacturing process can be simplified. For this reason, it becomes possible to manufacture several semiconductor light-emitting devices at once.
(4) Since it becomes possible to share the mask for photolithography used at the time of electrode formation of the light emitting element side wafer and the mask for photolithography used at the time of electrode formation of the submount member side wafer, an efficient semiconductor The light emitting element can be manufactured and the manufacturing cost can be reduced.

なお、上記実施の形態では、発光素子側ウェハとサブマウント部材側ウェハを重ね合わせ接合してから分離する方法を説明したが、本発明においては、発光素子側ウェハ単独を発光素子単位で分離してからサブマウント部材と接合することも可能である。   In the above embodiment, the method of separating the light emitting element side wafer and the submount member side wafer after being bonded is described. However, in the present invention, the light emitting element side wafer alone is separated for each light emitting element. It is also possible to join the submount member later.

また、バンプの形成は発光素子側ウェハに限定されず、サブマウント部材側ウェハに対して行うようにしても良い。   The formation of the bump is not limited to the light emitting element side wafer, but may be performed on the submount member side wafer.

本発明により得られる半導体発光素子の一実施の形態の説明図であり、（ａ）は半導体発光素子の断面説明図、（ｂ）は（ａ）のｂ−ｂ部における発光素子の底面説明図、（ｃ）はサブマウント部材の平面説明図である。It is explanatory drawing of one Embodiment of the semiconductor light-emitting device obtained by this invention, (a) is sectional explanatory drawing of a semiconductor light-emitting device, (b) is bottom surface explanatory drawing of the light-emitting device in the bb part of (a). (C) is a plane explanatory view of a submount member. 本発明の実施の形態に係る半導体発光素子の製造方法のフローチャートである。3 is a flowchart of a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention. 本発明の実施の形態に係る半導体発光素子の製造方法における各工程の断面説明図である。It is sectional explanatory drawing of each process in the manufacturing method of the semiconductor light-emitting device concerning embodiment of this invention. 本発明の実施の形態に係る複合基板の説明図であり、（ａ）は発光素子側ウェハの平面説明図、（ｂ）はサブマウント部材側ウェハの平面説明図、（ｃ）は発光素子側ウェハとサブマウント部材側ウェハを接合した複合基板の説明図である。It is explanatory drawing of the composite substrate which concerns on embodiment of this invention, (a) is plane explanatory drawing of the light emitting element side wafer, (b) is plane explanatory drawing of the submount member side wafer, (c) is the light emitting element side. It is explanatory drawing of the composite substrate which joined the wafer and the submount member side wafer. 本発明の実施の形態に係るサブマウント部材側ウェハの断面説明図である。It is a section explanatory view of the submount member side wafer concerning an embodiment of the invention. 本発明の実施の形態に係る発光素子側ウェハとサブマウント部材側ウェハの接合状態を示す断面説明図である。It is a section explanatory view showing the joined state of the light emitting element side wafer and submount member side wafer concerning an embodiment of the invention. 発光素子側ウェハとサブマウント部材側ウェハとを接合した複合基板を分離して半導体発光素子を得る方法の説明図である。It is explanatory drawing of the method of isolate | separating the composite substrate which joined the light emitting element side wafer and the submount member side wafer, and obtaining a semiconductor light emitting element. フリップチップボンディング型半導体発光装置に使用される半導体発光素子の従来例を示す図であり、（ａ）は半導体発光素子の断面説明図、（ｂ）は（ａ）のｂ−ｂ部における発光素子の底面説明図、（ｃ）はサブマウント部材の平面説明図である。It is a figure which shows the prior art example of the semiconductor light-emitting device used for a flip chip bonding type semiconductor light-emitting device, (a) is sectional explanatory drawing of a semiconductor light-emitting device, (b) is the light-emitting device in the bb part of (a). (C) is a plane explanatory view of a submount member.

符号の説明Explanation of symbols

１：発光素子
２：発光ダイオード
３：ｎ側電極
４：ｐ側電極
５：金属層
６、７：バンプ
１０：サブマウント部材
１１：ＡｌＮ基板
１２：Ｔｉ／Ｎｉ／Ａｕメッキ
１３：Ａｕメッキ
１４、１５：電極
１６：ＳｉＯ2膜
１７、１８：電極
１９、２０：スルーホール
２１：発光素子単位
２２：絶縁膜
２３：レジスト
２４：発光素子側ウェハ
２５：サブマウント部材単位
２６：サブマウント部材側ウェハ
２７：半導体発光素子形成用複合基板

1: Light-emitting element 2: Light-emitting diode 3: n-side electrode 4: p-side electrode 5: metal layer 6, 7: bump 10: submount member 11: AlN substrate 12: Ti / Ni / Au plating 13: Au plating 14 15: Electrode 16: SiO 2 film 17, 18: Electrode 19, 20: Through hole 21: Light emitting element unit 22: Insulating film 23: Resist 24: Light emitting element side wafer 25: Submount member unit 26: Submount member side wafer 27: Composite substrate for forming a semiconductor light emitting device

Claims (6)

光透過性基板にＧａＮ系化合物半導体を成長させたウェハを形成する工程と、
前記ウェハにｐ側電極及びｎ側電極を備え、前記ウェハのほぼ全面に亘り前記ｎ側電極及び前記ｐ側電極と電気的に導通した平面状の金属層を形成し、前記平面状の金属層の上にレジストを形成して選択的にバンプを形成し、前記レジスト及び表面に露出している部分の前記金属層を除去することにより、前記ｐ側電極と電気的に導通したバンプ及び前記ｎ側電極と電気的に導通したバンプを備えた複数の発光素子を前記ウェハのほぼ全面に亘り配置して発光素子側ウェハを得る工程と、
前記ウェハの前記複数の発光素子に対応する複数のサブマウント部材を配置してサブマウント部材側ウェハを得る工程と、
前記発光素子側ウェハと前記サブマウント部材側ウェハを接合して前記サブマウント部材側ウェハの実装用電極と前記発光素子側ウェハの前記ｐ側電極及びｎ側電極とをスルーホールを介して導通させる工程とを含むことを特徴とする半導体発光素子形成用複合基板の製造方法。 Forming a wafer on which a GaN-based compound semiconductor is grown on a light-transmitting substrate;
The planar metal layer is provided with a p-side electrode and an n-side electrode on the wafer, and a planar metal layer electrically connected to the n-side electrode and the p-side electrode is formed over substantially the entire surface of the wafer. A bump is selectively formed by forming a resist on the resist, and the bump and the n-side electrode electrically connected to the p-side electrode are removed by removing the resist and the metal layer exposed on the surface. Arranging a plurality of light emitting elements having bumps electrically connected to the side electrodes over substantially the entire surface of the wafer to obtain a light emitting element side wafer;
Arranging a plurality of submount members corresponding to the plurality of light emitting elements of the wafer to obtain a submount member side wafer;
The light emitting element side wafer and the submount member side wafer are joined and the mounting electrode of the submount member side wafer is electrically connected to the p side electrode and the n side electrode of the light emitting element side wafer through a through hole. A process for producing a composite substrate for forming a semiconductor light emitting element. 前記光透過性基板は、サファイア基板である請求項１に記載の半導体発光素子形成用複合基板の製造方法。   The method for manufacturing a composite substrate for forming a semiconductor light emitting element according to claim 1, wherein the light transmissive substrate is a sapphire substrate. 前記サブマウント部材側ウェハは、窒化アルミニウム基板に前記バンプが接合される電極が形成されたものである請求項１または２に記載の半導体発光素子形成用複合基板の製造方法。   The method for manufacturing a composite substrate for forming a semiconductor light emitting element according to claim 1, wherein the submount member side wafer is formed by forming an electrode to which the bump is bonded to an aluminum nitride substrate. 光透過性基板にＧａＮ系化合物半導体を成長させたウェハを形成する工程と、
前記ウェハにｐ側電極及びｎ側電極を備え、前記ウェハのほぼ全面に亘り前記ｎ側電極及び前記ｐ側電極と電気的に導通した平面状の金属層を形成し、前記平面状の金属層の上にレジストを形成して選択的にバンプを形成し、前記レジスト及び表面に露出している部分の前記金属層を除去することにより、前記ｐ側電極と電気的に導通したバンプ及び前記ｎ側電極と電気的に導通したバンプを備えた複数の発光素子を前記ウェハのほぼ全面に亘り行列状に形成して発光素子側ウェハを得る工程と、
前記ウェハの前記複数の発光素子に対応する複数のサブマウント部材を配置してサブマウント部材側ウェハを得る工程と、
前記発光素子側ウェハと前記サブマウント部材側ウェハとを接合して前記サブマウント部材側ウェハの実装用電極と前記発光素子側ウェハの前記ｐ側電極及びｎ側電極とをスルーホールを介して導通させた複合基板を形成する工程と、
前記複合基板を前記発光素子単位に分離する工程とを含むことを特徴とする半導体発光素子の製造方法。 Forming a wafer on which a GaN-based compound semiconductor is grown on a light-transmitting substrate;
The planar metal layer is provided with a p-side electrode and an n-side electrode on the wafer, and a planar metal layer electrically connected to the n-side electrode and the p-side electrode is formed over substantially the entire surface of the wafer. A bump is selectively formed by forming a resist on the resist, and the bump and the n-side electrode electrically connected to the p-side electrode are removed by removing the resist and the metal layer exposed on the surface. Forming a light emitting element side wafer by forming a plurality of light emitting elements provided with bumps electrically connected to the side electrodes in a matrix over substantially the entire surface of the wafer;
Arranging a plurality of submount members corresponding to the plurality of light emitting elements of the wafer to obtain a submount member side wafer;
The light emitting element side wafer and the submount member side wafer are joined, and the mounting electrode of the submount member side wafer is electrically connected to the p side electrode and the n side electrode of the light emitting element side wafer through a through hole. Forming the composite substrate, and
And a step of separating the composite substrate into the light emitting element units. 前記光透過性基板は、サファイア基板である請求項４に記載の半導体発光素子の製造方法。   The method of manufacturing a semiconductor light emitting element according to claim 4, wherein the light transmissive substrate is a sapphire substrate. 前記サブマウント部材側ウェハは、窒化アルミニウム基板に前記バンプが接合される電極が形成されたものである請求項４または５に記載の半導体発光素子の製造方法。   6. The method of manufacturing a semiconductor light emitting element according to claim 4, wherein the submount member side wafer is formed by forming an electrode to which the bump is bonded to an aluminum nitride substrate.
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Publication number Priority date Publication date Assignee Title
TWI284421B (en) * 2005-06-21 2007-07-21 Uni Light Technology Inc LED structure for flip-chip package and method thereof
EP1897151A4 (en) * 2005-06-22 2010-03-10 Seoul Opto Device Co Ltd Light emitting device and method of manufacturing the same
JP2008147556A (en) * 2006-12-13 2008-06-26 Nichia Chem Ind Ltd Semiconductor laser device and manufacturing method therefor
JP4724222B2 (en) 2008-12-12 2011-07-13 株式会社東芝 Method for manufacturing light emitting device
JP5294902B2 (en) * 2009-01-27 2013-09-18 シチズン電子株式会社 Manufacturing method of surface mounted light emitting device
JP5519383B2 (en) * 2010-04-16 2014-06-11 シチズンホールディングス株式会社 Semiconductor light emitting device
KR101719670B1 (en) * 2010-11-19 2017-03-24 한국전자통신연구원 Wafer level packaged GaN power device and the manufacturing method thereof
KR101230622B1 (en) 2010-12-10 2013-02-06 이정훈 Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same
JP5537446B2 (en) 2011-01-14 2014-07-02 株式会社東芝 Light emitting device, light emitting module, and method of manufacturing light emitting device
JP5603793B2 (en) 2011-02-09 2014-10-08 株式会社東芝 Semiconductor light emitting device
JP5644711B2 (en) * 2011-07-27 2014-12-24 豊田合成株式会社 Light emitting chip manufacturing method, light emitting chip, and joined body
JP5809965B2 (en) * 2011-12-27 2015-11-11 シチズンホールディングス株式会社 Semiconductor light emitting device
US9269873B2 (en) 2012-03-13 2016-02-23 Citizen Holdings Co., Ltd. Semiconductor light emitting device and method for manufacturing same
KR101700899B1 (en) * 2012-05-16 2017-02-01 이정훈 Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same
JP6218131B2 (en) * 2012-09-19 2017-10-25 シチズン電子株式会社 Semiconductor device and mounting method thereof
JP6394052B2 (en) * 2013-05-13 2018-09-26 日亜化学工業株式会社 Light emitting device and manufacturing method thereof
KR102409220B1 (en) * 2014-01-07 2022-06-16 루미리즈 홀딩 비.브이. Light emitting device package
JP2018010899A (en) * 2016-07-11 2018-01-18 株式会社ディスコ Light-emitting diode chip manufacturing method and light-emitting diode chip
JP2018010898A (en) * 2016-07-11 2018-01-18 株式会社ディスコ Light-emitting diode chip manufacturing method and light-emitting diode chip

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