JP4255842B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4255842B2 JP4255842B2 JP2004004537A JP2004004537A JP4255842B2 JP 4255842 B2 JP4255842 B2 JP 4255842B2 JP 2004004537 A JP2004004537 A JP 2004004537A JP 2004004537 A JP2004004537 A JP 2004004537A JP 4255842 B2 JP4255842 B2 JP 4255842B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32052—Shape in top view
- H01L2224/32055—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
前記放熱板は、上面中央部に突出するように設けられ前記半導体チップを支持する突出部と、前記突出部の裏面の周囲に前記突出部を保持するように設けられ前記封止樹脂の裏面に露出した複数個の支持部と、前記複数個の放熱端子と、前記支持部および前記放熱端子の下端面よりも後退した肉薄部とが一体になった構造を有する。前記突出部の下面および前記肉薄部の下面は前記封止樹脂で被覆されており、前記突出部に連続した複数箇所の支持部は、前記突出部の周囲に互いに対称な位置に配置されている。更に、前記支持部、前記放熱端子および前記電気信号用端子の相互間の間隔は、隣接する前記電気信号用端子どうしの相互間の間隔以上であり、前記放熱端子は前記電気信号用端子と実質的に同一の形状および配列を有する。
図1は本発明の実施の形態1における半導体装置の構造を示す。図1(a)、(b)は断面図、(c)は下面図である。図1(a)は、(c)のA−A線に沿った断面、(b)はB−B線に沿った断面を示す。図1(d)は、この半導体装置を構成する放熱板を取り出して示した下面図、図1(e)は、この半導体装置を構成するリードフレームの構造を示す下面図である。
図2に示す実施の形態2における半導体装置は、図1の半導体装置における放熱板20下面への封止樹脂7埋め込みの効率を改善した放熱板構造を有する。図2(a)、(b)は断面図、(c)は下面図である。図2(a)は、(c)のC−C線に沿った断面、(b)はD−D線に沿った断面を示す。図2(d)は、この半導体装置を構成する放熱板を取り出して示した下面図である。
図3Aは、実施の形態3における半導体装置を示す。図3A(a)は断面図、(b)は下面図である。図3(a)は、(b)のE−E線に沿った断面を示す。図3(c)は、この半導体装置を構成する放熱板を取り出して示した下面図である。
図4は、実施の形態4における半導体装置を示す。図4(a)は断面図、(b)は下面図である。図4(a)は、(b)のG−G線に沿った断面を示す。図4(c)は、この半導体装置を構成する放熱板を取り出して示した下面図である。
図5Aは、実施の形態5における半導体装置を示す。図5A(a)は断面図、(b)は下面図である。図5A(a)は、(b)のH−H線に沿った断面を示す。図5A(c)は、この半導体装置を構成する放熱板を取り出して示した下面図である。本実施の形態は、図4に示した実施の形態4の改良例である。
2 放熱板
2a 突出部
2b 支持部
2c 中央凹部
2d ハーフエッチング部
2e 放熱端子
3 接着材
4 吊りリード
4a ランド
5 端子
5a コーナーランド
6 ワイヤー
7 封止樹脂
7a チップと放熱板間の樹脂
8 半導体装置
9 基板
10、10a 電極
11、11a はんだ材料
12 配線
13 ビアホール
14 内層配線
15 はんだボール
20、21、25、28、29、31 放熱板
20a、21a、25a、27a 突出部
20b、21b、25c 支持部
20c、21c、25e、28a、29a、31a ハーフエッチング部
20d、21d、25d、28b、29b、31b 放熱端子
21e、25f、27b、29c、31c 貫通穴
22 隙間
23 放熱板21下面
24 矢印
25b 補助突出部
26 輪郭形状
30 樹脂流路
31d 中央放熱端子
32、33 放熱経路
34 シート
35 矢印
L1 支持部と放熱端子の間隔
L2 支持部どうしの間隔
L3 電気信号用端子どうし間の間隔
L4 支持部の幅
L5 リードフレーム厚み
L6 支持部の長さ
Claims (5)
- 半導体チップと、上面に前記半導体チップが搭載され下面に複数個の放熱端子が設けられた放熱板と、その放熱板の周囲に格子状に規則的に配列された複数個の電気信号用端子と、前記半導体チップと前記電気信号用端子とを電気的に接続する接続部材と、前記電気信号用端子および前記放熱端子の下端面を露出させて、前記半導体チップ、前記放熱板、前記電気信号用端子および前記接続部材を封止した封止樹脂とを備えた半導体装置において、
前記放熱板は、上面中央部に突出するように設けられ前記半導体チップを支持する突出部と、前記突出部の裏面の周囲に前記突出部を保持するように設けられ前記封止樹脂の裏面に露出した複数個の支持部と、前記複数個の放熱端子と、前記支持部および前記放熱端子の下端面よりも後退した肉薄部とが一体になった構造を有し、
前記突出部の下面および前記肉薄部の下面は前記封止樹脂で被覆されており、
前記突出部に連続した複数箇所の支持部は、前記突出部の周囲に互いに対称な位置に配置されており、
前記支持部、前記放熱端子および前記電気信号用端子の相互間の間隔は、隣接する前記電気信号用端子どうしの相互間の間隔以上であり、
前記放熱端子は前記電気信号用端子と実質的に同一の形状および配列を有することを特徴とする半導体装置。 - 半導体チップと、上面に前記半導体チップが搭載され下面に複数個の放熱端子が設けられた放熱板と、その放熱板の周囲に格子状に規則的に配列された複数個の電気信号用端子と、前記半導体チップと前記電気信号用端子とを電気的に接続する接続部材と、前記電気信号用端子および前記放熱端子の下端面を露出させて、前記半導体チップ、前記放熱板、前記電気信号用端子および前記接続部材を封止した封止樹脂とを備えた半導体装置において、
前記放熱板は、上面中央部に突出するように設けられ前記半導体チップを支持する突出部と、前記突出部の裏面の周囲に前記突出部を保持するように設けられ前記封止樹脂の裏面に露出した複数個の支持部と、前記複数個の放熱端子と、前記支持部および前記放熱端子の下端面よりも後退した肉薄部とが一体になった構造を有し、
前記突出部の下面および前記肉薄部の下面は前記封止樹脂で被覆されており、
前記突出部に連続した複数箇所の支持部は、前記突出部の周囲に互いに対称な位置に配置されており、
前記突出部に連続した前記支持部の幅は、リードフレーム厚みの1/2以上であり、
前記支持部の長さはリードフレーム厚み以上であることを特徴とする半導体装置。 - 前記放熱端子は、放熱板の外周部のみに、対称的に配置された請求項1または2記載の半導体装置。
- 前記放熱板の肉薄部の一部に貫通穴が形成されている請求項1または2記載の半導体装置。
- 前記貫通穴の位置は、すくなくとも半切断部に連続している請求項4記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004004537A JP4255842B2 (ja) | 2004-01-09 | 2004-01-09 | 半導体装置 |
TW093140926A TW200527640A (en) | 2004-01-09 | 2004-12-28 | Semiconductor device |
US11/029,785 US20050151242A1 (en) | 2004-01-09 | 2005-01-05 | Semiconductor device |
CNB2005100039106A CN100421247C (zh) | 2004-01-09 | 2005-01-10 | 半导体器件 |
US12/152,400 US20080308927A1 (en) | 2004-01-09 | 2008-05-14 | Semiconductor device with heat sink plate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004004537A JP4255842B2 (ja) | 2004-01-09 | 2004-01-09 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005197604A JP2005197604A (ja) | 2005-07-21 |
JP4255842B2 true JP4255842B2 (ja) | 2009-04-15 |
Family
ID=34737196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004004537A Expired - Fee Related JP4255842B2 (ja) | 2004-01-09 | 2004-01-09 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20050151242A1 (ja) |
JP (1) | JP4255842B2 (ja) |
CN (1) | CN100421247C (ja) |
TW (1) | TW200527640A (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8022532B2 (en) * | 2005-06-06 | 2011-09-20 | Rohm Co., Ltd. | Interposer and semiconductor device |
JP2010103244A (ja) * | 2008-10-22 | 2010-05-06 | Sony Corp | 半導体装置及びその製造方法 |
JP2011077108A (ja) * | 2009-09-29 | 2011-04-14 | Elpida Memory Inc | 半導体装置 |
JP2012104518A (ja) * | 2010-11-05 | 2012-05-31 | Sumitomo Heavy Ind Ltd | 封止装置の基板受け渡し機構及び封止装置の基板受け渡し方法 |
CN102683221B (zh) * | 2011-03-17 | 2017-03-01 | 飞思卡尔半导体公司 | 半导体装置及其组装方法 |
US9922920B1 (en) | 2016-09-19 | 2018-03-20 | Nanya Technology Corporation | Semiconductor package and method for fabricating the same |
CN116387169B (zh) * | 2023-06-05 | 2023-09-05 | 甬矽半导体(宁波)有限公司 | 封装方法和封装结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000091488A (ja) * | 1998-09-08 | 2000-03-31 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材 |
US6281568B1 (en) * | 1998-10-21 | 2001-08-28 | Amkor Technology, Inc. | Plastic integrated circuit device package and leadframe having partially undercut leads and die pad |
US6667541B1 (en) * | 1998-10-21 | 2003-12-23 | Matsushita Electric Industrial Co., Ltd. | Terminal land frame and method for manufacturing the same |
JP2001196534A (ja) * | 2000-01-12 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置および半導体モジュール |
JP3428591B2 (ja) * | 2001-06-27 | 2003-07-22 | 松下電器産業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP3502377B2 (ja) * | 2001-06-27 | 2004-03-02 | 松下電器産業株式会社 | リードフレーム、樹脂封止型半導体装置及びその製造方法 |
US6828661B2 (en) * | 2001-06-27 | 2004-12-07 | Matsushita Electric Industrial Co., Ltd. | Lead frame and a resin-sealed semiconductor device exhibiting improved resin balance, and a method for manufacturing the same |
JP2003017646A (ja) * | 2001-06-29 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
JP3638136B2 (ja) * | 2001-12-27 | 2005-04-13 | 株式会社三井ハイテック | リードフレームおよびこれを用いた半導体装置 |
JP2003204027A (ja) * | 2002-01-09 | 2003-07-18 | Matsushita Electric Ind Co Ltd | リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法 |
US6630631B1 (en) * | 2002-03-27 | 2003-10-07 | Intel Corporation | Apparatus and method for interconnection between a component and a printed circuit board |
-
2004
- 2004-01-09 JP JP2004004537A patent/JP4255842B2/ja not_active Expired - Fee Related
- 2004-12-28 TW TW093140926A patent/TW200527640A/zh unknown
-
2005
- 2005-01-05 US US11/029,785 patent/US20050151242A1/en not_active Abandoned
- 2005-01-10 CN CNB2005100039106A patent/CN100421247C/zh not_active Expired - Fee Related
-
2008
- 2008-05-14 US US12/152,400 patent/US20080308927A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CN100421247C (zh) | 2008-09-24 |
JP2005197604A (ja) | 2005-07-21 |
US20080308927A1 (en) | 2008-12-18 |
US20050151242A1 (en) | 2005-07-14 |
TW200527640A (en) | 2005-08-16 |
CN1638109A (zh) | 2005-07-13 |
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