JP4240848B2 - Bonding method of electronic parts - Google Patents

Bonding method of electronic parts Download PDF

Info

Publication number
JP4240848B2
JP4240848B2 JP2001181059A JP2001181059A JP4240848B2 JP 4240848 B2 JP4240848 B2 JP 4240848B2 JP 2001181059 A JP2001181059 A JP 2001181059A JP 2001181059 A JP2001181059 A JP 2001181059A JP 4240848 B2 JP4240848 B2 JP 4240848B2
Authority
JP
Japan
Prior art keywords
indium layer
electronic component
solution
joining
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001181059A
Other languages
Japanese (ja)
Other versions
JP2002373913A5 (en
JP2002373913A (en
Inventor
昌夫 中沢
健次 中村
雅俊 赤川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2001181059A priority Critical patent/JP4240848B2/en
Publication of JP2002373913A publication Critical patent/JP2002373913A/en
Publication of JP2002373913A5 publication Critical patent/JP2002373913A5/ja
Application granted granted Critical
Publication of JP4240848B2 publication Critical patent/JP4240848B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

【０００１】
【発明の属する技術分野】
本発明は電子部品の接合方法に関し、一層詳細には、常温接合による電子部品の接合方法に関する。
【０００２】
【従来の技術】
半導体チップをパッケージあるいは配線基板に搭載する場合、はんだによる接合、あるいは導電性接着剤を用いて、半導体チップの電極端子と配線基板の配線パターンとの電気的接合を行っているのが一般的である。
【０００３】
【発明が解決しようとする課題】
上記のはんだや導電性接着剤を用いる場合には、２００℃前後の加熱工程が必要である。
このような加熱工程を経ると、接合に必要な金属面の酸化や、金属間化合物の生成により、変質や脆弱化が生じやすいという課題がある。また、加熱炉といった、大型設備が必要となり、コスト高となる課題がある。
さらに、はんだバンプの溶融、導電性接着剤の軟化等、接続時に体積変化を伴う接合部材を使用するため、半導体チップの電極端子間、基板の配線パターン間が短絡するおそれがあり、狭ピッチ化に限界がある。
今後ますます多端子化、狭ピッチ化、小型化が進む中で、上記の課題を解決できる、いわゆる常温接合の技術開発が急がれている。
【０００４】
本発明は上記要望に応えるべくしてなされ、その目的とするところは、常温接合を可能とする、電子部品の接合方法を提供するにある。
【０００５】
【課題を解決するための手段】
上記目的による本発明に係る電子部品の接合方法では、一方の電子部品の接合部位にインジウム層を形成する工程と、他方の電子部品の前記一方の電子部品の接合部位と対応する部位に金属から成る接続端子を形成する工程と、前記インジウム層を、溶液中で表面処理して表面が酸化被膜のない清浄な面となるように清浄化する清浄化工程と、前記一方の電子部品のインジウム層と、他方の電子部品の酸化被膜のない清浄な表面状態の接続端子とを前記溶液中で接触させ、押圧して両金属層間を接合する接合工程とを含むことを特徴としている。
溶液中で接合することで、インジウム層表面に酸化被膜が形成されにくく、良好な接合が行える。
前記インジウム層を電解めっきで形成すると好適である。
前記接続端子を、金めっきもしくは銅めっきにより形成すると好適である。
【０００６】
前記清浄化工程において、弱アルカリ性の電解液中で、前記一方の電子部品を陰極としてインジウム層を電解処理して、インジウム層表面を酸化被膜のない清浄な面に清浄化し、前記接合工程を、前記一方の電子部品を電解液から取り出すことなしに該電解液中で行うようにすると好適である。
インジウムは酸性溶液中では溶解するので、弱アルカリ性の電解液を用いるとよい。電解処理により、インジウム層の表面が清浄化され、電解液から取り出すことなしに、電解液中で接合工程を行うことにより、インジウム金属表面に酸化被膜が形成されるのを防止できる。
【０００７】
あるいは前記清浄化工程において、弱アルカリ性の還元性溶液中でインジウム層を還元処理して、インジウム層表面を酸化被膜のない清浄な面に清浄化し、前記接合工程を、前記一方の電子部品を還元性溶液から取り出すことなしに該還元性溶液中で行うようにするとよい。
還元性溶液中でインジウム層表面の酸化被膜が除去され、清浄化される。
【０００８】
【発明の実施の形態】
以下、本発明の好適な実施の形態を添付図面に基づいて詳細に説明する。
図１は、電子部品の接合構造の一例を示し、ＢＧＡ（ボールグリッドアレイ）型パッケージ（一方の電子部品）１０に、半導体チップ（他方の電子部品）１２をフリップチップ接続法によって搭載した例を示す説明図である。
半導体チップ１２の端子部（図示せず）には、金ワイヤあるいは金めっきにより金バンプ（接続端子）１６が形成されている。
【０００９】
一方、パッケージ本体（配線基板）１４の片面には、銅箔をエッチングしてチップ搭載用の配線パターン（図示せず）が形成され、該配線パターン上に、インジウム層１８が形成されている。インジウム層１８に、対応する金バンプ１６が接触するように位置合わせして半導体チップ１２をパッケージ本体１４上に載置し、常温で両者を加圧することによって、インジウム層１８と金バンプ１６間に金属間化合物が生成され、両者は強固に接合される。
金バンプ１６の表面は酸化被膜のない清浄な面となっている。インジウムは、空気中では酸化被膜が形成されやすい。そこで、後記するような手段によって、酸化被膜を除去した清浄な面として後、圧接接合する必要がある。
【００１０】
パッケージ本体１４のインジウム層１８は、電解インジウムめっきによって形成することができる。
インジウムめっき液は市販のものを用いることができる。例えば、大和化成株式会社製のＤＡＩＮ ＩＮ―ＰＬ３０のインジウムめっき液を好適に用いることができる。この市販のインジウムめっき液を用いた場合、めっき条件は、液温が３０℃前後、電流密度が２Ａ／ｄｍ2前後が好適であった。
もちろんインジウムめっき液はこれに限定されるものではない。めっき条件も通常の条件で行えばよい。
また、半導体チップ１２の金バンプ１６は、上記では金ワイヤにより形成したが、はんだによりバンプを形成し、このバンプ上に金めっきを施すようにしてもよい。
【００１１】
次に接合方法についてさらに詳細に説明する。
本発明では、上記のように、パッケージ本体（一方の電子部品）１４の接合部位にインジウム層１８を形成し、半導体チップ（他方の電子部品）１２の接合部位に金バンプ（接続端子）１６を形成した後、インジウム層１８を溶液中で清浄化し、溶液中で、半導体チップ１２の金バンプ１６とパッケージ本体１４のインジウム層１８とを接触させ、押圧して両金属層を接合するのである。
【００１２】
半導体チップ１２とパッケージ本体１４とを、溶液中で接合することで、インジウム層１８表面に酸化被膜が形成されにくく、良好な接合が行える。
インジウム層１８の清浄化方法について次に説明する。
まず第１の方法は、弱アルカリ性の電解液中で、パッケージ本体（配線基板）１４を陰極として、また陽極に例えば白金を用いて、インジウム層１８を電解処理する方法である。陰極となるインジウム層１８から水素が発生する状態に数分間保持する。これによりインジウム層１８表面が還元処理され、清浄化される。
電解液としては、特に限定されないが、クエン酸カリウム等の伝導塩を含む溶液とする。クエン酸カリウムの濃度としては、例えば１００ｇ／ｌ程度でよい。電解条件も特に限定されず、常温で、陰極から水素が発生する状態で、数分（例えば５分）間保持することで十分な清浄化が行える。
電解液を弱アルカリ性とするのは、インジウムは酸性溶液中では溶解するからである。
【００１３】
また、インジウム層１８の第２の清浄化方法は、弱アルカリ性の還元性溶液中でインジウム層１８を還元処理する方法である。
還元性溶液中でインジウム層１８表面の酸化被膜が除去され、清浄化される。
還元性溶液の組成の一例を下記に示す。
ジメチルアミンボラン ５ｇ／ｌ
酢酸タリウム １０ｐｐｍ
上記の組成で、クエン酸カリウムあるいはリン酸カリウム等を添加してｐＨ７〜８の弱アルカリ性に調整する。
上記の還元性溶液にパッケージ本体（配線基板）１４を浸漬し、５０℃で５分間保持することにより、インジウム層１８を十分に清浄化できた。
なお、還元性溶液ももちろん上記に限定されるものではない。
【００１４】
接合工程は上記の電解液中もしくは還元性溶液中でそのまま引き続いて行う。
すなわち、パッケージ本体１４を電解液もしくは還元性溶液から取り出すことなしに、半導体チップ１２も液中に浸漬し、インジウム層１８と対応する金バンプ１６とを位置合わせして接触させ、常温で、両者を数秒間押圧することで、インジウム層１８と金バンプ１６とが強固に接合する。
このように、液中で接合工程を行うことで、インジウム層１８の表面に酸化被膜が形成されるのが防止され、金属間化合物が生成されて両金属が強固に接合されるのである。
接合強度は、引き剥がし試験により、インジウム層１８の部位で破断が生じることから、インジウム層１８と金バンプ１６との間の接合強度は十分であることがわかる。
【００１５】
上記では、半導体チップ１２をパッケージ本体（配線基板）１４に搭載する例で説明したが、常温における金属間接合が要求される、他の電子部品同士の接合にも適用できることはもちろんである。
また上記では、インジウム層１８と金バンプ１６との間の接合例を示したが、清浄な表面状態のインジウム層と清浄な表面状態の銅層との間の接合も十分な接合強度で接合できることがわかった。
【００１６】
【発明の効果】
以上のように本発明によれば、常温で、金属あるいは導電性接着剤を溶融させることなく接合することができるので、狭ピッチの配線パターン間等であっても、短絡させることなく接合できるという著効を奏する。
また、高温加熱工程やそのための加熱炉が不要となり、コストの低減化も図れる。
【図面の簡単な説明】
【図１】 電子部品の接合例を示す説明図である。
【符号の説明】
１０ パッケージ
１２ 半導体チップ
１４ パッケージ本体
１６ 金バンプ
１８ インジウム層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for bonding electronic components, and more particularly to a method for bonding electronic components by room temperature bonding.
[0002]
[Prior art]
When mounting a semiconductor chip on a package or wiring board, it is common to use soldering or a conductive adhesive to electrically connect the electrode terminals of the semiconductor chip and the wiring pattern of the wiring board. is there.
[0003]
[Problems to be solved by the invention]
When using the above-mentioned solder or conductive adhesive, a heating step of around 200 ° C. is necessary.
After such a heating step, there is a problem that alteration and weakening are likely to occur due to oxidation of metal surfaces necessary for bonding and generation of intermetallic compounds. Moreover, a large-scale facility such as a heating furnace is required, and there is a problem that costs are increased.
In addition, the use of joint members that change volume during connection, such as melting solder bumps and softening conductive adhesive, may cause short circuits between the electrode terminals of the semiconductor chip and between the wiring patterns of the board, resulting in a narrow pitch. There is a limit.
As the number of terminals, narrow pitch, and miniaturization continue to increase in the future, there is an urgent need to develop technology for so-called room temperature bonding that can solve the above-mentioned problems.
[0004]
The present invention has been made in response to the above-mentioned demand, and an object of the present invention is to provide a method for joining electronic components that enables room temperature joining .
[0005]
[Means for Solving the Problems]
In the method for joining electronic components according to the present invention for the above purpose, a step of forming an indium layer at a joining portion of one electronic component and a portion corresponding to the joining portion of the one electronic component of the other electronic component from a metal. Forming a connection terminal comprising: a cleaning step of surface-treating the indium layer in a solution so that the surface is a clean surface without an oxide film; and the indium layer of the one electronic component And a bonding step of bringing the other electronic component into contact with the connection terminal having a clean surface state without an oxide film in the solution and pressing to join the two metal layers.
By bonding in a solution, an oxide film is hardly formed on the surface of the indium layer, and good bonding can be performed.
The indium layer is preferably formed by electrolytic plating.
It is preferable that the connection terminal is formed by gold plating or copper plating.
[0006]
In the cleaning step, in the weak alkaline electrolyte, the indium layer is subjected to electrolytic treatment using the one electronic component as a cathode, the surface of the indium layer is cleaned to a clean surface without an oxide film, and the bonding step is performed. It is preferable to perform the one electronic component in the electrolytic solution without taking it out of the electrolytic solution.
Since indium dissolves in an acidic solution, a weak alkaline electrolyte may be used. By the electrolytic treatment, the surface of the indium layer is cleaned, and it is possible to prevent an oxide film from being formed on the surface of the indium metal by performing the bonding step in the electrolytic solution without taking it out of the electrolytic solution.
[0007]
Alternatively, in the cleaning step, the indium layer is reduced in a weak alkaline reducing solution to clean the surface of the indium layer to a clean surface without an oxide film, and the one electronic component is reduced in the bonding step. It is good to carry out in this reducing solution, without taking out from a neutral solution.
In the reducing solution, the oxide film on the surface of the indium layer is removed and cleaned.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows an example of an electronic component bonding structure, in which a semiconductor chip (the other electronic component) 12 is mounted on a BGA (ball grid array) type package (one electronic component) 10 by a flip chip connection method. It is explanatory drawing shown.
Gold bumps (connection terminals) 16 are formed on the terminal portions (not shown) of the semiconductor chip 12 by gold wires or gold plating.
[0009]
On the other hand, on one side of the package body (wiring substrate) 14, a copper foil is etched to form a chip mounting wiring pattern (not shown), and an indium layer 18 is formed on the wiring pattern. The semiconductor chip 12 is placed on the package body 14 and aligned with the indium layer 18 so that the corresponding gold bumps 16 are in contact with each other. An intermetallic compound is produced, and both are firmly bonded.
The surface of the gold bump 16 is a clean surface without an oxide film. Indium tends to form an oxide film in the air. Therefore, it is necessary to form a clean surface from which the oxide film has been removed by means such as described later, and then press contact.
[0010]
The indium layer 18 of the package body 14 can be formed by electrolytic indium plating.
A commercially available indium plating solution can be used. For example, an indium plating solution of DAIN IN-PL30 manufactured by Daiwa Kasei Co., Ltd. can be suitably used. When this commercially available indium plating solution was used, the plating temperature was preferably about 30 ° C. and the current density was about 2 A / dm 2 .
Of course, the indium plating solution is not limited to this. The plating conditions may be performed under normal conditions.
Further, although the gold bumps 16 of the semiconductor chip 12 are formed with gold wires in the above, bumps may be formed with solder, and gold plating may be performed on the bumps.
[0011]
Next, the joining method will be described in more detail.
In the present invention, as described above, the indium layer 18 is formed at the joint portion of the package body (one electronic component) 14, and the gold bump (connection terminal) 16 is formed at the joint portion of the semiconductor chip (the other electronic component) 12. After the formation, the indium layer 18 is cleaned in a solution, and the gold bumps 16 of the semiconductor chip 12 and the indium layer 18 of the package body 14 are brought into contact with each other in the solution and pressed to join both metal layers.
[0012]
By bonding the semiconductor chip 12 and the package main body 14 in a solution, it is difficult to form an oxide film on the surface of the indium layer 18 and good bonding can be performed.
Next, a method for cleaning the indium layer 18 will be described.
The first method is a method in which the indium layer 18 is electrolytically treated in a weak alkaline electrolyte using the package body (wiring substrate) 14 as a cathode and platinum as the anode, for example. The indium layer 18 serving as the cathode is kept in a state where hydrogen is generated for several minutes. As a result, the surface of the indium layer 18 is reduced and cleaned.
Although it does not specifically limit as electrolyte solution, It is set as the solution containing conductive salts, such as potassium citrate. The concentration of potassium citrate may be about 100 g / l, for example. Electrolysis conditions are not particularly limited, and sufficient cleaning can be performed by holding for several minutes (for example, 5 minutes) in a state where hydrogen is generated from the cathode at room temperature.
The reason why the electrolytic solution is weakly alkaline is that indium dissolves in an acidic solution.
[0013]
The second cleaning method for the indium layer 18 is a method for reducing the indium layer 18 in a weak alkaline reducing solution.
In the reducing solution, the oxide film on the surface of the indium layer 18 is removed and cleaned.
An example of the composition of the reducing solution is shown below.
Dimethylamine borane 5g / l
Thallium acetate 10ppm
With the above composition, potassium citrate or potassium phosphate is added to adjust the pH to 7-8 weak alkalinity.
The indium layer 18 was sufficiently cleaned by immersing the package body (wiring board) 14 in the reducing solution and holding the package body (wiring board) 14 at 50 ° C. for 5 minutes.
Of course, the reducing solution is not limited to the above.
[0014]
The joining process is carried out as it is in the above electrolytic solution or reducing solution.
That is, without removing the package body 14 from the electrolytic solution or reducing solution, the semiconductor chip 12 is also immersed in the solution, and the indium layer 18 and the corresponding gold bump 16 are aligned and brought into contact with each other at room temperature. Is pressed for several seconds, whereby the indium layer 18 and the gold bump 16 are firmly bonded.
Thus, by performing a joining process in a liquid, it is prevented that an oxide film is formed on the surface of the indium layer 18, an intermetallic compound is produced | generated, and both metals are joined firmly.
As for the bonding strength, it is found that the bonding strength between the indium layer 18 and the gold bump 16 is sufficient because the tearing occurs at the site of the indium layer 18 by the peeling test.
[0015]
In the above description, the example in which the semiconductor chip 12 is mounted on the package body (wiring substrate) 14 has been described, but it is needless to say that the present invention can also be applied to bonding of other electronic components that require metal-to-metal bonding at room temperature.
Moreover, although the example of joining between the indium layer 18 and the gold bump 16 has been described above, joining between the clean surface state indium layer and the clean surface state copper layer can be performed with sufficient joint strength. I understood.
[0016]
【The invention's effect】
As described above, according to the present invention, since bonding can be performed at room temperature without melting metal or conductive adhesive, bonding can be performed without short-circuiting even between narrow pitch wiring patterns. Remarkably effective.
In addition, a high-temperature heating process and a heating furnace therefor are not required, and costs can be reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing an example of joining electronic components.
[Explanation of symbols]
10 Package 12 Semiconductor Chip 14 Package Body 16 Gold Bump 18 Indium Layer

Claims (5)

一方の電子部品の接合部位にインジウム層を形成する工程と、
他方の電子部品の前記一方の電子部品の接合部位と対応する部位に金属から成る接続端子を形成する工程と、
前記インジウム層を、溶液中で表面処理して表面が酸化被膜のない清浄な面となるように清浄化する清浄化工程と、
前記一方の電子部品のインジウム層と、他方の電子部品の酸化被膜のない清浄な表面状態の接続端子とを前記溶液中で接触させ、押圧して両金属層間を接合する接合工程とを含むことを特徴とする電子部品の接合方法。A step of forming an indium layer at a bonding site of one electronic component;
Forming a connection terminal made of a metal at a portion corresponding to a bonding portion of the one electronic component of the other electronic component;
A cleaning step for cleaning the indium layer in a solution so that the surface is a clean surface without an oxide film ;
A bonding step of bringing the indium layer of the one electronic component into contact with the connection terminal having a clean surface state without an oxide film of the other electronic component in the solution and pressing to join the two metal layers. A method of joining electronic parts characterized by the above. 前記インジウム層を電解めっきで形成することを特徴とする請求項１記載の電子部品の接合方法。  The method for joining electronic parts according to claim 1, wherein the indium layer is formed by electrolytic plating. 前記接続端子を、金めっきもしくは銅めっきにより形成することを特徴とする請求項１または２記載の電子部品の接合方法。  3. The method of joining electronic components according to claim 1, wherein the connection terminal is formed by gold plating or copper plating. 前記清浄化工程において、弱アルカリ性の電解液中で、前記一方の電子部品を陰極としてインジウム層を電解処理して、インジウム層表面を酸化被膜のない清浄な面に清浄化し、
前記接合工程を、前記一方の電子部品を電解液から取り出すことなしに該電解液中で行うことを特徴とする請求項１〜３いずれか１項記載の電子部品の接合方法。In the cleaning step, in the weak alkaline electrolyte, the indium layer is electrolytically treated using the one electronic component as a cathode, and the surface of the indium layer is cleaned to a clean surface without an oxide film,
The method for joining electronic components according to claim 1, wherein the joining step is performed in the electrolytic solution without taking out the one electronic component from the electrolytic solution. 前記清浄化工程において、弱アルカリ性の還元性溶液中でインジウム層を還元処理して、インジウム層表面を酸化被膜のない清浄な面に清浄化し、
前記接合工程を、前記一方の電子部品を還元性溶液から取り出すことなしに該還元性溶液中で行うことを特徴とする請求項１〜３いずれか１項記載の電子部品の接合方法。In the cleaning step, the indium layer is reduced in a weak alkaline reducing solution to clean the surface of the indium layer to a clean surface without an oxide film,
The method for joining electronic components according to claim 1, wherein the joining step is performed in the reducing solution without removing the one electronic component from the reducing solution.
JP2001181059A 2001-06-15 2001-06-15 Bonding method of electronic parts Expired - Fee Related JP4240848B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001181059A JP4240848B2 (en) 2001-06-15 2001-06-15 Bonding method of electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001181059A JP4240848B2 (en) 2001-06-15 2001-06-15 Bonding method of electronic parts

Publications (3)

Publication Number Publication Date
JP2002373913A JP2002373913A (en) 2002-12-26
JP2002373913A5 JP2002373913A5 (en) 2007-03-01
JP4240848B2 true JP4240848B2 (en) 2009-03-18

Family

ID=19021386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001181059A Expired - Fee Related JP4240848B2 (en) 2001-06-15 2001-06-15 Bonding method of electronic parts

Country Status (1)

Country Link
JP (1) JP4240848B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4036786B2 (en) 2003-04-24 2008-01-23 唯知 須賀 Electronic component mounting method

Also Published As

Publication number Publication date
JP2002373913A (en) 2002-12-26

Similar Documents

Publication Publication Date Title
JP3886712B2 (en) Manufacturing method of semiconductor device
TWI223361B (en) Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same
US6689639B2 (en) Method of making semiconductor device
CN103025055A (en) Printed wiring board and a method of production thereof
JP2006279062A (en) Semiconductor element and semiconductor device
JP4997837B2 (en) Semiconductor element bonding method and semiconductor device
JP3998484B2 (en) How to connect electronic components
US6838009B2 (en) Rework method for finishing metallurgy on chip carriers
JP3400408B2 (en) Flip chip mounting method
JP4240848B2 (en) Bonding method of electronic parts
JP2001274539A (en) Electrode joining method for printed wiring board loaded with electronic device
JPWO2002062117A1 (en) How to join electronic components
JPWO2007072876A1 (en) Method for manufacturing printed wiring board
JP2002373913A5 (en)
TWI241704B (en) Surface treatment for oxidation removal in integrated circuit package assemblies
JP2000349111A (en) Electrode for solder bonding
JP4667637B2 (en) Bonding method of electronic parts
JP3465014B2 (en) Package insertion board and method of manufacturing the same
JP3582111B2 (en) Manufacturing method of printed wiring board
CN107119298A (en) Pcb surface processing method
JP2005252047A (en) Semiconductor device
JP4038985B2 (en) Tape carrier for semiconductor devices
JP2626028B2 (en) Method for manufacturing semiconductor ceramic electronic component
JP2000164801A (en) Integrated semiconductor device
JP2929141B2 (en) Electronic component mounting substrate and method of manufacturing the same

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070111

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070111

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081016

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081028

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20081216

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081222

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120109

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120109

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130109

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130109

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140109

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees