JP4215596B2 - Solid-state imaging device - Google Patents

Solid-state imaging device Download PDF

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JP4215596B2
JP4215596B2 JP2003298105A JP2003298105A JP4215596B2 JP 4215596 B2 JP4215596 B2 JP 4215596B2 JP 2003298105 A JP2003298105 A JP 2003298105A JP 2003298105 A JP2003298105 A JP 2003298105A JP 4215596 B2 JP4215596 B2 JP 4215596B2
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英夫 千ヶ崎
俊文 尾崎
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Hitachi Ltd
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Description

本発明は固体撮像装置の小型化に際し高感度な信号出力を得るための固体撮像装置に関する。   The present invention relates to a solid-state imaging device for obtaining a highly sensitive signal output when the solid-state imaging device is miniaturized.

従来、固体撮像素子は、図５に示すインターライン転送方式のＣＣＤ型固体撮像素子が広く用いられている。図５中、１０３はホトダイオード、１０４は読み出しゲート、１０５は垂直電荷転送素子、１０２は水平電荷転送素子、１０１は出力回路である。ホトダイオード１０３で光電変換された信号電荷は所定の期間蓄積された後、読み出しゲート１０４をオンして、全画素同時に垂直電荷転送素子１０５に読み出される。ついで垂直電荷転送素子１０５と、水平電荷転送素子１０２の中を転送され、出力回路１０１により電圧に変換されて読み出される。   Conventionally, as a solid-state image sensor, an interline transfer type CCD solid-state image sensor shown in FIG. 5 has been widely used. In FIG. 5, 103 is a photodiode, 104 is a readout gate, 105 is a vertical charge transfer element, 102 is a horizontal charge transfer element, and 101 is an output circuit. After the signal charge photoelectrically converted by the photodiode 103 is accumulated for a predetermined period, the readout gate 104 is turned on and is read out to the vertical charge transfer element 105 at the same time for all pixels. Next, it is transferred through the vertical charge transfer element 105 and the horizontal charge transfer element 102, converted into a voltage by the output circuit 101, and read out.

一般にこのようなＣＣＤ型固体撮像装置の出力回路は、水平電荷転送素子から送られてくる信号電荷を浮遊拡散層に入力してその電圧変化を検出する、いわゆる、浮遊拡散層型出力回路が広く用いられている。このような浮遊拡散層型出力回路の一従来例を図６，図７に示す。図６は平面図、図７は図６中の線Ｃ−Ｃ′の断面図である。図７中の１は低濃度ｎ型シリコン基板、２は低濃度ｐ型ウエル
、３は垂直電荷転送素子に混入するスメアを低減するためのｐ型第二ウエル、４は電荷転送素子の埋め込みチャネルとなるｎ型層、５は高濃度ｎ型浮遊拡散層、６はチャネルストッパ、７は絶縁膜、８は局所酸化膜、９はフィールドプレート電極、１０は出力障壁電極、１１は転送電極、１２は出力トランジスタのゲート電極も兼ねるポリシリコン配線、１３はＡｌ配線、１４は高濃度ｎ型浮遊拡散層５とＡｌ配線１３を接続するコンタクト、１５はポリシリコン配線１２とＡｌ配線１３を接続するコンタクトである。また、図６中の１６は信号電荷の排出のための高濃度ｎ型拡散層からなるリセットドレイン拡散層、１７はリセット電極である。 In general, the output circuit of such a CCD type solid-state imaging device has a wide range of so-called floating diffusion layer type output circuits in which a signal charge sent from a horizontal charge transfer element is inputted to the floating diffusion layer and its voltage change is detected. It is used. One conventional example of such a floating diffusion layer type output circuit is shown in FIGS. 6 is a plan view, and FIG. 7 is a sectional view taken along line CC ′ in FIG. In FIG. 7, 1 is a low-concentration n-type silicon substrate, 2 is a low-concentration p-type well, 3 is a p-type second well for reducing smear mixed in the vertical charge transfer element, and 4 is a buried channel of the charge transfer element. N-type layer, 5 is a high-concentration n-type floating diffusion layer, 6 is a channel stopper, 7 is an insulating film, 8 is a local oxide film, 9 is a field plate electrode, 10 is an output barrier electrode, 11 is a transfer electrode, 12 Is a polysilicon wiring also serving as the gate electrode of the output transistor, 13 is an Al wiring, 14 is a contact connecting the high-concentration n-type floating diffusion layer 5 and the Al wiring 13, and 15 is a contact connecting the polysilicon wiring 12 and the Al wiring 13. It is. In FIG. 6, 16 is a reset drain diffusion layer made of a high concentration n-type diffusion layer for discharging signal charges, and 17 is a reset electrode.

この浮遊拡散層型出力回路は以下の動作により信号電荷を検出する。まず、リセット電極１７にリセットパルスを印加し浮遊拡散層５の電圧をリセットドレイン拡散層１６に印加されている所定の直流電圧（リセット電圧）と等しい値に設定する。続いて転送電極１１にクロックパルスを印加すると水平電荷転送素子
１０２内を順次転送された信号電荷は、所定の直流電圧が印加された出力障壁電極１０を越えて浮遊拡散層５内に流れ込む。この結果、浮遊拡散層５の電圧は信号電荷の流入によって先の基準電圧よりも△Ｖだけ低下する。この信号電荷による電圧変化はＡｌ配線１３を介して接続された出力トランジスタのゲート電極も兼ねるポリシリコン配線１２の電圧変化として検出される。なお、通例、ホトダイオードで発生する過剰電荷を基板に逃がすために、ｎ型シリコン基板１にはｐ型ウエル２に対して逆バイアスが印加される。 This floating diffusion layer type output circuit detects signal charges by the following operation. First, a reset pulse is applied to the reset electrode 17 to set the voltage of the floating diffusion layer 5 equal to a predetermined DC voltage (reset voltage) applied to the reset drain diffusion layer 16. Subsequently, when a clock pulse is applied to the transfer electrode 11, the horizontal charge transfer element
The signal charges sequentially transferred in the 102 flow into the floating diffusion layer 5 over the output barrier electrode 10 to which a predetermined DC voltage is applied. As a result, the voltage of the floating diffusion layer 5 is lowered by ΔV from the previous reference voltage due to the inflow of signal charges. This voltage change due to the signal charge is detected as a voltage change in the polysilicon wiring 12 which also serves as the gate electrode of the output transistor connected via the Al wiring 13. In general, a reverse bias is applied to the n-type silicon substrate 1 with respect to the p-type well 2 in order to release excess charges generated in the photodiode to the substrate.

さて、このような浮遊拡散層型出力回路における検出感度ηはη＝δＶS ／
δＱS＝１／ＣDで表せる。ここで、δＶSは出力電圧の変化量、δＱSは信号電荷
の変化量、ＣD は検出容量である。従って、検出感度ηを大きくするには検出容量ＣD を小さくしなければならない。図６及び図７に示す浮遊拡散層型出力回路の検出容量ＣD は構成要素に分別すると、図８の等価回路で表せる。図８中の
ＣJ は浮遊拡散層５とｐ型第二ウエル３間の接合容量、ＣOGは浮遊拡散層５と出
力障壁電極１０間の静電容量、ＣRSは浮遊拡散層５とリセット電極１７間の静電容量、ＣL はＡｌ配線１３とフィールドプレート電極９間、或いはｐ型第二ウエル３間の静電容量、およびポリシリコン配線１２とフィールドプレート電極９との静電容量、ＣDGは出力回路部１０１におけるポリシリコン配線１２とｐ型第二ウエル３との静電容量でる。これらの成分のうちＣOGとＣRSの低減法については
、特公昭61−25224 号公報に高濃度ｎ型浮遊拡散層５を出力障壁電極１０，リセット電極１７より隔てて配置する方法が述べられている。一方、ＣJ の低減法については、特開昭59−65470号，特開昭62−33463号公報に浮遊拡散層５直下のｐ型ウエル２を完全に空乏化する方法が述べられている。 Now, the detection sensitivity η in such a floating diffusion layer type output circuit is η = δV S /
It can be expressed by δQ S = 1 / C D. Here, the amount of change .DELTA.V S is the output voltage, .delta.Q S change amount of the signal charge, C D is the detection capacity. Therefore, in order to increase the detection sensitivity η must reduce the detected capacitance C D. Detected capacitance C D of the floating diffusion layer-type output circuit shown in FIG. 6 and 7 when fractionated components, expressed by the equivalent circuit of FIG. In FIG.
C J is the junction capacitance between the floating diffusion layer 5 and the p-type second well 3, C OG is the capacitance between the floating diffusion layer 5 and the output barrier electrode 10, and C RS is between the floating diffusion layer 5 and the reset electrode 17. capacitance, C L is the capacitance between the Al wiring 13 and the field plate electrode 9, or the capacitance between the p-type second well 3, and a polysilicon wiring 12 and the field plate electrode 9, C DG output This is the capacitance between the polysilicon wiring 12 and the p-type second well 3 in the circuit unit 101. The reduction method C OG and C RS of these components, a high concentration n-type floating diffusion layer 5 outputs the guard electrode 10, a method of spaced than the reset electrode 17 described in JP-B-61-25224 ing. On the other hand, as a method for reducing C J , JP-A-59-65470 and JP-A-62-33463 describe a method of completely depleting the p-type well 2 immediately below the floating diffusion layer 5.

しかし、以下の理由により従来の浮遊拡散層型出力回路の検出容量ＣDの低減はいまだに不十分である。 However, it is still insufficient reduction in the detected capacitance C D of the conventional floating diffusion type output circuit for the following reasons.

従来技術では、ＣL の低減方法については何ら考慮されていない。従って、本発明の目的はＣLを低減することにある。 In the prior art, no consideration for the method of reducing C L. Accordingly, an object of the present invention is to reduce the C L.

本発明の目的を達成するための手段として、フィールドプレート電極９を取り去り、かつ、局所酸化膜８直下のチャネルストッパ６とｐ型ウエル２を空乏化した。   As means for achieving the object of the present invention, the field plate electrode 9 was removed, and the channel stopper 6 and the p-type well 2 immediately below the local oxide film 8 were depleted.

本発明の目的を達成するための手段により、ポリシリコン配線１２のチャネルストッパ６上の寄生容量をなくすことができる。   By means for achieving the object of the present invention, the parasitic capacitance on the channel stopper 6 of the polysilicon wiring 12 can be eliminated.

本発明によれば、従来は局所酸化膜８の上に有ったフィールドプレート電極９を取り去って、局所酸化膜８直下のｐ型ウエルをポリシリコン配線１２に加わるリセット電圧と基板電圧により空乏化することでポリシリコン配線１２とＡｌ配線１３の寄生容量をなくすことができる。この結果、検出容量ＣD を大幅に減少させ検出感度の向上が可能となる。 According to the present invention, traditional is removed the field plate electrode 9 there was on the local oxide film 8, the depletion by the reset voltage and the substrate voltage applied to the p-type well immediately below the local oxide film 8 to the polysilicon wiring 12 Therefore, the parasitic capacitance of the polysilicon wiring 12 and the Al wiring 13 can be eliminated. As a result, the detection capacity CD can be greatly reduced, and the detection sensitivity can be improved.

＜実施例１＞
以下、本発明の第一の実施例を図１から図４により説明する。図１は本発明の第一の実施例の電荷検出部周辺の平面図、図２は図１中のＡ−Ａ′の断面図、図３は図１中のＢ−Ｂ′の断面図である。図１中、２３は垂直電荷転送素子に混入するスメアを低減するためのｐ型第二ウエル、２４はｐ型第二ウエル２３内に設けられた電荷転送素子の埋め込みチャネルとなるｎ型層、２５はポリシリコン配線１２とＡｌ配線１３を接続するコンタクトである。図３中の２６は動作時には空乏化するチャネルストッパ層である。 <Example 1>
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a plan view of the periphery of a charge detection unit according to the first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'in FIG. 1, and FIG. 3 is a sectional view taken along line BB' in FIG. is there. In FIG. 1, 23 is a p-type second well for reducing smear mixed in the vertical charge transfer element, 24 is an n-type layer serving as a buried channel of the charge transfer element provided in the p-type second well 23, Reference numeral 25 denotes a contact for connecting the polysilicon wiring 12 and the Al wiring 13. 3 in FIG. 3 is a channel stopper layer that is depleted during operation.

本浮遊拡散層型出力回路は従来例と同様の動作によって信号電荷を検出する。   This floating diffusion layer type output circuit detects signal charges by the same operation as in the conventional example.

本実施例の構造は以下の製造方法により作成される。すなわち、低濃度ｎ型シリコン基板１上に低濃度ｐ型ウエル２をイオン打ち込みと熱拡散により形成する
。次に、局所酸化膜形成領域以外を窒化膜Ａで覆い、ボロンイオン打ち込みによりチャネルストッパ２６を形成し、表面酸化により局所酸化膜８を形成する。先の窒化膜Ａを除去した後、新たな窒化膜Ｂをｐ型第二ウエル２３形成領域以外の部分に形成しイオン打ち込みによりｐ型第二ウエル２３を形成する。このとき、局所酸化膜８が在る領域にはイオン打ち込みはなされない。ついで、先の窒化膜Ｂを残したまま、ｎ型層２４の形成領域以外を新たなホトレジストで覆いｎ型層２４をイオン打ち込みにより形成する。この形成法により、ｐ型第二ウエル２３とｎ型層２４は、窒化膜Ｂもしくは局所酸化膜をマスクとして自己整合的に形成される。 The structure of the present embodiment is created by the following manufacturing method. That is, the low concentration p-type well 2 is formed on the low concentration n-type silicon substrate 1 by ion implantation and thermal diffusion. Next, the region other than the local oxide film formation region is covered with the nitride film A, the channel stopper 26 is formed by implanting boron ions, and the local oxide film 8 is formed by surface oxidation. After removing the previous nitride film A, a new nitride film B is formed in a portion other than the region where the p-type second well 23 is formed, and the p-type second well 23 is formed by ion implantation. At this time, no ion implantation is performed in the region where the local oxide film 8 is present. Next, the n-type layer 24 is formed by ion implantation while covering the region other than the formation region of the n-type layer 24 with a new photoresist while leaving the previous nitride film B. By this formation method, the p-type second well 23 and the n-type layer 24 are formed in a self-aligned manner using the nitride film B or the local oxide film as a mask.

次に、全領域をゲート酸化して絶縁膜７を形成した後第一層目のポリシコンを堆積し、パターニングを行って出力障壁電極１０，ポリシリコン配線１２を形成する。ついで、第二層のポリシコンを堆積とパターニングにより転送電極１１を形成する。この後、浮遊拡散層５を設ける領域外をホトレジストで覆いイオン打ち込みにより浮遊拡散層５を形成する。さらに、りんガラス膜を堆積した後、浮遊拡散層５とＡｌ配線１３を接続するコンタクト１４と、ポリシリコン配線１２とＡｌ配線１３を接続するコンタクト２５を設ける領域外をホトレジストで覆いエッチングにより形成する。次に、Ａｌを堆積してＡｌ配線１３を形成する。   Next, the entire region is gate-oxidized to form the insulating film 7, and then the first layer of polysilicon is deposited and patterned to form the output barrier electrode 10 and the polysilicon wiring 12. Next, a transfer electrode 11 is formed by depositing and patterning a second layer of polysilicon. Thereafter, the outside of the region where the floating diffusion layer 5 is provided is covered with a photoresist, and the floating diffusion layer 5 is formed by ion implantation. Further, after depositing the phosphor glass film, a region outside the region where the contact 14 for connecting the floating diffusion layer 5 and the Al wiring 13 and the contact 25 for connecting the polysilicon wiring 12 and the Al wiring 13 are provided is covered with a photoresist and etched. . Next, Al is deposited to form an Al wiring 13.

本実施例によれば以下の効果がある。第一に、図２に示すようにｐ型第二ウエル２３とｎ型層２４は自己整合で形成される。これにより、ｐ型第二ウエル２３はｎ型浮遊拡散層５に印加されるリセット電圧により拡散層２４の周辺で完全に空乏化し、接合周辺部分の寄生容量をなくすことができる。   According to the present embodiment, there are the following effects. First, as shown in FIG. 2, the p-type second well 23 and the n-type layer 24 are formed in a self-aligned manner. As a result, the p-type second well 23 is completely depleted around the diffusion layer 24 by the reset voltage applied to the n-type floating diffusion layer 5, and the parasitic capacitance in the peripheral portion of the junction can be eliminated.

第二に、図３に示すようにポリシリコン配線１２とＡｌ配線１３を接続するコンタクト２５をｎ型層２４上に形成した。これにより、フィールドプレート電極９上のポリシリコン配線１２の面積を低減しＡｌ配線１３とフィールドプレート電極９間、或いはｐ型第二ウエル２３間の静電容量をなくすことができるので
ＣL を減少できる。一方、本発明の構造によれば浮遊拡散層５と同電位のｎ型層２４の面積は増加するが、ｎ型層２４直下のｐ型第二ウエル２３とｐ型ウエル２を完全に空乏化することにより容量の増加はわずかにできる。従って、検出容量ＣD を低減できる。 Second, a contact 25 for connecting the polysilicon wiring 12 and the Al wiring 13 was formed on the n-type layer 24 as shown in FIG. Thereby, the area of the polysilicon wiring 12 on the field plate electrode 9 can be reduced, and the capacitance between the Al wiring 13 and the field plate electrode 9 or between the p-type second well 23 can be eliminated.
C L can be reduced. On the other hand, according to the structure of the present invention, the area of the n-type layer 24 having the same potential as that of the floating diffusion layer 5 is increased, but the p-type second well 23 and the p-type well 2 immediately below the n-type layer 24 are completely depleted. By doing so, the capacity can be increased slightly. Therefore, it is possible to reduce the detected capacitance C D.

なお、ｎ型層２４直下のｐ型第二ウエル２３，ｐ型ウエル２は特開平3−
289173号公報に述べられているような方法でｐ型第二ウエル２３を０.８μｍ 程度の深さまで浅くすれば、ｎ型基板１に印加される電圧とｎ型浮遊拡散層５に印加されるリセット電圧により容易に空乏化が可能である。 The p-type second well 23 and the p-type well 2 immediately below the n-type layer 24 are disclosed in
If the p-type second well 23 is shallowed to a depth of about 0.8 μm by the method described in Japanese Patent No. 289173, the voltage applied to the n-type substrate 1 and the n-type floating diffusion layer 5 are applied. It can be easily depleted by the reset voltage.

第三に、従来構造のフィールドプレート電極９を取り去って、かつ、局所酸化膜８直下のチャネルストッパ２６とｐ型ウエル２を空乏化した。図４を用いこの点について更に詳しく説明する。図４は図３中に示す局所酸化膜８直下のｐ型ウエル２内部最低電位の局所酸化膜８の幅依存性のシミュレーション結果の一例である。図に示すように、例えば、局所酸化膜８の幅を１.８μｍ 以下とすれば、浮遊拡散層５とポリシリコン配線１２に印加されるリセット電圧とｎ型基板１に印加される逆バイアス電圧により、局所酸化膜８直下のｐ型ウエル２内部電位は０Ｖより大きくなり空乏化することが分かる。従って、ポリシリコン配線１２とｐ型ウエル２間の静電容量をなくすことができる。なお、ポリシリコン配線１２をゲートとして持つトランジスタのチャネルと拡散層２４間の耐圧劣化が生じないようにするためには、素子分離部の最低電位が上記トランジスタのチャネル電圧より低くなるように設定すればよい。
＜実施例２＞
本発明の第二の実施例を図９ないし図１１を参照して説明する。図９は本発明の第二の実施例の電荷検出部周辺の平面図、図１０は図９中のＥ−Ｅ′の断面図
、図１１は図９中のＦ−Ｆ′の断面図である。図９，図１０の中で９１はフィールドプレート電極、９２は水平電荷転送素子のｐ型ウエル２の空乏化を容易にするｎ型ウエルである。 Third, the field plate electrode 9 having a conventional structure was removed, and the channel stopper 26 and the p-type well 2 immediately below the local oxide film 8 were depleted. This point will be described in more detail with reference to FIG. FIG. 4 is an example of a simulation result of the width dependence of the local oxide film 8 at the lowest potential inside the p-type well 2 immediately below the local oxide film 8 shown in FIG. As shown in the figure, for example, if the width of the local oxide film 8 is 1.8 μm or less, the reset voltage applied to the floating diffusion layer 5 and the polysilicon wiring 12 and the reverse bias voltage applied to the n-type substrate 1 are shown. Thus, it can be seen that the internal potential of the p-type well 2 immediately below the local oxide film 8 becomes larger than 0 V and is depleted. Accordingly, the capacitance between the polysilicon wiring 12 and the p-type well 2 can be eliminated. In order to prevent the breakdown voltage degradation between the channel of the transistor having the polysilicon wiring 12 as a gate and the diffusion layer 24, the minimum potential of the element isolation portion is set to be lower than the channel voltage of the transistor. That's fine.
<Example 2>
A second embodiment of the present invention will be described with reference to FIGS. 9 is a plan view of the periphery of the charge detection portion of the second embodiment of the present invention, FIG. 10 is a cross-sectional view taken along line EE ′ in FIG. 9, and FIG. 11 is a cross-sectional view taken along line FF ′ in FIG. is there. 9 and 10, reference numeral 91 is a field plate electrode, and 92 is an n-type well that facilitates depletion of the p-type well 2 of the horizontal charge transfer element.

本実施例は第一の実施例に水平電荷転送素子の空乏化を容易とし転送効率を上げるためのｎ型ウエル９２を設けたものである。しかし、この結果、ｎ型層２４とｎ型シリコン基板１間のパンチスルー耐圧がｎ型層の周辺で劣化するという弊害が生じる。そこで、フィールドプレート電極９１をｎ型層２４の周辺に設けてアイソレーション性能の向上を図った。なお、ｎ型層２４から所定の距離を隔ててフィールドプレート電極９を配置すればｎ型層２４から伸びる空乏層を十分に伸ばすことができるためｎ型層２４周辺の寄生容量は生じない。従って、本実施例によれば検出容量ＣD の低減効果は第一の実施例とほぼ同程度にでき、水平電荷転送素子の転送効率向上との両立ができる。
＜実施例３＞
本発明の第三の実施例を図１２により説明する。本図は第一の実施例の図１のＢ−Ｂ′に対応する部分の断面図である。１２６は素子分離のためのｐ型拡散層
、その他の符号は第一の実施例と同様である。本実施例では第一の実施例の局所酸化膜８を取り去り、かつ、ｐ型第二ウエル２３より濃度の濃いｐ型拡散層126だけで素子分離を行うものである。従って、本実施例の動作は第一の実施例と同じである。本実施例によれば局所酸化膜の形成工程をなくすことができる。 In this embodiment, an n-type well 92 is provided in order to facilitate the depletion of the horizontal charge transfer element and increase the transfer efficiency in the first embodiment. However, as a result, there arises an adverse effect that the punch-through breakdown voltage between the n-type layer 24 and the n-type silicon substrate 1 deteriorates around the n-type layer. Therefore, the field plate electrode 91 is provided around the n-type layer 24 to improve the isolation performance. If the field plate electrode 9 is arranged at a predetermined distance from the n-type layer 24, the depletion layer extending from the n-type layer 24 can be sufficiently extended, so that no parasitic capacitance around the n-type layer 24 is generated. Therefore, the effect of reducing the detected capacitance C D according to the present embodiment can nearly equalized in the first embodiment, it is compatible with the transfer efficiency of the horizontal charge transfer device.
<Example 3>
A third embodiment of the present invention will be described with reference to FIG. This figure is a sectional view of a portion corresponding to BB 'in FIG. 1 of the first embodiment. Reference numeral 126 denotes a p-type diffusion layer for element isolation, and the other symbols are the same as those in the first embodiment. In this embodiment, the local oxide film 8 of the first embodiment is removed, and element isolation is performed only by the p-type diffusion layer 126 having a concentration higher than that of the p-type second well 23. Therefore, the operation of this embodiment is the same as that of the first embodiment. According to this embodiment, the step of forming the local oxide film can be eliminated.

さて、以上の実施例ではＣＣＤ型撮像素子の浮遊拡散層型出力回路の検出感度向上のために、寄生容量を低減する三つの方法について述べた。一方、寄生容量は、全ての集積回路で動作速度や検出感度を制限する原因である。既述した三つの方法は、全ての集積回路の寄生容量低減効果があることは言うまでもない。特に、配線層下のウエルを空乏化する第三の方法は、広く適応が可能である。以下
、ＣＣＤ型撮像素子の配線遅延、ＭＯＳ型撮像素子の配線遅延と感度向上のために本発明の第三の手段を適応した例を述べる。
＜実施例４＞
本発明の第四の実施例を図１３により説明する。図１３は図５のＤ−Ｄ′の断面図である。図１３中、１９はｎ型光電変換層、２０は高濃度ｐ型暗電流抑圧層
、２１は垂直電荷転送素子の下層ポリシリコン配線、２２は垂直電荷転送素子の上層ポリシリコン配線、９３は画素部全領域に設けられｎ型光電変換層１９からｎ型基板１への過剰電荷の掃きだしを低い印加電圧で行うための第一のｎ型ウエル、９４は二つのｎ型光電変換層の分離を可能とするための第二のｎ型ウエルである。 In the above embodiment, three methods for reducing the parasitic capacitance have been described in order to improve the detection sensitivity of the floating diffusion layer type output circuit of the CCD type image pickup device. On the other hand, parasitic capacitance is a cause of limiting the operation speed and detection sensitivity in all integrated circuits. Needless to say, the three methods described above have the effect of reducing the parasitic capacitance of all integrated circuits. In particular, the third method for depleting the well under the wiring layer can be widely applied. An example in which the third means of the present invention is applied to improve the wiring delay of the CCD image sensor, the wiring delay of the MOS image sensor, and the sensitivity will be described below.
<Example 4>
A fourth embodiment of the present invention will be described with reference to FIG. 13 is a cross-sectional view taken along the line DD ′ of FIG. In FIG. 13, 19 is an n-type photoelectric conversion layer, 20 is a high-concentration p-type dark current suppression layer, 21 is a lower polysilicon wiring of the vertical charge transfer element, 22 is an upper polysilicon wiring of the vertical charge transfer element, and 93 is a pixel. The first n-type well 94 is provided in the entire region for sweeping excess charges from the n-type photoelectric conversion layer 19 to the n-type substrate 1 with a low applied voltage, and 94 separates the two n-type photoelectric conversion layers. A second n-type well to enable.

本構造は以下の製造方法により作成される。低濃度ｎ型シリコン基板１上に低濃度ｐ型ウエル２と第一のｎ型ウエル９３をイオン打ち込みと熱拡散により形成する。次に、局所酸化膜８の形成領域をホトレジストで覆い、イオン打ち込みと熱拡散により第二のｎ型ウエル９４を形成する。ついで、局所酸化膜８の形成領域以外を窒化膜Ａで覆い、まず、ボロンイオン打ち込みによりチャネルストッパ６を形成し、続けて表面酸化により局所酸化膜８を形成する。先の窒化膜Ａを除去した後、新たな窒化膜Ｂをパターニングし局所酸化膜の形成領域から所定の距離を離してｎ型光電変換層１９をイオン打ち込みと熱拡散により形成する。次に、全領域をゲート酸化して絶縁膜７を形成した後、第一層目のポリシコンを堆積し、パターニングを行って垂直電荷転送素子の下層ポリシリコン配線２１を形成する。ついで、全領域を再びゲート酸化して絶縁膜７を形成した後、第二層目のポリシコンを堆積し、前記と同様に上層ポリシリコン配線２２を形成する。最後に、先に形成された下層ポリシリコン配線２１をマスクにして高濃度ｐ型暗電流抑圧層２０をイオン打ち込みと熱拡散により形成する。 This structure is created by the following manufacturing method. A low-concentration p-type well 2 and a first n-type well 93 are formed on the low-concentration n-type silicon substrate 1 by ion implantation and thermal diffusion. Next, the formation area of local oxide film 8 covered with a photoresist to form the second n-type well 94 by ion implantation and thermal diffusion. Next, the region other than the region where the local oxide film 8 is formed is covered with the nitride film A. First, the channel stopper 6 is formed by boron ion implantation, and then the local oxide film 8 is formed by surface oxidation. After the previous nitride film A is removed, a new nitride film B is patterned , and an n-type photoelectric conversion layer 19 is formed by ion implantation and thermal diffusion at a predetermined distance from the local oxide film formation region. Next, the entire region is gate-oxidized to form the insulating film 7, and then the first-layer polysilicon is deposited and patterned to form the lower polysilicon wiring 21 of the vertical charge transfer element. Next, the entire region is gate-oxidized again to form the insulating film 7, and then the second-layer polysilicon is deposited, and the upper polysilicon wiring 22 is formed in the same manner as described above. Finally, the high-concentration p-type dark current suppression layer 20 is formed by ion implantation and thermal diffusion using the previously formed lower polysilicon wiring 21 as a mask.

本実施例では、第一のｎ型ウエル９３がｎ型シリコン基板１側から表面に空乏層が伸びるのを容易にしている。また、第二のｎ型ウエル９４が横方向に拡散しチャネルストッパ６のｐ型層の濃度を打ち消し、局所酸化膜８下の表面はｎ型化している。この結果、下層ポリシリコン配線２１に加わえられる駆動時のパルス電圧が通例負値の低電圧ＶL よりもわずかに高い電圧で局所酸化膜８下のｐ型反転層がなくなりｎ型シリコン基板１まで全半導体領域が空乏化し、下層ポリシリコン配線２１のｐ型ウエル２に対する静電容量をなくすことができる。これにより、垂直転送素子の時定数が減少し駆動が容易となり高速駆動が可能となる。 In this embodiment, the first n-type well 93 makes it easy for the depletion layer to extend from the n-type silicon substrate 1 side to the surface. Further, the second n-type well 94 diffuses in the lateral direction to cancel the concentration of the p-type layer of the channel stopper 6 and the surface under the local oxide film 8 is made n-type. As a result, the p-type inversion layer under the local oxide film 8 disappears when the pulse voltage at the time of driving applied to the lower polysilicon wiring 21 is slightly higher than the low voltage V L which is usually a negative value. Thus, the entire semiconductor region is depleted, and the capacitance of the lower polysilicon wiring 21 to the p-type well 2 can be eliminated. As a result, the time constant of the vertical transfer element is reduced, driving becomes easy, and high-speed driving is possible.

なお、ｎ型光電変換層１９より広く高濃度なｐ型暗電流抑圧層２０を形成することにより、図中Ｘ点の電位障壁の高さをＹ点の電位障壁の高さより高くでき、過剰な信号電荷は直ちにｎ型シリコン基板１に排出され隣接画素に流れ込むことはない。さらに、第二のｎ型ウエル９４を形成するためのイオン打ち込みを局所酸化膜１８の形成領域には行わないことにより上述した隣接画素間の分離は更に強化される。   In addition, by forming the p-type dark current suppressing layer 20 wider and higher in concentration than the n-type photoelectric conversion layer 19, the height of the potential barrier at the point X in the figure can be made higher than the height of the potential barrier at the point Y. The signal charge is immediately discharged to the n-type silicon substrate 1 and does not flow into adjacent pixels. Further, the above-described separation between adjacent pixels is further strengthened by not performing ion implantation for forming the second n-type well 94 in the region where the local oxide film 18 is formed.

さらに、本発明はＭＯＳ型固体撮像装置の配線遅延低減や感度向上にも有効である。以下、図１４から図１６を用いて説明する。図１４はＭＯＳ型撮像素子の回路構成を示す一例、図１５は図１４のＨ−Ｈ′部の断面図、図１６はＧ−Ｇ′部の断面図である。図１４中の２０１は垂直シフトレジスタ、２０２は水平シフトレジスタ、２０３は水平信号線、２０４は水平スイッチ、２０５は垂直ゲート線、２０６は垂直スイッチ、２０７はホトダイオード、２０８はＡｌ垂直信号線である。本素子では垂直シフトレジスタ２０１で選択された垂直ゲート線２０５に接続されている垂直スイッチ２０６がオンしてホトダイオード２０７に蓄積されている信号電荷をＡｌ垂直信号線２０８に読み出す。ついで、水平シフトレジスタ２０２選択信号により水平スイッチ２０４が順次オン・オフして垂直信号線２０８の信号電荷を順次水平信号線２０３に読み出す。   Furthermore, the present invention is effective for reducing wiring delay and improving sensitivity of the MOS type solid-state imaging device. Hereinafter, description will be made with reference to FIGS. FIG. 14 is an example showing the circuit configuration of the MOS type image pickup device, FIG. 15 is a cross-sectional view taken along the line H-H 'in FIG. 14, and FIG. 16 is a cross-sectional view taken along the line GG'. 14, 201 is a vertical shift register, 202 is a horizontal shift register, 203 is a horizontal signal line, 204 is a horizontal switch, 205 is a vertical gate line, 206 is a vertical switch, 207 is a photodiode, and 208 is an Al vertical signal line. . In this element, the vertical switch 206 connected to the vertical gate line 205 selected by the vertical shift register 201 is turned on, and the signal charge accumulated in the photodiode 207 is read to the Al vertical signal line 208. Next, the horizontal switch 204 is sequentially turned on / off by the horizontal shift register 202 selection signal, and the signal charges on the vertical signal lines 208 are sequentially read out to the horizontal signal lines 203.

このようなＭＯＳ型固体撮像装置における第一の課題はＡｌ垂直信号線２０８とウエル間の寄生容量により信号が大きく減少し、ＳＮが劣化することである。
＜実施例５＞
図１５はこの課題を解決する本発明の第五の実施例である。図１５中の５１はｎ型基板、５２はｐ型ウエル、５３はｎ型受光層、５４は高濃度ｐ型暗電流抑圧層、５５は絶縁膜、５６は局所酸化膜、５７はｎ型ウエル、２０８はＡｌ垂直信号線である。Ａｌ垂直信号線２０８は正電圧にバイアスされ、ｎ型受光層５３のリセット時ｎ型層はＡｌ垂直信号線２０８のバイアス電圧に等しい。 The first problem in such a MOS type solid-state imaging device is that the signal is greatly reduced due to the parasitic capacitance between the Al vertical signal line 208 and the well, and the SN is deteriorated.
<Example 5>
FIG. 15 shows a fifth embodiment of the present invention for solving this problem. 15, 51 is an n-type substrate, 52 is a p-type well, 53 is an n-type light-receiving layer, 54 is a high-concentration p-type dark current suppressing layer, 55 is an insulating film, 56 is a local oxide film, and 57 is an n-type well. 208 are Al vertical signal lines. The Al vertical signal line 208 is biased to a positive voltage, and when the n-type light receiving layer 53 is reset, the n-type layer is equal to the bias voltage of the Al vertical signal line 208.

本実施例ではｎ型ウエル５７を設けることにより、ｎ型シリコン基板５１に印加する正電圧とＡｌ垂直信号線２０８に印加される正バイアスによって、Ａｌ垂直信号線２０８下からｎ型シリコン基板５１までの半導体領域は空乏化する。この結果、垂直信号線２０８のｐ型ウエル５２に対する静電容量がなくなり、垂直信号線２０８の寄生容量が減少するため出力電圧の増大が可能となる。なお、第四の実施例で述べたと同様に、ｎ型受光層５３より広く高濃度ｐ型暗電流抑圧層５４を形成することにより、過剰な信号電荷が画素部に流れ込むことがない。さらに、この構造により形成される図中Ｚ点の電位障壁によりＡｌ垂直信号線２０８下に発生する暗電流はｎ型受光層５３に流れ込むことなくｎ型シリコン基板５１に排出されるので空乏化に伴う暗電流の増加を防ぐことができる。
＜実施例６＞
また、ＭＯＳ型素子でもＣＣＤ型撮像素子の垂直電荷転送素子の場合と同様に配線遅延が問題となる。この問題を解決する第六の実施例を図１６により説明する図１６中の２０５は垂直ゲート線である。ホトダイオード２０７から信号を読み出すときに垂直ゲート線２０５は正電圧にバイアスされる。ｎ型受光層５３のリセット時ｎ型層はＡｌ垂直信号線２０８のバイアス電圧に等しい。本実施例ではｎ型ウエル５７を設けることにより、ｎ型シリコン基板５１に印加する正電圧と垂直ゲート線２０５に印加される正バイアスによって、垂直ゲート線２０５下からｎ型基板５１までの半導体領域は空乏化する。この結果、垂直ゲート線２０５のｐ型ウエル５２に対する静電容量をなくすことができる。これにより、垂直ゲート線２０５の時定数が減少し高速駆動が可能となり、垂直シフトレジスタ２０１のドライバ回路の負担が軽減される効果がある。さらに、本発明を水平信号線２０３下の構造に適応した場合、水平信号線２０３の寄生容量が減少して出力電圧の増大が可能となる。 In this embodiment, by providing the n-type well 57, from the bottom of the Al vertical signal line 208 to the n-type silicon substrate 51 by the positive voltage applied to the n-type silicon substrate 51 and the positive bias applied to the Al vertical signal line 208. The semiconductor region is depleted. As a result, the capacitance of the vertical signal line 208 with respect to the p-type well 52 is eliminated, and the parasitic capacitance of the vertical signal line 208 is reduced, so that the output voltage can be increased. As described in the fourth embodiment, by forming the high-concentration p-type dark current suppression layer 54 wider than the n-type light receiving layer 53, excessive signal charges do not flow into the pixel portion. Further, the dark current generated under the Al vertical signal line 208 is discharged to the n-type silicon substrate 51 without flowing into the n-type light-receiving layer 53 due to the potential barrier at the point Z in the figure formed by this structure. The accompanying increase in dark current can be prevented.
<Example 6>
Further, in the MOS type element, wiring delay becomes a problem as in the case of the vertical charge transfer element of the CCD type image pickup element. A sixth embodiment for solving this problem will be described with reference to FIG. 16. In FIG. 16, reference numeral 205 denotes a vertical gate line. When reading a signal from the photodiode 207, the vertical gate line 205 is biased to a positive voltage. When the n-type light receiving layer 53 is reset, the n-type layer is equal to the bias voltage of the Al vertical signal line 208. In this embodiment, by providing the n-type well 57, the semiconductor region from the bottom of the vertical gate line 205 to the n-type substrate 51 by the positive voltage applied to the n-type silicon substrate 51 and the positive bias applied to the vertical gate line 205. Is depleted. As a result, the electrostatic capacitance with respect to the p-type well 52 of the vertical gate line 205 can be eliminated. As a result, the time constant of the vertical gate line 205 is reduced, high speed driving is possible, and the burden on the driver circuit of the vertical shift register 201 is reduced. Furthermore, when the present invention is applied to the structure under the horizontal signal line 203, the parasitic capacitance of the horizontal signal line 203 is reduced, and the output voltage can be increased.

なお、第五，第六の実施例で、第四の実施例と同様にチヤネルストッパと第二のｎ型ウェルを形成し素子分離をより確実にすることもできる。   In the fifth and sixth embodiments, a channel stopper and a second n-type well can be formed similarly to the fourth embodiment to further ensure element isolation.

本発明の第一の実施例を示す固体撮像装置における電荷検出部周辺の平面図。1 is a plan view around a charge detection unit in a solid-state imaging device showing a first embodiment of the present invention. 図１中のＡ−Ａ′の断面図。Sectional drawing of AA 'in FIG. 図１中のＢ−Ｂ′の断面図。Sectional drawing of BB 'in FIG. 局所酸化膜直下のｐ型ウエル内部電位の局所酸化膜の幅Ｗ依存性の電位解析の一例の説明図。Explanatory drawing of an example of the electric potential analysis of the width W dependence of the local oxide film of the p-type well internal potential directly under a local oxide film. インターライン転送方式のＣＣＤ型固体撮像装置のブロック図。1 is a block diagram of an interline transfer type CCD solid-state imaging device. FIG. 従来の固体撮像装置における電荷検出部周辺の平面図。The top view of the electric charge detection part periphery in the conventional solid-state imaging device. 図６中のＣ−Ｃ′の断面図。Sectional drawing of CC 'in FIG. 電荷検出部の対地静電容量を示す等価回路図。FIG. 6 is an equivalent circuit diagram illustrating a ground capacitance of the charge detection unit. 本発明の第二の実施例を示す固体撮像装置における電荷検出部周辺の平面図。The top view of the electric charge detection part periphery in the solid-state imaging device which shows the 2nd Example of this invention. 図９のＥ−Ｅ′の断面図。Sectional drawing of EE 'of FIG. 図９のＦ−Ｆ′の断面図。Sectional drawing of FF 'of FIG. 本発明の第三の実施例を示す固体撮像装置における電荷検出部周辺の断面図。Sectional drawing of the charge detection part periphery in the solid-state imaging device which shows the 3rd Example of this invention. 本発明の第四の実施例を示す図５中の垂直転送レジスタ配線Ｄ−Ｄ´の断面図。Sectional drawing of the vertical transfer register wiring DD 'in FIG. 5 which shows the 4th Example of this invention. ＭＯＳ型固体撮像装置のブロック図。The block diagram of a MOS type solid-state imaging device. 本発明の第五の実施例を示す図１４中のＨ−Ｈ´部の断面図。Sectional drawing of the HH 'part in FIG. 14 which shows the 5th Example of this invention. 本発明の第六の実施例を示す図１４中のＧ−Ｇ´部の断面図。Sectional drawing of the GG 'part in FIG. 14 which shows the 6th Example of this invention.

符号の説明Explanation of symbols

１、５１・・ｎ型基板、２、５２・・ｐ型ウエル、５・・高濃度ｎ型浮遊拡散層、６、２６・・チャネルストッパ、１２６・・素子分離のためのｐ型拡散層、７、５５・・絶縁膜、８、１８、５６・・局所酸化膜、１０・・出力障壁電極、１２、２１・・ポリシリコン配線、１６・・垂直ゲート線、１３、２０８・・Ａｌ配線、１４、２５・・コンタクト、１６・・高濃度ｎ型リセットドレイン拡散層、１７・・リセット電極、２３・・ｐ型第二ウエル、２４・・ｎ型層、５７、９３・・ｎ型ウエル、９４・・第二のｎ型ウエル。
1, 51... N-type substrate , 2 , 52... P-type well, 5... High-concentration n-type floating diffusion layer, 6 , 26. 7, 55, ... Insulating film, 8, 18 , 56 ... Local oxide film, 10 ... Output barrier electrode, 12, 21 ... Polysilicon wiring, 16 ... Vertical gate line , 13, 208 ... Al wiring, 14 , 25 ... Contact, 16... High concentration n-type reset drain diffusion layer, 17... Reset electrode, 23... P-type second well, 24... N-type layer, 57 , 93. 94 .. Second n-type well.

Claims (3)

第１導電型の半導体基板と、該第一導電型の半導体基板上に設けられた第二導電型のウエルと、該第二導電型のウエル上に設けられた絶縁膜を半導体表面に有する素子分離部と、該素子分離部の該絶縁膜上に選択回路により選択され、信号電荷の読み出される配線を具備した固体撮像装置において、前記素子分離部の該絶縁膜下の前記第二導電型のウエル表面に第一導電型のウエルが形成され、前記第二導電型のウエルに対し前記第一導電型の半導体基板にはホトダイオードで発生する過剰電荷排出のための逆バイアスが印加され、前記配線に前記逆バイアスと同極性の電圧が印加され、該配線直下の該素子分離部の該絶縁膜と前記第一導電型の半導体基板間における前記第二導電型のウエルを含む半導体領域が空乏化することを特徴とする固体撮像装置。   An element having a semiconductor substrate having a first conductivity type semiconductor substrate, a second conductivity type well provided on the first conductivity type semiconductor substrate, and an insulating film provided on the second conductivity type well. In a solid-state imaging device including a separation unit and a wiring on which the signal charge is read out and selected by the selection circuit on the insulating film of the element separation unit, the second conductivity type below the insulation film of the element separation unit A well of a first conductivity type is formed on the surface of the well, and a reverse bias is applied to the semiconductor substrate of the first conductivity type with respect to the second conductivity type well to discharge excess charges generated by a photodiode, A voltage having the same polarity as the reverse bias is applied to the semiconductor region including the second conductivity type well between the insulating film of the element isolation portion and the first conductivity type semiconductor substrate immediately below the wiring. It is characterized by Body imaging apparatus. 前記素子分離部は半導体表面にチャネルストッパを備え、該チャネルストッパ下に横方向拡散により形成された第一導電型の第二のｎウエルを有することを特徴とする請求項１に記載の固体撮像装置。 2. The solid-state imaging according to claim 1 , wherein the element isolation part includes a channel stopper on a semiconductor surface, and has a second n-well of the first conductivity type formed by lateral diffusion under the channel stopper. apparatus. 第１導電型の半導体基板と、該第一導電型の半導体基板上に設けられた第二導電型のウエルと、該第二導電型のウエル上に設けられた絶縁膜を半導体表面に有する素子分離部と、該素子分離部の該絶縁膜上に電荷転送素子を駆動するための配線を具備した固体撮像装置において、前記素子分離部の該絶縁膜下の前記第二導電型のウエル表面に第一導電型のウエルが形成され、前記素子分離部は半導体表面にチャネルストッパを備え、該チャネルストッパ下に横方向拡散により形成された第一導電型の第二のｎウエルを有し、前記第二導電型のウエルに対し前記第一導電型の半導体基板にはホトダイオードで発生する過剰電荷排出のための逆バイアスが印加され、前記配線には前記分離部表面に第二導電型層が形成されない駆動パルス電圧が印加され、前記配線直下の該素子分離部の該絶縁膜と前記第一導電型の半導体基板間における前記第二導電型のウエルを含む半導体領域が空乏化することを特徴とする固体撮像装置。   An element having a semiconductor substrate having a first conductivity type semiconductor substrate, a second conductivity type well provided on the first conductivity type semiconductor substrate, and an insulating film provided on the second conductivity type well. In a solid-state imaging device having an isolation portion and a wiring for driving a charge transfer element on the insulating film of the element isolation portion, the surface of the second conductivity type well under the insulating film of the element isolation portion A well of a first conductivity type is formed, the element isolation portion includes a channel stopper on a semiconductor surface, and has a second n well of the first conductivity type formed by lateral diffusion under the channel stopper; A reverse bias is applied to the semiconductor substrate of the first conductivity type for discharging the excess charge generated by the photodiode with respect to the well of the second conductivity type, and a second conductivity type layer is formed on the surface of the separation portion of the wiring. Drive pulse voltage that is not Is, the solid-state imaging apparatus characterized by depleted semiconductor region including the second conductivity type well between the semiconductor substrate of the device separation section the insulating film and the first conductivity type directly under the wiring.
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