JP4211642B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4211642B2
JP4211642B2 JP2004065972A JP2004065972A JP4211642B2 JP 4211642 B2 JP4211642 B2 JP 4211642B2 JP 2004065972 A JP2004065972 A JP 2004065972A JP 2004065972 A JP2004065972 A JP 2004065972A JP 4211642 B2 JP4211642 B2 JP 4211642B2
Authority
JP
Japan
Prior art keywords
region
semiconductor
polycrystalline silicon
impurity concentration
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004065972A
Other languages
Japanese (ja)
Other versions
JP2005259797A (en
Inventor
哲也 林
正勝 星
秀明 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2004065972A priority Critical patent/JP4211642B2/en
Priority to US10/898,224 priority patent/US7138668B2/en
Priority to EP04017889.9A priority patent/EP1503425B1/en
Publication of JP2005259797A publication Critical patent/JP2005259797A/en
Application granted granted Critical
Publication of JP4211642B2 publication Critical patent/JP4211642B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

本発明は半導体装置に関する。   The present invention relates to a semiconductor device.

本発明の背景となる従来技術として、本出願人が出願した特開２００３−３１８４１３号公報がある。
上記の従来技術は、Ｎ＋型の炭化珪素基板領域上にＮ−型のエピタキシャル領域が形成された半導体基体の一主面にＮ型の多結晶シリコン領域が接するように形成されており、エピタキシャル領域とＮ型の多結晶シリコン領域とはヘテロ接合をしている。また、Ｎ＋型炭化珪素基板領域の裏面には裏面電極が形成されている。
上記のような構成の従来技術は、裏面電極をカソード、多結晶シリコン領域をアノードとして両方の間に電圧を印加すると、多結晶シリコン領域とエピタキシャル領域の接合界面において整流作用が生じ、ダイオード特性が得られる。
例えば、カソードを接地してアノードに正電位を印加した場合は、ダイオードの順方向特性に相当する導通特性が得られ、アノードに負電位を印加した場合は、ダイオードの逆方向特性に相当する阻止特性が得られ、順方向特性および逆方向特性ともに金属電極と半導体材料から構成されるショットキー接合のごとき特性を示す。
従来技術においては、多結晶シリコン領域の不純物濃度や導電型を変えることで、例えば所定の逆方向特性（それに応じた順方向特性）を有するダイオードを任意に調整できるため、ショットキー接合によるダイオードに比べて、必要に応じて最適な耐圧系に調整できるという利点を持つ。 As a prior art which is the background of the present invention, there is JP-A-2003-318413 filed by the present applicant.
The above prior art is formed so that an N-type polycrystalline silicon region is in contact with one main surface of a semiconductor substrate in which an N − -type epitaxial region is formed on an N + -type silicon carbide substrate region. The region and the N-type polycrystalline silicon region are in a heterojunction. A back electrode is formed on the back surface of the N + type silicon carbide substrate region.
In the conventional technology configured as described above, when a voltage is applied between the back electrode as a cathode and the polycrystalline silicon region as an anode, a rectifying action occurs at the junction interface between the polycrystalline silicon region and the epitaxial region, and the diode characteristics are reduced. can get.
For example, when a positive potential is applied to the anode with the cathode grounded, a conduction characteristic corresponding to the forward characteristic of the diode is obtained, and when a negative potential is applied to the anode, a blocking characteristic corresponding to the reverse characteristic of the diode is obtained. Characteristics are obtained, and both forward characteristics and reverse characteristics are characteristics such as a Schottky junction composed of a metal electrode and a semiconductor material.
In the prior art, by changing the impurity concentration and conductivity type of the polycrystalline silicon region, for example, a diode having a predetermined reverse characteristic (forward characteristic corresponding thereto) can be arbitrarily adjusted. In comparison, it has the advantage that it can be adjusted to the optimum pressure resistance system as required.

特開２００３−３１８４１３号公報JP 2003-318413 A

しかし、従来構造においては、単に多結晶シリコンを用いてヘテロ接合を形成するだけなので、逆方向特性の漏れ電流特性がショットキー接合ダイオードと同様の傾向を示し、ショットキー接合とは異なる高い遮断性能や温度特性を引き出すことができなかった。
本発明は、上記のような従来技術の問題を解決するためになされたものであり、ショットキー接合ダイオードとは異なる高い遮断性能と高温に強い特性を引き出すことが可能な半導体装置を提供することを目的とする。 However, in the conventional structure, since the heterojunction is simply formed using polycrystalline silicon, the leakage current characteristic of the reverse direction characteristic tends to be the same as that of the Schottky junction diode, and the high cutoff performance is different from that of the Schottky junction. And temperature characteristics could not be extracted.
The present invention has been made in order to solve the above-described problems of the prior art, and provides a semiconductor device capable of extracting a high cut-off performance different from a Schottky junction diode and a characteristic resistant to high temperatures. With the goal.

上記の問題を解決するため、本発明においては、第一導電型の第一の半導体領域（例えば図１の炭化珪素半導体基体１００に相当）と、前記第一の半導体領域とはバンドギャップが異なり、かつ前記第一の半導体領域とヘテロダイオードを形成する第二の半導体領域（例えば図１の多結晶シリコン層１０１に相当）とを有し、少なくとも前記第二の半導体領域の所定領域が第二導電型からなり、前記ヘテロダイオードに逆バイアスを印加したときに、前記所定領域の一部は空乏化しないように不純物濃度や前記所定領域の厚み等を構成している。   In order to solve the above problem, in the present invention, the first conductivity type first semiconductor region (e.g., corresponding to the silicon carbide semiconductor substrate 100 of FIG. 1) and the first semiconductor region have different band gaps. And a second semiconductor region (for example, corresponding to the polycrystalline silicon layer 101 in FIG. 1) forming a hetero diode, and at least a predetermined region of the second semiconductor region is a second region. It is of a conductive type, and has an impurity concentration, a thickness of the predetermined region, etc. so that a part of the predetermined region is not depleted when a reverse bias is applied to the hetero diode.

第一の半導体領域を第一導電型とした場合に、第二の半導体領域の所定領域を第二導電型とし、さらに、第二の半導体領域の一部は空乏化しないように、不純物濃度および第二の半導体領域の厚み等を構成することで、順方向特性はショットキー接合ダイオードのごとく、逆方向特性はＰＮ接合ダイオードのごとく動作する。つまり、順方向特性は第一の半導体領域および第二の半導体領域に広がるそれぞれの内蔵電位から決まる電圧降下の和で電流を流すことができるため、従来構造（例えばショットキー接合ダイオード）と同等の特性を得ることができる。
また、逆方向特性となる遮断時においては、第二の半導体領域側からの伝導電子の供給元を抑えることができるため、ヘテロ接合界面のヘテロ障壁を介して生じる漏れ電流を大幅に低減することができる。つまり、従来構造で得られたショットキー接合と同様な漏れ電流特性とはならずに、本発明の構成では、ＰＮ接合ダイオードに見られるような所定の電界下で発生するキャリアによる漏れ電流特性を観測できるほど、低い漏れ電流特性を得られる。これは数値計算によって確認している。
さらに、第二の半導体領域側の空乏化していない部分の厚みが第二の半導体領域における電子の拡散長よりも大きくなるようにすることで、さらに漏れ電流が低減される。このことから、より高い温度での動作が可能となる。 When the first semiconductor region is the first conductivity type, the predetermined region of the second semiconductor region is the second conductivity type, and further, the impurity concentration and the second semiconductor region are not depleted. By configuring the thickness of the second semiconductor region and the like, the forward characteristics operate like a Schottky junction diode and the reverse characteristics operate like a PN junction diode. In other words, since the forward characteristic can flow a current with the sum of the voltage drops determined from the respective built-in potentials extending in the first semiconductor region and the second semiconductor region, it is equivalent to the conventional structure (for example, a Schottky junction diode). Characteristics can be obtained.
In addition, at the time of shut-off with reverse characteristics, the supply source of conduction electrons from the second semiconductor region side can be suppressed, so that leakage current generated through the hetero barrier at the heterojunction interface can be greatly reduced. Can do. That is, the leakage current characteristic similar to that of the Schottky junction obtained in the conventional structure is not obtained, but the structure of the present invention has a leakage current characteristic due to carriers generated under a predetermined electric field as seen in a PN junction diode. The lower the leakage current characteristics, the more observable. This is confirmed by numerical calculation.
Furthermore, the leakage current is further reduced by making the thickness of the non-depleted portion on the second semiconductor region side larger than the electron diffusion length in the second semiconductor region. This allows operation at higher temperatures.

（実施例１）
図１は本発明による半導体装置の実施例１の断面図である。本実施例においては、炭化珪素を基板材料とした半導体装置を一例として説明する。
例えば炭化珪素のポリタイプが４ＨタイプのＮ＋型である炭化珪素基板１上にＮ−型のエピタキシャル領域２が形成された炭化珪素半導体基体１００を用いている。炭化珪素基板１としては、例えば抵抗率が数ｍΩｃｍから数１０ｍΩｃｍ、厚さが２００〜４００μｍ程度のものを用いることができる。エピタキシャル領域２としては、例えばＮ型の不純物濃度が１０１５〜１０１８ｃｍ−３、厚みが数μｍ〜数１０μｍのものを用いることができるが、本実施例では不純物濃度が１０１６ｃｍ−３、厚みが１０μｍのものを用いた場合で説明する。なお、本実施例１では、一例として炭化珪素基板１上にエピタキシャル領域２を形成した炭化珪素半導体基体１００で説明するが、抵抗率の大きさに関わらず炭化珪素基板１のみで形成された基板を使用してもかまわない。 Example 1
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. In this embodiment, a semiconductor device using silicon carbide as a substrate material will be described as an example.
For example, a silicon carbide semiconductor substrate 100 in which an N − type epitaxial region 2 is formed on a silicon carbide substrate 1 in which the polytype of silicon carbide is a 4H type N + type is used. As silicon carbide substrate 1, for example, a substrate having a resistivity of several mΩcm to several tens of mΩcm and a thickness of about 200 to 400 μm can be used. As the epitaxial region 2, for example, an N-type impurity concentration of 10 15 to 10 18 cm −3 and a thickness of several μm to several tens of μm can be used. In this embodiment, the impurity concentration is 10 16 cm −3. A case where a thickness of 10 μm is used will be described. In the first embodiment, the silicon carbide semiconductor substrate 100 having the epitaxial region 2 formed on the silicon carbide substrate 1 will be described as an example, but the substrate formed only by the silicon carbide substrate 1 regardless of the resistivity. Can be used.

エピタキシャル領域２の炭化珪素基板１との接合面に対向する主面（図１においてエピタキシャル領域２の上面）に接するように、第二の半導体領域の一例として炭化珪素よりもバンドギャップの小さい第一の多結晶シリコン領域３（多結晶シリコン層１０１）が堆積されている。第一の多結晶シリコン領域３には不純物が導入されており、ここではＰ型高濃度にドープされている。また、本実施例では、一例として第一の多結晶シリコン領域３の不純物濃度が１０１８ｃｍ−３、厚みが０.５μｍとした場合で説明する。 As an example of the second semiconductor region, the first having a band gap smaller than that of silicon carbide so as to be in contact with the main surface (upper surface of epitaxial region 2 in FIG. 1) facing the bonding surface of epitaxial region 2 with silicon carbide substrate 1. The polycrystalline silicon region 3 (polycrystalline silicon layer 101) is deposited. Impurities are introduced into the first polycrystalline silicon region 3, and here, the first polycrystalline silicon region 3 is doped at a high P-type concentration. In the present embodiment, the case where the first polycrystalline silicon region 3 has an impurity concentration of 10 18 cm −3 and a thickness of 0.5 μm will be described as an example.

エピタキシャル領域２と第一の多結晶シリコン領域３の接合部は、炭化珪素と多結晶シリコンのバンドギャップが異なる材料によるヘテロ接合からなっており、その接合界面には、図１１のエネルギーバンド図に示すようなエネルギー障壁が存在している。また、本実施例においては炭化珪素基板１の裏面側には裏面金属電極４が形成されている。裏面金属電極４は炭化珪素基板１とオーミック接続されており、金属材料としては、例えばＴｉ（チタン）厚さ５０００Åとその上にＮｉ（ニッケル）厚さ３０００Åを堆積したもの等を用いることができる。   The junction between epitaxial region 2 and first polycrystalline silicon region 3 is made of a heterojunction made of materials having different band gaps between silicon carbide and polycrystalline silicon, and the junction interface is shown in the energy band diagram of FIG. There are energy barriers as shown. In the present embodiment, a back metal electrode 4 is formed on the back side of the silicon carbide substrate 1. The back metal electrode 4 is ohmically connected to the silicon carbide substrate 1, and as the metal material, for example, a Ti (titanium) thickness of 5000 mm and a Ni (nickel) thickness of 3000 mm deposited thereon can be used. .

上記のように、本実施例１では多結晶シリコン層１０１をアノード、裏面金属電極４をカソードとした縦型のダイオードを構成する場合について説明する。本実施例においては、説明を判りやすくするために多結晶シリコン層１０１をアノードとして簡単な構成としているが、図２に示すように、例えば多結晶シリコン層１０１の端部への電界集中を防止するための電界緩和領域５を形成したり、多結晶シリコン層１０１の表面に表面金属電極６を形成していても良い。   As described above, in the first embodiment, a case in which a vertical diode having the polycrystalline silicon layer 101 as an anode and the back metal electrode 4 as a cathode will be described. In this embodiment, the polycrystalline silicon layer 101 is used as an anode for easy understanding, but as shown in FIG. 2, for example, electric field concentration at the end of the polycrystalline silicon layer 101 is prevented. For this purpose, the electric field relaxation region 5 may be formed, or the surface metal electrode 6 may be formed on the surface of the polycrystalline silicon layer 101.

次に、本実施例の動作について説明する。
裏面金属電極４をカソード、第一の多結晶シリコン領域３をアノードとして両方の間に電圧を印加すると、第一の多結晶シリコン領域３と炭化珪素のエピタキシャル領域２の接合界面において整流作用が生じ、ダイオード特性が得られる。
まず、アノードを接地電位としカソードに負電位を印加すると、ヘテロ接合界面のエネルキーバンド図は、図１２の破線から実線のように推移する。図１２に示すように、カソード側から供給される電子にとってはヘテロ接合界面に形成されるエネルギー障壁が減少するため、電子はカソード側からアノード側へと流れるのに対し、アノード側から供給される正孔にとっては、ヘテロ接合界面に形成されているエネルギー障壁が残るため、アノード側からカソード側には供給されない。よって、アノード側においては、カソード側から供給された電子がアノード側で供給される正孔と対消滅することで順方向電流が流れる。このように、順方向特性は、本実施の形態においては、アノード側の電流主成分が正孔であり、カソード側の電流主成分が電子であるという、ショットキーダイオードとは異なる性質を有するものの、外見的にはカソード側に正孔が注入されない多数キャリアデバイスとして従来構造並びにショットキー接合ダイオードのごとく動作する。つまり、順方向特性はヘテロ接合部からエピタキシャル領域２および第一の多結晶シリコン領域３にそれぞれ広がる内蔵電位の和から決まる電圧降下で電流を流すことができる。例えば本実施例においては、ヘテロ接合部からエピタキシャル領域２および第一の多結晶シリコン領域３にそれぞれ広がる内蔵電位の和が約１.３Ｖであり、それに応じた電圧降下で順方向電流が流れる。 Next, the operation of this embodiment will be described.
When a voltage is applied between the back metal electrode 4 as a cathode and the first polycrystalline silicon region 3 as an anode, a rectifying action is produced at the junction interface between the first polycrystalline silicon region 3 and the silicon carbide epitaxial region 2. , Diode characteristics can be obtained.
First, when the anode is grounded and a negative potential is applied to the cathode, the energy band diagram of the heterojunction interface changes from a broken line to a solid line in FIG. As shown in FIG. 12, for electrons supplied from the cathode side, the energy barrier formed at the heterojunction interface decreases, so that electrons flow from the cathode side to the anode side, whereas they are supplied from the anode side. For holes, the energy barrier formed at the heterojunction interface remains, so that it is not supplied from the anode side to the cathode side. Therefore, on the anode side, a forward current flows as electrons supplied from the cathode side annihilate with holes supplied on the anode side. Thus, in this embodiment, the forward characteristic is different from a Schottky diode in that the current main component on the anode side is holes and the current main component on the cathode side is electrons. Apparently, it operates like a conventional structure and a Schottky junction diode as a majority carrier device in which holes are not injected into the cathode side. In other words, the forward characteristic allows a current to flow with a voltage drop determined by the sum of the built-in potentials extending from the heterojunction portion to the epitaxial region 2 and the first polycrystalline silicon region 3 respectively. For example, in this embodiment, the sum of the built-in potentials extending from the heterojunction portion to the epitaxial region 2 and the first polycrystalline silicon region 3 is about 1.3 V, and a forward current flows with a corresponding voltage drop.

次に、アノードを接地電位としてカソードに正電位を印加すると、ヘテロ接合界面のエネルキーバンド図は、図１３の破線の熱平衡状態から実線のように推移し、いわゆる逆バイアス状態となる。図１３に示すように、アノード側のヘテロ接合界面には、第一の多結晶シリコン領域３がＰ型の高不純物濃度で形成されているため、電子が欠乏状態となっているために、ヘテロ接合界面に形成されるエネルギー障壁を介して流れる電子電流が発生しにくい。また、カソード側のヘテロ接合界面においては、エピタキシャル領域２がＮ型でワイドギャップな炭化珪素で形成されているため、正孔が欠乏状態となっているために、アノード側に流れる正孔電流が発生しにくい。このように、本実施の形態の逆方向特性は、図７に示すように、ＰＮ接合ダイオードのごとく動作する。
これは従来構造がショットキー接合ダイオードのような漏れ電流特性を示すのとは大きく異なる。本発明の構成では、後述するように、ＰＮ接合ダイオードに見られるような所定の電界下で発生するキャリアによる漏れ電流特性が優勢になるぐらいに、ヘテロ接合界面のヘテロ障壁を介して生じる漏れ電流を大幅に低減することが可能となる。この本実施の形態で示したヘテロ接合が上述した動作メカニズムを取ることを発見し、数値計算によって明らかにしたのは我々が最初である。 Next, when a positive potential is applied to the cathode with the anode as the ground potential, the energy band diagram of the heterojunction interface changes from the thermal equilibrium state indicated by the broken line in FIG. 13 to a solid line, which is a so-called reverse bias state. As shown in FIG. 13, since the first polycrystalline silicon region 3 is formed at a high impurity concentration of P-type at the heterojunction interface on the anode side, electrons are in a deficient state. Electron current that flows through the energy barrier formed at the junction interface is unlikely to occur. In addition, at the heterojunction interface on the cathode side, since the epitaxial region 2 is formed of N-type and wide gap silicon carbide, the hole current is deficient. Hard to occur. Thus, the reverse characteristic of the present embodiment operates as a PN junction diode as shown in FIG.
This is significantly different from the conventional structure that exhibits leakage current characteristics like a Schottky junction diode. In the configuration of the present invention, as will be described later, the leakage current generated through the hetero barrier at the heterojunction interface is such that leakage current characteristics due to carriers generated under a predetermined electric field as seen in a PN junction diode become dominant. Can be greatly reduced. We first discovered that the heterojunction shown in this embodiment adopts the above-mentioned operation mechanism and made it clear by numerical calculation.

以下、逆方向特性について詳細に説明する。
ショットキー接合ダイオードの逆方向特性は、半導体材料の電子親和力とショットキー金属の仕事関数の差によって形成されるショットキー障壁の高さでほぼ一義的に決まる。しかし、従来構造や本実施例におけるヘテロ接合ダイオードは、大きく分けて下記３つの要素で逆方向特性が決まる。
第１は、ショットキー接合と同様に、それぞれの半導体材料の電子親和力の差によって形成されたヘテロ障壁の高さによって決定される多数キャリア（ここでは電子）の逆阻止能力である。
第２は、漏れ電流の起源となる多数キャリアの発生源によって決まる漏れ電流供給能力である。
第３は、ヘテロ接合ダイオードに印加された電圧が、各々の半導体材料の誘電率や不純物濃度によって双方の半導体材料への電位分配が決まる耐圧保持能力である。本実施例においては、互いに関連する上記第２と第３の要件に特徴を有する。 Hereinafter, the reverse characteristics will be described in detail.
The reverse characteristics of the Schottky junction diode are determined almost uniquely by the height of the Schottky barrier formed by the difference between the electron affinity of the semiconductor material and the work function of the Schottky metal. However, the conventional structure and the heterojunction diode in this embodiment can be roughly divided into the following three elements to determine the reverse characteristics.
The first is the reverse blocking ability of majority carriers (here, electrons) determined by the height of the heterobarrier formed by the difference in electron affinity of each semiconductor material, similar to the Schottky junction.
The second is the leakage current supply capability determined by the generation source of majority carriers that is the source of the leakage current.
The third is a withstand voltage holding capability in which the voltage applied to the heterojunction diode determines the potential distribution to both semiconductor materials depending on the dielectric constant and impurity concentration of each semiconductor material. This embodiment is characterized by the second and third requirements related to each other.

第１の逆阻止能力は、本実施例の場合、炭化珪素からなるエピタキシャル領域２および第一の多結晶シリコン領域３の各々の半導体材料によってほぼ決まるため、従来構造と同等の性能を有する。   In the case of the present embodiment, the first reverse blocking capability is almost determined by the respective semiconductor materials of the epitaxial region 2 made of silicon carbide and the first polycrystalline silicon region 3, and therefore has the same performance as the conventional structure.

次に、第２の漏れ電流供給能力は、本実施例の場合、従来構造に比べて格段に小さくなっている。つまり、Ｎ型のエピタキシャル領域２にとって多数キャリアとなる伝導電子が第一の多結晶シリコン領域３で発生しにくいように、伝導電子の発生起源を抑える構成となっている。すなわち、第一の多結晶シリコン領域３をＰ型で形成し、かつ、第一の多結晶シリコン領域３の一部は空乏化しないような不純物濃度や厚みなどで構成されている。前者に関しては、第一の多結晶シリコン領域３自体が伝導電子の供給源にならないことに寄与しており、後者に関しては、第一の多結晶シリコン領域３が全域空乏化して例えば図２などに示すような表面金属電極６からの伝導電子の供給が行われないように、少なくともアノード側の伝導電子供給源と分断することに寄与している。さらに、第一の多結晶シリコン領域の空乏化せずに残っている領域の厚みが、第一の多結晶シリコン領域における電子の拡散長より大きい場合は、より一層、電子の供給源から分断できる。   Next, in the case of the present embodiment, the second leakage current supply capability is much smaller than that of the conventional structure. That is, the generation of conduction electrons is suppressed so that conduction electrons that become majority carriers in the N type epitaxial region 2 are less likely to be generated in the first polycrystalline silicon region 3. That is, the first polycrystalline silicon region 3 is formed in a P-type, and a part of the first polycrystalline silicon region 3 is configured with an impurity concentration and a thickness so as not to be depleted. Regarding the former, it contributes to the fact that the first polycrystalline silicon region 3 itself does not become a source of conduction electrons, and regarding the latter, the first polycrystalline silicon region 3 is depleted throughout, for example in FIG. This contributes to separation from the conduction electron supply source on the anode side so that conduction electrons are not supplied from the surface metal electrode 6 as shown. Further, when the thickness of the first polycrystalline silicon region remaining undepleted is larger than the electron diffusion length in the first polycrystalline silicon region, it can be further separated from the electron supply source. .

さらに、第３の耐圧保持能力という観点では、バンドギャップが狭い半導体材料側（ここでは第一の多結晶シリコン領域３側）での所定の電界下で発生するキャリアを抑制する効果を有しており、例えば第一の多結晶シリコン領域３にてアバランシェ降伏が起こりにくい構造となっている。ヘテロ接合を形成するそれぞれの半導体領域に電位分配される割合は、耐圧保持能力に大きく影響し、半導体材料の誘電率や不純物濃度で概ね決まる。例えば誘電率が同等であれば、同程度の不純物濃度の場合概ね半分ずつ印加される。すなわち、バンドギャップが大きく所定の電界下で発生するキャリアが小さいエピタキシャル領域２の特性を生かすためには、少なくともカソード／アノード間に印加される電位差の半分以上をエピタキシャル領域２にて保持する必要が有り、第一の多結晶シリコン領域３の不純物濃度をエピタキシャル領域２の不純物濃度に比べて同等以上にすることで効果を得ることができる。   Furthermore, from the viewpoint of the third breakdown voltage holding capability, it has the effect of suppressing carriers generated under a predetermined electric field on the semiconductor material side (here, the first polycrystalline silicon region 3 side) with a narrow band gap. For example, an avalanche breakdown is unlikely to occur in the first polycrystalline silicon region 3. The ratio of potential distribution to each semiconductor region forming the heterojunction greatly affects the withstand voltage holding capability, and is generally determined by the dielectric constant and impurity concentration of the semiconductor material. For example, if the dielectric constant is the same, approximately half is applied when the impurity concentration is about the same. That is, in order to take advantage of the characteristics of the epitaxial region 2 having a large band gap and a small number of carriers generated under a predetermined electric field, it is necessary to hold at least half of the potential difference applied between the cathode and the anode in the epitaxial region 2. The effect can be obtained by setting the impurity concentration of the first polycrystalline silicon region 3 to be equal to or higher than the impurity concentration of the epitaxial region 2.

さらに、エピタキシャル領域２の耐圧保持力をさらに生かすためには、電位分配される割合が、各材料の臨界電界強度の比率以上にエピタキシャル領域２に電位が分配されることでさらに効果を得ることができる。
このことから、本実施例においては、例えばエピタキシャル領域２の不純物濃度が１０１６ｃｍ−３、厚みが１０μｍとしているのに対して、第一の多結晶シリコン領域３の不純物濃度が１０１８ｃｍ−３、厚みが０.５μｍとしている。このとき、本実施例においてカソード／アノード間に１０００Ｖの電圧を印加した場合を数値計算すると、第一の多結晶シリコン領域３に拡がる電位差は高々１０Ｖ以下となり、電界の広がりも０.２μｍ程度となる。つまり、９９０Ｖはエピタキシャル領域２にて電圧を保持していることになる。ここでは、第一の多結晶シリコン領域３の不純物濃度が１０１８ｃｍ−３の場合を一例として示しているが、第一の多結晶シリコン領域３の不純物濃度が高いほど、上記本実施の形態における３つの要件とも、より高い遮断性を実現する方向に作用するため、遮断性を向上するには、第一の多結晶シリコン領域３の不純物濃度は高いほうが良い。 Furthermore, in order to further utilize the withstand voltage holding force of the epitaxial region 2, it is possible to obtain further effects by distributing the potential to the epitaxial region 2 so that the potential distribution ratio is higher than the ratio of the critical electric field strength of each material. it can.
Therefore, in this embodiment, an impurity concentration of 10 16 cm -3 in the epitaxial region 2, whereas the thickness is set to 10 [mu] m, the impurity concentration of the first polysilicon region 3 10 18 cm - 3 and the thickness is 0.5 μm. At this time, when a voltage of 1000 V is applied between the cathode and the anode in this embodiment, the potential difference spreading to the first polycrystalline silicon region 3 is at most 10 V and the electric field spread is about 0.2 μm. Become. That is, 990 V holds the voltage in the epitaxial region 2. Here, the case where the impurity concentration of the first polycrystalline silicon region 3 is 10 18 cm −3 is shown as an example. However, the higher the impurity concentration of the first polycrystalline silicon region 3 is, the above-described embodiment. Since the three requirements in (1) act in the direction of realizing higher blocking properties, the impurity concentration of the first polycrystalline silicon region 3 is preferably higher in order to improve the blocking properties.

上記のように、ショットキー接合ダイオードのごとく耐圧保持をエピタキシャル領域２にて行い、かつ、第一の多結晶シリコン領域３側における伝導電子の発生を抑えることで漏れ電流特性を劇的に改善している。そのため、本実施例を数値計算した結果をみてみると、図７に示したように、逆方向特性がＰＮ接合のように、所定の電界下で発生するキャリアによって漏れ電流が決まるような波形が得られている。このことから、本実施例においては、常温での漏れ電流を抑えることができるため、より高い温度での動作も可能となる。   As described above, withstand voltage is maintained in the epitaxial region 2 like a Schottky junction diode, and the leakage current characteristics are dramatically improved by suppressing the generation of conduction electrons on the first polycrystalline silicon region 3 side. ing. Therefore, looking at the result of numerical calculation of this example, as shown in FIG. 7, there is a waveform in which the leakage current is determined by carriers generated in a predetermined electric field, such as a PN junction, as shown in FIG. Has been obtained. Therefore, in this embodiment, since the leakage current at normal temperature can be suppressed, operation at a higher temperature is possible.

以上、説明したように、本実施例においては、エピタキシャル領域２がＮ型の場合には、第一の多結晶シリコン領域３をＰ型に限定し、かつ、一部が空乏化しない構成とすることで漏れ電流を低減している。また、漏れ電流の発生する割合が小さいエピタキシャル領域２の特性を最低限生かすために、第一の多結晶シリコン領域３の不純物濃度をエピタキシャル領域２の不純物濃度と同等以上とし、さらに、エピタキシャル領域２の耐圧保持力をさらに生かすためには、エピタキシャル領域２と第一の多結晶シリコン領域３の臨界電界強度の比率以上にエピタキシャル領域２に電位が分配される構成としている。また、第一の多結晶シリコン領域の空乏化せずに残っている領域の厚みが、第一の多結晶シリコン領域における電子の拡散長より大きくなるようにしている。   As described above, in this embodiment, when the epitaxial region 2 is N-type, the first polycrystalline silicon region 3 is limited to P-type and a part thereof is not depleted. This reduces the leakage current. Further, in order to make the best use of the characteristics of the epitaxial region 2 in which the rate of occurrence of leakage current is small, the impurity concentration of the first polycrystalline silicon region 3 is made equal to or higher than the impurity concentration of the epitaxial region 2, and further, the epitaxial region 2 In order to make further use of the withstand voltage holding power, the potential is distributed to the epitaxial region 2 at a ratio higher than the ratio of the critical electric field strength between the epitaxial region 2 and the first polycrystalline silicon region 3. Further, the thickness of the region remaining without depletion of the first polycrystalline silicon region is set to be larger than the diffusion length of electrons in the first polycrystalline silicon region.

このように構成することで、ヘテロ接合ダイオードのアノード／カソード間に逆バイアスを印加した場合に、第一の多結晶シリコン領域３からの電子の供給が劇的に減り、少なくとも逆方向漏れ電流特性がＰＮ接合のごとく、所定電界により発生するキャリアが主因の漏れ電流特性が得られる構成となるため、漏れ電流が大きく減少する。   With this configuration, when a reverse bias is applied between the anode / cathode of the heterojunction diode, the supply of electrons from the first polycrystalline silicon region 3 is drastically reduced, and at least reverse leakage current characteristics are obtained. As in the case of a PN junction, since the leakage current characteristic mainly due to carriers generated by a predetermined electric field can be obtained, the leakage current is greatly reduced.

つまり、本実施の形態は外見的な順方向特性はショットキーダイオードと同等でありながら、逆方向特性はＰＮ接合と同様の漏れ電流メカニズムもつため、ショットキーダイオードに比べて漏れ電流が小さいという特徴を有する。   That is, this embodiment has the characteristic that the forward characteristic is the same as that of the Schottky diode, but the reverse characteristic has the same leakage current mechanism as that of the PN junction, and therefore the leakage current is smaller than that of the Schottky diode. Have

なお、図１および図２においては、多結晶シリコン層１０１が第一の多結晶シリコン領域３単一の導電型および不純物濃度にて説明してきたが、例えば図８や図３のように多結晶シリコン領域３とは導電型もしくは不純物濃度が異なる第二の多結晶シリコン領域７を有していても良い。つまり、第一の多結晶シリコン領域３と第二の多結晶シリコン領域７とで多結晶シリコン層１０１を構成している場合である。上記第二の多結晶シリコン領域７はＰ型もしくはＮ型のどちらでもあって良いし、不純物濃度も第一の多結晶シリコン領域３よりも大きくても小さくても良い。いずれにしても、ヘテロ接合ダイオードの構成の中に、少なくとも一部でも本実施例で説明した構成が含まれていれば、効果をもたらすことが可能である。   In FIGS. 1 and 2, the polycrystalline silicon layer 101 has been described with the first polycrystalline silicon region 3 having a single conductivity type and impurity concentration. For example, as shown in FIGS. The silicon region 3 may have a second polycrystalline silicon region 7 having a different conductivity type or impurity concentration. That is, the first polycrystalline silicon region 3 and the second polycrystalline silicon region 7 constitute the polycrystalline silicon layer 101. The second polycrystalline silicon region 7 may be either P-type or N-type, and the impurity concentration may be larger or smaller than that of the first polycrystalline silicon region 3. In any case, if at least a part of the configuration of the heterojunction diode includes the configuration described in this embodiment, it is possible to bring about an effect.

なお、図３は、図２の構成において、第一の多結晶シリコン領域３の一部を第二の多結晶シリコン領域７にした構造であるが、図１の構成において、図３のように第一の多結晶シリコン領域３の一部を第二の多結晶シリコン領域７にした構造も勿論可能である。
また、図８に示すように、第一の多結晶シリコン領域３と表面金属電極６との間に第二の多結晶シリコン領域７を設けた構造のように、積層する形状で導電型および不純物濃度が異なっていても良い。また、図８とは逆に、第一の多結晶シリコン領域３を表面金属電極６とで挟みこむように、第二の多結晶シリコン領域７を第一の多結晶シリコン領域３の下に形成していても良い。上記第二の多結晶シリコン領域７はＰ型もしくはＮ型のどちらでもあって良いし、不純物濃度も第一の多結晶シリコン領域３よりも大きくても小さくても良い。いずれにしても、本発明で発見した動作特性を発揮する構成が含まれていれば、同様の効果をもたらすことが可能である。 3 shows a structure in which a part of the first polycrystalline silicon region 3 is replaced with a second polycrystalline silicon region 7 in the configuration of FIG. 2, but in the configuration of FIG. Of course, a structure in which a part of the first polycrystalline silicon region 3 is the second polycrystalline silicon region 7 is also possible.
Further, as shown in FIG. 8, the conductive type and impurity are formed in a stacked shape as in the structure in which the second polycrystalline silicon region 7 is provided between the first polycrystalline silicon region 3 and the surface metal electrode 6. The concentration may be different. In contrast to FIG. 8, the second polycrystalline silicon region 7 is formed under the first polycrystalline silicon region 3 so that the first polycrystalline silicon region 3 is sandwiched between the surface metal electrodes 6. May be. The second polycrystalline silicon region 7 may be either P-type or N-type, and the impurity concentration may be larger or smaller than that of the first polycrystalline silicon region 3. In any case, the same effect can be obtained as long as the configuration that exhibits the operation characteristics discovered in the present invention is included.

（実施例２）
図４は本発明による半導体装置の実施例２の断面図であり、実施例１の図２に対応した図である。本実施例においては、図２と同様の動作をする部分の説明は省略し、異なる特徴ついて詳しく説明する。
図４では図２で示したヘテロ接合ダイオードのヘテロ接合界面の一部に、ゲート絶縁膜９を介してゲート電極８を形成し、所謂トランジスタを構成している。図４に示すように、本実施例においてはエピタキシャル領域２に溝を形成した構成としているが、溝を形成しないいわゆるプレーナ型の構成でもかまわない。 (Example 2)
4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, corresponding to FIG. 2 of the first embodiment. In the present embodiment, the description of the same operation as in FIG. 2 is omitted, and different features will be described in detail.
In FIG. 4, a gate electrode 8 is formed on a part of the heterojunction interface of the heterojunction diode shown in FIG. 2 via a gate insulating film 9 to form a so-called transistor. As shown in FIG. 4, in this embodiment, a groove is formed in the epitaxial region 2, but a so-called planar type structure in which no groove is formed may be used.

次に動作を説明する。本実施例においては、例えば表面電極６を接地し、裏面金属電極４に正電位を印加して使用する。
まず、ゲート電極８を例えば接地電位もしくは負電位とした場合は、遮断状態を保持する。すなわち、第一の多結晶シリコン領域３とエピタキシャル領域２とのヘテロ接合界面には、それぞれ伝導電子に対するエネルギー障壁が形成されているためである。このとき、本実施例においては、実施例１で説明したように、漏れ電流特性が所定の電界下で発生するキャリアが主因となる程小さくなるように構成をしているため、より高い遮断性を保持できると共に、漏れ電流の温度特性が非常に小さいという効果を有している。 Next, the operation will be described. In this embodiment, for example, the front electrode 6 is grounded and a positive potential is applied to the back metal electrode 4 for use.
First, when the gate electrode 8 is set to a ground potential or a negative potential, for example, the cut-off state is maintained. That is, energy barriers for conduction electrons are formed at the heterojunction interface between the first polycrystalline silicon region 3 and the epitaxial region 2. At this time, in the present embodiment, as described in the first embodiment, since the leakage current characteristic is configured to become smaller as the main cause is a carrier generated under a predetermined electric field, higher blocking performance is achieved. Can be maintained, and the temperature characteristic of the leakage current is very small.

次に、遮断状態から導通状態へと転じるべくゲート電極８に正電位を印加した場合は、ゲート絶縁膜９を介して第一の多結晶シリコン領域３とエピタキシャル領域２が接するヘテロ接合界面までゲート電界が及ぶため、ゲート電極８近傍の第一の多結晶シリコン領域３およびエピタキシャル領域２には伝導電子の反転層が形成される。すなわち、ゲート電極８近傍の第一の多結晶シリコン領域３とエピタキシャル領域２との接合界面における第一の多結晶シリコン領域３側のポテンシャルが押し下げられ、かつ、エピタキシャル領域２側のエネルギー障壁が急峻になることからエネルギー障壁中を伝導電子が導通することが可能となる。   Next, when a positive potential is applied to the gate electrode 8 so as to change from the cutoff state to the conduction state, the gate is connected to the heterojunction interface where the first polycrystalline silicon region 3 and the epitaxial region 2 are in contact via the gate insulating film 9. Since an electric field is applied, an inversion layer of conduction electrons is formed in the first polycrystalline silicon region 3 and the epitaxial region 2 in the vicinity of the gate electrode 8. That is, the potential on the first polycrystalline silicon region 3 side at the junction interface between the first polycrystalline silicon region 3 near the gate electrode 8 and the epitaxial region 2 is pushed down, and the energy barrier on the epitaxial region 2 side is steep. Therefore, conduction electrons can be conducted through the energy barrier.

図４においては、一例として表面金属電極６とエピタキシャル領域２とを第一の多結晶シリコン領域３を介して、ゲート電極８（絶縁膜９を介して）でつなぐ構造を示しているが、図５に示すように、表面金属電極６と第一の多結晶シリコン領域３との間に、第二の多結晶シリコン領域７を介していても良い。つまり第一の多結晶シリコン領域３と第二の多結晶シリコン領域７とで多結晶シリコン層１０１を構成している場合である。上記の第二の多結晶シリコン領域７の導電型および不純物濃度はいずれでも良いが、例えばＮ型の高不純物濃度とすれば、伝導電子の供給が行いやすい。   FIG. 4 shows a structure in which the surface metal electrode 6 and the epitaxial region 2 are connected by the gate electrode 8 (via the insulating film 9) through the first polycrystalline silicon region 3 as an example. As shown in FIG. 5, a second polycrystalline silicon region 7 may be interposed between the surface metal electrode 6 and the first polycrystalline silicon region 3. That is, the first polycrystalline silicon region 3 and the second polycrystalline silicon region 7 constitute the polycrystalline silicon layer 101. The second polycrystalline silicon region 7 may have any conductivity type and impurity concentration. However, for example, if the N-type high impurity concentration is used, conduction electrons can be easily supplied.

また、図６に示すように、ゲート電極８にゲート絶縁膜９を介して接する多結晶シリコン領域を第三の多結晶シリコン領域１０で形成してもよい。この場合には第一の多結晶シリコン領域３と第二の多結晶シリコン領域７と第三の多結晶シリコン領域１０とで多結晶シリコン層１０１を構成している。上記の第三の多結晶シリコン領域１０の導電型および不純物濃度はいずれでも良いが、例えばＰ型で第一の多結晶シリコン領域よりも低不純物濃度で形成すれば、電流が導通するチャネル部がより反転しやすくなり、さらに駆動力が向上する。   Further, as shown in FIG. 6, a polycrystalline silicon region that is in contact with the gate electrode 8 through the gate insulating film 9 may be formed by a third polycrystalline silicon region 10. In this case, the first polycrystalline silicon region 3, the second polycrystalline silicon region 7, and the third polycrystalline silicon region 10 constitute a polycrystalline silicon layer 101. The third polycrystalline silicon region 10 may have any conductivity type and impurity concentration. For example, if the third polycrystalline silicon region 10 is P-type and formed with a lower impurity concentration than the first polycrystalline silicon region, a channel portion through which current is conducted can be obtained. It becomes easier to reverse, and the driving force is further improved.

次に導通状態から遮断状態に移行すべく、再びゲート電極８を接地電位にすると、第一の多結晶シリコン領域３およびエピタキシャル領域２のヘテロ接合界面に形成されていた伝導電子の反転状態が解除され、エネルギー障壁中のトンネリングが止まる。そして、第一の多結晶シリコン領域３からエピタキシャル領域２への伝導電子の流れが止まり、さらにエピタキシャル領域２中にあった伝導電子は炭化珪素基板１に流れ枯渇すると、エピタキシャル領域２側にはヘテロ接合部から空乏層が広がり遮断状態となる。   Next, when the gate electrode 8 is set to the ground potential again to shift from the conductive state to the cut-off state, the inversion state of the conduction electrons formed at the heterojunction interface between the first polycrystalline silicon region 3 and the epitaxial region 2 is released. And tunneling in the energy barrier stops. Then, when the flow of conduction electrons from the first polycrystalline silicon region 3 to the epitaxial region 2 stops and further, the conduction electrons in the epitaxial region 2 flow to the silicon carbide substrate 1 and are depleted, the heterojunction is formed on the epitaxial region 2 side. A depletion layer spreads from the junction and enters a cut-off state.

また、本実施例においては、従来構造と同様に、例えば表面金属電極６を接地し、裏面金属電極４に負電位が印加された逆方向導通（還流動作）も可能である。
例えば表面金属電極６およびゲート電極８を接地電位とし、裏面金属電極４に所定の正電位が印加されると、伝導電子に対するエネルギー障壁は消滅し、エピタキシャル領域２側から第一の多結晶シリコン領域３側に伝導電子が流れ、逆導通状態となる。このとき、正孔の注入はなく伝導電子のみで導通するため、逆導通状態から遮断状態に移行する際の逆回復電流による損失も小さい。
なお、上述したゲート電極８を接地にせずに制御電極として使用する場合も可能である。 Further, in this embodiment, as in the conventional structure, for example, reverse conduction (reflux operation) in which the front surface metal electrode 6 is grounded and a negative potential is applied to the back surface metal electrode 4 is also possible.
For example, when the front surface metal electrode 6 and the gate electrode 8 are set to the ground potential and a predetermined positive potential is applied to the back surface metal electrode 4, the energy barrier to the conduction electrons disappears, and the first polycrystalline silicon region is formed from the epitaxial region 2 side. Conduction electrons flow to the side 3 and reverse conduction is established. At this time, since there is no injection of holes and conduction is performed only with conduction electrons, loss due to reverse recovery current when shifting from the reverse conduction state to the cutoff state is small.
It is also possible to use the gate electrode 8 described above as a control electrode without being grounded.

このように、本実施例においては一例としてヘテロ接合部をゲート駆動するスイッチ素子（トランジスタ）の一部に実施例１で説明した漏れ電流低減機構を使用した場合を説明してきたが、図９または図１０のようなスイッチ素子の一部に内蔵された還流ダイオードとして使用しても良い。
図９は炭化珪素からなるＭＯＳＦＥＴにヘテロダイオードが内蔵された構成をしており、第一導電型の炭化珪素基板１１およびエピタキシャル領域１２からなる半導体基体に、第二導電型のベース領域１３と第一導電型のソース領域１４が形成されており、エピタキシャル領域１２とベース領域１３とソース領域１４の上面に接するようにゲート絶縁膜１５を介してゲート電極１６が形成されている。また、ベース領域１３とソース領域１４はソース電極１７に接続されており、炭化珪素基板１１はドレイン電極１８に接続されている。さらに、エピタキシャル領域１２とはバンドギャップが異なり、例えば多結晶シリコンからなる第一の多結晶シリコン領域１９がエピタキシャル領域１２とヘテロ接合を形成するように配置されている。この第一の多結晶シリコン領域１９はソース電極１７に接続されている。このように、ＭＯＳＦＥＴの内蔵還流ダイオードとして用いられた場合においても、前述の通り、遮断状態におけるヘテロ接合部での漏れ電流を大幅に低減することができるため、遮断性が高く、高温動作に強い半導体装置を提供することができる。 As described above, in the present embodiment, as an example, the case where the leakage current reducing mechanism described in the first embodiment is used for a part of the switch element (transistor) that drives the heterojunction is described. You may use as a free-wheeling diode incorporated in a part of switch elements like FIG.
FIG. 9 shows a structure in which a hetero diode is built in a MOSFET made of silicon carbide, and a second conductive type base region 13 and a second conductive type are formed on a semiconductor substrate made of a first conductive type silicon carbide substrate 11 and an epitaxial region 12. A source region 14 of one conductivity type is formed, and a gate electrode 16 is formed through a gate insulating film 15 so as to be in contact with the upper surfaces of the epitaxial region 12, the base region 13, and the source region 14. Base region 13 and source region 14 are connected to source electrode 17, and silicon carbide substrate 11 is connected to drain electrode 18. Further, the band gap is different from that of the epitaxial region 12, and the first polycrystalline silicon region 19 made of, for example, polycrystalline silicon is arranged so as to form a heterojunction with the epitaxial region 12. The first polycrystalline silicon region 19 is connected to the source electrode 17. Thus, even when used as a built-in free-wheeling diode of a MOSFET, as described above, the leakage current at the heterojunction in the cut-off state can be greatly reduced, so that the cut-off property is high and the high-temperature operation is strong. A semiconductor device can be provided.

図１０においても同様であり、炭化珪素からなるJＦＥＴ（ソース領域２４と第一の多結晶シリコン領域２９は奥行き方向に交互に形成されている）にヘテロダイオードが内蔵された構成で還流ダイオードとして用いられた場合、遮断状態におけるヘテロ接合部での漏れ電流を大幅に低減することができるため、遮断性が高く、高温動作に強い半導体装置を提供することができる。なお、図１０において、２１は炭化珪素基板、２２はエピタキシャル領域、２３はベース領域、２４はソース領域、２５は絶縁膜、２６はゲート電極、２７はソース電極、２８はドレイン電極、２９は第一の多結晶シリコン領域である。
以上のように、いずれにしても、トランジスタを構成する各部において、少なくとも一部でも本実施例で説明した第一の多結晶シリコン領域が含まれていれば、漏れ電流低減の効果をもたらすことが可能である。 The same applies to FIG. 10, which is used as a free-wheeling diode in a configuration in which a heterodiode is incorporated in a JFET made of silicon carbide (the source region 24 and the first polycrystalline silicon region 29 are alternately formed in the depth direction). In this case, since the leakage current at the heterojunction portion in the cut-off state can be significantly reduced, it is possible to provide a semiconductor device that has a high cut-off property and is resistant to high-temperature operation. In FIG. 10, 21 is a silicon carbide substrate, 22 is an epitaxial region, 23 is a base region, 24 is a source region, 25 is an insulating film, 26 is a gate electrode, 27 is a source electrode, 28 is a drain electrode, and 29 is a first electrode. One polycrystalline silicon region.
As described above, in any case, if at least a part of the respective parts constituting the transistor includes the first polycrystalline silicon region described in this embodiment, the effect of reducing the leakage current can be brought about. Is possible.

以上、実施例１および実施例２においては、炭化珪素を基板材料とした半導体装置を一例として説明したが、基板材料はシリコン、シリコンゲルマン、窒化ガリウム、ダイヤモンドなどその他の半導体材料でもかまわない。
また、全ての実施例において、炭化珪素のポリタイプとして４Ｈタイプを用いて説明したが、６Ｈ、３Ｃ等その他のポリタイプでも構わない。 In the first and second embodiments, the semiconductor device using silicon carbide as the substrate material has been described as an example. However, the substrate material may be other semiconductor materials such as silicon, silicon germane, gallium nitride, and diamond.
In all the examples, the 4H type was used as the polytype of silicon carbide, but other polytypes such as 6H and 3C may be used.

また、全ての実施例において、裏面金属電極４と表面金属電極６とをエピタキシャル領域２を挟んで対向するように配置し、両者間の電流を縦方向に流す所謂縦型構造で説明してきたが、例えば裏面金属電極４と表面金属電極６とを同一主面上に配置し、両者間の電流を横方向に流す所謂横型構造であってもかまわない。   In all the embodiments, the back metal electrode 4 and the front metal electrode 6 are arranged so as to face each other with the epitaxial region 2 interposed therebetween, and the so-called vertical structure in which the current between them is passed in the vertical direction has been described. For example, a so-called lateral structure in which the back surface metal electrode 4 and the front surface metal electrode 6 are arranged on the same main surface and a current between them is flowed in the lateral direction may be used.

また、第一の多結晶シリコン領域３、第二の多結晶シリコン領域７、第三の多結晶シリコン領域１０に用いる材料として多結晶シリコンを用いた例で説明したが、炭化珪素とヘテロ接合を形成する半導体材料であれば各々別々の材料でも、どの材料でもかまわない。例えば単結晶シリコンやアモルファスシリコンなど他のシリコン材料でもかまわないし、ゲルマニウムやシリコンゲルマンなどの他の半導体材料でもよい。つまり、半導体材料が異なると、順方向動作時の内蔵電位と逆方向動作時の漏れ電流の大きさがそれぞれ異なって得られるが、いずれにしてもショットキー接合ダイオードとは異なる逆方向特性が得られるようなヘテロ接合が形成さえできれば、同様の効果が得られる。このように一般的な半導体材料で容易に実現することができるとともに、一般的な製造工程で作製することができる。   Moreover, although the example using a polycrystalline silicon as a material used for the 1st polycrystalline silicon area | region 3, the 2nd polycrystalline silicon area | region 7, and the 3rd polycrystalline silicon area | region 10 was demonstrated, silicon carbide and heterojunction are demonstrated. As long as it is a semiconductor material to be formed, each material may be a separate material or any material. For example, other silicon materials such as single crystal silicon and amorphous silicon may be used, and other semiconductor materials such as germanium and silicon germane may be used. In other words, different semiconductor materials provide different built-in potentials during forward operation and different leakage currents during reverse operation, but in any case, reverse characteristics different from those of Schottky junction diodes are obtained. As long as a heterojunction can be formed, the same effect can be obtained. As described above, it can be easily realized by a general semiconductor material and can be manufactured by a general manufacturing process.

また、一例として、エピタキシャル領域２としてＮ型の炭化珪素を、第一の多結晶シリコン領域３としてＰ型の多結晶シリコンを用いて説明しているが、Ｐ型の炭化珪素とＮ型の多結晶シリコンの組み合わせでもよい。   In addition, as an example, description has been given using N-type silicon carbide as the epitaxial region 2 and P-type polycrystalline silicon as the first polycrystalline silicon region 3, but P-type silicon carbide and N-type polycrystalline silicon are used. A combination of crystalline silicon may be used.

また、多結晶シリコン層１０１の不純物濃度が炭化珪素半導体基体１００の不純物濃度に比べて、少なくとも多結晶シリコン層１０１の臨界電界強度に対する炭化珪素半導体基体１００の臨界電界強度の比率以上に高くなるように構成すれば、遮断時において、炭化珪素半導体基体１００と多結晶シリコン層１０１間に印加されている電位差を、臨界電界の高い炭化珪素半導体基体１００側でもたせることにより、より高い遮断性能を実現することができる。
さらに本発明の主旨を逸脱しない範囲での変形を含むことは言うまでもない。 Further, the impurity concentration of polycrystalline silicon layer 101 is at least higher than the ratio of the critical electric field strength of silicon carbide semiconductor substrate 100 to the critical electric field strength of polycrystalline silicon layer 101 as compared with the impurity concentration of silicon carbide semiconductor substrate 100. With this configuration, a higher barrier performance is realized by causing the potential difference applied between the silicon carbide semiconductor substrate 100 and the polycrystalline silicon layer 101 to be on the side of the silicon carbide semiconductor substrate 100 having a high critical electric field. can do.
Further, it goes without saying that modifications are included within the scope not departing from the gist of the present invention.

本発明の実施例１を示す断面図。Sectional drawing which shows Example 1 of this invention. 本発明の実施例１における他の例を示す断面図。Sectional drawing which shows the other example in Example 1 of this invention. 本発明の実施例１におけるさらに他の例を示す断面図。Sectional drawing which shows the other example in Example 1 of this invention. 本発明の実施例２を示す断面図。Sectional drawing which shows Example 2 of this invention. 本発明の実施例２における他の例を示す断面図。Sectional drawing which shows the other example in Example 2 of this invention. 本発明の実施例２におけるさらに他の例を示す断面図。Sectional drawing which shows the other example in Example 2 of this invention. 本発明の逆方向特性を示す電流電圧特性図。The current-voltage characteristic figure which shows the reverse direction characteristic of this invention. 本発明の実施例１における他の例を示す断面図。Sectional drawing which shows the other example in Example 1 of this invention. 本発明の実施例２における他の例を示す断面図。Sectional drawing which shows the other example in Example 2 of this invention. 本発明の実施例２における他の例を示す断面図。Sectional drawing which shows the other example in Example 2 of this invention. 本発明の実施例１におけるヘテロ接合のエネルギーバンド図。The energy band figure of the heterojunction in Example 1 of this invention. 本発明の実施例１におけるヘテロ接合のエネルギーバンド図（順方向動作時）。The energy band figure of the heterojunction in Example 1 of this invention (at the time of forward operation | movement). 本発明の実施例１におけるヘテロ接合のエネルギーバンド図（逆方向動作時）。The energy band figure of the heterojunction in Example 1 of this invention (at the time of reverse operation | movement).

符号の説明Explanation of symbols

１…炭化珪素基板 ２…エピタキシャル領域
３…第一の多結晶シリコン領域 ４…裏面金属電極
５…電界緩和領域 ６…表面金属電極
７…第二の多結晶シリコン領域 ８…ゲート電極
９…ゲート絶縁膜 １０…第三の多結晶シリコン領域
１１…炭化珪素基板 １２…エピタキシャル領域
１３…ベース領域 １４…ソース領域
１５…ゲート絶縁膜 １６…ゲート電極
１７…ソース電極 １８…ドレイン電極
１９…第一の多結晶シリコン領域 ２１…炭化珪素基板
２２…エピタキシャル領域 ２３…ベース領域
２４…ソース領域 ２５…絶縁膜
２６…ゲート電極 ２７…ソース電極
２８…ドレイン電極 ２９…第一の多結晶シリコン領域
１００…炭化珪素半導体基体 １０１…多結晶シリコン層 DESCRIPTION OF SYMBOLS 1 ... Silicon carbide substrate 2 ... Epitaxial region 3 ... 1st polycrystalline silicon region 4 ... Back surface metal electrode 5 ... Electric field relaxation region 6 ... Front surface metal electrode 7 ... 2nd polycrystalline silicon region 8 ... Gate electrode 9 ... Gate insulation Film 10 ... Third polycrystalline silicon region 11 ... Silicon carbide substrate 12 ... Epitaxial region 13 ... Base region 14 ... Source region 15 ... Gate insulating film 16 ... Gate electrode 17 ... Source electrode 18 ... Drain electrode 19 ... First poly Crystalline silicon region 21 ... Silicon carbide substrate 22 ... Epitaxial region 23 ... Base region 24 ... Source region 25 ... Insulating film 26 ... Gate electrode 27 ... Source electrode 28 ... Drain electrode 29 ... First polycrystalline silicon region 100 ... Silicon carbide semiconductor Base 101 ... Polycrystalline silicon layer

Claims (7)

第一導電型の第一の半導体領域と、前記第一の半導体領域とはバンドギャップが異なり、かつ前記第一の半導体領域とヘテロダイオードを形成する第二の半導体領域とを有し、少なくとも前記第二の半導体領域の所定領域が第二導電型からなり、前記ヘテロダイオードに逆バイアスを印加したときに、前記所定領域の一部は空乏化しないように、前記所定領域の不純物濃度と厚さを設定したことを特徴とする半導体装置。   The first semiconductor region of the first conductivity type and the first semiconductor region have a second semiconductor region that is different in band gap and forms a hetero diode with the first semiconductor region, and at least the The predetermined region of the second semiconductor region is of a second conductivity type, and the impurity concentration and thickness of the predetermined region are not depleted when a reverse bias is applied to the heterodiode. A semiconductor device characterized by the above. 前記ヘテロダイオードに逆バイアスを印加したときに、前記所定領域の空乏化せずに残った厚みが、少なくとも前記第一の半導体領域にとって多数キャリアとなるキャリアに対する前記所定領域の拡散長よりも大きくなるように、前記所定領域の不純物濃度と厚さを設定したことを特徴とする請求項１に記載の半導体装置。   When a reverse bias is applied to the hetero-diode, the thickness of the predetermined region remaining without being depleted is at least larger than the diffusion length of the predetermined region with respect to carriers that become majority carriers for the first semiconductor region. The semiconductor device according to claim 1, wherein an impurity concentration and a thickness of the predetermined region are set as described above. 前記所定領域の不純物濃度が、少なくとも前記第一の半導体領域の不純物濃度以上であることを特徴とする請求項１または請求項２に記載の半導体装置。   The semiconductor device according to claim 1, wherein an impurity concentration of the predetermined region is at least equal to or higher than an impurity concentration of the first semiconductor region. 前記所定領域の不純物濃度が前記第一の半導体領域の不純物濃度に比べて、少なくとも前記第二の半導体領域の臨界電界強度に対する前記第一の半導体領域の臨界電界強度の比率以上に高いことを特徴とする請求項１乃至請求項３の何れかに記載の半導体装置。   The impurity concentration of the predetermined region is higher than the impurity concentration of the first semiconductor region, at least higher than the ratio of the critical electric field strength of the first semiconductor region to the critical electric field strength of the second semiconductor region. The semiconductor device according to claim 1. 前記第一の半導体領域からなる半導体基体と、前記半導体基体の所定領域に形成された第二導電型のベース領域および第一導電型のソース領域とを有し、少なくとも前記半導体基体および前記ソース領域に接するようにゲート絶縁膜を介してゲート電極を有し、前記半導体基体に接して前記半導体基体とはバンドギャップが異なり、かつ前記半導体基体とヘテロダイオードを形成する第二の半導体領域を有し、前記第二の半導体領域の少なくとも一部が前記第二導電型の所定領域となることを特徴とする前記請求項１乃至請求項４の何れかに記載の半導体装置。   A semiconductor substrate comprising the first semiconductor region; a second conductivity type base region and a first conductivity type source region formed in a predetermined region of the semiconductor substrate; and at least the semiconductor substrate and the source region A gate electrode through a gate insulating film so as to be in contact with the semiconductor substrate, and a second semiconductor region which is in contact with the semiconductor substrate and has a band gap different from that of the semiconductor substrate and forms a hetero diode with the semiconductor substrate. 5. The semiconductor device according to claim 1, wherein at least a part of the second semiconductor region is a predetermined region of the second conductivity type. 前記第一の半導体領域が炭化珪素から成ることを特徴とする請求項１乃至請求項５の何れかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, characterized in that said first semiconductor region is made of silicon carbide. 前記第二の半導体領域が単結晶シリコン、アモルファスシリコン、多結晶シリコンの少なくとも何れかであることを特徴とする請求項１乃至請求項６の何れかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, characterized in that said second semiconductor region is at least one of single crystal silicon, amorphous silicon, polycrystalline silicon.
JP2004065972A 2003-07-30 2004-03-09 Semiconductor device Expired - Lifetime JP4211642B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004065972A JP4211642B2 (en) 2004-03-09 2004-03-09 Semiconductor device
US10/898,224 US7138668B2 (en) 2003-07-30 2004-07-26 Heterojunction diode with reduced leakage current
EP04017889.9A EP1503425B1 (en) 2003-07-30 2004-07-28 Heterojunction semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004065972A JP4211642B2 (en) 2004-03-09 2004-03-09 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007170089A Division JP2007251213A (en) 2007-06-28 2007-06-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2005259797A JP2005259797A (en) 2005-09-22
JP4211642B2 true JP4211642B2 (en) 2009-01-21

Family

ID=35085263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004065972A Expired - Lifetime JP4211642B2 (en) 2003-07-30 2004-03-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4211642B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012144271A1 (en) 2011-04-19 2012-10-26 日産自動車株式会社 Semiconductor device and method for producing same

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012532B1 (en) 2005-09-12 2011-02-07 닛산 지도우샤 가부시키가이샤 Semiconductor device and method of manufacturing the same
JP5114865B2 (en) * 2006-04-26 2013-01-09 日産自動車株式会社 Semiconductor device
JP5211472B2 (en) * 2006-02-09 2013-06-12 日産自動車株式会社 Semiconductor device and manufacturing method thereof
JP5225549B2 (en) * 2006-03-15 2013-07-03 日本碍子株式会社 Semiconductor element
JP5560519B2 (en) * 2006-04-11 2014-07-30 日産自動車株式会社 Semiconductor device and manufacturing method thereof
KR100765024B1 (en) 2006-06-21 2007-10-09 닛산 지도우샤 가부시키가이샤 Method of manufacturing semiconductor device
JP4997913B2 (en) * 2006-10-17 2012-08-15 日産自動車株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5476743B2 (en) * 2009-03-04 2014-04-23 日産自動車株式会社 Semiconductor device
JP6148070B2 (en) * 2013-05-27 2017-06-14 ルネサスエレクトロニクス株式会社 Vertical channel junction SiC power FET and method of manufacturing the same
JP6305751B2 (en) * 2013-12-16 2018-04-04 新日本無線株式会社 Schottky diode and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012144271A1 (en) 2011-04-19 2012-10-26 日産自動車株式会社 Semiconductor device and method for producing same
US9252261B2 (en) 2011-04-19 2016-02-02 Nissan Motor Co., Ltd. Semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
JP2005259797A (en) 2005-09-22

Similar Documents

Publication Publication Date Title
JP5560519B2 (en) Semiconductor device and manufacturing method thereof
EP1935028B1 (en) Semiconductor device and method of manufacturing the same
JP4066946B2 (en) Semiconductor device
JP2005303027A (en) Semiconductor device
WO2011033550A1 (en) Semiconductor device
KR101668215B1 (en) Power semiconductor rectifier with controllable on-state voltage
JP4039376B2 (en) Semiconductor device
JP4211642B2 (en) Semiconductor device
JP4742539B2 (en) Semiconductor device
JP5216183B2 (en) Semiconductor device
JP5621198B2 (en) Semiconductor device
JP4033150B2 (en) Semiconductor device and manufacturing method thereof
JP2007214355A (en) Semiconductor device
JP4736386B2 (en) Manufacturing method of semiconductor device
JP5044885B2 (en) Semiconductor device and manufacturing method thereof
JP2006100365A (en) Semiconductor device
JP2007251213A (en) Semiconductor device
JP2006086397A (en) Semiconductor device and its manufacturing method
JP5114865B2 (en) Semiconductor device
JP5211479B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP5494848B2 (en) Semiconductor device
JP2007288030A (en) Semiconductor device
JP2012182508A (en) Semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070206

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070330

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070501

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070628

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20081007

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081020

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111107

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4211642

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121107

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121107

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131107

Year of fee payment: 5

EXPY Cancellation because of completion of term