JP4174008B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4174008B2
JP4174008B2 JP2003137754A JP2003137754A JP4174008B2 JP 4174008 B2 JP4174008 B2 JP 4174008B2 JP 2003137754 A JP2003137754 A JP 2003137754A JP 2003137754 A JP2003137754 A JP 2003137754A JP 4174008 B2 JP4174008 B2 JP 4174008B2
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Prior art keywords
semiconductor chip
substrate
bonding
pads
semiconductor
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JP2003137754A
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JP2004342849A5 (en
JP2004342849A (en
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学 角崎
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置およびその製造技術に関し、特に、スタックドＣＳＰ（Chip Size Package）を有する半導体装置に適用して有効な技術に関する。
【０００２】
【従来の技術】
半導体製品の高速化、高密度実装の要求から、１９９０年代半ばにはボール格子端子（Ball Grid Array：ＢＧＡ）型パッケージによる表面実装技術が開発され、チップ・サイズとほぼ同等で、かつパッケージの機能を備えた様々な構造のＣＳＰが実用化されている。
【０００３】
さらに、現在では、高密度実装の要望に応えるため、半導体チップを２個以上積み重ねたスタックドＣＳＰが製品化されている（例えば、非特許文献１参照）。これにより、複合メモリまたは複合機能デバイスが１パッケージとなり、高密度システム実装を実現することができる。このスタックドＣＳＰでは、上層の半導体チップが下層の半導体チップ上にペーストを介して積層されており、各々の半導体チップの表面の縁辺に配列されたボンディングパッドと、基板の表面に設けられた電極パッドとの間がボンディングワイヤによって電気的に接続されている。
【０００４】
【非特許文献１】
春日壽夫編著「超小型パッケージＣＳＰ／ＢＧＡ技術」日刊工業新聞社、１９９８年５月２８日、ｐ．１０５図７．３
【０００５】
【発明が解決しようとする課題】
ところで、一般の民生用機器においては小型、軽量のパッケージが積極的に採用され始めており、小型、軽量の差別化戦略から高密度実装技術の開発要求がますます強くなっている。しかしながら、通常は１つの実装基板上に半導体チップおよびオンチップ化が困難な回路素子、例えばコンデンサ、抵抗、インダクタ等が配置されるため、上記スタックドＣＳＰを用いて２個以上の半導体チップを積層し、半導体チップの高密度実装を実現したとしても、コンデンサ、抵抗、インダクタ等の実装面積は小さくすることができない。このため、コンデンサ、抵抗、インダクタ等の実装面積を小さくすることによって、さらなる実装基板の小型化を図ることが高密度実装技術における課題の１つとして残されている。
【０００６】
本発明の目的は、実装基板の小型化を図ることのできる技術を提供することにある。
【０００７】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
【０００８】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
【０００９】
本発明は、表面、前記表面とは反対側に位置する裏面、前記表面上に設けられた複数の第１電極パッド、前記表面上に設けられた複数の第２電極パッド、および前記裏面上に設けられた複数の接続パッドを有する基板と、第１主面、前記第１主面とは反対側に位置する第１裏面、前記第１主面と前記第１裏面との間の第１端面、および前記第１主面上に設けられた複数の第１ボンディングパッドを有し、前記基板の前記表面上に実装された第１半導体チップと、第２主面、前記第２主面とは反対側に位置する第２裏面、前記第２主面と前記第２裏面との間の第２端面、および前記第２主面上に設けられた複数の第２ボンディングパッドを有し、前記第１半導体チップ上に積層された第２半導体チップと、前記基板の前記表面上で、かつ前記第１半導体チップの周囲に実装された回路素子と、前記第１半導体チップの前記複数の第１ボンディングパッドと前記基板の前記複数の第１電極パッドとをそれぞれ電気的に接続する複数の第１ボンディングワイヤと、前記第２半導体チップの前記複数の第２ボンディングパッドと前記基板の前記複数の第２電極パッドとをそれぞれ電気的に接続する複数の第２ボンディングワイヤと、前記回路素子、前記第１半導体チップ、前記第２半導体チップ、前記複数の第１ボンディングワイヤ、および前記複数の第２ボンディングワイヤを封止する樹脂体と、前記基板の前記複数の接続パッドにそれぞれ設けられた複数のバンプと、を含み、前記第１電極パッドは、前記第２電極パッドよりも前記第１半導体チップ側に位置しており、前記回路素子は、前記基板の前記表面、前記第１半導体チップの前記第１端面および前記第１ボンディングワイヤにより囲まれており、前記第１ボンディングワイヤは、前記第２ボンディングワイヤと前記基板の前記表面との間に位置しており、前記回路素子は、絶縁体で被覆されているものである。
【００１１】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。
【００１２】
本実施の形態である半導体装置の一例を図１および図２を用いて説明する。図１は、パッケージ基板上に搭載された半導体チップおよびチップコンデンサを示す概略上面図、図２は、図１のＡ−Ａ線における要部断面図である。
【００１３】
図１および図２に示すように、パッケージ１には、１つのパッケージ基板２のチップ搭載面上に３つの半導体チップ３ａ〜３ｃが積み重ねて搭載されている。半導体チップ３ａ〜３ｃは単結晶シリコンで構成され、その素子形成面には半導体装置が形成されており、１段目の半導体チップ３ａは、例えばマイコン、２段目の半導体チップ３ｂは、例えば電気的一括消去型ＥＥＰＲＯＭ（Electric Erasable Programmable Read Only Memory）、３段目の半導体チップ３ｃは、例えばＳＲＡＭ（Static Random Access Memory）を例示することができる。１段目の半導体チップ３ａはペーストを用いてパッケージ基板２に接合されている。同様に、２段目の半導体チップ３ｂは１段目の半導体チップ３ａに、３段目の半導体チップ３ｃは２段目の半導体チップ３ｂにそれぞれペーストを用いて接合されている。
【００１４】
パッケージ基板２の表面には電極パッド４が設けられており、この電極パッド４と半導体チップ３ａ〜３ｃの表面の縁辺に配列されたボンディングパッドＢＰとがボンディングワイヤ５によって電気的に接続されている。またパッケージ基板２の裏面には接続パッド６が設けられており、この接続パッド６に外部端子７、例えばバンプが直接接続されている。ボンディングワイヤ５は、例えば直径が３０μｍ程度の金によって構成されている。電極パッド４および接続パッド６は、例えば銅によって構成されており、その表面にはメッキ処理が施されている。メッキ材は、例えば金または金とニッケルとの積層膜が採用される。パッケージ基板２の表面の電極パッド４と裏面の接続パッド６とは、パッケージ基板２を貫通したスルーホールを通して繋がっており、このスルーホールの内部に埋め込まれた基板内配線８によって電気的に接続されている。基板内配線８は、例えば銅によって構成される。
【００１５】
１段目の半導体チップ３ａの表面のボンディングパッドＢＰとパッケージ基板２の表面の電極パッド４とを結線するボンディングワイヤ５は、半導体チップ３ａの周辺部に触れないように半導体チップ３ａ側で盛り上がったループ形状となっており、１段目の半導体チップ３ａに最も近い電極パッド４と１段目の半導体チップ３ａの端面とは、１段目の半導体チップ３ａの厚さ以上、例えば０.２〜０.５ｍｍ程度離れている。
【００１６】
さらに、ボンディングワイヤ５のループ、１段目の半導体チップ３ａの端面およびパッケージ基板２に囲まれた空間にチップコンデンサ（図１中では、網掛けのハッチングで示す）９が搭載されている。すなわち、ボンディングワイヤ５はループ形状であり、また１段目の半導体チップ３ａには厚さがあることから、必然的に上記空間が形成される。この空間を有効活用することによって、従来は半導体チップを封止するパッケージ１の外に形成されていたチップコンデンサ９を、パッケージ１内に取り込むことができる。チップコンデンサ９は、例えばノイズ対策または電源安定化のために電源ピンとＧＮＤとの間に設置される。
【００１７】
なお、本実施の形態では、３つの半導体チップ３ａ〜３ｃを積層したスタックドＣＳＰに適用した場合について説明したが、積層する半導体チップの数はこれに限定されるものではなく、１層のＣＳＰまたは２層以上のスタックドＣＳＰにも適用することができる。
【００１８】
また、半導体チップを積層する場合、上層の半導体チップの面積を下層の半導体チップの面積より小さくする必要はなく、積層される半導体チップの順番はチップサイズに依存せず、任意に選ぶことができる。また上層の半導体チップのチップサイズと下層の半導体チップのチップサイズとをほぼ同じまたは同一としてもよい。
【００１９】
また、チップコンデンサ９のボンディングワイヤ５に近接する少なくともその一部を塗料または樹脂などの絶縁体で被覆してもよく、その場合チップコンデンサ９とボンディングワイヤ５との電気的な接触を防止することができる。
【００２０】
また、ボンディングワイヤ５のループ、１段目の半導体チップ３ａの端面およびパッケージ基板２に囲まれた空間に配置される回路素子は、チップコンデンサ９に限定されるものではなく、半導体チップ３ａ〜３ｃと独立したものであればよく、例えば他の半導体装置、単体トランジスタ、抵抗、インダクタ等を配置することができる。
【００２１】
また、パッケージ１の外部端子７をバンプとしたが、これに限定されるものではなく、例えばＰＧＡ（Pin Grid Array）のようなピンであってもよい。
【００２２】
次に、本実施の形態である半導体装置の製造方法を図３〜図７に示す半導体基板の要部断面図および図８に示す半導体基板の要部外観図を用いて説明する。
【００２３】
まず、図３に示すように、パッケージ基板２を準備する。実際には半導体装置がそれぞれ実装される複数個のパッケージ基板２が繋がっているが、ここでは２個のパッケージ基板２を示す。このパッケージ基板２の表面には複数個の電極パッド４が設けられ、裏面には複数個の接続パッド６が設けられており、両者は基板内配線８によって電気的に接続されている。
【００２４】
次に、絶縁性ペースト１０を用いてパッケージ基板２の表面のチップ搭載領域に１段目の半導体チップ３ａを接合する。続いて絶縁性ペースト１０を用いて１段目の半導体チップ３ａ上に２段目の半導体チップ３ｂを接合し、さらに絶縁性ペースト１０を用いて２段目の半導体チップ３ｂ上に３段目の半導体チップ３ｃを接合して、半導体チップ３ａ〜３ｃを積層する。
【００２５】
次に、図４に示すように、導電性ペースト１１を用いて、１段目の半導体チップ３ａに最も近い電極パッド４と１段目の半導体チップ３ａの端面との間であって、１段目の半導体チップ３ａから、例えば０.２〜０.５ｍｍ程度の範囲内の領域にチップコンデンサ９を接合する。この領域は、後にボンディングワイヤ、１段目の半導体チップ３ａの端面およびパッケージ基板２に囲まれる空間となる。
【００２６】
次に、図５に示すように、各々の半導体チップ３ａ〜３ｃの表面の縁辺に配列されたボンディングパッドと、パッケージ基板２の表面の電極パッド４とをボンディングワイヤ５を用いて接続する。その作業は自動化されており、ボンディング装置を用いて行われる。ボンディング装置には、あらかじめ半導体チップ３ａ〜３ｃの表面のボンディングパッドおよびパッケージ基板２の表面の電極パッド４の配置情報が入力されており、パッケージ基板２上に搭載された半導体チップ３ａ〜３ｃ、その表面のボンディングパッドおよびパッケージ基板２の表面の電極パッド４の相対的位置関係を画像として取り込みデータ処理を行って正確にボンディングワイヤ５が接続される。この際、ボンディングワイヤ５のループ形状は、チップコンデンサ９および半導体チップ３ａ〜３ｃの周辺部に触れないよう半導体チップ３ａ〜３ｃ側で盛り上がった形に制御される。
【００２７】
次に、図６に示すように、ボンディングワイヤ５が接続されたパッケージ基板２を金型成形機にセットし、温度を上げ液状化した樹脂１２を圧送して流し込み、モールド成形する。続いて余分な樹脂１２またはバリを取り除く。
【００２８】
次に、図７に示すように、例えば半田からなるバンプ１３をパッケージ基板２の裏面の接続パッド６に供給した後、リフロー処理を施してバンプ１３を溶解させ、バンプ１３と接続パッド６とを接続する。その後、図８に示すように、１個１個のパッケージ１に分離される。
【００２９】
このように、本実施の形態によれば、ボンディングワイヤ５のループ、１段目の半導体チップ３ａの端面およびパッケージ基板２に囲まれた空間にチップコンデンサ９を配置することができる。これにより、従来はパッケージ１の外に実装されていたチップコンデンサ９をパッケージ１内に取り込むことができるので、実装基板の面積を小さくすることができる。
【００３０】
以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
【００３１】
例えば、前記実施の形態では、スタックドＣＳＰに適用した場合について説明したが、基板上の構造物上に配置された半導体チップと、基板と半導体チップとを電気的に接続する手段であるワイヤボンディングとの組み合わせであればどのようなパッケージ形態にも適用でき、ベアチップ実装にも適用することができる。
【００３２】
また、ワイヤボンディングが一部でも行われていれば、本発明を適用することができるので、他のボンディング手段とが組み合わされたパッケージにも適用することができる。
【００３３】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
【００３４】
従来は半導体チップを搭載するパッケージの外に実装されていた回路素子が、パッケージに内蔵できることから、半導体チップおよび回路素子が実装される実装基板の面積を小さくすることができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態である半導体装置を示す半導体基板の要部平面図である。
【図２】図１のＡ−Ａ線における半導体基板の要部断面図である。
【図３】本発明の一実施の形態である半導体装置の製造方法を示す半導体基板の要部断面図である。
【図４】本発明の一実施の形態である半導体装置の製造方法を示す半導体基板の要部断面図である。
【図５】本発明の一実施の形態である半導体装置の製造方法を示す半導体基板の要部断面図である。
【図６】本発明の一実施の形態である半導体装置の製造方法を示す半導体基板の要部断面図である。
【図７】本発明の一実施の形態である半導体装置の製造方法を示す半導体基板の要部断面図である。
【図８】本発明の一実施の形態である半導体装置の製造方法を示す半導体基板の要部外観図である。
【符号の説明】
１ パッケージ
２ パッケージ基板
３ａ 半導体チップ
３ｂ 半導体チップ
３ｃ 半導体チップ
４ 電極パッド
５ ボンディングワイヤ
６ 接続パッド
７ 外部端子
８ 基板内配線
９ チップコンデンサ
１０ 絶縁性ペースト
１１ 導電性ペースト
１２ 樹脂
１３ バンプ
ＢＰ ボンディングパッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor device having a stacked CSP (Chip Size Package).
[0002]
[Prior art]
In response to the demand for high-speed and high-density mounting of semiconductor products, surface mounting technology using a ball grid terminal (BGA) type package was developed in the mid-1990s, which is almost equivalent to the chip size and functions of the package. CSPs having various structures with the above have been put into practical use.
[0003]
Furthermore, at present, a stacked CSP in which two or more semiconductor chips are stacked has been commercialized in order to meet the demand for high-density mounting (for example, see Non-Patent Document 1). Thereby, the composite memory or the composite functional device becomes one package, and high-density system mounting can be realized. In this stacked CSP, an upper semiconductor chip is stacked on a lower semiconductor chip via a paste, bonding pads arranged on the edge of the surface of each semiconductor chip, and electrode pads provided on the surface of the substrate Are electrically connected by a bonding wire.
[0004]
[Non-Patent Document 1]
Edited by Ikuo Kasuga, “Ultra-small package CSP / BGA technology”, Nikkan Kogyo Shimbun, May 28, 1998, p. 105 Figure 7.3
[0005]
[Problems to be solved by the invention]
By the way, in general consumer devices, small and light packages have begun to be actively adopted, and the demand for development of high-density mounting technology is increasing due to the differentiation strategy of small and light. However, since a semiconductor chip and circuit elements that are difficult to be on-chip, such as capacitors, resistors, and inductors, are usually disposed on one mounting substrate, two or more semiconductor chips are stacked using the stacked CSP. Even if high-density mounting of semiconductor chips is realized, the mounting area of capacitors, resistors, inductors, etc. cannot be reduced. For this reason, further downsizing of the mounting substrate by reducing the mounting area of capacitors, resistors, inductors and the like remains as one of the problems in the high-density mounting technology.
[0006]
An object of the present invention is to provide a technique capable of downsizing a mounting board.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0009]
The present invention provides a front surface, a back surface opposite to the front surface, a plurality of first electrode pads provided on the front surface, a plurality of second electrode pads provided on the front surface, and the back surface A substrate having a plurality of connection pads provided, a first main surface, a first back surface located on the opposite side of the first main surface, and a first end surface between the first main surface and the first back surface And a first semiconductor chip having a plurality of first bonding pads provided on the first main surface and mounted on the surface of the substrate, a second main surface, and the second main surface A second back surface located on the opposite side, a second end surface between the second main surface and the second back surface, and a plurality of second bonding pads provided on the second main surface, A second semiconductor chip stacked on one semiconductor chip, on the surface of the substrate, and on the first Circuit elements mounted around the semiconductor chip, and a plurality of first bonding wires that electrically connect the plurality of first bonding pads of the first semiconductor chip and the plurality of first electrode pads of the substrate, respectively. A plurality of second bonding wires that electrically connect the plurality of second bonding pads of the second semiconductor chip and the plurality of second electrode pads of the substrate, respectively, the circuit element, and the first semiconductor A resin body that seals the chip, the second semiconductor chip, the plurality of first bonding wires, and the plurality of second bonding wires, and a plurality of bumps respectively provided on the plurality of connection pads of the substrate; The first electrode pad is located closer to the first semiconductor chip than the second electrode pad, and the circuit element is Surrounded by the surface of the substrate, the first end surface of the first semiconductor chip and the first bonding wire, the first bonding wire is between the second bonding wire and the surface of the substrate And the circuit element is coated with an insulator .
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
[0012]
An example of the semiconductor device in this embodiment will be described with reference to FIGS. FIG. 1 is a schematic top view showing a semiconductor chip and a chip capacitor mounted on a package substrate, and FIG. 2 is a cross-sectional view of an essential part taken along line AA of FIG.
[0013]
As shown in FIGS. 1 and 2, in the package 1, three semiconductor chips 3 a to 3 c are stacked and mounted on the chip mounting surface of one package substrate 2. The semiconductor chips 3a to 3c are made of single crystal silicon, and a semiconductor device is formed on the element formation surface. The first-stage semiconductor chip 3a is, for example, a microcomputer, and the second-stage semiconductor chip 3b is, for example, an electric circuit. The batch erase type EEPROM (Electric Erasable Programmable Read Only Memory) and the third-stage semiconductor chip 3c can be exemplified by SRAM (Static Random Access Memory), for example. The first-stage semiconductor chip 3a is bonded to the package substrate 2 using a paste. Similarly, the second-stage semiconductor chip 3b is bonded to the first-stage semiconductor chip 3a, and the third-stage semiconductor chip 3c is bonded to the second-stage semiconductor chip 3b using paste.
[0014]
Electrode pads 4 are provided on the surface of the package substrate 2, and the electrode pads 4 and the bonding pads BP arranged on the edges of the surfaces of the semiconductor chips 3 a to 3 c are electrically connected by bonding wires 5. . A connection pad 6 is provided on the back surface of the package substrate 2, and an external terminal 7, for example, a bump is directly connected to the connection pad 6. The bonding wire 5 is made of, for example, gold having a diameter of about 30 μm. The electrode pad 4 and the connection pad 6 are made of, for example, copper, and the surface thereof is plated. As the plating material, for example, gold or a laminated film of gold and nickel is employed. The electrode pad 4 on the front surface of the package substrate 2 and the connection pad 6 on the back surface are connected through a through hole penetrating the package substrate 2 and are electrically connected by an in-substrate wiring 8 embedded in the through hole. ing. The in-substrate wiring 8 is made of, for example, copper.
[0015]
The bonding wire 5 connecting the bonding pad BP on the surface of the first-stage semiconductor chip 3a and the electrode pad 4 on the surface of the package substrate 2 swelled on the semiconductor chip 3a side so as not to touch the peripheral portion of the semiconductor chip 3a. The electrode pad 4 closest to the first-stage semiconductor chip 3a and the end face of the first-stage semiconductor chip 3a are at least the thickness of the first-stage semiconductor chip 3a, for example, 0.2 to It is about 0.5mm apart.
[0016]
Further, a chip capacitor 9 (shown by hatching in FIG. 1) is mounted in a space surrounded by the loop of the bonding wire 5, the end surface of the first-stage semiconductor chip 3 a and the package substrate 2. That is, since the bonding wire 5 has a loop shape and the first-stage semiconductor chip 3a has a thickness, the above space is inevitably formed. By effectively utilizing this space, the chip capacitor 9 that has been conventionally formed outside the package 1 for sealing the semiconductor chip can be taken into the package 1. The chip capacitor 9 is installed between a power supply pin and GND for noise countermeasures or power supply stabilization, for example.
[0017]
In the present embodiment, the case where the present invention is applied to a stacked CSP in which three semiconductor chips 3a to 3c are stacked has been described. However, the number of stacked semiconductor chips is not limited to this, and one layer of CSP or It can also be applied to a stacked CSP having two or more layers.
[0018]
Further, when stacking semiconductor chips, it is not necessary to make the area of the upper semiconductor chip smaller than the area of the lower semiconductor chip, and the order of the stacked semiconductor chips can be arbitrarily selected without depending on the chip size. . The chip size of the upper semiconductor chip and the chip size of the lower semiconductor chip may be substantially the same or the same.
[0019]
Further, at least a part of the chip capacitor 9 adjacent to the bonding wire 5 may be covered with an insulating material such as paint or resin, in which case the electrical contact between the chip capacitor 9 and the bonding wire 5 is prevented. Can do.
[0020]
Further, the circuit element disposed in the loop surrounded by the bonding wire 5, the end face of the first-stage semiconductor chip 3 a and the space surrounded by the package substrate 2 is not limited to the chip capacitor 9, but the semiconductor chips 3 a to 3 c. For example, another semiconductor device, a single transistor, a resistor, an inductor, or the like can be arranged.
[0021]
Further, although the external terminals 7 of the package 1 are bumps, the present invention is not limited to this, and for example, pins such as PGA (Pin Grid Array) may be used.
[0022]
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to a cross-sectional view of main parts of the semiconductor substrate shown in FIGS. 3 to 7 and an external view of main parts of the semiconductor substrate shown in FIG.
[0023]
First, as shown in FIG. 3, a package substrate 2 is prepared. Actually, a plurality of package substrates 2 on which semiconductor devices are respectively mounted are connected. Here, two package substrates 2 are shown. A plurality of electrode pads 4 are provided on the front surface of the package substrate 2, and a plurality of connection pads 6 are provided on the back surface, and both are electrically connected by wiring 8 in the substrate.
[0024]
Next, the first-stage semiconductor chip 3 a is bonded to the chip mounting region on the surface of the package substrate 2 using the insulating paste 10. Subsequently, the second-stage semiconductor chip 3b is bonded onto the first-stage semiconductor chip 3a using the insulating paste 10, and the third-stage semiconductor chip 3b is further bonded onto the second-stage semiconductor chip 3b using the insulating paste 10. The semiconductor chip 3c is joined and the semiconductor chips 3a to 3c are stacked.
[0025]
Next, as shown in FIG. 4, between the electrode pad 4 closest to the first-stage semiconductor chip 3a and the end face of the first-stage semiconductor chip 3a using the conductive paste 11, The chip capacitor 9 is joined to the region within the range of, for example, about 0.2 to 0.5 mm from the semiconductor chip 3a. This region becomes a space surrounded by the bonding wire, the end surface of the first-stage semiconductor chip 3a, and the package substrate 2 later.
[0026]
Next, as shown in FIG. 5, the bonding pads arranged on the edges of the surfaces of the respective semiconductor chips 3 a to 3 c and the electrode pads 4 on the surface of the package substrate 2 are connected using bonding wires 5. The operation is automated and is performed using a bonding apparatus. Arrangement information of the bonding pads on the surfaces of the semiconductor chips 3a to 3c and the electrode pads 4 on the surface of the package substrate 2 is input to the bonding apparatus in advance, and the semiconductor chips 3a to 3c mounted on the package substrate 2 The relative positional relationship between the bonding pads on the surface and the electrode pads 4 on the surface of the package substrate 2 is captured as an image, and data processing is performed to accurately connect the bonding wires 5. At this time, the loop shape of the bonding wire 5 is controlled to be raised on the side of the semiconductor chips 3a to 3c so as not to touch the peripheral portions of the chip capacitor 9 and the semiconductor chips 3a to 3c.
[0027]
Next, as shown in FIG. 6, the package substrate 2 to which the bonding wires 5 are connected is set on a mold molding machine, and the temperature of the liquefied resin 12 is raised by feeding and poured to mold. Subsequently, excess resin 12 or burrs are removed.
[0028]
Next, as shown in FIG. 7, after supplying bumps 13 made of, for example, solder to the connection pads 6 on the back surface of the package substrate 2, a reflow process is performed to dissolve the bumps 13 so that the bumps 13 and the connection pads 6 are bonded together. Connecting. Thereafter, as shown in FIG. 8, each package 1 is separated.
[0029]
Thus, according to the present embodiment, the chip capacitor 9 can be arranged in the space surrounded by the loop of the bonding wire 5, the end face of the first-stage semiconductor chip 3 a and the package substrate 2. Thereby, since the chip capacitor 9 conventionally mounted outside the package 1 can be taken into the package 1, the area of the mounting substrate can be reduced.
[0030]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0031]
For example, in the above-described embodiment, the case where the present invention is applied to the stacked CSP has been described. However, the semiconductor chip disposed on the structure on the substrate, the wire bonding which is a means for electrically connecting the substrate and the semiconductor chip, As long as it is a combination, it can be applied to any package form, and can also be applied to bare chip mounting.
[0032]
In addition, since the present invention can be applied if wire bonding is performed even in part, it can also be applied to a package combined with other bonding means.
[0033]
【The invention's effect】
Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0034]
Conventionally, a circuit element that has been mounted outside a package on which a semiconductor chip is mounted can be built in the package, so that the area of the mounting substrate on which the semiconductor chip and the circuit element are mounted can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view of an essential part of a semiconductor substrate showing a semiconductor device according to an embodiment of the present invention;
2 is a main-portion cross-sectional view of the semiconductor substrate taken along line AA in FIG.
FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in an embodiment of the invention;
6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in an embodiment of the invention; FIG.
7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in an embodiment of the invention; FIG.
FIG. 8 is an external view of the essential part of a semiconductor substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Package 2 Package substrate 3a Semiconductor chip 3b Semiconductor chip 3c Semiconductor chip 4 Electrode pad 5 Bonding wire 6 Connection pad 7 External terminal 8 Substrate wiring 9 Chip capacitor 10 Insulating paste 11 Conductive paste 12 Resin 13 Bump BP Bonding pad

Claims (3)

表面、前記表面とは反対側に位置する裏面、前記表面上に設けられた複数の第１電極パッド、前記表面上に設けられた複数の第２電極パッド、および前記裏面上に設けられた複数の接続パッドを有する基板と、
第１主面、前記第１主面とは反対側に位置する第１裏面、前記第１主面と前記第１裏面との間の第１端面、および前記第１主面上に設けられた複数の第１ボンディングパッドを有し、前記基板の前記表面上に実装された第１半導体チップと、
第２主面、前記第２主面とは反対側に位置する第２裏面、前記第２主面と前記第２裏面との間の第２端面、および前記第２主面上に設けられた複数の第２ボンディングパッドを有し、前記第１半導体チップ上に積層された第２半導体チップと、
前記基板の前記表面上で、かつ前記第１半導体チップの周囲に実装された回路素子と、
前記第１半導体チップの前記複数の第１ボンディングパッドと前記基板の前記複数の第１電極パッドとをそれぞれ電気的に接続する複数の第１ボンディングワイヤと、
前記第２半導体チップの前記複数の第２ボンディングパッドと前記基板の前記複数の第２電極パッドとをそれぞれ電気的に接続する複数の第２ボンディングワイヤと、
前記回路素子、前記第１半導体チップ、前記第２半導体チップ、前記複数の第１ボンディングワイヤ、および前記複数の第２ボンディングワイヤを封止する樹脂体と、
前記基板の前記複数の接続パッドにそれぞれ設けられた複数のバンプと、
を含み、
前記第１電極パッドは、前記第２電極パッドよりも前記第１半導体チップ側に位置しており、
前記回路素子は、前記基板の前記表面、前記第１半導体チップの前記第１端面および前記第１ボンディングワイヤにより囲まれており、
前記第１ボンディングワイヤは、前記第２ボンディングワイヤと前記基板の前記表面との間に位置しており、
前記回路素子は、絶縁体で被覆されていることを特徴とする半導体装置。Front surface, provided the back surface located opposite from said surface, said surface on the provided plurality of first electrode pads, the plurality of second electrode pads provided on the surface, and on the back a substrate having a plurality of connection pads which are,
First main surface, a first rear surface located on the opposite side to the first major surface, a first end surface between said first major surface and said first rear surface, and provided on the first major surface a plurality of first bonding pads were, a first semiconductor chip mounted on said surface before Symbol substrate,
A second main surface, a second back surface located on the opposite side of the second main surface, a second end surface between the second main surface and the second back surface, and the second main surface. A second semiconductor chip having a plurality of second bonding pads and stacked on the first semiconductor chip;
Circuit elements mounted on the surface of the substrate and around the first semiconductor chip;
A plurality of first bonding wires that respectively electrically connect the plurality of first bonding pads of the first semiconductor chip and the plurality of first electrode pads of the substrate;
A plurality of second bonding wires that respectively electrically connect the plurality of second bonding pads of the second semiconductor chip and the plurality of second electrode pads of the substrate;
A resin body that seals the circuit element, the first semiconductor chip , the second semiconductor chip, the plurality of first bonding wires, and the plurality of second bonding wires;
A plurality of bumps provided to each of the plurality of connection pads of the substrate,
Only including,
The first electrode pad is located closer to the first semiconductor chip than the second electrode pad;
The circuit element is surrounded by the surface of the substrate, the first end surface of the first semiconductor chip, and the first bonding wire ,
The first bonding wire is located between the second bonding wire and the surface of the substrate;
The semiconductor device, wherein the circuit element is covered with an insulator . 前記第１、第２ボンディングワイヤは、ループ形状に形成されていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first and second bonding wires are formed in a loop shape. 前記回路素子は、チップコンデンサ、抵抗、インダクタまたは単体トランジスタの何れかであることを特徴とする請求項２記載の半導体装置。  3. The semiconductor device according to claim 2, wherein the circuit element is any one of a chip capacitor, a resistor, an inductor, and a single transistor.
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