JP4154478B2 - Method for forming through electrode using photosensitive polyimide - Google Patents

Method for forming through electrode using photosensitive polyimide Download PDF

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Publication number
JP4154478B2
JP4154478B2 JP2002042756A JP2002042756A JP4154478B2 JP 4154478 B2 JP4154478 B2 JP 4154478B2 JP 2002042756 A JP2002042756 A JP 2002042756A JP 2002042756 A JP2002042756 A JP 2002042756A JP 4154478 B2 JP4154478 B2 JP 4154478B2
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hole
photosensitive polyimide
electrode
filled
metal
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JP2003243396A (en
Inventor
昌宏 青柳
博 仲川
和彦 所
克弥 菊地
殷實 鄭
博 板谷
繁昌 瀬川
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PI R&D Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
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PI R&D Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials For Photolithography (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、集積回路チップを３個以上積み重ねて、回路基板に直接搭載する技術、いわゆる３次元チップ積層技術のために用いることを目的として、集積回路チップ内に設けられる、チップの表から裏面に貫通した電極について、その形成方法に関する。図６に貫通電極を形成し、薄く加工したチップを多段に積層した、パッケージに搭載した状態を示す。このような３次元チップ積層技術については、Japanese Journal of Applied Physics, Vol.40, pp.3032-3037, (2001)に開示されている。
【０００２】
【従来の技術】
集積回路が形成されたシリコン、ガリウムヒ素、インジウム燐などの半導体基板にエッチング加工、レーザー加工などで穴を形成したのち、CVD法などにより酸化シリコン、窒化シリコンなどの絶縁膜を堆積し、さらに、絶縁膜上にシード層を形成した後、メッキ法による銅などの金属で穴を充填し、その後、裏面を研削して、金属面を露出させ、貫通電極を形成する方法が行われていた。
【０００３】
【発明の解決しようとする課題】
しかしながら、従来のCVD法などの絶縁膜堆積方法では、ミクロン以上の厚い膜を堆積するのに長時間を必要とし、また、堆積に必要なエネルギーも多大なものがあった。
また、薄い絶縁膜を用いた場合は、貫通電極と基板との間で形成される静電容量が多大となるため、信号遅延の原因となったり、信号線路として用いた場合に特性インピーダンスが低くなりすぎるなどの問題があった。
【０００４】
【問題を解決するための手段】
上記の問題点を解決するために、本発明では、半導体薄化基板からなる導電性の基板を用いて、その部材にエッチング加工により設けられた穴に対して、感光性ポリイミド絶縁膜を回転塗布により堆積させ、その後、最初の穴より小さい径の穴パターンを露光、現像により形成し、さらに、金属材料で貫通穴を埋め込み、基板裏面を研削して、金属を露出させて、貫通電極とするものである。
【０００５】
本発明の貫通電極構造は、グランド電位の基板に設けられた貫通穴の側面にポリイミド絶縁層が形成され、穴の中心に金属材料が埋め込まれた構造となる。これにより、同軸線路構造となるため、穴側面のポリイミド絶縁層の厚さを独立して制御することにより、広い範囲の特性インピーダンスを実現することが可能となる。例えば、高周波線路で一般に用いられる５０Ωの特性インピーダンスについても、容易に実現することができる。
【０００６】
同軸構造線路の特性インピーダンスZ0は、ln(D/d)*60/(εr)1/2で表される。ここで、Dは、外皮導体の内径、Dは、心線の外径、εrは、絶縁体の比誘電率である。
例えば、εr = 3.5 のポリイミド絶縁体を用いて、 D = 15μm、d = 3.15μm（またはD = 10μm、d = 2.1μm）とすれば、特性インピーダンスZ0は、50Ωとなり、また、D = 15μm、d = 6.27μm（またはD = 10μm、d = 4.18μm）とすれば、特性インピーダンスZ0は、28Ωとなる。
【０００７】
【発明の実施の形態】
本発明の実施例を図１から図５に示された作製プロセスの図面に基づいて説明する。
図1では、シリコン、ガリウムヒ素、インジウム燐など半導体を薄く加工した薄化基板を用いて、レーザー加工あるいはドライエッチング加工により深い穴を必要に応じて多数個形成する。この穴は、貫通電極構造に用いられる。穴の深さは、10ミクロン程度だけ基板の厚さより小さい値とし、貫通させないようにする。
【０００８】
図2では、US Patent 5502143に開示されているγ-バレロラクトンとピリジンを触媒に用いたブロック共重合法によって作成される溶媒可能な感光性ポリイミドを回転塗布法により堆積する。この工程において、回転する前に試料の周りを真空状態にして、ポリイミドを必要量だけ滴下した後、試料を回転させ、塗布が終了した後に、試料の周りを大気圧に戻すことにより、微細な穴にもポリイミドを充填することができる。
【０００９】
図3では、紫外線、X線、電子線などによる露光装置で穴の中心部のみ露光を行い、現像液を用いて、現像を行う。この工程においては、露光装置の焦点深度を可能なかぎり深く設定する。また、穴の側壁にポリイミドが所望の厚さ残存するように露光パターンおよび露光量を調節する。
【００１０】
図4では、おもて面からスパッタ法、真空蒸着法、メッキ法、プラズマ溶射法などによりアルミニウ ム、銅、金、銀、パラジウム、チタン、ニオブなどの金属膜を堆積する。ただし、メッキ法による場合は、スパッタ法、真空蒸着法などでシード層を形成したのち、メッキ工程を実施する。貫通穴に金属を充填するため、メッキ工程の採用が望ましい。例えば、US Patent 5421987, 6136707に開示されている微細な穴の中でメッキ速度が促進され、平坦面ではメッキ速度が抑制されるように工夫されたJets Technologyと呼ばれるメッキ技術が利用できる。
【００１１】
図5では、貫通電極の金属部が露出するように裏面を研削する。なお、上面に残ったポリイミドは、酸素プラズマによるアッシングで取り除くことができる。
【００１２】
ここで、薄化基板の厚さは、できるだけ薄いものを用いることとし、具体的には、100μm以下が望ましい。
【００１３】
【発明の効果】
本発明によれば、集積回路チップの中に形成された貫通電極構造において、同軸線路構造にすることが可能となるので、特性インピーダンスを任意の値に設定することができ、多層配線回路基板内のマイクロスリップ線路配線構造とのインピーダンスマッチングを最適化することができ、回路基板内での超高速信号伝送が可能となる。
【図面の簡単な説明】
本発明の実施例として、図1から図５までは、貫通電極の作成プロセス図面である。
【図１】 基本部材に対す穴あけ加工プロセスの図。
【図２】 リイミド絶縁膜の塗布プロセスの図。
【図３】 に埋め込まれたポリイミド絶縁膜への穴パターンの形成プロセスの図。
【図４】 リイミド絶縁膜の穴への金属メッキプロセスの図。
【図５】 板裏面の研削プロセスの図。
【図６】 多段積層チップを搭載したパッケージの図[0001]
BACKGROUND OF THE INVENTION
The present invention provides a technique for stacking three or more integrated circuit chips and mounting them directly on a circuit board, that is, a so-called three-dimensional chip stacking technique. The present invention relates to a method for forming an electrode that penetrates through the electrode. FIG. 6 shows a state in which through electrodes are formed and thinly processed chips are stacked in multiple stages and mounted in a package. Such a three-dimensional chip stacking technique is disclosed in Japanese Journal of Applied Physics, Vol. 40, pp. 3032-3037, (2001).
[0002]
[Prior art]
After forming holes in the semiconductor substrate such as silicon, gallium arsenide, indium phosphide, etc. on which the integrated circuit is formed by etching processing, laser processing, etc., deposit an insulating film such as silicon oxide, silicon nitride by CVD method, etc. After forming a seed layer on an insulating film, a hole is filled with a metal such as copper by a plating method, and then the back surface is ground to expose the metal surface to form a through electrode.
[0003]
[Problem to be Solved by the Invention]
However, in the conventional insulating film deposition method such as the CVD method, it takes a long time to deposit a thick film of micron or more, and much energy is required for the deposition.
In addition, when a thin insulating film is used, the capacitance formed between the through electrode and the substrate becomes large, which may cause signal delay or low characteristic impedance when used as a signal line. There were problems such as becoming too much.
[0004]
[Means for solving problems]
In order to solve the above problems, in the present invention, a photosensitive polyimide insulating film is spin-coated on a hole provided by etching in a member using a conductive substrate made of a semiconductor thinned substrate. After that, a hole pattern having a diameter smaller than the first hole is formed by exposure and development. Further, the through hole is filled with a metal material, the back surface of the substrate is ground, and the metal is exposed to form a through electrode. Is.
[0005]
The through electrode structure of the present invention has a structure in which a polyimide insulating layer is formed on the side surface of a through hole provided in a ground potential substrate, and a metal material is embedded in the center of the hole. Thereby, since it becomes a coaxial line structure, it becomes possible to implement | achieve the characteristic impedance of a wide range by controlling the thickness of the polyimide insulating layer of a hole side surface independently. For example, a characteristic impedance of 50Ω that is generally used in a high-frequency line can be easily realized.
[0006]
The characteristic impedance Z 0 of the coaxial structure line is expressed by ln (D / d) * 60 / (ε r ) 1/2 . Here, D is the inner diameter of the outer conductor, D is the outer diameter of the core wire, and ε r is the relative dielectric constant of the insulator.
For example, if a polyimide insulator with ε r = 3.5 is used and D = 15 μm and d = 3.15 μm (or D = 10 μm and d = 2.1 μm), the characteristic impedance Z 0 is 50Ω, and D = If 15 μm and d = 6.27 μm (or D = 10 μm, d = 4.18 μm), the characteristic impedance Z 0 is 28Ω.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to the drawings of manufacturing processes shown in FIGS.
In FIG. 1, a thin substrate obtained by thinly processing a semiconductor such as silicon, gallium arsenide, or indium phosphide is used to form a large number of deep holes as necessary by laser processing or dry etching processing. This hole is used for the through electrode structure. The depth of the hole is set to a value smaller than the thickness of the substrate by about 10 microns so as not to penetrate.
[0008]
In FIG. 2, solvent-soluble photosensitive polyimide prepared by block copolymerization using γ-valerolactone and pyridine as catalysts disclosed in US Pat. No. 5,502,143 is deposited by spin coating. In this process, the sample is evacuated before it is rotated, and after a required amount of polyimide is dropped, the sample is rotated. The holes can also be filled with polyimide.
[0009]
In FIG. 3, only the central part of the hole is exposed with an exposure apparatus using ultraviolet rays, X-rays, electron beams, etc., and development is performed using a developer. In this step, the depth of focus of the exposure apparatus is set as deep as possible. Further, the exposure pattern and the exposure amount are adjusted so that the polyimide has a desired thickness remaining on the side wall of the hole.
[0010]
In FIG. 4, a metal film such as aluminum, copper, gold, silver, palladium, titanium, or niobium is deposited from the front surface by sputtering, vacuum deposition, plating, plasma spraying, or the like. However, in the case of the plating method, after the seed layer is formed by a sputtering method, a vacuum deposition method or the like, the plating process is performed. In order to fill the through holes with metal, it is desirable to employ a plating process. For example, a plating technique called Jets Technology, which is devised so that the plating speed is accelerated in the fine holes disclosed in US Pat.
[0011]
In FIG. 5, the back surface is ground so that the metal part of the through electrode is exposed. The polyimide remaining on the upper surface can be removed by ashing with oxygen plasma.
[0012]
Here, the thickness of the thinned substrate is as thin as possible, and specifically, 100 μm or less is desirable.
[0013]
【The invention's effect】
According to the present invention, since the through-electrode structure formed in the integrated circuit chip can be a coaxial line structure, the characteristic impedance can be set to an arbitrary value, and the multilayer wiring circuit board Impedance matching with the micro-slip line wiring structure can be optimized, and ultrahigh-speed signal transmission within the circuit board becomes possible.
[Brief description of the drawings]
As an embodiment of the present invention, FIG. 1 to FIG.
FIG. 1 is a diagram of a drilling process for a basic member.
FIG. 2 is a view of a coating process of a imide insulating film.
FIG. 3 is a diagram of a process for forming a hole pattern in a polyimide insulating film embedded in FIG.
FIG. 4 is a diagram of a metal plating process for holes in a reimide insulating film.
FIG. 5 is a diagram of a grinding process of the back surface of the plate.
FIG. 6 is a diagram of a package on which a multi-layer stacked chip is mounted.

Claims (5)

半導体薄化基板について、微小径の深い穴を形成し、その後、感光性ポリイミドを前記穴の中に充填した後、紫外線、X線、電子ビーム又はイオンビームを用いて露光を行い、現像を行うことにより前記穴の中に充填された感光性ポリイミドの中心部に穴を形成した後、該穴にアルミニウム、銅、金、銀、パラジウム、チタン又はニオブである金属を充填し、その後、裏面を研削し、金属を露出させることにより、貫通電極を形成することを特徴とした貫通電極形成方法。For a semiconductor thinned substrate, a hole with a small diameter is formed, and after that photosensitive polyimide is filled into the hole, exposure is performed using ultraviolet rays, X-rays, an electron beam or an ion beam, and development is performed. after forming the hole in the center portion of the filled photosensitive polyimide in the hole by the row Ukoto, aluminum, copper, gold, silver, palladium, a metal is titanium or niobium filled into the hole, then A through electrode forming method, wherein the through electrode is formed by grinding the back surface and exposing the metal. 感光性ポリイミドとして、触媒を用いたブロック共重合法により作成され、溶媒に可溶な感光性ポリイミドを用いたことを特徴とする請求項１の貫通電極形成方法。2. The through electrode forming method according to claim 1, wherein the photosensitive polyimide is a photosensitive polyimide which is prepared by a block copolymerization method using a catalyst and is soluble in a solvent. 前記感光性ポリイミドは、ポジ型感光性ポリイミドであり、前記露光は、前記穴の中心部のみを露光することにより行なわれる請求項１又は２記載の方法。The method according to claim 1, wherein the photosensitive polyimide is a positive photosensitive polyimide, and the exposure is performed by exposing only a central portion of the hole. 前記半導体薄化基板がシリコン、ガリウムヒ素又はインジウム燐から成る請求項１ないし３のいずれか１項に記載の方法。4. A method according to any one of claims 1 to 3, wherein the semiconductor thinned substrate comprises silicon, gallium arsenide or indium phosphide. 感光性ポリイミドを前記穴の中に充填する工程は、該感光性ポリイミドを回転塗布により堆積させることにより行なわれる請求項１ないし４のいずれか１項に記載の方法。5. The method according to claim 1, wherein the step of filling the hole with photosensitive polyimide is performed by depositing the photosensitive polyimide by spin coating.
JP2002042756A 2002-02-20 2002-02-20 Method for forming through electrode using photosensitive polyimide Expired - Lifetime JP4154478B2 (en)

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JP4503963B2 (en) * 2003-09-18 2010-07-14 株式会社山武 Sensor electrode extraction method
FR2895568B1 (en) * 2005-12-23 2008-02-08 3D Plus Sa Sa COLLECTIVE MANUFACTURING METHOD OF 3D ELECTRONIC MODULES
JP2008277771A (en) * 2007-03-30 2008-11-13 Jsr Corp Method for film formation, structure having insulating film and its manufacturing method and electronic component
KR100879191B1 (en) * 2007-07-13 2009-01-16 앰코 테크놀로지 코리아 주식회사 Semiconductor package and fabricating method thereof
KR101025013B1 (en) * 2008-08-20 2011-03-25 한국전자통신연구원 Manufacturing method of stacked semiconductor package with the improved through via forming technology
EP2345933A4 (en) 2008-10-20 2013-01-23 Sumitomo Bakelite Co Positive photosensitive resin composition for spray coating and method for producing through electrode using same
KR101064757B1 (en) 2008-11-25 2011-09-15 한국전자통신연구원 Method of forming the through wafer via having thick insulation layer
JP5846185B2 (en) 2013-11-21 2016-01-20 大日本印刷株式会社 Through electrode substrate and semiconductor device using the through electrode substrate
JP7121499B2 (en) * 2018-02-07 2022-08-18 株式会社岡本工作機械製作所 Semiconductor device manufacturing method

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