JP4095706B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4095706B2
JP4095706B2 JP08080198A JP8080198A JP4095706B2 JP 4095706 B2 JP4095706 B2 JP 4095706B2 JP 08080198 A JP08080198 A JP 08080198A JP 8080198 A JP8080198 A JP 8080198A JP 4095706 B2 JP4095706 B2 JP 4095706B2
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layer
electrode
gate
semiconductor device
semiconductor layer
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JPH11284176A (en
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直樹 桜井
宏明 花岡
泰基 石田
学 下山
睦宏 森
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Hitachi Ltd
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Hitachi Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Electrodes Of Semiconductors (AREA)
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Description

【０００１】
【発明の属する技術分野】
本発明はＭＯＳゲートを有する半導体装置に関する。
【０００２】
【従来の技術】
パワーMOSFETや絶縁ゲートバイポーラトランジスタ（Insulated gate bipolartransistor以下ＩＧＢＴと称す）などのＭＯＳゲートをもちかつ大きな電流を制御する素子では、表面に多数のＭＯＳセルを形成し、縦方向に電流を流す。図１にＩＧＢＴを例として断面構造を示す。ｐ+ 層上にｎ- 層が形成され、ｎ- 層表面より多数のｐ層が形成されている。ｐ層内部には、ｎ+ 層が形成されている。また、ｎ+ 層，ｐ層，ｎ- 層にわたって表面にゲート酸化膜、さらにその上にゲート電極が設けられＭＯＳゲートを構成している。ゲート電極は絶縁膜によりおおわれ、表面をおおうエミッタ電極と絶縁されている。エミッタ電極はｐ層と
ｎ+ 層にオーミック接触している。また反対面（裏面）にはｐ+ 層と裏面電極がオーミック接触し、コレクタ電極となっている。
【０００３】
上記の構造の素子では、従来は、ＭＯＳゲートを設けないところにパットを設けワイヤボンデイングする方法であったが、導通面積を増やすために、エミッタ電極に直接ワイヤボンデイングする方法が一般的に利用されるようになっている。
【０００４】
【発明が解決しようとする課題】
従来は、エミッタ電極として、アルミニウムシリコン合金が使われてきた。これは、純粋なアルミニウムではシリコンがアルミニウムに拡散するため、ｐｎ接合が破壊されるため、それを防止するためである。パワーMOSFETやＩＧＢＴでは大きな電流が流れるため、ワイヤは数１００μｍの太いものを使用する。このワイヤをボンデイングするときの衝撃を緩和するためＬＳＩで使われるより厚い （３μｍ以上）アルミニウムシリコン合金を堆積して使用している。このため、堆積中にアルミニウムシリコン合金中のシリコンが集まってできるシリコン残さが成長しやすい。シリコン残さは堆積とともに大きくなるため表面付近の面積は小さく厚くあるに従って大きくなる。このため、表面付近がとがった形状となる。このシリコン残さ上にワイヤが打たれると、シリコン残さ先端に力が集中し、絶縁膜にクラックが入り、エミッタ電極とゲート電極の絶縁が破壊されるという問題があった。本発明は、従来と同等の主耐圧歩留まりを維持したまま、ワイヤボンデイング時の歩留まりを向上した半導体装置を提供することを目的とする。
【０００５】
【課題を解決するための手段】
本発明は、上記問題を解決するため、ＭＯＳゲートとその上にエミッタ電極が設けられさらにエミッタ電極にワイヤがボンデイングされている半導体装置において、エミッタ電極に純粋なアルミニウムが設けられ、かつエミッタ電極とMOSゲート間にバリア層を設けるものである。
【０００６】
純粋なアルミニウムを使用することによりシリコン残さをなくすことができる。これによりワイヤボンデイング時に発生するクラックを防止できワイヤボンデイング時の歩留まりを向上できる。さらに、バリア層によりシリコンがアルミニウムに拡散しｐｎ接合が破壊するのを防止できるため、従来と同等の主耐圧歩留まりが得られる。
【０００７】
【発明の実施の形態】
以下実施例を図面を使って、詳細に説明する。図２は、本発明の第１の実施例を示す。ｎ- 層表面１より多数のｐ層２が形成されている。ｐ層２内部には、
ｎ+ 層３が形成されている。また、ｎ+ 層３，ｐ層２，ｎ- 層１にわたって表面にゲート酸化膜１０、さらにその上にゲート電極１１が設けられＭＯＳゲートを構成している。ゲート電極１１は絶縁膜１２によりおおわれ、表面をおおうエミッタ電極２０と絶縁されている。エミッタ電極２０はｐ層２とｎ+ 層３にオーミック接触している。エミッタ電極２０上にはワイヤ３０がボンデイングされている。また、エミッタ電極２０と絶縁膜１２間にはバリア層２１が設けられている。エミッタ電極２０は純粋なアルミニウムにより形成されている。
【０００８】
純粋なアルミニウムを使用することによりシリコン残さをなくすことができる。これによりワイヤボンデイング時に発生するクラックを防止できワイヤボンデイング時の歩留まりを向上できる。さらに、バリア層によりシリコンがアルミニウムに拡散しｐｎ接合が破壊するのを防止できるため、従来と同等の主耐圧歩留まりが得られる。
【０００９】
バリア層２０としては、シリコンとの接触抵抗が小さいこと、高温の熱処理に耐えられること、従来のシリコンプロセスになじみやすいことからモリブデンシリサイドが望ましい。ところで、バリア層があまり薄いとシリコンが拡散してくるため、主耐圧歩留まりが低下する。図３は、モリブデンシリサイドの厚さと主耐圧歩留まりの関係を示したものである。モリブデンシリサイドの厚さが６００オングストローム以上で主耐圧不良が０になっている。これより、バリア層としてモリブデンシリサイドを使用する場合６００オングストローム以上必要である。
【００１０】
図４は、本発明の半導体装置をモジュールに組んだときの例である。絶縁板
５０上にはコレクタ配線５１，エミッタ配線５２，ゲート配線５３が設けられている。コレクタ配線５１上にはチップ６０が設けられ、コレクタ配線５１と図には現れていない裏面電極を通じてコレクタが接続されている。チップ６０表面にはゲートパット４０が設けられ、さらに導通領域は保護膜が部分的に取り除かれエミッタパット４１が設けられている。ゲートパット４０とゲート配線５３はゲートワイヤ３１により、またエミッタパット４１とエミッタ配線５２はエミッタワイヤ３２により接続されている。従来は、あまり強い力でワイヤをボンデイングするとシリコン残さによるクラックで不良が多発するため、弱い力でつけていた。本発明の半導体装置ではシリコン残さがないため、従来より強い力でボンデイングできるためワイヤに電流を繰り返し加えたときワイヤがはがれるまでの寿命を延ばすことができる。
【００１１】
図５は、本発明の半導体装置を使って構成したモータ駆動用インバータ回路の例を示す。図面の記号では半導体装置は１個しか示していないが、大電流を流すため、複数個の半導体装置が並列に接続されている。半導体装置２００には逆並列にダイオード２０１が接続されており、半導体装置が２個直列に接続され１相が形成されている。半導体装置が接続された中点より出力がでており、モータ
２０６と接続されている。上アーム側の半導体装置２００ａ,２００ｂ,２００ｃ，２００ｄのコレクタは共通であり、整流回路の高電位側と接続されている。また、下アーム側の半導体装置２００ｄ，２００ｅ，２００ｆのエミッタは共通であり、整流回路のアース側と接続されている。整流回路２０３は、交流２０２を直流に変換する。半導体装置２００は、この直流を受電し、再度交流に変換してモータを駆動する。上下の駆動回路２０４，２０５は、半導体装置のゲートに駆動信号を伝え、所定の周期で半導体装置をオン，オフさせる。本発明の半導体装置を組み込んだモジュールではワイヤに電流を繰り返し流したときワイヤがはがれるまでの時間が長くなるので、インバータの信頼性を向上させることができる。
【００１２】
【発明の効果】
純粋なアルミニウムを使用することによりシリコン残さをなくすことができる。これによりワイヤボンデイング時に発生するクラックを防止できワイヤボンデイング時の歩留まりを向上できる。さらに、バリア層によりシリコンがアルミニウムに拡散しｐｎ接合が破壊するのを防止できるため、従来と同等の主耐圧歩留まりが得られる。
【図面の簡単な説明】
【図１】従来例。
【図２】本発明の実施例。
【図３】モリブデンシリサイド厚と主耐圧不良の関係。
【図４】本発明を使用したモジュール。
【図５】本発明のＩＧＢＴを使ったインバータ回路。
【符号の説明】
１…ｎ- 層、２…ｐ層、３…ｎ+ 層、１０…ゲート酸化膜、１１…ゲート電極、１２…絶縁膜、２０…純粋なアルミニウム、２１…バリア層、３０…ワイヤ、３１…ゲートワイヤ、３２…エミッタワイヤ、４０…ゲートパット、４１…エミッタパット、５１…コレクタ配線、５２…エミッタ配線、５３…ゲート配線、
６０…チップ、２００…ＩＧＢＴ、２０１…ダイオード、２０２…交流電源、
２０３…整流回路、２０４…上アーム駆動回路、２０５…下アーム駆動回路、
２０６…モータ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a MOS gate.
[0002]
[Prior art]
In an element having a MOS gate and controlling a large current, such as a power MOSFET or an insulated gate bipolar transistor (hereinafter referred to as an IGBT), a large number of MOS cells are formed on the surface, and a current flows in the vertical direction. FIG. 1 shows a cross-sectional structure of an IGBT as an example. An n − layer is formed on the p + layer, and a large number of p layers are formed from the surface of the n − layer. An n + layer is formed inside the p layer. Further, a gate oxide film is provided on the surface over the n + layer, p layer, and n − layer, and a gate electrode is provided on the gate oxide film to constitute a MOS gate. The gate electrode is covered with an insulating film and insulated from the emitter electrode covering the surface. The emitter electrode is in ohmic contact with the p layer and the n + layer. The p + layer and the back electrode are in ohmic contact with the opposite surface (back surface) to form a collector electrode.
[0003]
In the device having the above structure, the conventional method is wire bonding by providing a pad where no MOS gate is provided. However, in order to increase the conduction area, a method of wire bonding directly to the emitter electrode is generally used. It has become so.
[0004]
[Problems to be solved by the invention]
Conventionally, an aluminum silicon alloy has been used as the emitter electrode. This is to prevent the pn junction from being broken because silicon diffuses into aluminum in pure aluminum. Since a large current flows in a power MOSFET or IGBT, a thick wire of several hundred μm is used. In order to reduce the impact when bonding this wire, a thicker (3 μm or more) aluminum silicon alloy used in LSI is deposited and used. For this reason, the silicon residue formed by the collection of silicon in the aluminum silicon alloy during deposition is likely to grow. Since the silicon residue increases with deposition, the area near the surface increases with decreasing thickness. For this reason, the surface vicinity becomes a sharp shape. When a wire is struck on the silicon residue, the force concentrates on the tip of the silicon residue, cracks are generated in the insulating film, and the insulation between the emitter electrode and the gate electrode is broken. An object of the present invention is to provide a semiconductor device in which the yield at the time of wire bonding is improved while maintaining the main breakdown voltage yield equivalent to the conventional one.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a semiconductor device in which a MOS gate and an emitter electrode are provided on the MOS gate, and a wire is bonded to the emitter electrode. A barrier layer is provided between the MOS gates.
[0006]
Silicon residue can be eliminated by using pure aluminum. Thereby, the crack which generate | occur | produces at the time of wire bonding can be prevented, and the yield at the time of wire bonding can be improved. Furthermore, since the barrier layer can prevent silicon from diffusing into aluminum and destroying the pn junction, a main breakdown voltage yield equivalent to the conventional one can be obtained.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments will be described in detail with reference to the drawings. FIG. 2 shows a first embodiment of the present invention. A number of p layers 2 are formed from the n − layer surface 1. In the p layer 2,
An n + layer 3 is formed. Further, a gate oxide film 10 is provided on the surface over the n + layer 3, the p layer 2, and the n − layer 1, and a gate electrode 11 is provided thereon to form a MOS gate. The gate electrode 11 is covered with an insulating film 12 and insulated from the emitter electrode 20 covering the surface. The emitter electrode 20 is in ohmic contact with the p layer 2 and the n + layer 3. A wire 30 is bonded onto the emitter electrode 20. A barrier layer 21 is provided between the emitter electrode 20 and the insulating film 12. The emitter electrode 20 is made of pure aluminum.
[0008]
Silicon residue can be eliminated by using pure aluminum. Thereby, the crack which generate | occur | produces at the time of wire bonding can be prevented, and the yield at the time of wire bonding can be improved. Furthermore, since the barrier layer can prevent silicon from diffusing into aluminum and destroying the pn junction, a main breakdown voltage yield equivalent to the conventional one can be obtained.
[0009]
As the barrier layer 20, molybdenum silicide is desirable because of its low contact resistance with silicon, resistance to high-temperature heat treatment, and easy compatibility with conventional silicon processes. By the way, if the barrier layer is too thin, silicon diffuses and the main breakdown voltage yield decreases. FIG. 3 shows the relationship between the molybdenum silicide thickness and the main breakdown voltage yield. The main breakdown voltage defect is 0 when the thickness of the molybdenum silicide is 600 angstroms or more. Accordingly, when molybdenum silicide is used as the barrier layer, 600 angstroms or more is necessary.
[0010]
FIG. 4 shows an example when the semiconductor device of the present invention is assembled in a module. On the insulating plate 50, a collector wiring 51, an emitter wiring 52, and a gate wiring 53 are provided. A chip 60 is provided on the collector wiring 51, and the collector is connected to the collector wiring 51 through a back electrode not shown in the drawing. A gate pad 40 is provided on the surface of the chip 60, and a protective film is partially removed from the conductive region, and an emitter pad 41 is provided. The gate pad 40 and the gate wiring 53 are connected by the gate wire 31, and the emitter pad 41 and the emitter wiring 52 are connected by the emitter wire 32. Conventionally, if a wire is bonded with a very strong force, defects often occur due to cracks caused by silicon residue, so it was applied with a weak force. Since there is no silicon residue in the semiconductor device of the present invention, it is possible to bond with a stronger force than before, so that the life until the wire is peeled off can be extended when a current is repeatedly applied to the wire.
[0011]
FIG. 5 shows an example of an inverter circuit for driving a motor constructed using the semiconductor device of the present invention. Although only one semiconductor device is shown by the symbol in the drawing, a plurality of semiconductor devices are connected in parallel to flow a large current. A diode 201 is connected in antiparallel to the semiconductor device 200, and two semiconductor devices are connected in series to form one phase. The output is from the midpoint where the semiconductor device is connected, and is connected to the motor 206. The collectors of the semiconductor devices 200a, 200b, 200c, and 200d on the upper arm side are common and are connected to the high potential side of the rectifier circuit. Further, the emitters of the semiconductor devices 200d, 200e, and 200f on the lower arm side are common and are connected to the ground side of the rectifier circuit. The rectifier circuit 203 converts the alternating current 202 into direct current. The semiconductor device 200 receives this direct current, converts it again into alternating current, and drives the motor. The upper and lower drive circuits 204 and 205 transmit a drive signal to the gate of the semiconductor device, and turn the semiconductor device on and off at a predetermined cycle. In the module incorporating the semiconductor device of the present invention, when a current is repeatedly passed through the wire, the time until the wire is peeled off becomes longer, so that the reliability of the inverter can be improved.
[0012]
【The invention's effect】
Silicon residue can be eliminated by using pure aluminum. Thereby, the crack which generate | occur | produces at the time of wire bonding can be prevented, and the yield at the time of wire bonding can be improved. Furthermore, since the barrier layer can prevent silicon from diffusing into aluminum and destroying the pn junction, a main breakdown voltage yield equivalent to the conventional one can be obtained.
[Brief description of the drawings]
FIG. 1 is a conventional example.
FIG. 2 shows an embodiment of the present invention.
FIG. 3 shows the relationship between molybdenum silicide thickness and main breakdown voltage failure.
FIG. 4 is a module using the present invention.
FIG. 5 is an inverter circuit using the IGBT of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... n < - > layer, 2 ... p layer, 3 ... n + layer, 10 ... Gate oxide film, 11 ... Gate electrode, 12 ... Insulating film, 20 ... Pure aluminum, 21 ... Barrier layer, 30 ... Wire, 31 ... Gate wire, 32 ... emitter wire, 40 ... gate pad, 41 ... emitter pad, 51 ... collector wiring, 52 ... emitter wiring, 53 ... gate wiring,
60 ... Chip, 200 ... IGBT, 201 ... Diode, 202 ... AC power supply,
203 ... rectifier circuit, 204 ... upper arm drive circuit, 205 ... lower arm drive circuit,
206: Motor.

Claims (3)

第１導電型の第１の半導体層と
第１の半導体の表面より形成された第２導電型の第２の半導体層と
第２の半導体層中に形成された第１導電型の第３の半導体層と
第３の半導体層，第１の半導体層，第２の半導体層表面に形成されたゲート酸化膜と
ゲート酸化膜上に形成されたゲート電極と
ゲート電極をおおう絶縁膜と
絶縁膜上に形成され、第２及び第３の半導体層とオーミック接触する電極と電極上に設けられたワイヤを有する半導体装置において
上記電極はアルミニウムであり、かつ電極と絶縁膜間にバリア層が設けられており、
該バリア層がモリブデンシリサイドであり、
該モリブデンシリサイドの厚さが６００オングストローム以上であることを特徴とする半導体装置。 A first conductive type first semiconductor layer; a second conductive type second semiconductor layer formed from the surface of the first semiconductor; and a first conductive type third semiconductor layer formed in the second semiconductor layer Semiconductor layer, third semiconductor layer, first semiconductor layer, gate oxide film formed on the surface of second semiconductor layer, gate electrode formed on gate oxide film, insulating film covering gate electrode, and insulating film A semiconductor device having an electrode in ohmic contact with the second and third semiconductor layers and a wire provided on the electrode
The electrode is aluminum, and a barrier layer is provided between the electrode and the insulating film ,
The barrier layer is molybdenum silicide;
A semiconductor device, wherein the thickness of the molybdenum silicide is 600 angstroms or more. 請求項１の半導体装置を使用したモジュール。A module using the semiconductor device according to claim 1. 請求項２のモジュールを使用したインバータ装置。An inverter device using the module according to claim 2.
JP08080198A 1998-03-27 1998-03-27 Semiconductor device Expired - Lifetime JP4095706B2 (en)

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US6703707B1 (en) * 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
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