JP4092214B2 - Semiconductor device - Google Patents

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JP4092214B2
JP4092214B2 JP2003008769A JP2003008769A JP4092214B2 JP 4092214 B2 JP4092214 B2 JP 4092214B2 JP 2003008769 A JP2003008769 A JP 2003008769A JP 2003008769 A JP2003008769 A JP 2003008769A JP 4092214 B2 JP4092214 B2 JP 4092214B2
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hole
insulating film
holes
semiconductor device
pad electrode
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JP2004221430A (en
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林　　哲也
寿史 高橋
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NEC Electronics Corp
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NEC Electronics Corp
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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置、特に、ボンディング強度向上のため、ボンディングパッド部にスルーホールを設けたものにおいて、プロービング強度の低下を防止した半導体装置に関するものである。
【０００２】
【従来の技術】
ボンディング強度を向上させた半導体装置としては、従来、図１０および図１１に示すようなものがある（例えば、特許文献１参照。）。以下、これを従来技術１と称する。
【０００３】
図１０は、従来技術１のボンディングパッド部の平面図、図１１は図１０の１０Ａ−１０Ａ’における断面図を示している。
【０００４】
従来技術１では、図１１に示すように、半導体基板１１１上に形成された層間絶縁膜１１２ａの上に、第１のパッド電極１１４ａが形成され、第１のパッド電極１１４ａ上に、シリコン酸化膜等からなる層間絶縁膜１１２ｂが形成され、層間絶縁膜１１２ｂに複数のスルーホール１１５が形成されている。複数のスルーホール１１５には金属層１１６が埋めこまれ、その上面は層間絶縁膜１１２ｂよりも低くされている。第２のパッド電極１１４ｂが金属層１１６および層間絶縁膜１１２ｂ上に形成され、それを覆う保護膜１１３に設けられた開口に露出した第２のパッド電極１１４ｂの上面がボンディングパッドとなる。
【０００５】
従来技術１では、上記のようにスルーホール１１５に埋めこまれる金属層１１６の上面を層間絶縁膜１１２ｂよりも低くすることにより、第２の金属パッド１１４ｂと層間絶縁膜１１２ｂとの界面が凹凸になるため、第２の金属パッド１１４ｂと層間絶縁膜１１２ｂとの密着性が向上し、ボンディング時における界面の滑りが防止され、ボンディング強度が向上する。
【０００６】
しかしながら、従来技術１では、パッド電極１１４ｂにプローブを当てて電気的測定を行なう際に、プローブが当たる時の衝撃によって、層間絶縁膜１１２ｂにクラックが発生するという問題が生じることがわかった。そしてその原因は、図１０に示すように、複数のスルーホール１１５が、マトリクス状に整列しているため、１０Ｂ−１０Ｂ’線上のように、層間絶縁膜１１２ｂが直線状に連続して存在する部分があり、プローブをこの方向に当てると、その層間絶縁膜１１２ｂの直線状の連続した部分にクラックが発生し易いためであると判明した。すなわち、層間絶縁膜として用いられるシリコン酸化膜等の絶縁膜はクラックが発生し易い膜であるため、図１２に示すように、プローブ１２０を図の矢印の方向に当てると、その方向における層間絶縁膜１１２ｂの直線状の連続した部分に１２１のようにクラックが発生する。また、下層のパッド電極１１４ａは、一般に上層の電極よりも厚さを薄くする場合が多く、このような場合、プローブの当たる衝撃の程度によっては、層間絶縁膜１１２ｂだけでなく、その下のパッド電極１１４ａまで、あるいはさらにその下の層間絶縁膜１１２ａにまでクラックが達する場合もある。このように、大きなクラックが発生すると、ボンディング強度の低下等の問題が生じることとなる。
【０００７】
一方、別の従来技術として、図１３および図１４に示されるようなものがある（例えば、特許文献２参照。）。以下、これを従来技術２と称する。
【０００８】
図１３は、従来技術２のボンディングパッド部の斜視図、図１４は図１３の１３Ａ−１３Ａ’における断面図を示している。
【０００９】
従来技術２では、図１４に示すように、半導体基板１３１上の絶縁膜１３２ａ上に形成された絶縁膜１３２ｂに複数の溝１３５が設けられ、その溝を埋め込むように電極層１３４が形成されている。電極層および絶縁膜１３２ｂ上に絶縁膜１３３が形成され、該絶縁膜１３３に形成された開口に露出する電極層１３４の上面がボンディングパッドとなっている。複数の溝１３５は、図１３のように、１３Ａ−１３Ａ’の方向に複数平行に配置されている。
【００１０】
なお、従来技術２において、溝１３５は、図１５の平面図に示すように、縦横に交差するように（格子状に）形成される場合もある。
【００１１】
このような従来技術２においては、図１３の１３Ａ−１３Ａ’の方向（溝１３５と交差する方向）には、絶縁膜１３２ｂが直線状にならず、不連続となっているため、プローブによる電気的測定の際、この方向にプローブを当てれば、上記従来技術１で生じるようなクラックの発生は防止、あるいは低減できると考えられる。溝１３５が図１５のように形成される場合も同様である。
【００１２】
【特許文献１】
特許第２９６４９９９号公報
【特許文献２】
特開２０００−３５７７０８号公報
【００１３】
【発明が解決しようとする課題】
しかしながら、従来技術２では、図１４および図１５のいずれも、溝１３５の開口面積が大きいために、溝形成のためのエッチングにおいて、加工が困難になるという問題が生じる。
【００１４】
すなわち、この溝１３５を形成するためのエッチング処理は、図示しない素子領域においてスルーホールを形成するためのエッチング処理と同時に行なわれるのが工程の増加を防ぐために好ましいが、溝１３５の開口面積は、素子領域のスルーホールと比較して非常に大きいため、素子領域のスルーホールと溝１３５のエッチング速度は大きく異なることになる。そのため、素子領域のスルーホールとボンディングパッド部の溝１３５とを同時にそれぞれ所望の深さに加工するのは極めて困難である。
【００１５】
したがって、本発明の目的は、ボンディングパッド部のボンディング強度を高くするとともに、プロービングにおいて層間絶縁膜にクラックが発生するのを防止することが可能であり、容易に製造することが可能な半導体装置を提供することにある。
【００１６】
【課題を解決するための手段】
本発明による半導体装置は、半導体基板上に選択的に設けられた第１パッド電極と、上記第１パッド電極上に設けられた第１絶縁膜と、上記第１パッド電極上において上記第１絶縁膜に選択的に設けられ、上記第１パッド電極に達する複数のスルーホールと、上記複数のスルーホールそれぞれに埋め込まれた金属層と、上記第１絶縁膜および上記複数のスルーホール上に選択的に設けられた第２パッド電極と、上記第２パッド電極の周辺部および上記第１絶縁膜を覆い、上記第２パッド電極の上記周辺部を除く上面を露出する開口を有する第２絶縁膜とを備え、上記第２パッド電極の上記開口に露出した上面がボンディングパッドとなる半導体装置であって、上記複数の第１スルーホールは、上記ボンディングパッドの縦方向および横方向それぞれに複数配置され、
上記横方向の隣り合う第１スルーホールの間において、上記縦方向に延在する直線上に上記第１スルーホールが複数配置されており、上記縦方向が上記半導体装置の電気的測定時に上記ボンディングパッドにプローブが当てられる方向と一致することを特徴としている。
【００１７】
このように、本発明によれば、半導体装置の電気的測定の際、プローブの当たる方向には第１絶縁膜が連なって存在せず、その方向の直線上には必ず複数のスルーホールに埋め込まれた金属層が介在しており、金属層は外部からストレスが加わってもクラックが発生し難いため、プローブの押圧によるクラックの発生を抑制することができる。また、スルーホールは、ボンディングパッドの縦方向および横方向のいずれにも複数形成されているため、そのホールの大きさは、ボンディングパッド部以外の素子領域に形成されるスルーホールの大きさと同等、あるいは大きさの差を小さくすることができ、従って、容易に両者を同時に形成することが可能となる。
【００１８】
また、本発明の半導体装置では、隣り合うスルーホールの間の領域を通る全ての方向の直線上に前記第１スルーホールが複数配置されていてもよい。かかる構成によれば、プローブの当たる方向が、上記縦方向と若干ずれた場合においても、そのずれた方向の直線上にも第１絶縁膜は連なって存在しないため、より確実にクラックの発生を防止できる。
【００１９】
【発明の実施の形態】
以下、本発明の上記および他の目的、特徴および利点を明確にすべく、添付した図面を参照しながら、本発明の実施の形態を以下に詳述する。
【００２０】
〔第１実施例〕
図１は、本発明の第１実施例による半導体装置におけるボンディングパッド部のマスクパターンを示している。図２は、図１のＡ−Ａ’線に対応するボンディングパッド部および素子領域の一部の断面図を示している。
【００２１】
図２に示されるように、ボンディングパッド部は、半導体基板１上に設けられたシリコン酸化膜からなる層間絶縁膜２ａ上に第１のパッド電極４ａが形成され、パッド電極４ａ上に、シリコン酸化膜からなる層間絶縁膜２ｂが形成され、層間絶縁膜２ｂに複数のスルーホール５が形成され、複数のスルーホール５には、タングステン膜が埋めこまれて金属プラグ６が形成されている。さらに、層間絶縁膜２ｂおよび複数の金属プラグ６上に第２の電極パッド４ｂが形成され、電極パッド４ｂ上にシリコン酸化膜からなる層間絶縁膜２ｃおよび保護膜３としてポリイミド膜が形成され、電極パッド４ｂの上面を露出するように保護膜３および層間絶縁膜２ｃに開口が設けられている。
【００２２】
図１における各パターンは、５’が図２のスルーホール５に、３’が図２の保護膜３の開口に、４ａ’がパッド電極４ａに、４ｂ’が電極パッド４ｂに対応している。なお、スルーホールパターン５’は正方形をなしているが、このマスクパターンを用いて形成される図２のスルーホール５は、角が丸くなるため、図１０の従来技術におけるスルーホール１１５と同様に円形となる。
【００２３】
本実施例のスルーホール５のマスクパターン５’は、図１に示されるように、本発明に従って、ボンディングパッド部におけるボンディングパッドの縁部を除く縦方向（Ａ−Ａ’方向）のいずれの場所においてもシリコン酸化膜２ｂがスルーホール５によって不連続とされるように配置されている。すなわち、横方向（Ｂ−Ｂ’方向）に隣り合うスルーホールの間の縦方向に延在する領域には、必ず複数のスルーホールが配置されている。なお、図１においては、スルーホールパターンは一部のみ示し、その他は省略しているが、実際はパッド全域（保護膜３の開口に露出する部分）に渡ってスルーホールが配置される。
【００２４】
そして、上記のように配置された複数のスルーホール５を有するボンディングパッドが、パッド電極４ｂにプローブを当てて電気的測定を行なう際に、図１のＡ−Ａ’の方向がプローブの当たる方向と一致するように半導体チップ上に配置される。すなわち、プローブ１００は、図２に示されるような方向でパッド電極４ｂに押し当てられる。
【００２５】
本実施例によれば、上記のように、プロービングの際、プローブが当たる方向において、シリコン酸化膜２ｂが不連続になっており、クラックの発生し難い材質である金属プラグ６が介在していることにより、プローブが電極パッド４ｂに当たる衝撃によってシリコン酸化膜２ｂに大きなクラックが発生することを防止することができる。プローブ１００の当たった部分のシリコン酸化膜２ｂに若干のクラックが発生する場合もあるが、すぐ隣に金属プラグ６が存在することにより、クラックはそれ以上大きくならず、半導体装置として問題とならない程度にクラックの発生を抑えることができる。
【００２６】
また、図２に示されるように、素子領域には、層間絶縁膜２ａ上に第１の配線７ａが、層間絶縁膜２ｂ上に第２の配線７ｂが形成され、第１および第２の配線７ａ，７ｂを接続するスルーホール８が層間絶縁膜２ｂに形成され、スルーホール８にはタングステン膜が埋めこまれて、第１および第２配線を電気的に接続する金属プラブ９が形成されている。
【００２７】
本半導体装置の製造においては、第１の配線７ａと第１のパッド電極４ａとが同時に（同じ工程で）、第２の配線７ｂと第２のパッド電極４ｂとが同時に形成される。また、ボンディングパッド部のスルーホール５と素子部のスルーホール８とが同時に、タングステンプラグ６および９とが同時に形成される。
【００２８】
スルーホール５および８は、層間絶縁膜２ｂ上にレジストパターンを形成し、該レジストパターンをマスクに、層間絶縁膜２ｂをエッチングすることにより同時に形成される。
【００２９】
本実施例においては、図１に示されるように、ボンディングパッド部に形成されるスルーホールが、パッドの縦方向（プロービングの方向）だけでなく、横方向（プロービング方向と垂直な方向）にも複数形成されているため、ボンディングパッド部のスルーホール５の面積が、素子部のスルーホール９の面積に対して極端に大きくなってしまうことがない。従って、パッド部スルーホール５と素子部スルーホール９とを同時に形成する場合でも、エッチング速度に大きな差が生じないため、スルーホール５および９それぞれを所望の深さに形成することが可能となる。
【００３０】
ここで、面積の異なるホールを同時に開口する場合、面積の小さいホールではエッチング速度が遅いため、アンダーエッチングに、面積の大きいホールではエッチング速度が早いため、オーバーエッチングになり、このエッチング速度の差が１０％を越えると、製造上のエッチマージンを確保できない。したがって、パッド部のスルーホール５の面積を、素子部のスルーホール９の面積に対し、エッチング速度の差が１０％以下となるような面積とするのが好ましい。
【００３１】
このように、本実施例によれば、ボンディング耐性向上のためにパッド部に設ける複数のスルーホールを、該スルーホールが形成される層間絶縁膜がプロービングの方向に不連続となるように配置し、さらに、プロービング方向と垂直な方向にもスルーホールを複数配置した構成とすることにより、ボンディング耐性を向上させるとともに、プロービングにおけるクラックの発生を抑えることが可能であり、且つ加工性のよい半導体装置が得られる。
【００３２】
なお、本実施例では、図２に示されるように、層間絶縁膜２ｂと第２パッド電極４ｂとの界面は平坦となっており、図１１の従来技術のように凹凸にはなっていないが、図２のように平坦であっても、スルーホール５に埋めこまれるタングステンプラグ６は、パッド電極４ｂとの密着性が良いため、スルーホール５が複数設けられていることにより、層間絶縁膜２ｂおよびタングステンプラグ６の上面とパッド電極４ｂとの界面の密着性が高くなるため、十分なボンディング耐性が得られる。勿論、本発明においても、図１１のように界面を凹凸にしてもかまわない。
【００３３】
〔第２実施例〕
図３および図４は、本実施例による半導体装置におけるボンディングパッド部のマスクパターンを示している。
【００３４】
図３は、図１のスルーホールパターン５’を十字状にした場合のマスクパターン、図４は、スルーホールパターン５’をＬ字状にした場合のマスクパターンを示している。
【００３５】
図３および４のＡ−Ａ’線に対応するボンディングパッド部および素子領域の一部の断面図は、実施例１と同様、図２のようになっている。なお、これらのスルーホールパターン５’を用いて形成されるスルーホール５の形状は、十字、Ｌ字の角部が丸みを帯びたものとなる。
【００３６】
図３および図４においても、第１実施例と同様に、複数のスルーホールパターンが、Ａ−Ａ’の方向、すなわちプロービングの方向に層間絶縁膜であるシリコン酸化膜２ｂが不連続となるように配置されており、これにより、プロービング時のクラックを抑制することができる。
【００３７】
また、十字・Ｌ字のスルーホールパターンの面積は、第１実施例と同様、素子部に形成されるスルーホールとこれら十字またはＬ字のスルーホールとを同時に形成する際に、エッチング速度の差が１０％以下となるような大きさとされている。したがって、スルーホールの加工性も良い。
【００３８】
さらに、本実施例では、図３および図４のように、ホールパターンを矩形以外の形状にすることにより、スルーホール５を第１実施例よりも密に配置することが可能となる。このように、スルーホール５（金属プラグ６）が密に配置されることにより、金属プラグ６および層間絶縁膜２ｂの上面と電極パッド４ｂの下面との界面の密着性が高まるため、第１実施例よりもさらにボンディング強度を向上させることができる。
【００３９】
［第３実施例］
図５〜９は、本実施例による半導体装置におけるボンディングパッド部のマスクパターンを示している。図５〜９のＡ−Ａ’線に対応するボンディングパッド部および素子領域の一部の断面図は、実施例１と同様、図２のようになっている。なお、これらのスルーホールパターン５’を用いて形成されるスルーホール５の形状も、角部が丸みを帯びたものとなる。
【００４０】
図５〜９に示すように、本実施例では、スルーホールパターン５’がそれぞれ、階段状、Ｖ字、Ｈ字、Ｔ字、Ｉ字（長方形）、となっており、適宜向きを変える等して配置することにより、シリコン酸化膜２ｂが全ての方向に不連続とされている。すなわち、隣り合うスルーホールに挟まれた領域を通る全ての方向の直線上に、必ず複数のスルーホールが配置されている。
【００４１】
また、図５〜９のスルーホールパターン５’の面積も、第１実施例と同様、素子部に形成されるスルーホールとこれらボンディングパッド部のスルーホール５とを同時に形成する際に、エッチング速度の差が１０％以下となるような大きさとされている。したがって、スルーホールの加工性も良い。
【００４２】
第１および第２実施例では、シリコン酸化膜２ｂがプロービングの方向に不連続となるようにスルーホール５を配置しており、これにより、プロービング時のクラックの発生を十分に抑えることが可能と考えられるが、プローブの押圧の仕方によっては、衝撃が大きくなる、あるいは衝撃の伝わる方向がプローブを当てる方向とずれてしまうというような場合も考えられ、このような場合、第１および第２実施例の構成では、クラックを十分に防止できない可能性も考えられる。すなわち、第１および第２実施例では、図１、３および４のＢ−Ｂ’線上のように、シリコン酸化膜２ｂが直線状に連続して存在する部分があり、この方向にプロービングの衝撃が伝わった場合、クラックが発生する可能性がある。
【００４３】
これに対し、本実施例では、上記のようにシリコン酸化膜２ｂが全ての方向に不連続となるようなスルーホール５の形状および配置とすることにより、プロービング時にボンディングパッドに加わる衝撃の方向がプローブの方向とずれた場合でも、確実にクラックの発生を抑制することが可能となる。
【００４４】
以上、本発明の実施の形態につき説明してきたが、本発明は上記各実施例に限定されず、本発明の技術思想の範囲内において、各実施例は適宜変更され得ることは明らかである。
【００４５】
例えば、スルーホールパターンは、上記したものに限らず、プロービングの方向に層間絶縁膜２ｂが不連続となるようにできるものであり、かつ加工性の良いものであればどのような形状でもよい。
【００４６】
また、上記各実施例では、ボンディングパッドの縁部にはスルーホールが配置されない例を示したが、縁部に接して配置されるスルーホールがあっても構わない。
【００４７】
【発明の効果】
以上説明した通り、本発明によれば、ボンディングパッド部にスルーホールを設けることによりボンディング強度を向上させるとともにプロービング時のクラック発生を抑制し、かつ加工性の良好な半導体装置が得られる。
【図面の簡単な説明】
【図１】本発明の第１実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図２】図１のＡ−Ａ’線に対応する半導体装置の断面図である。
【図３】本発明の第２実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図４】本発明の第２実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図５】本発明の第３実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図６】本発明の第３実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図７】本発明の第３実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図８】本発明の第３実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図９】本発明の第３実施例による半導体装置のボンディングパッド部のマスクパターンを示す図である。
【図１０】従来技術１による半導体装置のボンディングパッドの平面図である。
【図１１】図１０の１０Ａ−１０Ａ’における断面図である。
【図１２】従来技術１における問題点を説明するためのボンディングパッドの平面図である。
【図１３】従来技術２による半導体装置のボンディングパッドの斜視図である。
【図１４】図１３の１３Ａ−１３Ａ’における断面図である。
【図１５】従来技術２の別の例によるボンディングパッドの平面図である。
【符号の説明】
１ 半導体基板
２ａ、２ｂ、２ｃ、１１２ａ、１１２ｂ、１３２ａ、１３２ｂ 層間絶縁膜
３、１１３、１３３ 保護膜
４ａ、４ｂ、１１４ａ、１１４ｂ パッド電極
５、８、１１５ スルーホール
３’，４ａ’，４ｂ’，５’ マスクパターン
６、９、１１６ 金属プラグ
７ａ、７ｂ 配線
１００、１２０ プローブ
１２１ クラック
１３４ 電極層
１３５ 溝[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a decrease in probing strength is prevented in a case where a through hole is provided in a bonding pad portion in order to improve bonding strength.
[0002]
[Prior art]
Conventionally, semiconductor devices with improved bonding strength include those shown in FIGS. 10 and 11 (see, for example, Patent Document 1). Hereinafter, this is referred to as Prior Art 1.
[0003]
FIG. 10 is a plan view of the bonding pad portion of prior art 1, and FIG. 11 is a cross-sectional view taken along 10A-10A ′ of FIG.
[0004]
In prior art 1, as shown in FIG. 11, a first pad electrode 114a is formed on an interlayer insulating film 112a formed on a semiconductor substrate 111, and a silicon oxide film is formed on the first pad electrode 114a. An interlayer insulating film 112b made of, for example, is formed, and a plurality of through holes 115 are formed in the interlayer insulating film 112b. A metal layer 116 is buried in the plurality of through holes 115, and the upper surface thereof is lower than the interlayer insulating film 112b. The second pad electrode 114b is formed on the metal layer 116 and the interlayer insulating film 112b, and the upper surface of the second pad electrode 114b exposed in the opening provided in the protective film 113 covering the second pad electrode 114b serves as a bonding pad.
[0005]
In the prior art 1, the interface between the second metal pad 114b and the interlayer insulating film 112b is uneven by making the upper surface of the metal layer 116 buried in the through hole 115 lower than the interlayer insulating film 112b as described above. Therefore, the adhesion between the second metal pad 114b and the interlayer insulating film 112b is improved, the interface slip during bonding is prevented, and the bonding strength is improved.
[0006]
However, it has been found that the prior art 1 has a problem that a crack is generated in the interlayer insulating film 112b due to an impact when the probe hits the probe when the probe is applied to the pad electrode 114b. Then, as shown in FIG. 10, since the plurality of through holes 115 are arranged in a matrix, the interlayer insulating film 112b is continuously present in a straight line as on line 10B-10B ′. It has been found that when there is a portion and the probe is applied in this direction, cracks are likely to occur in the linear continuous portion of the interlayer insulating film 112b. That is, since an insulating film such as a silicon oxide film used as an interlayer insulating film is a film that easily generates cracks, as shown in FIG. 12, when the probe 120 is applied in the direction of the arrow in the figure, the interlayer insulating film in that direction is shown. Cracks are generated as indicated by 121 in the linear continuous portion of the film 112b. In addition, the lower pad electrode 114a is generally thinner than the upper electrode. In such a case, depending on the degree of impact of the probe, not only the interlayer insulating film 112b but also the pad below it is used. In some cases, cracks may reach the electrode 114a or even the interlayer insulating film 112a below the electrode 114a. Thus, when a big crack generate | occur | produces, problems, such as a fall of bonding strength, will arise.
[0007]
On the other hand, as another prior art, there is one as shown in FIGS. 13 and 14 (see, for example, Patent Document 2). Hereinafter, this is referred to as Prior Art 2.
[0008]
FIG. 13 is a perspective view of the bonding pad portion of the prior art 2, and FIG. 14 is a cross-sectional view taken along line 13A-13A ′ of FIG.
[0009]
In prior art 2, as shown in FIG. 14, a plurality of grooves 135 are provided in an insulating film 132b formed on an insulating film 132a on a semiconductor substrate 131, and an electrode layer 134 is formed so as to fill the grooves. Yes. An insulating film 133 is formed on the electrode layer and the insulating film 132b, and the upper surface of the electrode layer 134 exposed in the opening formed in the insulating film 133 serves as a bonding pad. As shown in FIG. 13, the plurality of grooves 135 are arranged in parallel in the direction of 13A-13A ′.
[0010]
In the prior art 2, as shown in the plan view of FIG. 15, the groove 135 may be formed so as to intersect vertically and horizontally (in a lattice shape).
[0011]
In such a conventional technique 2, the insulating film 132b is not linear but discontinuous in the direction of 13A-13A ′ in FIG. 13 (the direction intersecting the groove 135). It is considered that the occurrence of cracks as occurs in the prior art 1 can be prevented or reduced if the probe is applied in this direction at the time of target measurement. The same applies when the groove 135 is formed as shown in FIG.
[0012]
[Patent Document 1]
Japanese Patent No. 2964999 [Patent Document 2]
JP 2000-357708 A [0013]
[Problems to be solved by the invention]
However, in the related art 2, since both of FIG. 14 and FIG. 15 have a large opening area of the groove 135, there arises a problem that processing becomes difficult in etching for forming the groove.
[0014]
That is, the etching process for forming the groove 135 is preferably performed simultaneously with the etching process for forming a through hole in an element region (not shown) in order to prevent an increase in the number of steps. Since it is very large compared to the through hole in the element region, the etching rate of the through hole in the element region and the trench 135 is greatly different. For this reason, it is extremely difficult to process the through hole in the element region and the groove 135 in the bonding pad portion simultaneously to a desired depth.
[0015]
Accordingly, an object of the present invention is to provide a semiconductor device that can increase the bonding strength of the bonding pad portion and prevent cracks in the interlayer insulating film during probing and can be easily manufactured. It is to provide.
[0016]
[Means for Solving the Problems]
The semiconductor device according to the present invention includes a first pad electrode selectively provided on a semiconductor substrate, a first insulating film provided on the first pad electrode, and the first insulation on the first pad electrode. A plurality of through-holes selectively provided in the film and reaching the first pad electrode; a metal layer embedded in each of the plurality of through-holes; and the first insulating film and the plurality of through-holes selectively. A second pad electrode provided on the second pad electrode, and a second insulating film covering the peripheral portion of the second pad electrode and the first insulating film, and having an opening exposing an upper surface excluding the peripheral portion of the second pad electrode; And the upper surface of the second pad electrode exposed at the opening serves as a bonding pad, wherein the plurality of first through holes are formed in the longitudinal and lateral directions of the bonding pad. A plurality placed in, respectively,
A plurality of the first through holes are arranged on a straight line extending in the vertical direction between the adjacent first through holes in the horizontal direction, and the vertical direction is used for the bonding when the semiconductor device is electrically measured. It is characterized in that it coincides with the direction in which the probe is applied to the pad.
[0017]
As described above, according to the present invention, in the electrical measurement of the semiconductor device, the first insulating film does not exist continuously in the direction in which the probe hits, and the plurality of through holes are necessarily embedded on the straight line in the direction. Since the metal layer is interposed, and the metal layer is hardly cracked even when stress is applied from the outside, the generation of the crack due to the pressing of the probe can be suppressed. In addition, since a plurality of through holes are formed in both the vertical direction and the horizontal direction of the bonding pad, the size of the hole is the same as the size of the through hole formed in the element region other than the bonding pad portion. Alternatively, the difference in size can be reduced, and therefore both can be easily formed simultaneously.
[0018]
In the semiconductor device of the present invention, a plurality of the first through holes may be arranged on straight lines in all directions passing through a region between adjacent through holes. According to such a configuration, even when the direction in which the probe hits slightly deviates from the vertical direction, the first insulating film does not exist continuously on the straight line in the deviated direction, so that cracks can be generated more reliably. Can be prevented.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0020]
[First embodiment]
FIG. 1 shows a mask pattern of a bonding pad portion in a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a sectional view of a part of the bonding pad portion and the element region corresponding to the line AA ′ in FIG.
[0021]
As shown in FIG. 2, in the bonding pad portion, a first pad electrode 4a is formed on an interlayer insulating film 2a made of a silicon oxide film provided on a semiconductor substrate 1, and a silicon oxide film is formed on the pad electrode 4a. An interlayer insulating film 2b made of a film is formed, a plurality of through holes 5 are formed in the interlayer insulating film 2b, and a tungsten film is embedded in the plurality of through holes 5 to form metal plugs 6. Further, a second electrode pad 4b is formed on the interlayer insulating film 2b and the plurality of metal plugs 6. A polyimide film is formed on the electrode pad 4b as an interlayer insulating film 2c made of a silicon oxide film and a protective film 3. An opening is provided in the protective film 3 and the interlayer insulating film 2c so as to expose the upper surface of the pad 4b.
[0022]
In each pattern in FIG. 1, 5 ′ corresponds to the through hole 5 in FIG. 2, 3 ′ corresponds to the opening of the protective film 3 in FIG. 2, 4a ′ corresponds to the pad electrode 4a, and 4b ′ corresponds to the electrode pad 4b. . Although the through-hole pattern 5 ′ is square, the through-hole 5 of FIG. 2 formed using this mask pattern has rounded corners, so that it is similar to the through-hole 115 in the prior art of FIG. It becomes a circle.
[0023]
As shown in FIG. 1, the mask pattern 5 ′ of the through-hole 5 of this embodiment is located anywhere in the vertical direction (AA ′ direction) excluding the bonding pad edge in the bonding pad portion according to the present invention. The silicon oxide film 2b is disposed so as to be discontinuous by the through hole 5. That is, a plurality of through holes are always arranged in a region extending in the vertical direction between through holes adjacent in the horizontal direction (BB ′ direction). In FIG. 1, although only a part of the through hole pattern is shown and the others are omitted, in actuality, the through hole is arranged over the entire pad area (the part exposed at the opening of the protective film 3).
[0024]
When the bonding pad having the plurality of through holes 5 arranged as described above applies electrical measurement by applying a probe to the pad electrode 4b, the direction of AA ′ in FIG. Are arranged on the semiconductor chip so as to coincide with. That is, the probe 100 is pressed against the pad electrode 4b in the direction as shown in FIG.
[0025]
According to the present embodiment, as described above, in probing, the silicon oxide film 2b is discontinuous in the direction in which the probe hits, and the metal plug 6 which is a material that does not easily generate cracks is interposed. As a result, it is possible to prevent a large crack from occurring in the silicon oxide film 2b due to the impact of the probe hitting the electrode pad 4b. Although some cracks may occur in the silicon oxide film 2b in the portion where the probe 100 is hit, the presence of the metal plug 6 immediately adjacent to the crack does not increase any more and does not cause a problem as a semiconductor device. In addition, the occurrence of cracks can be suppressed.
[0026]
As shown in FIG. 2, in the element region, a first wiring 7a is formed on the interlayer insulating film 2a, and a second wiring 7b is formed on the interlayer insulating film 2b, so that the first and second wirings are formed. A through hole 8 for connecting 7a and 7b is formed in the interlayer insulating film 2b. A tungsten film is embedded in the through hole 8 to form a metal plug 9 for electrically connecting the first and second wirings. Yes.
[0027]
In manufacturing the semiconductor device, the first wiring 7a and the first pad electrode 4a are formed simultaneously (in the same process), and the second wiring 7b and the second pad electrode 4b are formed simultaneously. Further, the through hole 5 in the bonding pad portion and the through hole 8 in the element portion are formed at the same time, and the tungsten plugs 6 and 9 are formed at the same time.
[0028]
The through holes 5 and 8 are simultaneously formed by forming a resist pattern on the interlayer insulating film 2b and etching the interlayer insulating film 2b using the resist pattern as a mask.
[0029]
In this embodiment, as shown in FIG. 1, the through-hole formed in the bonding pad portion is not only in the vertical direction of the pad (probing direction) but also in the horizontal direction (direction perpendicular to the probing direction). Since a plurality of holes are formed, the area of the through hole 5 in the bonding pad portion does not become extremely large relative to the area of the through hole 9 in the element portion. Therefore, even when the pad portion through-hole 5 and the element portion through-hole 9 are formed at the same time, there is no significant difference in the etching rate, so that each of the through-holes 5 and 9 can be formed to a desired depth. .
[0030]
Here, when simultaneously opening holes with different areas, the etching rate is slow for holes with a small area, so overetching occurs for holes with a large area because the etching rate is fast, and this etching rate difference If it exceeds 10%, an etch margin in manufacturing cannot be secured. Therefore, it is preferable that the area of the through hole 5 in the pad portion is set such that the etching rate difference is 10% or less with respect to the area of the through hole 9 in the element portion.
[0031]
Thus, according to the present embodiment, the plurality of through holes provided in the pad portion for improving the bonding resistance are arranged so that the interlayer insulating film in which the through holes are formed is discontinuous in the probing direction. Furthermore, by adopting a configuration in which a plurality of through holes are arranged in a direction perpendicular to the probing direction, it is possible to improve the bonding resistance and to suppress the generation of cracks in the probing and to have a good workability. Is obtained.
[0032]
In the present embodiment, as shown in FIG. 2, the interface between the interlayer insulating film 2b and the second pad electrode 4b is flat and not uneven as in the prior art of FIG. 2, the tungsten plug 6 embedded in the through hole 5 has good adhesion to the pad electrode 4b. Therefore, the plurality of through holes 5 are provided, so that the interlayer insulating film Adhesiveness at the interface between the upper surface of 2b and the tungsten plug 6 and the pad electrode 4b is increased, so that sufficient bonding resistance can be obtained. Of course, in the present invention, the interface may be uneven as shown in FIG.
[0033]
[Second Embodiment]
3 and 4 show a mask pattern of the bonding pad portion in the semiconductor device according to the present embodiment.
[0034]
FIG. 3 shows a mask pattern when the through-hole pattern 5 ′ of FIG. 1 is made into a cross shape, and FIG. 4 shows a mask pattern when the through-hole pattern 5 ′ is made into an L shape.
[0035]
A cross-sectional view of a part of the bonding pad portion and the element region corresponding to the AA ′ line in FIGS. 3 and 4 is as shown in FIG. In addition, the shape of the through hole 5 formed using these through hole patterns 5 ′ is a cross and the corners of the L shape are rounded.
[0036]
3 and 4, as in the first embodiment, a plurality of through-hole patterns are formed so that the silicon oxide film 2b, which is an interlayer insulating film, becomes discontinuous in the direction AA ', that is, in the probing direction. Thus, cracks during probing can be suppressed.
[0037]
Further, the area of the cross / L-shaped through hole pattern is similar to that of the first embodiment in that the etching rate difference is different between the through hole formed in the element portion and the cross or L-shaped through hole. Is set to be 10% or less. Therefore, the workability of the through hole is good.
[0038]
Furthermore, in this embodiment, as shown in FIGS. 3 and 4, by making the hole pattern a shape other than a rectangle, the through holes 5 can be arranged more densely than in the first embodiment. Since the through holes 5 (metal plugs 6) are densely arranged in this manner, the adhesion at the interface between the upper surfaces of the metal plug 6 and the interlayer insulating film 2b and the lower surface of the electrode pad 4b is increased. Bonding strength can be further improved than in the example.
[0039]
[Third embodiment]
5 to 9 show mask patterns of bonding pads in the semiconductor device according to this embodiment. 2 is a sectional view of a part of the bonding pad portion and the element region corresponding to the line AA ′ in FIGS. In addition, the shape of the through hole 5 formed by using these through hole patterns 5 ′ is also rounded at the corners.
[0040]
As shown in FIGS. 5 to 9, in this embodiment, the through-hole pattern 5 ′ has a staircase shape, a V shape, an H shape, a T shape, and an I shape (rectangular shape). Thus, the silicon oxide film 2b is discontinuous in all directions. That is, a plurality of through holes are necessarily arranged on a straight line in all directions passing through a region sandwiched between adjacent through holes.
[0041]
Also, the area of the through-hole pattern 5 ′ in FIGS. 5 to 9 is the same as that in the first embodiment when the through-hole formed in the element portion and the through-hole 5 in these bonding pad portions are formed simultaneously. The difference is 10% or less. Therefore, the workability of the through hole is good.
[0042]
In the first and second embodiments, the through-hole 5 is disposed so that the silicon oxide film 2b is discontinuous in the probing direction, which makes it possible to sufficiently suppress the generation of cracks during probing. Although it is conceivable, depending on how the probe is pressed, the impact may increase, or the direction in which the impact is transmitted may deviate from the direction in which the probe is applied. In such a case, the first and second implementations are possible. In the example configuration, there is a possibility that cracks cannot be sufficiently prevented. That is, in the first and second embodiments, there is a portion where the silicon oxide film 2b continuously exists in a straight line as shown on the line BB 'in FIGS. 1, 3 and 4, and the impact of probing in this direction. If this is transmitted, cracks may occur.
[0043]
On the other hand, in the present embodiment, the shape and arrangement of the through hole 5 such that the silicon oxide film 2b is discontinuous in all directions as described above, the direction of impact applied to the bonding pad during probing is reduced. Even when the probe is deviated from the direction of the probe, the occurrence of cracks can be reliably suppressed.
[0044]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.
[0045]
For example, the through-hole pattern is not limited to the one described above, and may be any shape as long as the interlayer insulating film 2b can be discontinuous in the probing direction and has good workability.
[0046]
Further, in each of the above embodiments, an example in which a through hole is not arranged at the edge of the bonding pad is shown, but there may be a through hole arranged in contact with the edge.
[0047]
【The invention's effect】
As described above, according to the present invention, it is possible to improve the bonding strength by providing a through hole in the bonding pad portion, to suppress the generation of cracks during probing, and to obtain a semiconductor device with good workability.
[Brief description of the drawings]
FIG. 1 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a first embodiment of the present invention.
2 is a cross-sectional view of the semiconductor device corresponding to the line AA ′ in FIG. 1;
FIG. 3 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a third embodiment of the present invention.
FIG. 9 is a view showing a mask pattern of a bonding pad portion of a semiconductor device according to a third embodiment of the present invention.
10 is a plan view of a bonding pad of a semiconductor device according to prior art 1. FIG.
11 is a cross-sectional view taken along 10A-10A ′ of FIG.
12 is a plan view of a bonding pad for explaining a problem in prior art 1. FIG.
13 is a perspective view of a bonding pad of a semiconductor device according to prior art 2. FIG.
14 is a cross-sectional view taken along 13A-13A ′ of FIG.
15 is a plan view of a bonding pad according to another example of the prior art 2. FIG.
[Explanation of symbols]
1 Semiconductor substrate 2a, 2b, 2c, 112a, 112b, 132a, 132b Interlayer insulating film 3, 113, 133 Protective film 4a, 4b, 114a, 114b Pad electrode 5, 8, 115 Through hole 3 ', 4a', 4b ' , 5 'Mask pattern 6, 9, 116 Metal plug 7a, 7b Wiring 100, 120 Probe 121 Crack 134 Electrode layer 135 Groove

Claims (4)

半導体基板上に選択的に設けられた第１パッド電極と、
前記第１パッド電極上に設けられた第１絶縁膜と、
前記第１パッド電極上において前記第１絶縁膜に選択的に設けられ、前記第１パッド電極に達する複数の第１スルーホールと、
前記複数の第１スルーホールそれぞれに埋め込まれた第１金属層と、
前記第１絶縁膜および前記複数の第１スルーホール上に選択的に設けられた第２パッド電極と、
前記第２パッド電極の周辺部および前記第１絶縁膜を覆い、前記第２パッド電極の前記周辺部を除く上面を露出する開口を有する第２絶縁膜とを備え、
前記第２パッド電極の前記開口に露出した上面がボンディングパッドとなる半導体装置であって、
前記複数の第１スルーホールは、前記ボンディングパッドの縦方向および横方向それぞれに複数配置され、
横方向に隣り合う前記第１スルーホールの間の領域を通る全ての方向の直線上に前記第１スルーホールが複数配置されていることを特徴とする半導体装置。A first pad electrode selectively provided on a semiconductor substrate;
A first insulating film provided on the first pad electrode;
A plurality of first through holes that are selectively provided on the first insulating film on the first pad electrode and reach the first pad electrode;
A first metal layer embedded in each of the plurality of first through holes;
A second pad electrode selectively provided on the first insulating film and the plurality of first through holes;
A second insulating film that covers the peripheral portion of the second pad electrode and the first insulating film and has an opening that exposes an upper surface of the second pad electrode excluding the peripheral portion;
A semiconductor device in which an upper surface exposed at the opening of the second pad electrode is a bonding pad,
The plurality of first through holes are arranged in the vertical direction and the horizontal direction of the bonding pad,
Wherein a said first through hole in all directions on a straight line passing through the region between the first through-hole adjacent laterally are arranged. 前記第１スルーホールの形状は、円形であることを特徴とする請求項１記載の半導体装置。The shape of the first through hole, the semiconductor device according to claim 1, wherein the circular. 前記第１スルーホールの形状は、円形以外であることを特徴とする請求項１記載の半導体装置。The shape of the first through hole, the semiconductor device according to claim 1, wherein a is other than circular. 前記第１スルーホールの形状は、十字、Ｌ字、Ｔ字、Ｉ字、Ｖ字およびＨ字のいずれかであることを特徴とする請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein the shape of the first through hole is any one of a cross, an L shape, a T shape, an I shape, a V shape, and an H shape.
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