JP4066848B2 - Manufacturing method of multilayer printed wiring board - Google Patents

Manufacturing method of multilayer printed wiring board Download PDF

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JP4066848B2
JP4066848B2 JP2003052445A JP2003052445A JP4066848B2 JP 4066848 B2 JP4066848 B2 JP 4066848B2 JP 2003052445 A JP2003052445 A JP 2003052445A JP 2003052445 A JP2003052445 A JP 2003052445A JP 4066848 B2 JP4066848 B2 JP 4066848B2
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layer
plating
insulating resin
resist pattern
resin layer
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JP2004265967A (en
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利秀 伊藤
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株式会社トッパンＮｅｃサーキットソリューションズ
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、第１配線層の両面に絶縁層を介して複数の配線層が形成された多層プリント配線板及びその製造方法並びに半導体装置に関する。
【０００２】
【従来の技術】
近年、半導体実装技術の発展により半導体装置を実装する実装するプリント配線板においては、高密度、高精度の配線層を有する多層プリント配線板が要求されている。高密度、高精度の配線層を形成するために、プリント配線板は多層化され、配線層の線幅も小さくなり、配線層間の接続に用いられるビアホールはより小さい穴径とすることが求められている。そして、ビアホール用孔の孔加工も、位置ずれを極力小さくするように高い精度の加工が求められている。そのような、要求を満足するために、配線層と絶縁層を交互に形成して多層配線層を形成して多層プリント配線板を作製する、所謂ビルドアップ法が実用化されている。
【０００３】
ビルドアップ法にて多層プリント配線板を作製する従来技術（例えば、特許文献１参照）の一例を図７（ａ）〜（ｆ）に示す。
以下、図７（ａ）〜（ｆ）を参照して、ビルドアップ法による多層プリント配線板の製造方法について説明する。
まず、絶縁基材１１１の両面に銅箔１２１及び１２２を積層した両面銅張り積層板７１０を準備する（図７（ａ）参照）。
次に、両面銅張り積層板７１０の銅箔１２２をエッチング法にてパターニング処理を行って第１配線層１２２ａを形成し、絶縁基材１１１の所定位置をレーザー加工等により孔明け加工し、ビア用孔１４１を形成する（図７（ｂ）参照）。
【０００４】
次に、両面に感光性ドライフィルムをラミネートして感光層を形成し、第１配線層１２２ａ側の感光層をパターン露光、現像等の一連のパターニング処理を、銅箔１２１側の感光層は全面露光を行って、めっきレジストパターン１５１及び保護マスク層１５２を形成する。さらに、めっきレジストパターン１５１側の絶縁基材１１１及びビア用孔１４１表面のデスミア、触媒核付与処理及び無電解銅めっきを行って、めっき下地導電層を形成し、該めっき下地導電層をカソードにして電解銅めっきを行い、コンフォーマルビア１３１を形成する（図７（ｃ）参照）。
【０００５】
次に、両面に感光性ドライフィルムをラミネートして感光層を形成し、銅箔１２１側の感光層をパターン露光、現像等の一連のパターニング処理を、第１配線層１２２ａ側の感光層は全面露光を行って、レジストパターン１５３及び保護マスク層１５４を形成する。さらに、レジストパターン１５３をマスクにして銅箔１２１をエッチング処理する（図７（ｄ）参照）。
【０００６】
次に、レジストパターン１５３及び保護マスク層１５４を剥離処理し、絶縁基材１１１の一方の面に配線層１２１ａ、他方の面に配線層１２２ａを形成してコア基板７２０を作製する（図７（ｅ）参照）。
さらに、コア基板７２０の両面にビルドアップ層７３０及び７４０を形成し、４層プリント配線板７００を得る（図７（ｆ）参照）。
【０００７】
また、ビルドアップ法にて多層プリント配線板を作製する従来技術（例えば、特許文献２参照）の別の一例を図８（ａ）〜（ｄ）に示す。
以下、図８（ａ）〜（ｄ）を参照して、ビルドアップ法による多層プリント配線板の製造方法について説明する。
まず、絶縁基材１１４の両面に銅箔１２５及び１２６を積層した両面銅張り積層板８１０を準備する（図８（ａ）参照）。
次に、両面銅張り積層板６１０の銅箔１２６側の所定位置をレーザー加工等により孔明け加工し、ビア用孔１４２を形成する（図８（ｂ）参照）。
【０００８】
次に、銅箔１２５及び銅箔１２６をサブトラクティブ法にてパターニング処理して配線層１２５ａ及び配線層１２６ａ形成する。さらに、セミアディテブ法にて配線層１２６ａ上に配線層１２７を、ビア用孔１４２にビアホール１３４を形成してコア基板８２０を作製する（図８（ｃ）参照）。
【０００９】
次に、コア基板８２０の配線層１２７側に絶縁層１１５を介して、サブトラクティブ法にて配線層１２８を形成する。さらに、セミアディテブ法にて配線層１２９及びビアホール１３５を形成してビルドアップ層８３０を形成し、コア基板８２０及びビルドアップ層８３０からなる３層プリント配線板６００を得る（図８（ｄ）参照）。
【００１０】
【特許文献１】
特開２００１−９４２５２号公報
【特許文献２】
特開平０９−４６０４２号公報
【００１１】
【発明が解決しようとする課題】
上記従来技術を用いたビルドアップ法による多層プリント配線板の製造法では、サブトラクティブ法を用いているので、微細配線層の形成が難しい。
また、特許文献１の技術を用いて作製した多層プリント配線板は、絶縁基材に対して非対称構造になっているので反りを生じ易いと言う問題を有する。
【００１２】
本発明は上記問題点に鑑み考案されたもので、微細配線層の形成が可能な多層プリント配線板の製造方法及び反りを生じ難い多層プリント配線板並びに半導体装置を提供することを目的とする。
【００１７】
【課題を解決するための手段】
本発明に於いて上記課題を達成するために、以下の工程を少なくとも備えることを特徴とする、第１配線層の両面に絶縁樹脂層を介して複数の配線層が形成されている多層プリント配線板の製造方法としたものである。
（ａ）絶縁樹脂層及び銅箔からなる片面銅箔付樹脂シートを準備する工程。
（ｂ）前記片面銅箔付樹脂シートの前記絶縁樹脂層の所定位置にビア用孔を形成し無電解銅めっきによりめっき下地導電層を形成する工程。
（ｃ）前記銅箔上に支持体シートを貼着した後前記めっき下地導電層上にめっきレジストパターンを形成する工程。
（ｄ）前記めっき下地導電層をカソードにして電解銅めっきを行って所定厚の導体層及びフィルドビアを形成する工程。
（ｅ）前記めっきレジストパターンを剥離処理し、前記めっきレジストパターン下部にあった前記めっき下地導電層をフラッシュエッチングにて除去し、第２配線層及び前記フィルドビアを形成し、次に、前記支持体シートを除去する工程。
（ｆ）前記第２配線層側に第２の支持体シートを貼着した後、前記銅箔上に第２のレジストパターンを形成する工程。
（ｇ）前記第２のレジストパターンをマスクにして前記銅箔をエッチング処理し、前記第２のレジストパターンを剥離処理して、第１配線層を形成する工程。
（ｈ）前記第１配線層側に所定厚の第２の絶縁樹脂層を形成し、前記第２の絶縁樹脂層の所定位置に第２のビア用孔を形成し無電解銅めっきにより第２のめっき下地導電層を形成する工程。
（ｉ）前記第２の絶縁樹脂層側に第２のめっきレジストパターンを形成する工程。
（ｊ）前記第２のめっき下地導電層をカソードにして電解銅めっきを行い、所定厚の第２の導体層及び第２のビアを形成する工程。
（ｋ）前記第２のレジストパターンを剥離処理し、前記第２のめっきレジストパターン下部にあった前記第２のめっき下地導電層をフラッシュエッチングにて除去し、外側配線層及び前記第２のビアを形成する工程。
（ｌ）前記第２の支持体シートを前記工程（ｇ）の後から前記工程（ｋ）の間に除去する工程。
（ｍ）前記第２の絶縁樹脂層、前記外側配線層及び前記第２のビア形成工程を必要回数繰り返す工程。
【００１８】
前記第２の支持体シートを前記工程（ｇ）の後に除去し、前記工程（ｈ）において、前記第１配線層及び前記第２配線層側にそれぞれ所定厚の第２の絶縁樹脂層及び第３の絶縁樹脂層を形成し、前記第２の絶縁樹脂層及び前記第３の絶縁樹脂層の所定位置にそれぞれ第２のビア用孔及び第３のビア用孔を形成し無電解銅めっきにより第２のめっき下地導電層および第３のめっき下地導電層をそれぞれ形成し、前記工程（ｉ）において、前記第２の絶縁樹脂層側に第２のめっきレジストパターンを形成し、前記第３の絶縁樹脂層側に第３のめっきレジストパターンを形成し、前記工程（ｊ）において、前記第２のめっき下地導電層および前記第３のめっき下地導電層をカソードにして電解銅めっきを行い、前記第２の絶縁樹脂層側に所定厚の第２の導体層と第２のビアを形成し、前記第３の絶縁樹脂層側に所定厚の第３の導体層と第３のビアを形成し、前記工程（ｋ）において、前記第２のレジストパターン及び前記第３のめっきレジストパターンを剥離処理し、前記第２のめっきレジストパターン及び前記第３のめっきレジストパターンの下部にあった前記第２のめっき下地導電層及び前記第３のめっき下地導電層をフラッシュエッチングにて除去し、両面に前記外側配線層及び前記第２のビアと前記第３のビアを形成することを特徴とする上記の多層プリント配線板の製造方法としたものである。
【００１９】
前記支持体シートがポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルムのいずれかで形成されていることを特徴とする上記の多層プリント配線板の製造方法としたものである。
【００２０】
【発明の実施の形態】
以下本発明の実施の形態につき説明する。
本発明の多層プリント配線板の一実施例を図１（ａ）、（ｂ）及び（ｃ）に示す。また、本発明の多層プリント配線板に半導体を搭載した半導体装置の一実施例を図２（ａ）〜（ｄ）に示す。
本発明の多層プリント配線板１００は、図１（ａ）に示すように、第１配線層２１ａの一方の面に絶縁樹脂層１１を介して第２配線層２２ａ及びフィルドビア３１が形成されたビルドアップ層２０と、他方の面に第３配線層２３ａ及びコンフォーマルビア３２が形成されたビルドアップ層３０とで構成されており、第１配線層２１ａと第２配線層２２ａとはフィルドビア３１で、また第１配線層２１ａと第３配線層２３ａとはコンフォーマルビア３２で、それぞれ電気的に接続されている。第１配線層２１ａに対してビルドアップ層２０及びビルドアップ層３０が対称に形成された対称構造の３層プリント配線板構造になっている。
【００２１】
本発明の多層プリント配線板１００ａは、図１（ｂ）に示すように、第１配線層２１ａの一方の面に絶縁樹脂層１１を介して第２配線層２２ａ、コンフォーマルビアランド２２ｂ及びコンフォーマルビア３１ａが形成されたビルドアップ層２０ａと、他方の面に第３配線層２３ａ及びコンフォーマルビア３２が形成されたビルドアップ層３０とで構成されており、第１配線層２１ａと第２配線層２２ａとはコンフォーマルビア３１ａで、また第１配線層２１ａと第３配線層２３ａとはコンフォーマルビア３２で、それぞれ電気的に接続されている。さらに、第１配線層２１ａに対してビルドアップ層２０ａ及びビルドアップ層３０が対称に形成された対称構造の３層プリント配線板構造になっている。
【００２２】
また、本発明の多層プリント配線板２００は、図１（ｃ）に示すように、絶縁樹脂層１１の両面に第１配線層２１ａ、第２配線層２２ａ及びフィルドビア３１が形成された両面配線板４０と、両面配線板４０の一方の面に絶縁樹脂層１３を介して第３配線層２４ａ及びコンフォーマルビア３３が形成されたビルドアップ層５０と、他方の面に絶縁層１４を介して第４配線層２５ａ、ランド２５ｂ及びフィルドビア３４が形成されたビルドアップ層６０とで構成されており、第１配線層２１ａと第２配線層２２ａとはフィルドビア３１で、第１配線層２１ａと第３配線層２４ａとはコンフォーマルビア３３で、第２配線層２２ａと第４配線層２５ａとはフィルドビア３４で、それぞれ電気的に接続されている。さらに、絶縁樹脂層１１に対してビルドアップ層５０及びビルドアップ層６０が対称に形成された対称構造の４層プリント配線板構造になっている。
【００２３】
上記本発明の多層プリント配線板１００、１００ａ及び２００は、コア基板のないビルドアップ多層プリント配線板の構造とすることで、コア基板のＢＶＨ（ブラインドビアホール）による配線制約を取り除くことができるとともに、高密度化と薄型化が図れる。
具体的には、配線層のパターン設計自由度が増すとともに、配線層の収容性が向上し、薄型化及び微細配線層の形成が可能になり、高密度化が図れる。
また、対称構造のビルドアップ多層プリント配線板となっているため、薄型化しても配線板の反りが生じ難い。
【００２４】
以下、本発明の半導体装置について説明する。
本発明の半導体装置３００は、図２（ａ）に示すように、本発明の多層プリント配線板１００上のフィルドビアと半導体８０のパッド７１が接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板１００の絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
また、本発明の半導体装置４００は、図２（ｂ）に示すように、本発明の多層プリント配線板１００ａ上のコンフォーマルビアランドと半導体８０のパッド７１が接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板１００ａの絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
【００２５】
本発明の半導体装置５００は、図２（ｃ）に示すように、本発明の多層プリント配線板２００上のフィルドビアまたランドと半導体８０のパッド７１が半田９１を介して接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板２００の絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
また、本発明の半導体装置６００は、図２（ｄ）に示すように、本発明の多層プリント配線板２００上のフィルドビア３４またはランド２５ｂと半導体８０のパッド７１がバンプ９２を介して接合されて半導体８０が搭載されており、半導体８０と多層プリント配線板２００の絶縁樹脂層との間にはアンダーフィル８１樹脂を流し込んだ構造としている。
【００２６】
以下本発明の多層プリント配線板の製造方法について説明する
図３（ａ）〜（ｆ）及び図４（ｇ）〜（ｋ）は、本発明の多層プリント配線板の製造方法の第１の実施例を工程順に示す模式構成断面図である。
まず、銅箔２１上に、樹脂溶液を塗布するか、プリプレーグを積層して半硬化状態の絶縁樹脂層１１を形成した片面銅箔付樹脂シート１０を準備する（図３（ａ）参照）。
ここで、銅箔２１は、１２〜１８μｍ厚のものが、絶縁層樹脂層１１は、５０〜１００μｍ厚のものが、それぞれ使用される。さらに、片面銅箔付樹脂シート１０に硫酸８０〜１６０ｇ／Ｌと３５ｗｔ％過酸化水素９０〜１５０ｇ／Ｌを組成とする酸化性液を１５〜６０秒間スプレーすることにより、銅箔２１をマクロエッチングして、５〜１０μｍ厚の銅箔にする。これは、エッチング法で微細配線層を形成するための銅箔薄型化の一処方例である。
【００２７】
次に、片面銅箔付樹脂シート１０の絶縁樹脂層１１の所定位置をレーザ加工してビア用孔４１を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地層（特に、図示せず）を形成する（図３（ｂ）参照）。
ここで、レーザ加工のレーザーとしては、炭酸ガスレーザ、エキシマレーザ、ＹＡＧレーザ等が利用でき、例えば、炭酸ガスレーザを使用した場合スポット径（直径）０．１２５ｍｍのレーザビームを５〜２０ｍＪで１〜３パルス照射するのが好適である。
デスミア処方としては、例えば、ＭＬＢ２１１：シプレイ・ファーイースト（株）製を２０ｖｏｌ％、キューポジットＺが１０ｖｏｌ％からなる膨潤浴に６０〜８５℃で１〜５分間浸漬した後、ＭＬＢ２１３Ａ（シプレイ・ファーイースト（株）製）が１０ｖｏｌ％とＭＬＢ２１３Ｂ（シプレイ・ファーイースト（株）製）が１５ｖｏｌ％とからなるエッチング浴に５５〜７５℃で２〜１０分間浸漬処理し、ＭＬＢ２１６−２（シプレイ・ファーイースト（株）製）が２０ｖｏｌ％からなる中和浴に３５〜５５℃で２〜１０分間浸漬することにより、絶縁樹脂層１１表面及びビア用孔４１のデスミア処理を行う。
【００２８】
また、めっき触媒付与及びめっき下地導電層の形成処方としては、例えば、上記基板をプレディップＣＰ−３０２３（シプレイ・ファーイースト（株）製）浴に２５℃で６０秒間浸漬後、同社製キャタリスト同ＣＰ−３３１６浴に２５℃で１８０秒間、同社製アクセラレーター（ＮＲ−２ＡとＮＲ−２Ｂを各々１０ｖｏｌ％と３ｖｏｌ％で混合した水溶液）に２５℃で３００秒間順次浸漬して、絶縁樹脂層１１表面及びビア用孔４１にパラジウム触媒を付与した後無電解銅めっきを行ってめっき下地導電層（特に、図示せず）を形成する。
【００２９】
次に、銅箔２１上に支持体シート６１を貼着した後、感光性ドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１１上に貼着し、離型シートを剥離して絶縁樹脂層１１上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ2の紫外線を照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してめっきレジストパターン５１を形成する（図３（ｃ）参照）。
ここで、支持体シート６１は上記処理基板の補強及び処理工程での銅箔２１の保護を行うためのもので、ポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルム、ポリサルホンフィルム、ポリフェニルサルホンフィルム、ポリエーテルサルホンフィルム、ポフェニレンサルファイドフィルム、ポフェニレンエーテルフィルム、ポリエーテルエーテルケトンフィルム、ポフェニレンテレフタルアミドフィルムの中から工程処理条件等に合わせて適宜選択して使用する。
【００３０】
次に、めっきレジストパターン５１が形成された配線基板を硫酸銅めっき浴中に浸漬し、めっき下地導電層をカソードにして電解銅めっきを行い、絶縁樹脂層１１上に１０〜１５μｍ厚の導体層２２及びビア用孔４１にフィルドビア３１を形成する（図３（ｄ）参照）。
ここで、電解銅めっき条件としては、例えば、硫酸銅７０〜１００ｇ／Ｌ、硫酸１５０〜２５０ｇ／Ｌ、塩酸５０〜１００ｐｐｍの組成から成る硫酸銅めっき浴を用いて、電流密度１．５〜２．５Ａ／ｄｍ2の条件で２０〜５０分電解銅めっきを行って上記１０〜１５μｍ厚の銅からなる導体層を形成する。
また、ビア用孔４１にはフィルドビアを形成したが特に限定されるものではなく、フィルドビア、コンフォーマルビアを適宜選択して用いれば良い。
【００３１】
次に、０．５〜２ｗｔ％水酸化ナトリウム水溶液をスプレーして、めっきレジストパターン５１を剥離処理し、めっきレジストパターン５１下部にあっためっき下地導電層をフラッシュエッチングで除去し、支持体シート６１を除去して第２配線層２２ａを形成し、銅箔２１上に絶縁樹脂層１１を介して第２配線層２２ａ及びフィルドビア３１が形成されたビルドアップ層２０を形成する（図３（ｅ）参照）。
【００３２】
次に、第２配線層２２ａ側に支持体シート６２を貼着した後感光性のドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１１上に貼着し、離型シートを剥離して、絶縁樹脂層１１上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ2の紫外線を照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してレジストパターン５２を形成する（図３（ｆ）参照）。
ここで、支持体シート６２は上記処理基板の補強及び処理工程での銅箔２１の保護を行うためのもので、ポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルム、ポリサルホンフィルム、ポリフェニルサルホンフィルム、ポリエーテルサルホンフィルム、ポフェニレンサルファイドフィルム、ポフェニレンエーテルフィルム、ポリエーテルエーテルケトンフィルム、ポフェニレンテレフタルアミドフィルムの中から工程処理条件等に合わせて適宜選択して使用する。
【００３３】
次に、レジストパターン５２をマスクにして塩化第二銅２００〜４００ｇ／ｌ、塩酸１００〜１５０ｇ／ｌからなるエッチング液をスプレーして銅箔２１をエッチング除去し、レジストパターン５２を０．５〜２．０ｗｔ％の水酸化ナトリウム水溶液で剥離除去して、第１配線層２１ａを形成する（図４（ｇ）参照）。
【００３４】
次に、第１配線層２１ａ上に樹脂溶液を塗布するか、もしくはプリプレーグシート等を貼着するかの方法で、絶縁樹脂層１２を形成し、絶縁樹脂層１２の所定の位置にレーザー加工等によりビア用孔４２を形成し、上記図３（ｂ）と同じ処方で、デスミア、めっき触媒付与及び無電解銅めっきを行ってめっき下地導電層（特に、図示せず）形成する（図４（ｈ）参照）。
【００３５】
次に、感光性のドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１２上に貼着し、離型シートを剥離して絶縁樹脂層１２上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ2の紫外線を照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してめっきレジストパターン５３を形成する（図４（ｉ）参照）。
【００３６】
次に、めっきレジストパターン５３が形成された配線基板を硫酸銅めっき浴中に浸漬し、めっき下地導電層をカソードにして電解銅めっきを行い、絶縁樹脂層１１上に１０〜１５μｍ厚の導体層２３及びビア用孔４２にコンフォーマルビア３２を形成する（図４（ｊ）参照）。
ここで、電解銅めっき条件としては、上記図３（ｄ）の工程に用いた条件と同じ処方で良い。
また、ビア用孔４２にはコンフォーマルビアを形成したが特に限定されるものではなく、コンフォーマルビア、フィルドビアを適宜選択して用いれば良い。
【００３７】
次に、めっきレジストパターン５３を０．５〜２．０ｗｔ％水酸化ナトリウム水溶液で剥離除去し、めっきレジストパターン５３下部にあっためっき下地導電層をフラッシュエッチングで除去して第３配線層２３ａを形成し、支持体シート６２を除去して、第１配線層２１ａの一方の面に絶縁樹脂層１１を介して第２配線層２２ａ及びフィルドビア３１が形成されたビルドアップ層２０、他方の面に絶縁樹脂層１２を介して第３配線層２３ａ及びコンフォーマルビア３２が形成されたビルドアップ層３０からなる３層プリント配線板１００を得る（図４（ｋ）参照）。
さらに、必要に応じて上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返すことにより、所望の多層プリント配線板を得ることができる。
【００３８】
図５（ａ）〜（ｆ）及び図６（ｇ）〜（ｋ）は、本発明の多層プリント配線板の製造方法の第２の実施例を工程順に示す模式構成断面図である。
まず、図５（ａ）〜（ｆ）の工程は、上記図３（ａ）〜（ｆ）と同様の工程で処理し、第１配線層２１ａ、第２配線層２２ａ、ランド２２ｃ及びフィルドビア３２を形成し、絶縁樹脂層１１の両面に第１配線層２１ａと第２配線層２２ａランド２２ｂ及びフィルドビア３２が形成された両面配線板４０を得る（図６（ｇ）参照）。
【００３９】
次に、両面配線板４０の両面にプリプレーグシートを積層して絶縁樹脂層１３及び絶縁樹脂層１４を形成し、絶縁樹脂層１３及び絶縁樹脂層１４の所定の位置にレーザー加工等によりビア用孔４３及びビア用孔４４を形成し、デスミア、めっき触媒付与及び無電解銅めっきを行ってめっき下地導電層（特に、図示せず）形成する（図６（ｈ）参照）。
ここで、デスミア、めっき触媒付与及び無電解銅めっき条件としては、上記図３（ｂ）の工程に用いた条件と同じ処方で良い。
【００４０】
次に、感光性ドライフィルムを８０〜１２０℃の熱ロールで絶縁樹脂層１３及び絶縁樹脂層１４上に貼着し、離型シートを剥離して絶縁樹脂層１３及び絶縁樹脂層１４上に感光層を形成し、超高圧水銀ランプで５０〜２００ｍＪ／ｃｍ2の紫外線を両面照射してパターン露光した後、０．５〜２ｗｔ％炭酸ナトリウム水溶液をスプレー現像し、乾燥硬化してめっきレジストパターン５４及びめっきレジストパターン５５をそれぞれ形成する（図６（ｉ）参照）。
【００４１】
次に、めっきレジストパターン５４及びめっきレジストパターン５５が形成された配線基板を硫酸銅めっき浴中に浸漬し、めっき下地導電層をカソードにして電解銅めっきを行い、絶縁樹脂層１３上に１０〜１５μｍ厚の導体層２４及びビア用孔４３にコンフォーマルビア３３を、絶縁樹脂層１４上に１０〜１５μｍ厚の導体層２５及びビア用孔４４にフィルドビア３４をそれぞれ形成する（図６（ｊ）参照）。
ここで、電解銅めっき条件としては、上記図３（ｄ）の工程に用いた条件と同じ処方で良い。
【００４２】
次に、めっきレジストパターン５４及びめっきレジストパターン５５を０．５〜２．０ｗｔ％水酸化ナトリウム水溶液で剥離除去し、めっきレジストパターン５４及びめっきレジストパターン５５下部にあっためっき下地導電層をフラッシュエッチングで除去して、第３配線層２４ａ、第４配線層２５ａ及びランド２５ｂを形成し、両面配線板４０の一方の面に絶縁樹脂層１３を介して第３配線層２４ａ及びコンフォーマルビア３３が形成されたビルドアップ層５０、他方の面に絶縁樹脂層１３を介して第４配線層２５ａ及びフィルドビア３４が形成されたビルドアップ層５０をそれぞれ形成し、４層プリント配線板２００を得る（図６（ｋ）参照）。
さらに、必要に応じて上記絶縁樹脂層、配線層及びコンフォーマルビアもしくはフィルドビア形成工程を必要回数繰り返すことにより、所望の多層プリント配線板を得ることができる。
【００４３】
【発明の効果】
上記したように、本発明の多層プリント配線板は、コア基板のないビルドアップ多層プリント配線板の構造とすることで、配線層のパターン設計自由度が増すとともに、配線層の収容性が向上し、薄型化及び微細配線層の形成が可能になり、高密度化が図れる。
また、対称構造のビルドアップ多層プリント配線板となっているため、薄型化しても配線板の反りが生じ難い。
また、本発明の多層プリント配線板の製造方法では、セミアディティブ法を用いて配線層を形成しているので、微細パターンの配線層を容易に得ることができる。
また、支持体シートを用いているので、多層プリント配線板の製造工程中での保護層を兼ねた処理基板の補強を容易に実施でき、特に、薄型化した配線板を製造する場合には変形防止効果が発揮される。
【図面の簡単な説明】
【図１】（ａ）〜（ｃ）は、本発明の多層プリント配線板の一実施例を示す模式構成断面図である。
【図２】（ａ）〜（ｄ）は、本発明の半導体装置の一実施例を示す模式構成断面図である。
【図３】（ａ）及び（ｆ）は、本発明の多層プリント配線板の製造方法の第１の実施例における工程の一部を模式的に示す断面図である。
【図４】（ｇ）及び（ｋ）は、本発明の多層プリント配線板の製造方法の第１の実施例における工程の一部を模式的に示す断面図である。
【図５】（ａ）及び（ｆ）は、本発明の多層プリント配線板の製造方法の第２の実施例における工程の一部を模式的に示す断面図である。
【図６】（ｇ）及び（ｋ）は、本発明の多層プリント配線板の製造方法の第２の実施例における工程の一部を模式的に示す断面図である。
【図７】（ａ）及び（ｆ）は、従来の多層プリント配線板の製造法の工程一例を模式的に示す断面図である。
【図８】（ａ）及び（ｄ）は、従来の多層プリント配線板の製造法の工程一例を模式的に示す断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer printed wiring board in which a plurality of wiring layers are formed on both surfaces of a first wiring layer via insulating layers, a manufacturing method thereof, and a semiconductor device.
[0002]
[Prior art]
In recent years, multilayer printed wiring boards having high-density and high-precision wiring layers have been required for printed wiring boards for mounting semiconductor devices due to the development of semiconductor mounting technology. In order to form a high-density, high-precision wiring layer, the printed wiring board is multilayered, the line width of the wiring layer is reduced, and the via hole used for connection between the wiring layers is required to have a smaller hole diameter. ing. In addition, high-precision processing is also required for hole processing of the via-holes so as to minimize misalignment. In order to satisfy such requirements, a so-called build-up method in which a multilayer printed wiring board is manufactured by forming a multilayer wiring layer by alternately forming wiring layers and insulating layers has been put into practical use.
[0003]
An example of a conventional technique (see, for example, Patent Document 1) for producing a multilayer printed wiring board by a build-up method is shown in FIGS.
Hereinafter, a method for manufacturing a multilayer printed wiring board by the build-up method will be described with reference to FIGS.
First, a double-sided copper-clad laminate 710 in which copper foils 121 and 122 are laminated on both sides of an insulating base 111 is prepared (see FIG. 7A).
Next, the copper foil 122 of the double-sided copper-clad laminate 710 is subjected to a patterning process by an etching method to form a first wiring layer 122a, and a predetermined position of the insulating substrate 111 is drilled by laser processing or the like, and vias are formed. A working hole 141 is formed (see FIG. 7B).
[0004]
Next, a photosensitive dry film is laminated on both sides to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed on the photosensitive layer on the first wiring layer 122a side. Exposure is performed to form a plating resist pattern 151 and a protective mask layer 152. Furthermore, the plating base pattern conductive layer is formed by performing desmearing on the surface of the insulating substrate 111 and the via hole 141 on the side of the plating resist pattern 151, the catalyst nucleus applying treatment, and electroless copper plating, and the plating base conductive layer is used as a cathode. Then, electrolytic copper plating is performed to form the conformal via 131 (see FIG. 7C).
[0005]
Next, a photosensitive dry film is laminated on both surfaces to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed on the photosensitive layer on the copper foil 121 side, and the photosensitive layer on the first wiring layer 122a side is the entire surface. Exposure is performed to form a resist pattern 153 and a protective mask layer 154. Further, the copper foil 121 is etched using the resist pattern 153 as a mask (see FIG. 7D).
[0006]
Next, the resist pattern 153 and the protective mask layer 154 are peeled off, and the wiring layer 121a is formed on one surface of the insulating base 111 and the wiring layer 122a is formed on the other surface, so that the core substrate 720 is manufactured (FIG. 7 ( e)).
Further, build-up layers 730 and 740 are formed on both surfaces of the core substrate 720 to obtain a four-layer printed wiring board 700 (see FIG. 7F).
[0007]
Moreover, another example of the prior art (for example, refer patent document 2) which produces a multilayer printed wiring board by a buildup method is shown to Fig.8 (a)-(d).
Hereinafter, a method for manufacturing a multilayer printed wiring board by the build-up method will be described with reference to FIGS.
First, a double-sided copper-clad laminate 810 in which copper foils 125 and 126 are laminated on both sides of an insulating base 114 is prepared (see FIG. 8A).
Next, a predetermined position on the copper foil 126 side of the double-sided copper-clad laminate 610 is drilled by laser processing or the like to form a via hole 142 (see FIG. 8B).
[0008]
Next, the copper foil 125 and the copper foil 126 are patterned by a subtractive method to form the wiring layer 125a and the wiring layer 126a. Further, the core substrate 820 is manufactured by forming the wiring layer 127 on the wiring layer 126a and the via hole 134 in the via hole 142 by the semi-additive method (see FIG. 8C).
[0009]
Next, the wiring layer 128 is formed on the wiring layer 127 side of the core substrate 820 through the insulating layer 115 by a subtractive method. Further, the wiring layer 129 and the via hole 135 are formed by the semi-additive method to form the buildup layer 830, and the three-layer printed wiring board 600 including the core substrate 820 and the buildup layer 830 is obtained (see FIG. 8D). .
[0010]
[Patent Document 1]
JP 2001-94252 A [Patent Document 2]
Japanese Patent Laid-Open No. 09-46042
[Problems to be solved by the invention]
In the manufacturing method of the multilayer printed wiring board by the build-up method using the above-mentioned conventional technique, since the subtractive method is used, it is difficult to form a fine wiring layer.
Moreover, since the multilayer printed wiring board produced using the technique of patent document 1 has an asymmetric structure with respect to an insulating base material, it has the problem of being easy to produce a curvature.
[0012]
The present invention has been devised in view of the above problems, and an object of the present invention is to provide a method for manufacturing a multilayer printed wiring board capable of forming a fine wiring layer, a multilayer printed wiring board that hardly causes warpage, and a semiconductor device.
[0017]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, a multilayer printed wiring having a plurality of wiring layers formed on both surfaces of a first wiring layer via an insulating resin layer, comprising at least the following steps: This is a method for manufacturing a plate.
(A) an insulating resin So及 beauty copper foil or Ranaru step of preparing a single-sided copper foil with a resin sheet.
(B) A step of forming a via hole at a predetermined position of the insulating resin layer of the resin sheet with a single-sided copper foil and forming a plating base conductive layer by electroless copper plating.
(C) forming the plating underlying conductive layer TLR Kki resist pattern after adhering a support sheet on the copper foil.
; (D) plating underlying conductive layer to the cathode and subjected to electrolytic copper plating to form a conductor So及 beauty Firudobi A predetermined thickness step.
(E) a said plating resist pattern is removed process, the plating resist pattern the plating underlying conductive layer that has been in the lower removed by flash etching, to form the second wiring So及 beauty the filled vias, then the support Removing the body sheet .
(F) The process of forming a 2nd resist pattern on the said copper foil , after sticking a 2nd support body sheet to the said 2nd wiring layer side.
(G) the said copper foil as a mask the second resist pattern was etched, the second resist pattern is peeled off process, the step of forming the first wiring layer.
(H) A second insulating resin layer having a predetermined thickness is formed on the first wiring layer side, a second via hole is formed at a predetermined position of the second insulating resin layer , and the second is formed by electroless copper plating . forming a plating underlying conductive layer.
(I) A step of forming a second plating resist pattern on the second insulating resin layer side.
(J) A step of performing electrolytic copper plating using the second plating base conductive layer as a cathode to form a second conductor layer and a second via having a predetermined thickness.
(K) The second resist pattern is stripped, and the second plating base conductive layer under the second plating resist pattern is removed by flash etching, and the outer wiring layer and the second via are removed. forming a.
(L) A step of removing the second support sheet during the step (k) after the step (g).
(M) A step of repeating the second insulating resin layer, the outer wiring layer, and the second via formation step as many times as necessary.
[0018]
The second support sheet is removed after the step (g). In the step (h), a second insulating resin layer having a predetermined thickness and a second thickness on the first wiring layer side and the second wiring layer side, respectively. 3 and a second via hole and a third via hole at predetermined positions of the second insulating resin layer and the third insulating resin layer, respectively, by electroless copper plating. A second plating base conductive layer and a third plating base conductive layer are respectively formed, and in the step (i), a second plating resist pattern is formed on the second insulating resin layer side, and the third plating base conductive layer is formed. A third plating resist pattern is formed on the insulating resin layer side, and in the step (j), electrolytic copper plating is performed using the second plating base conductive layer and the third plating base conductive layer as a cathode, The second insulation resin layer side has a predetermined thickness A conductor layer and a second via are formed, a third conductor layer and a third via having a predetermined thickness are formed on the third insulating resin layer side, and in the step (k), the second resist is formed. The pattern and the third plating resist pattern are peeled off, and the second plating base conductive layer and the third plating base conductive located under the second plating resist pattern and the third plating resist pattern are removed. The layer is removed by flash etching, and the outer printed wiring layer, the second via and the third via are formed on both surfaces.
[0019]
The above- mentioned method for producing a multilayer printed wiring board is characterized in that the support sheet is formed of any one of a polyester film, a polyimide film, an amide film, and a polypropylene film.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
An embodiment of the multilayer printed wiring board of the present invention is shown in FIGS. 1 (a), (b) and (c). An embodiment of a semiconductor device in which a semiconductor is mounted on the multilayer printed wiring board of the present invention is shown in FIGS.
As shown in FIG. 1A, the multilayer printed wiring board 100 of the present invention has a build in which a second wiring layer 22a and a filled via 31 are formed on one surface of a first wiring layer 21a with an insulating resin layer 11 interposed therebetween. The up-layer 20 is composed of a build-up layer 30 having a third wiring layer 23a and a conformal via 32 formed on the other surface. The first wiring layer 21a and the second wiring layer 22a are filled vias 31. The first wiring layer 21a and the third wiring layer 23a are electrically connected by conformal vias 32, respectively. The three-layer printed wiring board structure has a symmetrical structure in which the build-up layer 20 and the build-up layer 30 are formed symmetrically with respect to the first wiring layer 21a.
[0021]
As shown in FIG. 1B, the multilayer printed wiring board 100a of the present invention has a second wiring layer 22a, a conformal via land 22b, and a conformal via on one surface of the first wiring layer 21a with an insulating resin layer 11 interposed therebetween. The build-up layer 20a in which the formal via 31a is formed, and the build-up layer 30 in which the third wiring layer 23a and the conformal via 32 are formed on the other surface, are constituted by the first wiring layer 21a and the second wiring layer 21a. The wiring layer 22a is electrically connected by a conformal via 31a, and the first wiring layer 21a and the third wiring layer 23a are electrically connected by a conformal via 32, respectively. Furthermore, it has a three-layer printed wiring board structure having a symmetrical structure in which the build-up layer 20a and the build-up layer 30 are formed symmetrically with respect to the first wiring layer 21a.
[0022]
Moreover, the multilayer printed wiring board 200 of the present invention is a double-sided wiring board in which a first wiring layer 21a, a second wiring layer 22a, and a filled via 31 are formed on both surfaces of an insulating resin layer 11, as shown in FIG. 40, a build-up layer 50 in which the third wiring layer 24a and the conformal via 33 are formed on one surface of the double-sided wiring board 40 via the insulating resin layer 13, and the second surface via the insulating layer 14 on the other surface. 4 wiring layers 25a, lands 25b, and a build-up layer 60 in which filled vias 34 are formed. The first wiring layer 21a and the second wiring layer 22a are filled vias 31, and the first wiring layer 21a and the third wiring layer 22a. The wiring layer 24a is electrically connected by a conformal via 33, and the second wiring layer 22a and the fourth wiring layer 25a are electrically connected by a filled via 34, respectively. Furthermore, a four-layer printed wiring board structure having a symmetrical structure in which the buildup layer 50 and the buildup layer 60 are formed symmetrically with respect to the insulating resin layer 11 is formed.
[0023]
The multilayer printed wiring boards 100, 100a and 200 of the present invention have a structure of a build-up multilayer printed wiring board without a core substrate, thereby removing wiring restrictions due to BVH (blind via holes) of the core substrate, High density and thinning can be achieved.
Specifically, the degree of freedom in designing the pattern of the wiring layer is increased, the capacity of the wiring layer is improved, the thickness can be reduced and the fine wiring layer can be formed, and the density can be increased.
In addition, since the build-up multilayer printed wiring board has a symmetric structure, the wiring board is hardly warped even if it is thinned.
[0024]
Hereinafter, the semiconductor device of the present invention will be described.
As shown in FIG. 2A, the semiconductor device 300 of the present invention has the filled via on the multilayer printed wiring board 100 of the present invention and the pad 71 of the semiconductor 80 bonded to each other, and the semiconductor 80 is mounted. Underfill 81 resin is poured between the insulating resin layers of the multilayer printed wiring board 100.
Further, as shown in FIG. 2B, the semiconductor device 400 of the present invention has the conformal via land on the multilayer printed wiring board 100a of the present invention and the pad 71 of the semiconductor 80 bonded to each other, and the semiconductor 80 is mounted. The underfill 81 resin is poured between the semiconductor 80 and the insulating resin layer of the multilayer printed wiring board 100a.
[0025]
In the semiconductor device 500 of the present invention, as shown in FIG. 2C, the filled via or land on the multilayer printed wiring board 200 of the present invention and the pad 71 of the semiconductor 80 are joined via the solder 91, and the semiconductor 80 is mounted. The underfill 81 resin is poured between the semiconductor 80 and the insulating resin layer of the multilayer printed wiring board 200.
In addition, as shown in FIG. 2D, the semiconductor device 600 of the present invention has the filled via 34 or land 25b on the multilayer printed wiring board 200 of the present invention and the pad 71 of the semiconductor 80 bonded via bumps 92. A semiconductor 80 is mounted, and an underfill 81 resin is poured between the semiconductor 80 and the insulating resin layer of the multilayer printed wiring board 200.
[0026]
Figure 3 below for a method for manufacturing a multilayer printed wiring board of the present invention (a) ~ (f) and FIG. 4 (g) ~ (k) is the first embodiment of a method for manufacturing a multilayer printed wiring board of the present invention It is a schematic structure sectional view showing an example in order of processes.
First, the resin sheet 10 with a single-sided copper foil in which a semi-cured insulating resin layer 11 is formed by applying a resin solution or laminating prepreg on the copper foil 21 is prepared (see FIG. 3A).
Here, the copper foil 21 has a thickness of 12 to 18 μm, and the insulating layer resin layer 11 has a thickness of 50 to 100 μm. Furthermore, the copper foil 21 is macro-etched by spraying an oxidizing solution having a composition of 80 to 160 g / L of sulfuric acid and 90 to 150 g / L of 35 wt% hydrogen peroxide on the resin sheet 10 with a single-sided copper foil for 15 to 60 seconds. Thus, a copper foil having a thickness of 5 to 10 μm is formed. This is a prescription example of thinning a copper foil for forming a fine wiring layer by an etching method.
[0027]
Next, a predetermined position of the insulating resin layer 11 of the single-sided copper foil-attached resin sheet 10 is laser processed to form via holes 41, desmearing, plating catalyst application and electroless copper plating are performed, and a plating underlayer (particularly, , Not shown) (see FIG. 3B).
Here, a carbon dioxide laser, an excimer laser, a YAG laser, or the like can be used as a laser for laser processing. For example, when a carbon dioxide laser is used, a laser beam having a spot diameter (diameter) of 0.125 mm is 1 to 3 at 5 to 20 mJ. It is preferable to perform pulse irradiation.
As a desmear prescription, for example, MLB211: manufactured by Shipley Far East Co., Ltd. is immersed in a swelling bath consisting of 20 vol% and Cueposit Z consisting of 10 vol% at 60 to 85 ° C. for 1 to 5 minutes, and then MLB213A (Shipley Fur Yeast Co., Ltd.) is immersed in an etching bath consisting of 10 vol% and MLB213B (Chipley Far East Co., Ltd.) is 15 vol% at 55 to 75 ° C. for 2 to 10 minutes, and MLB 216-2 (Shipley Fur) Yeast Co., Ltd.) is immersed in a neutralization bath consisting of 20 vol% at 35 to 55 ° C. for 2 to 10 minutes to perform desmear treatment of the surface of the insulating resin layer 11 and the via holes 41.
[0028]
In addition, as a prescription for forming a plating catalyst and forming a plating base conductive layer, for example, the above-mentioned substrate is immersed in a pre-dip CP-3023 (manufactured by Shipley Far East Co., Ltd.) bath at 25 ° C. for 60 seconds, and then a catalyst manufactured by the same company. Insulate the resin layer in the same CP-3316 bath for 180 seconds at 25 ° C and then in the same accelerator (NR-2A and NR-2B mixed in 10vol% and 3vol% respectively) at 25 ° C for 300 seconds. 11 After applying a palladium catalyst to the surface and via hole 41, electroless copper plating is performed to form a plating base conductive layer (not shown in particular).
[0029]
Next, after sticking the support body sheet 61 on the copper foil 21, the photosensitive dry film is stuck on the insulating resin layer 11 with a hot roll of 80 to 120 ° C., and the release sheet is peeled off to insulate the insulating resin. A photosensitive layer is formed on the layer 11, and after pattern exposure is performed by irradiating 50 to 200 mJ / cm 2 of ultraviolet light with an ultrahigh pressure mercury lamp, 0.5 to 2 wt% sodium carbonate aqueous solution is spray-developed, dried and cured. A plating resist pattern 51 is formed (see FIG. 3C).
Here, the support sheet 61 is for reinforcing the processing substrate and protecting the copper foil 21 in the processing step, and is a polyester film, polyimide film, amide film, polypropylene film, polysulfone film, polyphenylsulfone film. A polyether sulfone film, a polyphenylene sulfide film, a polyphenylene ether film, a polyether ether ketone film, and a polyphenylene terephthalamide film are appropriately selected according to process conditions and the like.
[0030]
Next, the wiring substrate on which the plating resist pattern 51 is formed is dipped in a copper sulfate plating bath, electrolytic copper plating is performed using the plating base conductive layer as a cathode, and a conductive layer having a thickness of 10 to 15 μm is formed on the insulating resin layer 11. A filled via 31 is formed in the via 22 and the via hole 41 (see FIG. 3D).
Here, as electrolytic copper plating conditions, for example, using a copper sulfate plating bath having a composition of copper sulfate 70 to 100 g / L, sulfuric acid 150 to 250 g / L, and hydrochloric acid 50 to 100 ppm, a current density of 1.5 to 2 is used. Electrolytic copper plating is performed for 20 to 50 minutes under the condition of 5 A / dm 2 to form a conductor layer made of copper having a thickness of 10 to 15 μm.
Further, although filled vias are formed in the via holes 41, the vias are not particularly limited, and filled vias and conformal vias may be appropriately selected and used.
[0031]
Next, a 0.5 to 2 wt% sodium hydroxide aqueous solution is sprayed to remove the plating resist pattern 51, and the plating base conductive layer under the plating resist pattern 51 is removed by flash etching. Is removed to form the second wiring layer 22a, and the build-up layer 20 in which the second wiring layer 22a and the filled via 31 are formed is formed on the copper foil 21 via the insulating resin layer 11 (FIG. 3E). reference).
[0032]
Next, after sticking the support sheet 62 on the second wiring layer 22a side, the photosensitive dry film is stuck on the insulating resin layer 11 with a hot roll of 80 to 120 ° C., and the release sheet is peeled off. Then, after forming a photosensitive layer on the insulating resin layer 11, pattern exposure is performed by irradiating 50 to 200 mJ / cm 2 of ultraviolet light with an ultra-high pressure mercury lamp, 0.5 to 2 wt% sodium carbonate aqueous solution is spray developed and dried and cured. Thus, a resist pattern 52 is formed (see FIG. 3F).
Here, the support sheet 62 is for reinforcing the processing substrate and protecting the copper foil 21 in the processing step, and is a polyester film, polyimide film, amide film, polypropylene film, polysulfone film, polyphenylsulfone film. A polyether sulfone film, a polyphenylene sulfide film, a polyphenylene ether film, a polyether ether ketone film, and a polyphenylene terephthalamide film are appropriately selected according to process conditions and the like.
[0033]
Next, using the resist pattern 52 as a mask, an etching solution comprising cupric chloride 200 to 400 g / l and hydrochloric acid 100 to 150 g / l is sprayed to remove the copper foil 21 by etching, and the resist pattern 52 is changed to 0.5 to 0.5. The first wiring layer 21a is formed by peeling off with a 2.0 wt% sodium hydroxide aqueous solution (see FIG. 4G).
[0034]
Next, an insulating resin layer 12 is formed by applying a resin solution on the first wiring layer 21a or a prepreg sheet or the like, and laser processing is performed at a predetermined position of the insulating resin layer 12 A via hole 42 is formed by, for example, desmear, plating catalyst application, and electroless copper plating in the same formulation as in FIG. 3B to form a plating base conductive layer (not shown in particular) (FIG. 4). (See (h)).
[0035]
Next, a photosensitive dry film is stuck on the insulating resin layer 12 with a hot roll of 80 to 120 ° C., the release sheet is peeled off to form a photosensitive layer on the insulating resin layer 12, and an ultra-high pressure mercury lamp After pattern exposure by irradiating 50 to 200 mJ / cm @ 2 with UV, 0.5 to 2 wt% aqueous sodium carbonate solution is spray developed and dried and cured to form a plating resist pattern 53 (see FIG. 4 (i)). .
[0036]
Next, the wiring substrate on which the plating resist pattern 53 is formed is immersed in a copper sulfate plating bath, and electrolytic copper plating is performed using the plating base conductive layer as a cathode, and a conductive layer having a thickness of 10 to 15 μm is formed on the insulating resin layer 11. The conformal via 32 is formed in the hole 23 and the via hole 42 (see FIG. 4J).
Here, the electrolytic copper plating conditions may be the same as the conditions used in the step of FIG.
In addition, although a conformal via is formed in the via hole 42, it is not particularly limited, and a conformal via and a filled via may be appropriately selected and used.
[0037]
Next, the plating resist pattern 53 is peeled and removed with a 0.5 to 2.0 wt% sodium hydroxide aqueous solution, and the plating base conductive layer located under the plating resist pattern 53 is removed by flash etching to form the third wiring layer 23a. Formed, the support sheet 62 is removed, the build-up layer 20 in which the second wiring layer 22a and the filled via 31 are formed on one surface of the first wiring layer 21a via the insulating resin layer 11, and on the other surface A three-layer printed wiring board 100 including the build-up layer 30 in which the third wiring layer 23a and the conformal via 32 are formed is obtained through the insulating resin layer 12 (see FIG. 4 (k)).
Furthermore, a desired multilayer printed wiring board can be obtained by repeating the insulating resin layer, the wiring layer, and the conformal via or filled via forming process as many times as necessary.
[0038]
FIGS. 5A to 5F and FIGS. 6G to 6K are schematic configuration sectional views showing a second embodiment of the method for manufacturing a multilayer printed wiring board according to the present invention in the order of steps.
First, the steps of FIGS. 5A to 5F are processed in the same manner as in FIGS. 3A to 3F, and the first wiring layer 21a, the second wiring layer 22a, the land 22c, and the filled via 32 are processed. And a double-sided wiring board 40 in which the first wiring layer 21a, the second wiring layer 22a land 22b, and the filled via 32 are formed on both surfaces of the insulating resin layer 11 is obtained (see FIG. 6G).
[0039]
Next, a prepreg sheet is laminated on both sides of the double-sided wiring board 40 to form the insulating resin layer 13 and the insulating resin layer 14, and for vias at predetermined positions of the insulating resin layer 13 and the insulating resin layer 14 by laser processing or the like. A hole 43 and a via hole 44 are formed, and desmear, plating catalyst application, and electroless copper plating are performed to form a plating base conductive layer (not shown) (see FIG. 6H).
Here, the desmear, plating catalyst application, and electroless copper plating conditions may be the same as the conditions used in the step of FIG.
[0040]
Next, the photosensitive dry film is stuck on the insulating resin layer 13 and the insulating resin layer 14 with a heat roll of 80 to 120 ° C., the release sheet is peeled off, and the photosensitive dry film is exposed on the insulating resin layer 13 and the insulating resin layer 14. After forming a layer, pattern exposure is performed by irradiating 50 to 200 mJ / cm 2 of ultraviolet rays with an ultrahigh pressure mercury lamp on both sides, 0.5 to 2 wt% aqueous sodium carbonate solution is spray developed, dried and cured, and then a plating resist pattern 54 is formed. Then, a plating resist pattern 55 is formed (see FIG. 6I).
[0041]
Next, the plating resist pattern 54 and the wiring substrate on which the plating resist pattern 55 is formed are immersed in a copper sulfate plating bath, and electrolytic copper plating is performed using the plating base conductive layer as a cathode. A conformal via 33 is formed in the conductor layer 24 and via hole 43 having a thickness of 15 μm, and a filled via 34 is formed in the conductor layer 25 and via hole 44 having a thickness of 10 to 15 μm on the insulating resin layer 14 (FIG. 6J). reference).
Here, the electrolytic copper plating conditions may be the same as the conditions used in the step of FIG.
[0042]
Next, the plating resist pattern 54 and the plating resist pattern 55 are stripped and removed with a 0.5 to 2.0 wt% sodium hydroxide aqueous solution, and the plating base conductive layer under the plating resist pattern 54 and the plating resist pattern 55 is flash etched. The third wiring layer 24a, the fourth wiring layer 25a, and the land 25b are formed, and the third wiring layer 24a and the conformal via 33 are formed on one surface of the double-sided wiring board 40 via the insulating resin layer 13. The formed buildup layer 50 and the buildup layer 50 having the fourth wiring layer 25a and the filled via 34 formed on the other surface via the insulating resin layer 13 are formed, respectively, to obtain the four-layer printed wiring board 200 (FIG. 6 (k)).
Furthermore, a desired multilayer printed wiring board can be obtained by repeating the insulating resin layer, the wiring layer, and the conformal via or filled via forming process as many times as necessary.
[0043]
【The invention's effect】
As described above, the multilayer printed wiring board according to the present invention has a build-up multilayer printed wiring board structure without a core substrate, thereby increasing the degree of freedom in pattern design of the wiring layer and improving the capacity of the wiring layer. Therefore, it is possible to reduce the thickness and form a fine wiring layer, and to increase the density.
In addition, since the build-up multilayer printed wiring board has a symmetric structure, the wiring board is hardly warped even if it is thinned.
Moreover, in the method for producing a multilayer printed wiring board according to the present invention, since the wiring layer is formed using a semi-additive method, a wiring layer having a fine pattern can be easily obtained.
In addition, since a support sheet is used, it is possible to easily reinforce the processing substrate that also serves as a protective layer during the manufacturing process of the multilayer printed wiring board, and in particular, when manufacturing a thin wiring board, Preventive effect is exhibited.
[Brief description of the drawings]
FIGS. 1A to 1C are schematic sectional views showing an embodiment of a multilayer printed wiring board according to the present invention.
FIGS. 2A to 2D are schematic cross-sectional views showing an embodiment of a semiconductor device of the present invention.
3 (a) and (f) are cross-sectional views schematically showing a part of the steps in the first example of the method for manufacturing a multi-layer printed wiring board of the present invention.
[4] (g) and (k) is a cross-sectional view schematically showing a part of the process in the first example of the method for manufacturing a multi-layer printed wiring board of the present invention.
5 (a) and (f) are cross-sectional views schematically showing a part of the process in the second embodiment of the method of manufacturing the multi-layer printed wiring board of the present invention.
6 (g) and (k) is a cross-sectional view schematically showing a part of the process in the second embodiment of the method of manufacturing the multi-layer printed wiring board of the present invention.
FIGS. 7A and 7F are cross-sectional views schematically showing an example of a process for manufacturing a conventional multilayer printed wiring board.
FIGS. 8A and 8D are cross-sectional views schematically showing an example of a process for manufacturing a conventional multilayer printed wiring board.

Claims (3)

以下の工程を少なくとも備えることを特徴とする、第１配線層の両面に絶縁樹脂層を介して複数の配線層が形成されている多層プリント配線板の製造方法。
（ａ）絶縁樹脂層及び銅箔からなる片面銅箔付樹脂シートを準備する工程。
（ｂ）前記片面銅箔付樹脂シートの前記絶縁樹脂層の所定位置にビア用孔を形成し無電解銅めっきによりめっき下地導電層を形成する工程。
（ｃ）前記銅箔上に支持体シートを貼着した後前記めっき下地導電層上にめっきレジストパターンを形成する工程。
（ｄ）前記めっき下地導電層をカソードにして電解銅めっきを行って所定厚の導体層及びフィルドビアを形成する工程。
（ｅ）前記めっきレジストパターンを剥離処理し、前記めっきレジストパターン下部にあった前記めっき下地導電層をフラッシュエッチングにて除去し、第２配線層及び前記フィルドビアを形成し、次に、前記支持体シートを除去する工程。
（ｆ）前記第２配線層側に第２の支持体シートを貼着した後、前記銅箔上に第２のレジストパターンを形成する工程。
（ｇ）前記第２のレジストパターンをマスクにして前記銅箔をエッチング処理し、前記第２のレジストパターンを剥離処理して、第１配線層を形成する工程。
（ｈ）前記第１配線層側に所定厚の第２の絶縁樹脂層を形成し、前記第２の絶縁樹脂層の所定位置に第２のビア用孔を形成し無電解銅めっきにより第２のめっき下地導電層を形成する工程。
（ｉ）前記第２の絶縁樹脂層側に第２のめっきレジストパターンを形成する工程。
（ｊ）前記第２のめっき下地導電層をカソードにして電解銅めっきを行い、所定厚の第２の導体層及び第２のビアを形成する工程。
（ｋ）前記第２のレジストパターンを剥離処理し、前記第２のめっきレジストパターン下部にあった前記第２のめっき下地導電層をフラッシュエッチングにて除去し、外側配線層及び前記第２のビアを形成する工程。
（ｌ）前記第２の支持体シートを前記工程（ｇ）の後から前記工程（ｋ）の間に除去する
工程。
（ｍ）前記第２の絶縁樹脂層、前記外側配線層及び前記第２のビア形成工程を必要回数繰り返す工程。The manufacturing method of the multilayer printed wiring board by which the several process layer is formed in the both surfaces of the 1st wiring layer via the insulating resin layer characterized by including the following processes at least.
(A) an insulating resin So及 beauty copper foil or Ranaru step of preparing a single-sided copper foil with a resin sheet.
(B) A step of forming a via hole at a predetermined position of the insulating resin layer of the resin sheet with a single-sided copper foil and forming a plating base conductive layer by electroless copper plating.
(C) forming the plating underlying conductive layer TLR Kki resist pattern after adhering a support sheet on the copper foil.
; (D) plating underlying conductive layer to the cathode and subjected to electrolytic copper plating to form a conductor So及 beauty Firudobi A predetermined thickness step.
(E) a said plating resist pattern is removed process, the plating resist pattern the plating underlying conductive layer that has been in the lower removed by flash etching, to form the second wiring So及 beauty the filled vias, then the support Removing the body sheet .
(F) The process of forming a 2nd resist pattern on the said copper foil , after sticking a 2nd support body sheet to the said 2nd wiring layer side.
(G) the said copper foil as a mask the second resist pattern was etched, the second resist pattern is peeled off process, the step of forming the first wiring layer.
(H) A second insulating resin layer having a predetermined thickness is formed on the first wiring layer side, a second via hole is formed at a predetermined position of the second insulating resin layer , and the second is formed by electroless copper plating . forming a plating underlying conductive layer.
(I) A step of forming a second plating resist pattern on the second insulating resin layer side.
(J) A step of performing electrolytic copper plating using the second plating base conductive layer as a cathode to form a second conductor layer and a second via having a predetermined thickness.
(K) The second resist pattern is stripped, and the second plating base conductive layer under the second plating resist pattern is removed by flash etching, and the outer wiring layer and the second via are removed. forming a.
(L) The second support sheet is removed during the step (k) after the step (g).
Process.
(M) A step of repeating the second insulating resin layer, the outer wiring layer, and the second via formation step as many times as necessary. 前記第２の支持体シートを前記工程（ｇ）の後に除去し、前記工程（ｈ）において、前記第１配線層及び前記第２配線層側にそれぞれ所定厚の第２の絶縁樹脂層及び第３の絶縁樹脂層を形成し、前記第２の絶縁樹脂層及び前記第３の絶縁樹脂層の所定位置にそれぞれ第２のビア用孔及び第３のビア用孔を形成し無電解銅めっきにより第２のめっき下地導電層および第３のめっき下地導電層をそれぞれ形成し、前記工程（ｉ）において、前記第２の絶縁樹脂層側に第２のめっきレジストパターンを形成し、前記第３の絶縁樹脂層側に第３のめっきレジストパターンを形成し、前記工程（ｊ）において、前記第２のめっき下地導電層および前記第３のめっき下地導電層をカソードにして電解銅めっきを行い、前記第２の絶縁樹脂層側に所定厚の第２の導体層と第２のビアを形成し、前記第３の絶縁樹脂層側に所定厚の第３の導体層と第３のビアを形成し、前記工程（ｋ）において、前記第２のレジストパターン及び前記第３のめっきレジストパターンを剥離処理し、前記第２のめっきレジストパターン及び前記第３のめっきレジストパターンの下部にあった前記第２のめっき下地導電層及び前記第３のめっき下地導電層をフラッシュエッチングにて除去し、両面に前記外側配線層及び前記第２のビアと前記第３のビアを形成することを特徴とする請求項１記載の多層プリント配線板の製造方法。The second support sheet is removed after the step (g). In the step (h), a second insulating resin layer having a predetermined thickness and a second thickness on the first wiring layer side and the second wiring layer side, respectively. 3 and a second via hole and a third via hole at predetermined positions of the second insulating resin layer and the third insulating resin layer, respectively, by electroless copper plating. A second plating base conductive layer and a third plating base conductive layer are respectively formed, and in the step (i), a second plating resist pattern is formed on the second insulating resin layer side, and the third plating base conductive layer is formed. A third plating resist pattern is formed on the insulating resin layer side, and in the step (j), electrolytic copper plating is performed using the second plating base conductive layer and the third plating base conductive layer as a cathode, The second insulation resin layer side has a predetermined thickness A conductor layer and a second via are formed, a third conductor layer and a third via having a predetermined thickness are formed on the third insulating resin layer side, and in the step (k), the second resist is formed. The pattern and the third plating resist pattern are peeled off, and the second plating base conductive layer and the third plating base conductive located under the second plating resist pattern and the third plating resist pattern are removed. 2. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the layer is removed by flash etching, and the outer wiring layer, the second via, and the third via are formed on both sides. 前記支持体シートがポリエステルフィルム、ポリイミドフィルム、アミドフィルム、ポリプロピレンフィルムのいずれかで形成されていることを特徴とする請求項１又は２に記載の多層プリント配線板の製造方法。The method for producing a multilayer printed wiring board according to claim 1 or 2 , wherein the support sheet is formed of any one of a polyester film, a polyimide film, an amide film, and a polypropylene film.
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