JP4053771B2 - Controllable semiconductor circuit element blocking in both directions - Google Patents

Controllable semiconductor circuit element blocking in both directions Download PDF

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JP4053771B2
JP4053771B2 JP2001543787A JP2001543787A JP4053771B2 JP 4053771 B2 JP4053771 B2 JP 4053771B2 JP 2001543787 A JP2001543787 A JP 2001543787A JP 2001543787 A JP2001543787 A JP 2001543787A JP 4053771 B2 JP4053771 B2 JP 4053771B2
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recombination
transition
circuit element
channel
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JP2003516639A (en
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イェネー ティハニイ，
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Infineon Technologies AG
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Description

【０００１】
本発明は、制御可能な半導体素子、特に、電界効果によって制御可能な半導体回路素子に関する。この半導体素子は以下の特徴を有する。
【０００２】
第１の導電領域、および第１の導電型の第２の導電領域、
第１の導電領域と第２の導電領域との間に配置された、第２の導電型のチャネル領域、
絶縁されてチャネル領域と向き合う配置の制御電極。
【０００３】
このような半導体回路素子は、例えば、従来技術により公知のＭＯＳＦＥＴ（酸化金属電界効果トランジスタ）である。従来技術による垂直パワーＭＯＳＦＥＴ（ｖｅｒｔｉｋａｌｅｓ Ｌｅｉｓｔｕｎｇｓ−ＭＯＳＦＥＴ）の実施形態は、Ｓｔｅｎｇｌ／Ｔｉｈａｎｙｉの「Ｌｅｉｓｔｕｎｇｓ−ＭＯＳＦＥＴ−Ｐｒａｘｉｓ」Ｐｆｌａｕｍ Ｖｅｒｌａｇ、Ｍｕｅｎｃｈｅｎ、１９９２、２９ページ以下、に記載され、図１ａにおいて横断面が部分的に示される。ＭＯＳＦＥＴは、第１の導電型（ｎ）の導電領域１２としてソース領域を有し、この導電領域は、第２の導電型（ｐ）の井戸状のチャネル領域（ボディ（Ｂｏｄｙ）領域または遮断領域と呼ばれる）に埋め込まれる。ソース領域１２は、外部からソース電極４０を介してコンタクト可能であり、ソース電極４０は、ソース領域１２を通ってチャネル領域の中にまで達し、従って、ソース領域１２とチャネル領域１８とを短絡させる（ｋｕｒｚｓｃｈｌｉｅｓｓｔ）。
【０００４】
チャネル領域１８は、第１の導電型（ｎ）の第２の導電領域１４、１６（ＭＯＳＦＥＴのドレイン領域）に埋め込まれ、第２の導電領域は、ｎ型ドーピングされたチャネル領域１８を包囲する領域１４、およびドレイン電極を接合するための、強くｎ型ドーピングされた領域１６を有する。チャネル領域１８ならびに絶縁されてソース領域１２およびドレイン領域１４と向き合うゲート電極が、ＭＯＳＦＥＴの制御電極２０として半導体の上部に配置され、半導体において、順方向とも呼ばれるソース領域１２、および逆方向とも呼ばれるドレイン領域が形成される。
【０００５】
図１ａによる垂直ＭＯＳＦＥＴの代替回路図が図１ｂにおいて示される。この図は、理想ＭＯＳＦＥＴ Ｔ１とダイオードＤｉとの組合せとして示され、ダイオードは、ＭＯＳＦＥＴのソース端子Ｓとドレイン端子Ｄとの間に流れ方向に
接続される。正電圧をソースドレイン方向に印加すると導電するダイオードは、ドレイン領域１４、１６とボディ領域１８との間のｐｎ遷移およびボディ領域１８とソース領域１２との間の短絡の結果として生じる。
【０００６】
集積ダイオードの存在は、ＭＯＳＦＥＴを用いるいくつかの場合に不利である。なぜなら、このダイオードは、フロー電圧（Ｆｌｕｓｓｓｐａｎｎｕｎｇ）をドレインソース方向に印加した場合にのみＭＯＳＦＥＴが導電するようにし、電圧をソースドレイン方向に印加した場合はＭＯＳＦＥＴがダイオードのように導電するように作用する。
【０００７】
ソース領域とボディ領域との間に短絡がなければ、ＭＯＳＦＥＴにおいて寄生バイポーラトランジスタが動作する。このトランジスタは、異なったドーピングがされた領域の連続、すなわち第１の導電型のソース領域、第１の導電型に対して相補的な第２の導電型のチャネル領域、および第１の導電型のドレイン領域によって形成され、このトランジスタのベースはチャネル領域によって形成され、このトランジスタのエミッタ／コレクタはソース領域／ドレイン領域によって形成される。
【０００８】
図１ｃは、ソース領域とドレイン領域との間に短絡がないＭＯＳＦＥＴの電気の代替回路図を示す。この図は、理想ＭＯＳＦＥＴＴ１とバイポーラトランジスタとの組合せとして表される。バイポーラトランジスタＢ１のコレクタエミッタ線Ｃ−Ｅは、ＭＯＳＦＥＴＴ１のドレイン−ソース線Ｄ−Ｓと平列に接続される。寄生バイポーラトランジスタＢ１のベース領域は、ＭＯＳＦＥＴのチャネル領域によって、エミッタ領域はＭＯＳＦＥＴのソース領域によって、およびコレクタ領域はＭＯＳＦＥＴのドレイン領域によって形成される。
【０００９】
図１ｄにおいて、この半導体回路素子の特性曲線が示すように、寄生バイポーラトランジスタＢ１は、図１ｃによる半導体回路素子の耐電圧に影響を及ぼす。値ＵＣＥ０のドレインソース電圧ＵＤＳの場合、寄生バイポーラトランジスタＢ１のコレクタエミッタ破壊電圧、従って、半導体回路素子のドレインソース方向Ｄ−Ｓの最大障壁電圧に達する。特性曲線から理解され得るように、ゲートソース電圧が上昇するに従って、耐電圧はわずかに上昇する。この破壊電圧に達するまで、半導体素子の応答は理想ＭＯＳＦＥＴの応答に対応する。
【００１０】
短絡されないソース領域および遮断領域を有するＭＯＳＦＥＴにおいて耐電圧が低減されると、動作中、すなわち制御電位をゲート端子に印加した場合、および流れ電圧をドレインとソースとの間に印加した場合、基板内の荷電担体が集まる。この荷電担体は寄生バイポーラトランジスタのベースを制御させ、それによってこのトランジスタは導電性になる。このようなＭＯＳＦＥＴのドレーンソース方向の耐電圧は、短絡されたソース領域およびボディ領域を有する類似の素子の耐電圧のわずか１／３ほどにすぎない。
【００１１】
本発明の目的は、主要電圧方向（順方向）における障壁電圧を低減せずに両方向に遮断する、制御可能な半導体回路素子を利用可能にすることである。
【００１２】
この課題は、冒頭で述べた半導体回路素子によって解決される。この半導体回路素子は、遮断領域で形成される第１の導電型および第２の導電型の荷電担体の再結合を促す材料を含む、遮断領域において形成された少なくとも１つの再結合をさらに有する。本発明による半導体回路素子の場合、チャネル領域と、２つの導電性領域のうちの１つとの間に短絡は提供されない。
【００１３】
互いに隣接して配置される、第１の導電型の第１の導電性領域、第２の導電型のチャネル領域および第２の導電型の第２の導電性領域の連続によって、本発明による半導体回路素子において寄生バイポーラトランジスタが形成される。しかしながら、半導体回路素子のチャネル領域における、および寄生バイポーラトランジスタのベース領域における再結合領域を提供することは、寄生バイポーラトランジスタの電気的応答を変化させる。第１の導電性領域と第２の導電性領域との間に流れ電圧を印加した場合、２つの導電性領域のうちの１つとチャネル領域との間の空間電荷領域において、第１の導電型および第２の導電型の荷電担体、すなわち、ホールおよび電子が生成される。第１の導電型の荷電担体は、再結合領域の境界、またはこの領域の表面において、第２の導電型の荷電担体とわずかに再結合し得る。再結合領域によって、寄生バイポーラトランジスタは、ごくわずかに制御されるように達成され、および十分な大きさの再結合領域が存在する場合に寄生バイポーラトランジスタがもはや能動状態にないことが達成される。
【００１４】
本発明による半導体回路素子の耐電圧は特定の方向（順方向）で、従って、導電性領域のうちの１つとチャネル領域との間に短絡を有する従来のこのような半導体回路素子の耐電圧に相当する。同時に、本発明による半導体回路素子は、別の方向（逆方向）で流れ電圧を印加した場合にも遮断する。なぜなら、導電性領域とチャネル領域との間に短絡が存在しないからである。
【００１５】
本発明の有利な実施形態は従属請求項から明らかになる。
【００１６】
再結合領域の材料は、好適には、金属である。さらなる実施形態により、ポリシリコンまたは他の半導体材料を含む再結合領域、あるいはシリコンまたは他の対応する半導体結合を含む再結合領域が提供され得る。
【００１７】
１実施形態によると再結合領域はプレート状に形成され、荷電担体を再結合するために、わずかな体積で可能なかぎり大きい表面を利用可能にする。本発明による半導体回路素子は、好適には、セル状に構成される、すなわち同様に構成され、同様に制御される複数のセルが存在し、これらのセルは各々第１の導電領域、チャネル領域および第２の導電領域を有する。この場合、各セルは再結合領域を有する。
【００１８】
チャネル領域、好適には各セルのチャネル領域において、複数の、特にプレート状または帯状に形成された再結合領域が互いに距離を置いて形成され得る。この場合、好適には、個々の再結合領域は、第２の導電型の強くドーピングされた領域によって互いに接続され、再結合領域間、または互いに離れて配置される様々な再結合領域の部分間で荷電担体のわずかな交換を可能にする。
【００１９】
チャネル領域によって、すなわち、第２の導電型の材料を含む領域によって再結合領域が完全に包囲される実施形態と並んで、本発明のさらなる実施形態によると、第１の導電型の材料を含む領域によって再結合領域を第１の導電領域と接続することが提供される。ＭＯＳＦＥＴの場合、ボディ領域とも呼ばれる遮断領域と、第１の導電領域との間に、再結合領域の材料として金属またはシリサイドを用いた場合、素子の逆方向の耐電圧を決定するショットキコンタクトが生じる。
【００２０】
本発明のさらなる実施形態により、第１の導電領域は、第１の接続電極を接続するためのより強くドーピングされた接続領域、および接合域とチャネル領域との間のより弱くドーピングされた遷移領域を有し、第２の導電領域は、第２の電極を接合するための強くドーピングされた第２の接合領域、および第２の接合領域とチャネル領域との間に配置されるより弱くドーピングされた２つの遷移領域を有することを提供する。本発明による半導体回路素子の耐電圧は、基本的には、遷行領域をドーピングすることによって、および遷移領域によって決定されたチャネル領域からの接合領域の距離によって決定される。この実施形態において、各導電領域は弱くドーピングされた遷移領域を有し、遷移領域の厚さおよびドーピングによって、半導体回路素子の順方向および逆方向のほぼ同じ耐電圧が調整され得る。
【００２１】
本発明は、次に、図を用いた実施例において詳細に説明される。
【００２２】
図において、他に記載がない限り、同じ参照符号は同じ意味を有する同じ部分および領域を示す。
【００２３】
図２は、第１の実施形態による、本発明による半導体回路素子の横断面の１部を示す。図示された半導体回路素子は、垂直ｎ型導電性ＭＯＳトランジスタ、特に、ｎ型導電性ＭＯＳＦＥＴの構成を有する。ｎ型導電性半導体１０において、ボディ領域または遮断領域とも呼ばれるｐ型導電性領域はチャネル領域１８として形成される。このｐ型領域に、強くドーピングされたｎ型導電性領域１２が再び埋め込まれ、これはＭＯＳＦＥＴの第１の導電領域またはソース領域として利用される。半導体１０はｎ型導電領域１４を有し、およびソース領域に背を向けた側の領域において、強くドーピングされたｎ型導電性領域１６を有し、これらの領域は共に第２の導電領域またはドレイン領域を形成する。強くドーピングされた領域１６は、ドレイン電極Ｄへの接合のために用いられる。
【００２４】
ソース領域１２は、例えばアルミニウムを含むソース電極４０、Ｓと接続され、このソース電極４０は半導体１０の表面においてソース領域を接触させる。少なくとも１つのゲート電極２０はＭＯＳＦＥＴの制御電極として利用され、遮断領域１２を介して、および絶縁層３０によってこの遮断領域から分離されて配置される。ゲート電極２０は、例えば、ポリシリコンを含み、絶縁層３０は、例えば、酸化シリコンを含む。図示された構造は、好適には、左右、および図面に対して垂直方向に何度も繰返され、それによって半導体回路素子のセル状の構造が生じる。半導体回路素子の電流耐性（Ｓｔｒｏｍｆｅｓｔｉｇｋｅｉｔ）はセルの数とともに上昇する。
【００２５】
図示されたＭＯＳＦＥＴは寄生バイポーラトランシステを有し、このトランジスタのエミッタ領域はソース領域１２によって形成され、トランジスタのベース領域はチャネル領域１８によって形成され、トランジスタのコレクタ領域は垂直ＭＯＳＦＥＴのドレイン領域１４、１６によって形成される。
【００２６】
ＭＯＳＦＥＴのチャネル領域１８、または寄生バイポーラトランジスタのベース領域において、この領域においてｎ型荷電担体およびｐ型荷電担体の再結合を促す材料を含む再結合領域１９が配置される。再結合領域は、好適には、金属、ポリシリコンまたはシリサイドを含み、例えば、プレート状に形成される。
【００２７】
本発明による半導体回路素子において、ドレイン領域１４、１６および領域１６に付与された、詳しく図示されないドレイン電極と、ソース領域１２またはソース電極４０との間に正電圧が印加された場合、ドレイン領域１４とチャネル領域１８との間の空間電荷領域において荷電担体、すなわち、電子およびホールが生成される。
【００２８】
この場合、ホールは空間電荷領域における電場に基いてドレイン領域１４、１６に流れ、ホールは遮断領域に流れる。再結合領域１９の表面において注入された（ｉｎｊｉｚｉｅｒｔ）ホールの電子との再結合は強化されて生じるので、寄生バイポーラトランジスタが活性になること、およびドレインソース方向の障壁電圧が低減されることが回避される。
【００２９】
換言すると、寄生バイポーラトランジスタのベース領域におけるｎ型荷電担体およびｐ型荷電担体の良好な再結合の可能性は、このトランジスタの電流増幅率βを低減し、その結果、ＭＯＳＦＥＴの耐電圧をドレインソース線上のＭＯＳＦＥＴの耐電圧を共に決定する、このトランジスタのコレクタエミッタ破壊電圧を上昇させる。
【００３０】
さらに、図示された半導体回路素子はＭＯＳＦＥＴのように機能する。すなわち、正の制御電位がゲート電極２０に印加された場合、ソース領域１２とドレイン領域１４との間のチャネル領域において導電性チャネルが形成される。このチャネルはドレイン領域１６とソース電極１４との間に流れ電圧を印加した場合に、ドレイン端子Ｄとソース端子Ｓとの間に電流が流れることを可能にする。
【００３１】
再結合領域１９の材料および幾何学的構造を適切に選択することによって、ＭＯＳＦＥＴの破壊電圧は、第１の導電領域（ソース領域）１２とチャネル領域１８との間に短絡が生じた場合、すなわち寄生バイポーラトランジスタのベースエミッタ線が短絡された場合に破壊電圧が生じるまで上昇され得るが、このような短絡の不利な影響、すなわち逆方向（ソースドレイン方向）の耐電圧の不足を甘受しなくてよい。図示されたＭＯＳＦＥＴは、ソース電極４０またはソース領域１２とドレイン領域１４、１６との間に正電圧を印加した場合も遮断領域１８とソース領域１２との間のｐｎ型遷移が原因で遮断する。
【００３２】
図２において示されるように、領域１６は強くｎ型ドーピングされるのではなく、強くｐ型ドーピングされ得る。半導体回路素子は、その後、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒｔｒａｎｓｉｓｔｏｒ＝絶縁ゲート型バイポーラトランジスタ）として機能する。
【００３３】
再結合領域１９は、好適には、わずかな体積を用いて大きい平面を有するように形成される。
【００３４】
従って、再結合領域は、好適には、プレート状または図３において図２の線ａ−ａ’に沿う横断面を用いて示されるように、基本的に平列に延びる複数の帯状の部分から形成される。図３における破線は、これらの部分の上に存在するゲート電極２０の位置を具体的に示す。点線はその上に存在するソース電極４０、Ｓの位置を具体的に示す。
【００３５】
図４は、図３において記入された交線ｃ−ｃ’に沿う半導体回路素子の横断面を示し、再結合領域１９を形成する帯が平列して並ぶ状態がこの横断面から明確になる。再結合領域１９の個々の下部領域は、好適には、強くｐ型ドーピングされた領域１８１によって互いに接続され、再結合領域１９の下部領域間で電荷交換１９が促される。
【００３６】
図５は、本発明による半導体回路素子のさらなる実施形態を示す。この実施形態において、再結合領域１９および強くｎ型ドーピングされたソース領域１２は、ｎ型導電性領域１３によって互いに接続される。再結合領域１９の材料は、この実施形態の場合、好適には、金属またはシリサイドである。
【００３７】
図６は、図５による半導体回路素子の代替回路図を示す。ソース領域の部分であるｎ型導電性領域１３と再結合領域１９との間にショットキ遷移が形成され、この遷移はショットキダイオードＤｓとしてソース端子ＳとＭＯＳＦＥＴの基板端子との間に記入される。ドレイン端子Ｄと基板端子との間のダイオードＤ２は、ドレイン領域１４、１６と遮断領域１８（ｐ型ボディ領域とも呼ばれる）との間のｐｎ型遷移によって形成される。ショットキダイオードＤｓは、半導体回路素子の逆方向の（ソースドレイン方向）の障壁電圧を決定し、ドレイン領域１４、１６と遮断領域１８との間のダイオードＤ２またはｐｎ型遷移はＭＯＳＦＥＴの順方向（ドレインソース方向）の耐電圧を決定する。
【００３８】
図７は、本発明のさらなる実施形態による半導体回路素子の断面の１部を示す。図８は、図７において記入された交線ｃ−ｃ’に沿う半導体回路素子の断面を示す。ゲート電極６０は、この実施形態において、半導体１０１に「埋め込まれ」て配置され、絶縁層７０によって取巻かれる。ソース電極８０は、上方で半導体１０１を停止させる。第１の強くｎ型ドーピングされた導電性領域（ソース領域）５２はソース電極８０の下、およびゲート電極６０の溝構造間に配置される。ソース領域５２にｐ型ドーピングされた遮断領域５８が接合され、この遮断領域においてｎ型荷電担体およびｐ型荷電担体を支持する（ｆｏｅｒｄｅｒｎｄ）材料を含む再結合領域５９が配置される。ゲート電極６０およびこれを取巻く絶縁層７０は、ｎ型ドーピングされた領域５４まで下方へ延び、このｎ型ドーピングされた領域５６は、図示されたＭＯＳＦＥＴの第２の導電性領域（ドレイン領域）を形成する。
【００３９】
ｐ型導電性チャネル領域５８によって完全に包囲される再結合領域１９の実施例と並んで、図７は、絶縁層９０によってソース電極８０、Ｓおよびソース領域５２から絶縁される再結合領域５９’の実施例を示す。これは、遮断領域における再結合領域５９’の可能な作製方法の結果である。この場合、ソース電極８０の堆積の前に、例えば、エッチングによって遮断領域５８にホールが付与され、次に、ソース領域５２の下の高さまで再結合を促す材料で埋められる。次に、再結合を促す材料の上に位置するホールにおいて絶縁層９０が付与される。
【００４０】
特に図８における平面図から明らかなように、図７による本発明の半導体回路素子は格子状のゲート電極６０を有し、格子の間隙において、絶縁層７０によってゲート電極６０から絶縁されたチャネル領域５８が再結合領域５９とともに配置される。従って、半導体回路素子は、同時に制御される、同様に構成された複数のセルを有する。本発明による半導体回路素子の電流耐性は、セルの数が増加すると向上する。ゲート電極６０に正の制御電位を印加する場合、ゲート電極６０に沿って導電性のチャネルが半導体１０５の垂直方向に形成される。この際、ドレイン電極Ｄとソース電極Ｓとの間に流れ電圧を印加すると、ドレイン電極Ｄとソース電極Ｓとの間に電流が流れることが可能になる。
【００４１】
図９は、ゲート電極６０および絶縁層７０を含む溝状の構造を有する本発明の半導体回路素子のさらなる実施形態の横断面の１部が示される。この実施形態において、ソース領域は、ゲート電極６０およびソース電極８０に隣接して配置される強くｎ型ドーピングされた領域５２、ならびに残りの領域において強くドーピングされた領域５２を包囲する通常のｎ型ドーピングされた領域５３を含む。再結合領域５９は、この実施形態において、領域５３の下に配置されたｐ型ドーピングされた遮断領域５８から、ｎ型ドーピングされた領域５３まで延び、上方で絶縁層９０によってソース電極８０から絶縁される。この実施形態において、再結合領域５９は、好適には、金属またはシリサイドを含み、ｎ型ドーピングされた領域５３と共にショットキコンタクトを形成する。図９による半導体回路素子の代替回路図は図６に対応する。
【００４２】
図２〜図６において示される半導体回路素子の場合、ゲート電極Ｇとソース電極Ｓとの間に正電圧が印加され、およびドレイン電極Ｄとソース電極Ｓとの間に正電圧が印加されると、遮断領域１８において水平方向の導電性チャネルが形成される一方で、図７および図８による実施例においては垂直方向の導電性チャネルが形成される。この実施形態は、図２〜図６において示された実施形態よりも空間節約的（ｐｌａｔｚｓｐａｒｅｎｄ）である。
【００４３】
強くｎ型ドーピングされた領域５６を強くＰ型ドーピングされた領域と取替えると、図７〜図９において示される素子はＩＧＢＴとして機能する。
【００４４】
図１０は、水平方向の構造方式のＭＯＳＦＥＴとして形成される、本発明による半導体回路素子のさらなる実施形態を示す。強くｎ型ドーピングされたドレイン領域２１６およびｎ型ドーピングされたソース領域２１２は、半導体２００のｐ型ドーピングされた遮断領域２１８内配置され、ソース電極Ｓおよびドレイン電極Ｇを用いて半導体２００の同じ側から接触可能である。ゲート電極Ｇは絶縁層２３０によって絶縁され、半導体２００上に配置される。ｎ型荷電担体とｐ型荷電担体の再結合を促す材料を含む再結合領域が遮断領域２１８に配置される。
【００４５】
図１１は、本発明による、両方向に遮断する半導体回路素子のさらなる実施例を横断面の側面図で示す。図１２において、図１１の構成の切断面Ａ−Ａ’に沿う横断面が示される。
【００４６】
本発明による半導体回路素子は、強くｎ型ドーピングされた第２の接合領域１１２およびこの第２に接合領域１１２に隣接して配置される、第２の接合領域１１２よりも弱くｎ型ドーピングされた第２の遷移領域１１４を有する半導体１００を有する。この際、第２の接合領域１１２および第２の遷移領域１１４は、半導体回路素子の第２の導電性領域（ドレイン領域）を形成する。第２の遷移領域１１４に隣接してｐ型ドーピングされたチャネル領域１１６が形成されるこの領域は、必ずしも一様にドーピングされる必要はない。このチャネル領域はｎ型ドーピングされた第１の遷移領域１１８と接合される。第１の遷移１１８に隣接して、第１の遷移領域１１８よりも強くｎ型ドーピングされた第１の接合領域１１０が形成され、第１の接合領域１１０および第１の遷移領域１１８は、半導体回路素子の第１の導電性領域（ソース領域）を形成する。第２の接合領域１１２、第２の遷移領域１１４、チャネル領域１１６、第１の遷移領域１１８および第１の接合領域１１０は、実施例において層状に重ねられて配置される。第２の端子電極１４０は、好適には、金属またはポリシリコンを含み、第２の接合領域１１２と接触するように半導体１００の裏側に付与され、第１の端子電極１４１は、好適には、金属またはポリシリコンを含み、第２の接合領域１１２と接触するように半導体の表側に付与される。
【００４７】
正の制御電位をゲート電極に印加した場合、この半導体回路素子においては半導体の表面に沿って、ソース領域２１２とドレイン領域２１６との間に導電性チャネルが形成される。ｎ型荷電担体およびｐ型荷電担体は、この実施形態においても再結合領域２１９において互いに再結合し得、その結果、ｎ型導電性ソース領域２１２、ｐ型導電性チャネル領域２１８およびｎ型導電性ドレイン領域２１６の連続によって形成された寄生バイポーラトランジスタの制御が回避される。
【００４８】
第２の接合領域１１２およびこの接合領域に接合する第２の遷移領域１１４は、ＭＯＳＦＥＴのドレイン領域を形成する。第１の接合領域１１０およびこの接合領域に接合する第１の遷移領域１１８は、ＭＯＳＦＥＴのソース領域を形成する。この場合、図１１において示されるＦＥＴが対称的な構成であるためにドレイン端子およびソース端子は交換可能である。
【００４９】
ドレイン領域１１２、１１４とソース領域１１０、１１８との間のチャネル領域において導電性チャネルの形成を可能にするために、制御電極１２０、１２２、１２４、１２６が提供される。この電極は絶縁層１２１、１２３、１２５、１２７によって包囲され、ｎ型ドーピングされた第１の遷移領域１１４からｐ型ドーピングされたチャネル領域１１６を通って、ｎ型ドーピングされた第２の遷移領域１１８へ半導体１００の垂直方向に延びる。図２から明らかなように、実施例において、共通プレート１２６によって接続された、ほぼ平列の制御電極１２０、１２２、１２４が提供される。その結果、制御電極１２０、１２２、１２４は、共通の制御電位に置かれ得る。共通プレートは、絶縁層１２７によって半導体１００から絶縁され、垂直方向に、好適には、半導体１００の表側または裏側まで延び、制御電位に接合される。好適には、第１の接合領域１１０および／または第２の接合領域１１２は、共通プレート１２６に沿って電流を導くチャネルが形成されることを回避するために、共通プレート１２６までは延びない。制御電極１２０、１２２、１２４を共通の制御電位に置くために、当然、共通プレート１２６と並んで任意のさらなる実施形態が考えられ得る。
【００５０】
半導体１００において制御電極１２０、１２２、１２４が多く提供されるほど、電極面は大きくなり、この電極面に沿って電流を導くチャネルが形成され得、ＭＯＳＦＥＴの電流耐性はより大きくなる。
【００５１】
制御電極１２０、１２２、１２４が作製された後、制御電極１２０、１２２、１２４の上および端子電極１４１の下の絶縁材料を含む領域は、制御電極１２０、１２２、１２４が形成された溝を絶縁材料で埋めることによって生じる。
【００５２】
本発明により、制御電極１２０、１２２、１２４と隣接するチャネル領域１１６において、チャネル領域においてｎ型荷電担体およびｐ型荷電担体の再結合を促す再結合領域１３０、１３２、１３４が提供される。再結合領域１３０、１３２、１３４は、好適には、プラチナ等の金属、またはシリサイドを含む。好適には、再結合領域１３０、１３２、１３４と制御電極との間の距離は小さく、好適には、５μｍよりも小さい。
【００５３】
図３は、半導体１００の周縁領域を示し、この周辺領域において本発明による半導体回路素子が形成される。図３から明らかなように、チャネル領域１１６は横方向では半導体１００の端部に達しない。さらに、第２の端子電極１４１は、半導体１００の横方向で、最も近くに位置する制御電極１２６の端部の上にまで伸びるだけである。第２の接合領域１１０は、最も外側の制御電極１２６の上に位置する絶縁領域１２７の端部から離れた部分にまで達するだけである。従って、最も外側の制御電極１２６の、端部に向く側面においては、第１の接合領域１１２と第２の接合領域１１０との間に導電性チャネルが形成され得ない。第１の遷移領域１１４と第２の遷移領域１１８は周縁領域において互いに接続される。
【００５４】
本発明による半導体回路素子において、第１の端子電極（ドレイン電極）１４０、Ｄと第２の端子電極（ソース電極）１４１、Ｓとの間に正電圧が印加された場合、ドレイン領域１１２、１１４とチャネル領域との間の空間電荷領域において荷電担体、すなわち電子およびホールが生成される。この場合、電子は空間電荷領域における電場に基づいてドレイン領域１１２、１１４またはドレインン電極１４０に流れ、ホールはチャネル領域１１６に流れる。チャネル領域において、好適には、金属を含む再結合領域１３０、１３２、１３４、１３６はチャネル領域に注入されたホールの電子との結合を促す。このようにして、ｎ型導電性ドレイン領域１１２、１１４、ｐ型導電性チャネル領域１１６およびｎ型導電性ソース領域１１８、１１０の連続により形成された寄生バイポーラトランジスタが活性化されて、ＭＯＳＦＥＴのドレインソース方向の障壁電圧が低減されることが回避される。
【００５５】
ドレインソース電圧と並んで、正の制御電位が制御電極１２０、１２２、１２４、１２６に印加された場合、制御電極１２０、１２２、１２４、１２６に沿って導電性チャネルが形成され、ドレイン領域１１２、１１４とソース領域１１０、１１８との間において荷電担体の交換を可能にする。
【００５６】
ドレインソース方向のＭＯＳＦＥＴの耐電圧は、第２の遷移領域１１４のドーピングおよび第２の遷移領域１１４の「厚さ」、すなわち強くドーピングされた第２の接合領域１１２とチャネル領域１１６との間の距離によって最終的に（ｍａｓｓｇｅｂｌｉｃｈ）決定される。
【００５７】
ソースドレイン方向で正電圧を印加した場合、第２の遷移領域１１８とチャネル領域１１６との間の空間電荷領域において荷電担体が生成され、ホールはチャネル領域１１６に注入され、ホールはここで再結合領域１３０、１３２、１３４、１３６において電子と再結合され、その結果、寄生バイポーラトランジスタが活性化されることが避けられる。ソースドレイン方向の素子の耐電圧は、第１の遷移領域１１８のドーピング、および強くドーピングされた第１の接合領域１１０とチャネル領域１１６との間の距離によって最終的に決定される。
【００５８】
本発明による素子（Ｂａｕｅｌｅｍｅｎｔ）は、両方向、すなわちドレインソース方向およびソースドレイン方向で遮断する。好適には、第１の遷移領域１１４、１１８は同様にドーピングされ、同一の層厚を有し、ドレインソース方向およびソースドレイン方向に同一の障壁電圧が達成される。ソース領域として強くｎ型ドーピングされた領域のみを取扱い、ドレインソース方向の障壁電圧がソースドレイン方向よりも大きい図１〜図８による半導体素子とは逆に、図１１〜図１３による回路構成の場合、従って、ドレインソース方向およびソースドレイン方向で同じ障壁電圧が達成され得る。
【００５９】
素子をシリコン技術で作製する場合、およびチャネル領域の厚さａが０．５μｍ〜１μｍ、および第１の遷移領域１１４、１１８の厚さｂが約５μｍで作製する場合、これらの領域１４、１８が弱くドーピングされると約５０Ｖの障壁電圧が達成され得る。
【００６０】
制御電極からの再結合領域の距離ｘは、好適には、１μｍより小さい。
【００６１】
図１４において、本発明による半導体回路素子を作製する方法が具体的に示される。第１の方法（図１４ａ）において、強くｎ型ドーピングされた第２の接合領域１１２、および第２の接合領域に隣接して配置されたより弱くｎ型ドーピングされた第２の遷移領域１１４を有する半導体１００が作製される。半導体１００において、第２の遷移領域１１４に隣接するｐ型ドーピングされたチャネル領域１１６が形成され、ｎ型ドーピングされた第１の遷移領域１１８に接合される。第１の遷移領域１１８は、第１の遷移領域１１８に隣接して配置される強くｎ型ドーピングされた第１の接合領域１１０よりも弱くドーピングされる。
【００６２】
次の方法工程（図１４ｂ）において、第１の溝１６０、１６２、１６４が生成され、これらは半導体１００の表側１７０から始まって第２の遷移領域１１４にまで延びる。あるいは、溝は半導体１００の裏側１７２から始まって第１の遷移領域１１８にまで延びるように生成され得る。さらに、第１の溝１６０、１６２、１６４に隣接する第２の溝１６１、１６３、１６５が生成され、これらは表側から始まってチャネル領域１１６にまで延びる。あるいは、第２の溝は裏側１７２から始まってチャネル領域１１６にまで延び得る。
【００６３】
次の方法工程（図１４ｃ）において、後の電極１２０、１２２、１２４を半導体１００から絶縁するために絶縁材料を含む層１２１ａ、１２３ａ、１２５ａは第１の溝１６０、１６２、１６４の側面に作製される。
【００６４】
次の方法工程において、制御電極１２０、１２４、１２６を作製するために、電極材料を含む層が第１の溝１６０、１６２、１６４に堆積される。この層は半導体１００の垂直方向の高さに第１の遷移領域１１８にまで及ぶ。さらに、第２の溝１６１、１６３、１６５において、再結合材料を含む層が堆積される。この層は半導体１００の垂直方向の高さに第２の遷移領域１１８との境界の下にまで延びるので、これによって生じる再結合領域１３０、１３２、１１４はチャネル領域１１６によってのみ包囲される。
【００６５】
次の方法工程において、端子電極１４０、１４１、が半導体の表側１７０および裏側１７２に付与される前に、第１の溝および第２の溝は絶縁材料を用いて埋められ、図１１による配置になる。
【図面の簡単な説明】
【図１】 図１は、従来技術によるＭＯＳＦＥＴの横断面図（図１ａ）、およびこのＭＯＳＦＥＴの代替回路図（図１ｂ）、代替回路図（図１ｃ）およびソース領域と主体領域との間に短絡がないＭＯＳＦＥＴの特性曲線（図１ｄ）を示す。
【図２】 図２は、第１の実施形態に従った、本発明による半導体回路素子の横断面の１部である。
【図３】 図３は、図２の半導体回路素子の線ａ−ａ’に沿う横断面を示す。
【図４】 図４は、図２および図３の半導体回路素子の線ｂ−ｂ’に沿う横断面を示す。
【図５】 図５は、第２の実施形態に従った、本発明による半導体回路素子の横断面の１部である。
【図６】 図６は、図５の半導体回路素子の代替回路図である。
【図７】 図７は、第３の実施形態に従った、本発明による半導体回路素子の横断面の１部である。
【図８】 図８は、図７の半導体回路素子の線ｃ−ｃ’に沿う横断面を示す。
【図９】 図９は、第４の実施形態に従った、本発明による半導体回路素子の横断面の１部である。
【図１０】 図１０は、本発明による半導体回路素子の水平方向の形成を示す。
【図１１】 図１１は、さらなる実施形態に従った、本発明による半導体回路素子の横断面の側面図である。
【図１２】 図１２は、図１１の半導体回路素子の切断面Ａ−Ａ’に沿う横断面の横断面図である。
【図１３】 図１３は、図１１および図１２の、半導体回路素子の周辺領域の横断面を示す側面図である。
【図１４】 図１４は、作製方法の種々の方法工程の中の、図１１および図１２の半導体回路素子の横断面を示す。
【符号の説明】
（参照符号一覧）
１０ 半導体
１００ 半導体
１０５ 半導体
１１０ 第２の接合領域
１１２ 第１の接合領域
１１４ 第１の移行領域
１１６ チャネル領域
１１８ 第２の遷移領域
１２ 第１の導電領域
１２０、１２２、１２４、１２６ 制御電極
１２１、１２３、１２５、１２７ 絶縁層
１２６ 共有プレート
１２７ 絶縁層
１２０、１３２、１３４、１３６ 再結合領域
１４、１６ 第２の導電領域
１４０ 第１の結合電極
１４１ 第２の結合電極
１６０、１６２、１６４ 第１の溝
１６１、１６３、１６５ 第２の溝
１７０ 半導体の表側
１７２ 半導体の裏側
１８ 遮断領域
１８１ 強くｎ型ドーピングされた架橋領域
１９ 再結合領域
２００ 半導体
２１６ 第２の導電領域
２１８ 遮断領域
２１９ 再結合領域
２３０ 絶縁領域
３０ 絶縁領域
４０ ソース電極
５２ 第１の導電領域
５４、５６ 第２の導電領域
５８ 遮断領域
５９、５９’ 再結合領域
７０ 絶縁層
８０ ソース電極
９０ 絶縁層
Ｂ ベース
Ｂ１ バイポーラトランジスタ
Ｃ コレクタ
Ｄ ドレイン端子
Ｄ２ ダイオード
ＤＣＢ、ＤＳ ダイオード
Ｅ エミッタ
Ｇ ゲート端子、ゲート電極
Ｓ ソース端子、ソース電極
Ｔ１ ＭＯＳＦＥＴ[0001]
The present invention relates to a controllable semiconductor device, and more particularly to a semiconductor circuit device controllable by a field effect. This semiconductor element has the following characteristics.
[0002]
A first conductive region, and a second conductive region of a first conductivity type,
A channel region of a second conductivity type disposed between the first conductive region and the second conductive region;
A control electrode that is insulated and positioned to face the channel region.
[0003]
Such a semiconductor circuit element is, for example, a MOSFET (metal oxide field effect transistor) known from the prior art. Embodiments of prior art vertical power MOSFETs (Verticales Leistungs-MOSFET) are described in Stengl / Tihanyi's “Leistungs-MOSFET-Praxis” Pflaum Verlag, Muenchen, 1992, pp. 29 et seq. Indicated. The MOSFET has a source region as the conductive region 12 of the first conductivity type (n), which is a well-shaped channel region (body (Body) region or blocking region) of the second conductivity type (p). Embedded in). The source region 12 can be contacted from the outside through the source electrode 40, and the source electrode 40 reaches the channel region through the source region 12, and thus short-circuits the source region 12 and the channel region 18. (Kurzschliest).
[0004]
The channel region 18 is embedded in the second conductive regions 14 and 16 (MOSFET drain region) of the first conductivity type (n), and the second conductive region surrounds the n-type doped channel region 18. It has a region 14 and a strongly n-type doped region 16 for joining the drain electrode. A channel region 18 and a gate electrode that is insulated and faces the source region 12 and the drain region 14 are disposed on the semiconductor as the control electrode 20 of the MOSFET. A region is formed.
[0005]
An alternative circuit diagram of the vertical MOSFET according to FIG. 1a is shown in FIG. 1b. This figure is shown as a combination of an ideal MOSFET T1 and a diode Di, with the diode in the flow direction between the source terminal S and the drain terminal D of the MOSFET.
Connected. A diode that conducts when a positive voltage is applied in the source-drain direction results from a pn transition between the drain regions 14, 16 and the body region 18 and a short circuit between the body region 18 and the source region 12.
[0006]
The presence of integrated diodes is disadvantageous in some cases using MOSFETs. This is because the diode conducts only when a flow voltage (Flasspanning) is applied in the drain-source direction, and acts so that the MOSFET conducts like a diode when a voltage is applied in the source-drain direction. .
[0007]
If there is no short circuit between the source region and the body region, the parasitic bipolar transistor operates in the MOSFET. The transistor comprises a series of differently doped regions, ie, a source region of a first conductivity type, a channel region of a second conductivity type complementary to the first conductivity type, and a first conductivity type The transistor base is formed by a channel region, and the emitter / collector of the transistor is formed by a source region / drain region.
[0008]
FIG. 1c shows an electrical alternative circuit diagram of a MOSFET without a short circuit between the source and drain regions. This figure is expressed as a combination of an ideal MOSFET T1 and a bipolar transistor. The collector-emitter line CE of the bipolar transistor B1 is connected in parallel with the drain-source line DS of the MOSFET T1. The base region of the parasitic bipolar transistor B1 is formed by the channel region of the MOSFET, the emitter region is formed by the source region of the MOSFET, and the collector region is formed by the drain region of the MOSFET.
[0009]
In FIG. 1d, the parasitic bipolar transistor B1 affects the withstand voltage of the semiconductor circuit element according to FIG. 1c, as indicated by the characteristic curve of this semiconductor circuit element. Value U CE0 Drain-source voltage U DS In this case, the collector-emitter breakdown voltage of the parasitic bipolar transistor B1, and thus the maximum barrier voltage in the drain-source direction DS of the semiconductor circuit element is reached. As can be understood from the characteristic curve, the withstand voltage slightly increases as the gate-source voltage increases. Until this breakdown voltage is reached, the response of the semiconductor element corresponds to the response of the ideal MOSFET.
[0010]
When the withstand voltage is reduced in a MOSFET having a source region and a cutoff region that are not short-circuited, during operation, i.e., when a control potential is applied to the gate terminal, and when a flow voltage is applied between the drain and source, Charge carriers gather. This charge carrier controls the base of the parasitic bipolar transistor, thereby making it conductive. The withstand voltage in the drain source direction of such a MOSFET is only about 1/3 that of a similar device having a shorted source region and body region.
[0011]
It is an object of the present invention to make available a controllable semiconductor circuit element that blocks in both directions without reducing the barrier voltage in the main voltage direction (forward direction).
[0012]
This problem is solved by the semiconductor circuit element described at the beginning. The semiconductor circuit element further has at least one recombination formed in the blocking region that includes a material that facilitates recombination of charge carriers of the first and second conductivity types formed in the blocking region. In the case of a semiconductor circuit element according to the invention, no short circuit is provided between the channel region and one of the two conductive regions.
[0013]
A semiconductor according to the invention is formed by a sequence of a first conductive region of a first conductivity type, a channel region of a second conductivity type and a second conductive region of a second conductivity type arranged adjacent to each other A parasitic bipolar transistor is formed in the circuit element. However, providing a recombination region in the channel region of the semiconductor circuit element and in the base region of the parasitic bipolar transistor changes the electrical response of the parasitic bipolar transistor. When a flow voltage is applied between the first conductive region and the second conductive region, in the space charge region between one of the two conductive regions and the channel region, the first conductivity type And charge carriers of the second conductivity type, ie holes and electrons, are generated. The charge carrier of the first conductivity type may slightly recombine with the charge carrier of the second conductivity type at the boundary of the recombination region or at the surface of this region. With the recombination region, the parasitic bipolar transistor is achieved with very little control, and when there is a sufficiently large recombination region, the parasitic bipolar transistor is no longer active.
[0014]
The withstand voltage of the semiconductor circuit element according to the present invention is in a specific direction (forward direction), and therefore the withstand voltage of such a conventional semiconductor circuit element having a short circuit between one of the conductive regions and the channel region. Equivalent to. At the same time, the semiconductor circuit element according to the present invention also shuts off when a flow voltage is applied in another direction (reverse direction). This is because there is no short circuit between the conductive region and the channel region.
[0015]
Advantageous embodiments of the invention emerge from the dependent claims.
[0016]
The material of the recombination zone is preferably a metal. Further embodiments may provide a recombination region comprising polysilicon or other semiconductor material or a recombination region comprising silicon or other corresponding semiconductor bond.
[0017]
According to one embodiment, the recombination zone is shaped like a plate, making the largest possible surface available in a small volume to recombine charge carriers. The semiconductor circuit element according to the present invention is preferably configured in the form of a cell, that is, a plurality of cells that are similarly configured and similarly controlled, and each of these cells includes a first conductive region and a channel region. And a second conductive region. In this case, each cell has a recombination region.
[0018]
In the channel region, preferably the channel region of each cell, a plurality of recombination regions, in particular in the form of plates or strips, can be formed at a distance from one another. In this case, preferably, the individual recombination regions are connected to each other by a strongly doped region of the second conductivity type, and between the recombination regions or between the various recombination region parts arranged apart from each other. Allows a slight exchange of charge carriers.
[0019]
Along with the embodiment in which the recombination region is completely surrounded by the channel region, i.e. the region comprising the second conductivity type material, according to a further embodiment of the present invention, it comprises the first conductivity type material. A region provides for connecting the recombination region with the first conductive region. In the case of a MOSFET, when a metal or silicide is used as a material for a recombination region between a blocking region, also called a body region, and a first conductive region, a Schottky contact that determines a withstand voltage in the reverse direction of the element is generated. .
[0020]
According to a further embodiment of the invention, the first conductive region comprises a more heavily doped connection region for connecting the first connection electrode and a weakly doped transition region between the junction region and the channel region. And the second conductive region is a weakly doped second junction region for bonding the second electrode, and a weakly doped region disposed between the second junction region and the channel region. Having two transition regions. The withstand voltage of the semiconductor circuit element according to the invention is basically determined by doping the transition region and by the distance of the junction region from the channel region determined by the transition region. In this embodiment, each conductive region has a weakly doped transition region, and approximately the same breakdown voltage in the forward and reverse directions of the semiconductor circuit element can be adjusted by the thickness and doping of the transition region.
[0021]
The invention will now be described in detail in the examples using the figures.
[0022]
In the figures, the same reference signs refer to the same parts and regions having the same meaning unless otherwise stated.
[0023]
FIG. 2 shows a part of a cross section of a semiconductor circuit element according to the invention according to a first embodiment. The illustrated semiconductor circuit element has a configuration of a vertical n-type conductive MOS transistor, particularly an n-type conductive MOSFET. In the n-type conductive semiconductor 10, a p-type conductive region that is also called a body region or a blocking region is formed as a channel region 18. This p-type region is again filled with a heavily doped n-type conductive region 12, which is used as the first conductive region or source region of the MOSFET. The semiconductor 10 has an n-type conductive region 14 and a heavily doped n-type conductive region 16 in the region facing away from the source region, both of which are second conductive regions or A drain region is formed. The heavily doped region 16 is used for bonding to the drain electrode D.
[0024]
The source region 12 is connected to source electrodes 40 and S containing, for example, aluminum, and the source electrode 40 contacts the source region on the surface of the semiconductor 10. At least one gate electrode 20 is used as a control electrode of the MOSFET and is arranged through the blocking region 12 and separated from the blocking region by the insulating layer 30. The gate electrode 20 includes, for example, polysilicon, and the insulating layer 30 includes, for example, silicon oxide. The illustrated structure is preferably repeated many times in the right and left and in the direction perpendicular to the drawing, resulting in a cellular structure of semiconductor circuit elements. The current tolerance of semiconductor circuit elements increases with the number of cells.
[0025]
The illustrated MOSFET has a parasitic bipolar transformer system, where the emitter region of the transistor is formed by the source region 12, the base region of the transistor is formed by the channel region 18, and the collector region of the transistor is the drain region 14 of the vertical MOSFET. 16.
[0026]
In the channel region 18 of the MOSFET, or in the base region of the parasitic bipolar transistor, a recombination region 19 containing a material that promotes recombination of n-type and p-type charge carriers is disposed in this region. The recombination region preferably includes metal, polysilicon, or silicide, and is formed in a plate shape, for example.
[0027]
In the semiconductor circuit device according to the present invention, when a positive voltage is applied between the drain electrode (not shown in detail) applied to the drain regions 14, 16 and 16 and the source region 12 or the source electrode 40, the drain region 14 Charge carriers, ie electrons and holes, are generated in the space charge region between the channel region 18 and the channel region 18.
[0028]
In this case, holes flow to the drain regions 14 and 16 based on the electric field in the space charge region, and holes flow to the blocking region. Since recombination with electrons of the holes injected at the surface of the recombination region 19 is strengthened, it is avoided that the parasitic bipolar transistor is activated and the barrier voltage in the drain-source direction is reduced. Is done.
[0029]
In other words, the possibility of a good recombination of n-type and p-type charge carriers in the base region of the parasitic bipolar transistor reduces the current amplification factor β of this transistor, so that the withstand voltage of the MOSFET is reduced to the drain source. The collector-emitter breakdown voltage of this transistor, which together determines the withstand voltage of the MOSFET on the line, is increased.
[0030]
Furthermore, the illustrated semiconductor circuit element functions like a MOSFET. That is, when a positive control potential is applied to the gate electrode 20, a conductive channel is formed in the channel region between the source region 12 and the drain region 14. This channel allows a current to flow between the drain terminal D and the source terminal S when a flow voltage is applied between the drain region 16 and the source electrode 14.
[0031]
By appropriately selecting the material and geometric structure of the recombination region 19, the breakdown voltage of the MOSFET can be reduced when a short circuit occurs between the first conductive region (source region) 12 and the channel region 18, that is, If the base-emitter line of the parasitic bipolar transistor is short-circuited, it can be raised until breakdown voltage occurs. However, the disadvantageous effect of such a short-circuit, that is, lack of the withstand voltage in the reverse direction (source-drain direction) is not accepted. Good. In the illustrated MOSFET, even when a positive voltage is applied between the source electrode 40 or the source region 12 and the drain regions 14 and 16, the MOSFET is cut off due to the pn-type transition between the cutoff region 18 and the source region 12.
[0032]
As shown in FIG. 2, region 16 is not strongly n-type doped, but can be strongly p-type doped. Thereafter, the semiconductor circuit element functions as an IGBT (Insulated Gate Bipolar transistor = insulated gate bipolar transistor).
[0033]
The recombination region 19 is preferably formed to have a large plane with a small volume.
[0034]
Thus, the recombination zone is preferably from a plurality of strip-like portions extending essentially in a row, as shown in the form of a plate or in FIG. 3 using a cross-section along line aa ′ of FIG. It is formed. The broken line in FIG. 3 specifically shows the position of the gate electrode 20 existing on these portions. The dotted line specifically indicates the position of the source electrodes 40 and S existing thereon.
[0035]
FIG. 4 shows a cross section of the semiconductor circuit element along the intersection line cc ′ entered in FIG. 3, and the state in which the bands forming the recombination region 19 are arranged in parallel becomes clear from this cross section. . The individual lower regions of the recombination region 19 are preferably connected to each other by a strongly p-type doped region 181 to facilitate charge exchange 19 between the lower regions of the recombination region 19.
[0036]
FIG. 5 shows a further embodiment of a semiconductor circuit element according to the invention. In this embodiment, the recombination region 19 and the strongly n-type doped source region 12 are connected to each other by an n-type conductive region 13. In this embodiment, the material of the recombination region 19 is preferably metal or silicide.
[0037]
FIG. 6 shows an alternative circuit diagram of the semiconductor circuit element according to FIG. A Schottky transition is formed between the n-type conductive region 13 which is a part of the source region and the recombination region 19, and this transition is caused by the Schottky diode D. s Is written between the source terminal S and the substrate terminal of the MOSFET. The diode D2 between the drain terminal D and the substrate terminal is formed by a pn-type transition between the drain regions 14 and 16 and the blocking region 18 (also called p-type body region). Schottky diode D s Determines the barrier voltage in the reverse direction (source drain direction) of the semiconductor circuit element, and the diode D2 or pn type transition between the drain regions 14, 16 and the blocking region 18 is the forward direction of the MOSFET (drain source direction). Determine the withstand voltage.
[0038]
FIG. 7 shows a part of a cross section of a semiconductor circuit element according to a further embodiment of the invention. FIG. 8 shows a cross section of the semiconductor circuit element along the intersection line cc ′ entered in FIG. 7. In this embodiment, the gate electrode 60 is “embedded” in the semiconductor 101 and is surrounded by an insulating layer 70. The source electrode 80 stops the semiconductor 101 above. The first strongly n-type doped conductive region (source region) 52 is disposed under the source electrode 80 and between the trench structure of the gate electrode 60. A p-type doped blocking region 58 is joined to the source region 52, and a recombination region 59 including an n-type charge carrier and a material supporting the p-type charge carrier is disposed in the blocking region. The gate electrode 60 and the insulating layer 70 surrounding it extend down to the n-type doped region 54, which n-type doped region 56 defines the second conductive region (drain region) of the illustrated MOSFET. Form.
[0039]
Alongside the embodiment of recombination region 19 that is completely surrounded by p-type conductive channel region 58, FIG. 7 shows recombination region 59 ′ that is insulated from source electrodes 80, S and source region 52 by insulating layer 90. Examples of This is the result of a possible fabrication method of the recombination region 59 ′ in the blocking region. In this case, before deposition of the source electrode 80, holes are provided in the blocking region 58, for example by etching, and then filled with a material that promotes recombination to a height below the source region 52. Next, an insulating layer 90 is applied in the holes located over the material that promotes recombination.
[0040]
As is apparent from the plan view of FIG. 8 in particular, the semiconductor circuit element of the present invention according to FIG. 7 has a grid-like gate electrode 60, and a channel region insulated from the gate electrode 60 by the insulating layer 70 in the gap of the grid. 58 is arranged with the recombination region 59. Thus, the semiconductor circuit element has a plurality of similarly configured cells that are controlled simultaneously. The current tolerance of the semiconductor circuit element according to the present invention improves as the number of cells increases. When a positive control potential is applied to the gate electrode 60, a conductive channel is formed along the gate electrode 60 in the vertical direction of the semiconductor 105. At this time, when a flow voltage is applied between the drain electrode D and the source electrode S, a current can flow between the drain electrode D and the source electrode S.
[0041]
FIG. 9 shows a portion of a cross section of a further embodiment of a semiconductor circuit element of the present invention having a groove-like structure including a gate electrode 60 and an insulating layer 70. In this embodiment, the source region is a normal n-type surrounding a heavily n-doped region 52 disposed adjacent to the gate electrode 60 and the source electrode 80 and a heavily doped region 52 in the remaining regions. A doped region 53 is included. In this embodiment, the recombination region 59 extends from the p-type doped blocking region 58 disposed below the region 53 to the n-type doped region 53 and is insulated from the source electrode 80 by the insulating layer 90 above. Is done. In this embodiment, the recombination region 59 preferably comprises a metal or silicide and forms a Schottky contact with the n-type doped region 53. An alternative circuit diagram of the semiconductor circuit element according to FIG. 9 corresponds to FIG.
[0042]
2 to 6, when a positive voltage is applied between the gate electrode G and the source electrode S and a positive voltage is applied between the drain electrode D and the source electrode S. A horizontal conductive channel is formed in the blocking region 18, while in the embodiment according to FIGS. 7 and 8, a vertical conductive channel is formed. This embodiment is more space-saving than the embodiment shown in FIGS.
[0043]
When the strongly n-type doped region 56 is replaced with a strongly P-type doped region, the device shown in FIGS. 7-9 functions as an IGBT.
[0044]
FIG. 10 shows a further embodiment of a semiconductor circuit element according to the invention, which is formed as a horizontally structured MOSFET. A strongly n-type doped drain region 216 and an n-type doped source region 212 are disposed within the p-type doped blocking region 218 of the semiconductor 200 and are on the same side of the semiconductor 200 using the source electrode S and the drain electrode G. Can be contacted. The gate electrode G is insulated by the insulating layer 230 and is disposed on the semiconductor 200. A recombination region including a material that promotes recombination of the n-type and p-type charge carriers is disposed in the blocking region 218.
[0045]
FIG. 11 shows a further embodiment of a semiconductor circuit element blocking in both directions according to the invention in a cross-sectional side view. In FIG. 12, a cross section along the cutting plane AA ′ of the configuration of FIG. 11 is shown.
[0046]
The semiconductor circuit element according to the present invention has a second n-doped region 112 that is heavily n-doped and a second n-type doped weaker than the second junction region 112 that is disposed adjacent to the second junction region 112. A semiconductor 100 having a second transition region 114 is included. At this time, the second junction region 112 and the second transition region 114 form a second conductive region (drain region) of the semiconductor circuit element. This region where the p-type doped channel region 116 is formed adjacent to the second transition region 114 need not necessarily be uniformly doped. This channel region is joined to the n-type doped first transition region 118. Adjacent to the first transition 118 is a first junction region 110 that is more strongly n-type doped than the first transition region 118, and the first junction region 110 and the first transition region 118 are made of semiconductors. A first conductive region (source region) of the circuit element is formed. The second junction region 112, the second transition region 114, the channel region 116, the first transition region 118, and the first junction region 110 are arranged in a layered manner in the embodiment. The second terminal electrode 140 preferably includes metal or polysilicon and is applied to the back side of the semiconductor 100 so as to contact the second bonding region 112, and the first terminal electrode 141 is preferably It includes metal or polysilicon and is applied to the front side of the semiconductor so as to be in contact with the second bonding region 112.
[0047]
When a positive control potential is applied to the gate electrode, in this semiconductor circuit element, a conductive channel is formed between the source region 212 and the drain region 216 along the surface of the semiconductor. The n-type and p-type charge carriers can also recombine with each other in the recombination region 219 in this embodiment, so that the n-type conductive source region 212, the p-type conductive channel region 218, and the n-type conductive carrier Control of the parasitic bipolar transistor formed by the continuation of the drain region 216 is avoided.
[0048]
The second junction region 112 and the second transition region 114 joined to this junction region form the drain region of the MOSFET. The first junction region 110 and the first transition region 118 joined to this junction region form the source region of the MOSFET. In this case, since the FET shown in FIG. 11 has a symmetrical configuration, the drain terminal and the source terminal can be exchanged.
[0049]
Control electrodes 120, 122, 124, 126 are provided to allow the formation of conductive channels in the channel region between the drain regions 112, 114 and the source regions 110, 118. This electrode is surrounded by insulating layers 121, 123, 125, 127 and passes from the n-type doped first transition region 114 through the p-type doped channel region 116 to the n-type doped second transition region. 118 extends in the vertical direction of the semiconductor 100. As is apparent from FIG. 2, in an embodiment, generally parallel control electrodes 120, 122, 124 connected by a common plate 126 are provided. As a result, the control electrodes 120, 122, 124 can be placed at a common control potential. The common plate is insulated from the semiconductor 100 by the insulating layer 127, extends in the vertical direction, preferably to the front side or back side of the semiconductor 100, and is bonded to the control potential. Preferably, the first junction region 110 and / or the second junction region 112 do not extend to the common plate 126 to avoid the formation of channels that conduct current along the common plate 126. Of course, any further embodiment can be envisaged alongside the common plate 126 to place the control electrodes 120, 122, 124 at a common control potential.
[0050]
The more control electrodes 120, 122, 124 are provided in the semiconductor 100, the larger the electrode surface becomes, and a channel for conducting current can be formed along this electrode surface, so that the current resistance of the MOSFET becomes larger.
[0051]
After the control electrodes 120, 122, 124 are fabricated, the region including the insulating material above the control electrodes 120, 122, 124 and under the terminal electrode 141 insulates the groove where the control electrodes 120, 122, 124 are formed. Caused by filling with material.
[0052]
The present invention provides recombination regions 130, 132, 134 that facilitate recombination of n-type and p-type charge carriers in the channel region 116 in the channel region 116 adjacent to the control electrodes 120, 122, 124. Recombination regions 130, 132, 134 preferably include a metal such as platinum or silicide. Preferably, the distance between the recombination regions 130, 132, 134 and the control electrode is small, preferably less than 5 μm.
[0053]
FIG. 3 shows a peripheral region of the semiconductor 100, in which the semiconductor circuit element according to the present invention is formed. As apparent from FIG. 3, the channel region 116 does not reach the end of the semiconductor 100 in the lateral direction. Furthermore, the second terminal electrode 141 only extends over the end of the nearest control electrode 126 in the lateral direction of the semiconductor 100. The second junction region 110 only reaches a portion away from the end of the insulating region 127 located on the outermost control electrode 126. Therefore, a conductive channel cannot be formed between the first junction region 112 and the second junction region 110 on the side surface of the outermost control electrode 126 facing the end. The first transition region 114 and the second transition region 118 are connected to each other in the peripheral region.
[0054]
In the semiconductor circuit element according to the present invention, when a positive voltage is applied between the first terminal electrodes (drain electrodes) 140, D and the second terminal electrodes (source electrodes) 141, S, the drain regions 112, 114 Charge carriers, ie electrons and holes, are generated in the space charge region between the channel region and the channel region. In this case, electrons flow to the drain regions 112 and 114 or the drain electrode 140 based on the electric field in the space charge region, and holes flow to the channel region 116. In the channel region, preferably, the recombination regions 130, 132, 134, 136 containing metal facilitate the coupling of electrons injected into the channel region with electrons. In this manner, the parasitic bipolar transistor formed by the continuation of the n-type conductive drain regions 112 and 114, the p-type conductive channel region 116, and the n-type conductive source regions 118 and 110 is activated, and the drain of the MOSFET is activated. It is avoided that the barrier voltage in the source direction is reduced.
[0055]
Along with the drain-source voltage, when a positive control potential is applied to the control electrodes 120, 122, 124, 126, conductive channels are formed along the control electrodes 120, 122, 124, 126, and the drain regions 112, Allow charge carrier exchange between 114 and source regions 110, 118.
[0056]
The withstand voltage of the MOSFET in the drain-source direction depends on the doping of the second transition region 114 and the “thickness” of the second transition region 114, ie between the heavily doped second junction region 112 and the channel region 116. It is finally determined by the distance.
[0057]
When a positive voltage is applied in the source / drain direction, charge carriers are generated in the space charge region between the second transition region 118 and the channel region 116, and holes are injected into the channel region 116, where the holes recombine. Recombination with electrons in the regions 130, 132, 134, 136 is avoided, so that the parasitic bipolar transistor is not activated. The breakdown voltage of the device in the source / drain direction is ultimately determined by the doping of the first transition region 118 and the distance between the heavily doped first junction region 110 and the channel region 116.
[0058]
The element according to the present invention blocks in both directions, ie the drain-source direction and the source-drain direction. Preferably, the first transition regions 114, 118 are similarly doped, have the same layer thickness, and achieve the same barrier voltage in the drain source direction and the source drain direction. In the case of the circuit configuration according to FIGS. 11 to 13 as opposed to the semiconductor element according to FIGS. 1 to 8 which deals only with a strongly n-type doped region as the source region and the barrier voltage in the drain-source direction is larger than the source-drain direction. Thus, the same barrier voltage can be achieved in the drain-source direction and the source-drain direction.
[0059]
When the device is manufactured by silicon technology, and when the thickness a of the channel region is 0.5 μm to 1 μm and the thickness b of the first transition regions 114 and 118 is approximately 5 μm, these regions 14 and 18 are formed. A barrier voltage of about 50V can be achieved if is weakly doped.
[0060]
The distance x of the recombination region from the control electrode is preferably less than 1 μm.
[0061]
In FIG. 14, a method for fabricating a semiconductor circuit element according to the present invention is specifically illustrated. In the first method (FIG. 14a), having a strongly n-type doped second junction region 112 and a weaker n-type doped transition region 114 disposed adjacent to the second junction region The semiconductor 100 is manufactured. In the semiconductor 100, a p-type doped channel region 116 adjacent to the second transition region 114 is formed and joined to the n-type doped first transition region 118. The first transition region 118 is doped less than the strongly n-type doped first junction region 110 disposed adjacent to the first transition region 118.
[0062]
In the next method step (FIG. 14 b), first grooves 160, 162, 164 are created, starting from the front side 170 of the semiconductor 100 and extending to the second transition region 114. Alternatively, the trench can be created to start from the back side 172 of the semiconductor 100 and extend to the first transition region 118. In addition, second grooves 161, 163, 165 adjacent to the first grooves 160, 162, 164 are generated and extend from the front side to the channel region 116. Alternatively, the second groove may start from the back side 172 and extend to the channel region 116.
[0063]
In the next method step (FIG. 14 c), layers 121 a, 123 a, 125 a containing an insulating material are formed on the side surfaces of the first grooves 160, 162, 164 in order to insulate the subsequent electrodes 120, 122, 124 from the semiconductor 100. Is done.
[0064]
In the next method step, a layer containing electrode material is deposited in the first grooves 160, 162, 164 to create the control electrodes 120, 124, 126. This layer extends to the first transition region 118 at the vertical height of the semiconductor 100. Further, in the second groove 161, 163, 165, a layer containing a recombination material is deposited. This layer extends to the vertical height of the semiconductor 100 to below the boundary with the second transition region 118, so that the resulting recombination regions 130, 132, 114 are surrounded only by the channel region 116.
[0065]
In the next method step, before the terminal electrodes 140, 141 are applied to the front side 170 and back side 172 of the semiconductor, the first and second grooves are filled with an insulating material, resulting in the arrangement according to FIG. Become.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a MOSFET according to the prior art (FIG. 1a), and an alternative circuit diagram (FIG. 1b), an alternative circuit diagram (FIG. 1c) of the MOSFET, and between a source region and a main region; The characteristic curve (FIG. 1d) of MOSFET without a short circuit is shown.
FIG. 2 is a part of a cross section of a semiconductor circuit element according to the invention, according to a first embodiment.
FIG. 3 shows a cross-section along the line aa ′ of the semiconductor circuit element of FIG.
4 shows a cross section along the line bb ′ of the semiconductor circuit element of FIGS. 2 and 3. FIG.
FIG. 5 is a part of a cross section of a semiconductor circuit element according to the invention, according to a second embodiment.
6 is an alternative circuit diagram of the semiconductor circuit element of FIG. 5. FIG.
FIG. 7 is a part of a cross section of a semiconductor circuit element according to the invention, according to a third embodiment.
FIG. 8 shows a cross-section along the line cc ′ of the semiconductor circuit element of FIG.
FIG. 9 is a part of a cross section of a semiconductor circuit element according to the invention, according to a fourth embodiment.
FIG. 10 shows the horizontal formation of semiconductor circuit elements according to the invention.
FIG. 11 is a cross-sectional side view of a semiconductor circuit element according to the present invention, according to a further embodiment.
12 is a cross-sectional view of a cross section taken along the section line AA ′ of the semiconductor circuit element of FIG. 11. FIG.
13 is a side view showing a cross section of the peripheral region of the semiconductor circuit element in FIGS. 11 and 12. FIG.
FIG. 14 shows a cross section of the semiconductor circuit element of FIGS. 11 and 12 in various method steps of the fabrication method.
[Explanation of symbols]
(List of reference codes)
10 Semiconductor
100 semiconductor
105 Semiconductor
110 Second bonding region
112 1st joining area | region
114 First transition region
116 channel region
118 Second transition region
12 First conductive region
120, 122, 124, 126 Control electrode
121, 123, 125, 127 Insulating layer
126 Shared plate
127 Insulating layer
120, 132, 134, 136 Recombination zone
14, 16 Second conductive region
140 First coupling electrode
141 Second coupling electrode
160, 162, 164 first groove
161, 163, 165 Second groove
170 Front side of semiconductor
172 The back side of the semiconductor
18 Blocking area
181 Strongly n-doped cross-linked region
19 Recombination zone
200 Semiconductor
216 second conductive region
218 Blocking area
219 Recombination zone
230 Insulation area
30 Insulation area
40 source electrode
52 First conductive region
54, 56 Second conductive region
58 Blocking area
59, 59 'recombination zone
70 Insulating layer
80 Source electrode
90 Insulating layer
B base
B1 Bipolar transistor
C collector
D Drain terminal
D2 diode
D CB , D S diode
E Emitter
G Gate terminal, gate electrode
S source terminal, source electrode
T1 MOSFET

Claims (15)

制御可能な半導体回路素子であって、
第１の導電型の第１の導電領域および第２の導電領域と、
該第１の導電領域と該第２の導電領域との間に配置された第２の導電型のチャネル領域と、
該チャネル領域に対して絶縁されて配置される制御電極と、
該チャネル領域において形成された少なくとも１つの再結合領域であって、該少なくとも１つの再結合領域は、該第１の導電型および該第２の導電型の荷電担体の再結合を促す材料を含み、該再結合領域の材料は、金属およびシリサイドからなる群から選択される材料である、少なくとも１つの再結合領域と
を含み、
該第２の導電領域は、端子電極に接続するためのより強度にドーピングされた第２の接合領域と、該チャネル領域に隣接する、より弱くドーピングされた第２の遷移領域とを有し、
該第１の導電領域は、端子電極に接続するためのより強度にドーピングされた第１の接合領域と、該チャネル領域に隣接する、より弱くドーピングされた第１の遷移領域とを有し、
該第１の導電領域は、該第１の遷移領域と該再結合領域との間の界面においてショットキー接合が存在するように該チャネル領域内に形成されており、
該チャネル領域は、該チャネル領域と該第２の遷移領域との間の界面においてｐｎ接合が存在するように該第２の遷移領域内に形成されている、半導体回路素子。A controllable semiconductor circuit element comprising:
A first conductive region and a second conductive region of a first conductivity type;
A channel region of a second conductivity type disposed between the first conductive region and the second conductive region;
A control electrode disposed insulated from the channel region;
At least one recombination region formed in the channel region, the at least one recombination region comprising a material that facilitates recombination of the charge carriers of the first conductivity type and the second conductivity type. The recombination region material comprises at least one recombination region that is a material selected from the group consisting of metals and silicides;
The second conductive region has a more heavily doped second junction region for connection to the terminal electrode and a weakly doped second transition region adjacent to the channel region;
The first conductive region has a more heavily doped first junction region for connection to a terminal electrode and a weakly doped first transition region adjacent to the channel region;
The first conductive region is formed in the channel region such that a Schottky junction is present at an interface between the first transition region and the recombination region;
The semiconductor circuit element, wherein the channel region is formed in the second transition region such that a pn junction exists at an interface between the channel region and the second transition region. 前記再結合領域は、プレート状に形成されている、請求項１に記載の半導体回路素子。  The semiconductor circuit element according to claim 1, wherein the recombination region is formed in a plate shape. 前記再結合領域は、帯状に形成されており、互いに平行に配置されている、請求項１に記載の半導体回路素子。The semiconductor circuit element according to claim 1 , wherein the recombination regions are formed in a band shape and are arranged in parallel to each other. 前記再結合領域は、前記チャネル領域によって完全に包囲されている、請求項１〜３のいずれか一項に記載の半導体回路素子。  The semiconductor circuit element according to claim 1, wherein the recombination region is completely surrounded by the channel region. 前記第１の導電領域と前記チャネル領域と前記第２の導電領域とは、層状に重ねられて配置されている、請求項１〜４のいずれか一項に記載の半導体回路素子。  5. The semiconductor circuit element according to claim 1, wherein the first conductive region, the channel region, and the second conductive region are arranged so as to overlap each other in layers. 前記第１の導電領域および前記第２の導電領域の第１の遷移領域および第２の遷移領域は、同じ層の厚さを有する、請求項５に記載の半導体回路素子。  The semiconductor circuit element according to claim 5, wherein the first transition region and the second transition region of the first conductive region and the second conductive region have the same layer thickness. 前記第１の遷移領域および前記第２の遷移領域は、少なくとも同じドーピング濃度を有する、請求項１〜６のいずれか一項に記載の半導体回路素子。  The semiconductor circuit element according to claim 1, wherein the first transition region and the second transition region have at least the same doping concentration. 前記少なくとも１つの再結合領域から前記少なくとも１つの制御電極への距離は、１μｍよりも小さい、請求項１に記載の半導体回路素子。  The semiconductor circuit element according to claim 1, wherein a distance from the at least one recombination region to the at least one control electrode is less than 1 μm. 半導体回路素子を作製する方法であって、
該方法は、
半導体を提供する工程であって、該半導体は、第１の導電型の第２の接合領域と、該第２の接合領域に隣接して配置され、該第２の接合領域よりも弱くドーピングされた、該第１の導電型の第２の遷移領域と、該第２の遷移領域に隣接して配置された、第２の導電型のチャネル領域と、該チャネル領域に隣接して配置された、該第１の導電型の第１の遷移領域と、該第１の遷移領域に隣接して配置され、該第１の遷移領域よりも強くドーピングされた、該第１の導電型の第１の接合領域とを有し、該チャネル領域は、該チャネル領域と該第２の遷移領域との間の界面においてｐｎ接合が存在するように該第２の遷移領域内に設けられ、該第１の接合領域は、該第１の遷移領域内に設けられ、該第１の遷移領域は、該チャネル領域内に設けられる、工程と、
絶縁層によって包囲された少なくとも１つの制御電極を作製する工程であって、該制御電極は、該第１の遷移領域から、該チャネル領域を通って、該第２の遷移領域にまで少なくとも延びる、工程と、
該チャネル領域に再結合層を堆積することにより、少なくとも１つの再結合領域を作製する工程であって、該少なくとも１つの再結合領域は、該第１の遷移領域と該再結合領域との間の界面においてショットキー接合が存在するように作製され、該再結合層は、該第１の導電型および該第２の導電型の荷電担体の再結合を促す材料から形成されており、該再結合領域の材料は、金属およびシリサイドからなる群から選択される材料である、工程と
を包含し、
該少なくとも１つの再結合領域を作製する工程は、
該半導体の一方の側から始まって、該チャネル領域にまで延びる少なくとも１つの第２の溝を生成する工程と、
該チャネル領域における該第２の溝に第１の導電型および第２の導電型の荷電担体の再結合を促す材料を堆積させる工程と、
該第２の溝を絶縁材料で埋める工程と
を包含する、方法。A method for producing a semiconductor circuit element, comprising:
The method
Providing a semiconductor, wherein the semiconductor is disposed adjacent to the second junction region of the first conductivity type, and adjacent to the second junction region, and is weakly doped than the second junction region. In addition, the second transition region of the first conductivity type, the channel region of the second conductivity type disposed adjacent to the second transition region, and disposed adjacent to the channel region A first transition region of the first conductivity type and a first conductivity type first disposed adjacent to the first transition region and more strongly doped than the first transition region. The channel region is provided in the second transition region such that a pn junction is present at the interface between the channel region and the second transition region, and The junction region is provided in the first transition region, and the first transition region is provided in the channel region. The steps,
Creating at least one control electrode surrounded by an insulating layer, the control electrode extending at least from the first transition region, through the channel region, to the second transition region; Process,
Depositing a recombination layer in the channel region to create at least one recombination region, wherein the at least one recombination region is between the first transition region and the recombination region. The recombination layer is formed of a material that promotes recombination of the charge carriers of the first conductivity type and the second conductivity type, and the recombination layer is formed so that a Schottky junction exists at the interface of The material of the bonding region comprises a process selected from the group consisting of metal and silicide, and
Creating the at least one recombination zone comprises:
Generating at least one second trench starting from one side of the semiconductor and extending to the channel region;
Depositing a material that promotes recombination of charge carriers of a first conductivity type and a second conductivity type in the second groove in the channel region;
Filling the second groove with an insulating material. 前記第２の接合領域と前記第２の遷移領域と前記チャネル領域と前記第１の遷移領域と前記第１の接合領域とは、層状に重ねられて配置されている、請求項９に記載の方法。  The second junction region, the second transition region, the channel region, the first transition region, and the first junction region are arranged in a layered manner. Method. 前記少なくとも１つの制御電極を作製する工程は、
前記半導体の一方の側から始まって該一方側から離れた遷移領域にまで延びる少なくとも１つの第１の溝を該半導体に生成することと、
該第１の溝において絶縁層を堆積させることと、
該第１の溝において電極材料を堆積させることにより、該制御電極を作製することと、
該第１の溝を絶縁材料で埋めることと
を包含する、請求項１０に記載の方法。Producing the at least one control electrode comprises:
Generating at least one first trench in the semiconductor starting from one side of the semiconductor and extending to a transition region remote from the one side;
Depositing an insulating layer in the first trench;
Making the control electrode by depositing an electrode material in the first groove;
11. The method of claim 10, comprising filling the first trench with an insulating material. 前記第１の溝と前記第２の溝との距離は、１μｍよりも小さい、請求項１１に記載の方法。The method of claim 11 , wherein a distance between the first groove and the second groove is less than 1 μm. 複数の互いに隣接する第１の溝および第２の溝が作製され、該複数の溝において、それぞれの制御電極または再結合領域が作製される、請求項１１〜１２のいずれか一項に記載の方法。The first groove and the second groove are fabricated adjacent a plurality of mutually, in the groove of the plurality, each of the control electrodes or recombination region is produced, according to any one of claims 11 to 12 Method. 前記第１の遷移領域および前記第２の遷移領域は、少なくとも同じドーピング濃度を有する、請求項９〜１２のいずれか一項に記載の方法。  The method according to any one of claims 9 to 12, wherein the first transition region and the second transition region have at least the same doping concentration. 前記第１の遷移領域および前記第２の遷移領域は、少なくとも同じ層の厚さを有する、請求項９〜１２のいずれか一項に記載の方法。  13. A method according to any one of claims 9 to 12, wherein the first transition region and the second transition region have at least the same layer thickness.
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