JP3889562B2 - Semiconductor device - Google Patents

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Publication number
JP3889562B2
JP3889562B2 JP2000267784A JP2000267784A JP3889562B2 JP 3889562 B2 JP3889562 B2 JP 3889562B2 JP 2000267784 A JP2000267784 A JP 2000267784A JP 2000267784 A JP2000267784 A JP 2000267784A JP 3889562 B2 JP3889562 B2 JP 3889562B2
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semiconductor element
metal layer
insulating substrate
temperature
fixed
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JP2002076236A (en
Inventor
誠一 早川
克明 斉藤
勝美 石川
敦 佐々木
晃一 須田
阪東　　明
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

【０００１】
【発明の属する技術分野】
本発明は内部絶縁型の半導体モジュールに係り、特に比較的大電流容量のパッケージ型パワー半導体モジュールに好適な半導体装置に関する。
【０００２】
【従来の技術】
特開平９−１４８５２３号公報には半導体素子のチップ上の周辺部に温度検出用素子を配置して熱抵抗の増加を検出する半導体装置の開示がある。
【０００３】
図３は、従来の内部絶縁型の半導体モジュールの半導体装置の断面構造を示す。この図において、絶縁基板４は、アルミナなどの絶縁材で作られ、その一方の面には、配線パターンが形成された金属層５ａがろう材６ａにより接合され、他方の面には、半田などによる接合を可能とする為の金属層５ｂがろう材６ｂにより接合されている。
【０００４】
そして、複数個の半導体素子１は、絶縁基板４の一方の主面に形成されている金属層５ａの所定の部分にソルダー３ａにより接合され、サーミスタ２は金属層５ａの所定の部分にソルダー３ｂにより接合され、さらに絶縁基板４のもう一方の面に形成されている金属層５ｂがソルダー３ｃにより、支持基板７に積層される。
【０００５】
そして、これらの半導体素子１は、金属ワイヤ９により、金属層５ａの所定の部分に対して配線が施されている。支持基板７は、半導体素子１で発生した熱を拡散させるヒートシンクを兼ねている。
【０００６】
電流入出力用の配線端子１２ａおよび信号入出力用の配線端子１２ｂを有する樹脂体８は、金属層５ａに形成されている配線パターンの所定の部分と配線端子１２ａおよび実装基板１１と信号入出力用の配線端子１２ｂを接続するものである。
【０００７】
実装基板１１にはドライバＩＣを含めた制御回路及び電位の上げ下げを行うレベルシフト回路が形成され、半導体素子１の駆動を行う。このとき、ケース内部には、半導体素子１を保護するためのゲル１０が封入される。樹脂体８及び支持基板７はネジ１６により外部冷却フィン１５へ取り付けられる。
【０００８】
図３の半導体装置を使用した回路の例を図５に示す。
【０００９】
この図において、１７ａは上アームの半導体素子であるＩＧＢＴ、１７ｂは下アームのＩＧＢＴ、１８はダイオード、１９は負荷、２０はサーミスタ、２１は電源、２２ａは上アームの制御回路、２２ｂは下アームの制御回路である。半導体素子１７ａは制御回路２２ａにより駆動され、半導体素子１７ｂは制御回路２２ｂにより駆動される。この場合、サーミスタ２０の一端は半導体素子１７ｂの接地側に、一端は制御回路側に接続されている。この場合、半導体素子１７ｂの温度は制御回路２２ｂに接続されたサーミスタ２０の電位により測定され、その温度が半導体素子１７ｂの使用可能範囲を超えたときは、制御回路２２ｂから半導体素子１７ｂに駆動の停止信号が伝わり、半導体素子１７ｂの駆動が停止する。
【００１０】
しかしながら、前記の方法では、半導体素子の発熱による熱は半導体素子から、半導体素子の固着されている金属層、絶縁基板、サーミスタの固着されている金属層、サーミスタへと伝わる為、熱の一部が絶縁基板下の支持基板、冷却フィンに拡散する。そのため、半導体素子の温度とサーミスタの温度に差が生じ、半導体素子の温度を正確に測定できなかった。その為、半導体素子の使用可能な温度範囲に相当するサーミスタの検出温度設定を別に行う必要があった。
【００１１】
【発明が解決しようとする課題】
本発明は、上記の課題を解決するもので、その目的は、半導体素子の温度とサーミスタの温度との検出温度差を小さくすることで、半導体素子の温度を正確に検出できる半導体装置を提供する。
【００１２】
【課題を解決するための手段】
本発明の要旨は以下のとおりである。
外部冷却フィンと、両側主面に固着された金属層を有する絶縁基板が該絶縁基板の片側主面に固着された支持基板を介して接合されてなる半導体装置において、前記絶縁基板の他の片側主面に固着された同じ金属層に半導体素子及び温度検出体が電気的に接続し、前記半導体素子と前記温度検出体の接合されている金属層のうち、前記半導体素子と前記温度検出体の間の金属層が前期絶縁基板と接合されていないことを特徴とする半導体装置である。
また、外部冷却フィンと、両側主面に固着された金属層を有する絶縁基板が該絶縁基板の片側主面に固着された支持基板を介して接合されてなる半導体装置において、前記絶縁基板の他の片側主面に固着された同じ金属層に半導体素子及び温度検出体が電気的に接続され、該半導体素子及び温度検出体がドライバＩＣを搭載した実装基板と電気的に接続し、前記半導体素子と前記温度検出体の接合されている金属層のうち、前記半導体素子と前記温度検出体の間の金属層が前期絶縁基板と接合されていないことを特徴とする半導体装置である。
【００１３】
更に、絶縁基板の片側主面上の金属層に固着された半導体素子及び温度検出体と、前記絶縁基板の他の片側主面の金属層に固着された支持基板を有し、該支持基板上の絶縁基板の半導体素子及び温度検出体を封止してなる樹脂体によって冷却フィンと結合し、前記半導体素子と前記温度検出体の接合されている金属層のうち、前記半導体素子と前記温度検出体の間の金属層が前期絶縁基板と接合されていないことを特徴とする半導体装置である。
【００１４】
本発明は半導体素子の固着された絶縁基板上の金属層に温度検出体を固着した半導体装置であり、半導体素子と温度検出体の固着された絶縁基板上の金属層について絶縁基板と金属層との接合をなくした半導体装置である。
【００１５】
【発明の実施の形態】
本発明は半導体素子の固着された絶縁基板上の金属層に温度検出体（サーミスタ）の端子の一端を固着することにより、半導体素子の温度と温度検出体の温度差を１／１０〜１／１０００℃小さくすることができ、従来の方法に比べて半導体素子の温度検出の精度を向上できる。
【００１６】
更に、半導体素子、温度検出体の固着されている金属層の中で半導体素子から温度検出体が固着している部分を絶縁基板と接合しないことで、熱の絶縁基板へ拡散を防ぎ、半導体素子の温度検出の精度を更に向上できる。
【００１７】
以下、本発明を実施例を用いて具体的に説明する。
【００１８】
【実施例１】
図１は本発明の半導体装置の構成断面図である。温度検出体である温度検出体（以下サーミスタという）２は半導体素子１の固着された金属層５ａと同じ金属層にその外部接続用端子の一端が固定されている。
【００１９】
この場合、半導体素子１で発生した熱は、熱伝導率のよい金属層５ａを伝わり、サーミスタ２に達する。このため、絶縁基板４、支持基板７への放熱が少なく、半導体素子１の温度とサーミスタ２の温度差が小さくなり、サーミスタ２により測定される温度は従来に比べ半導体素子１の温度に近い値となる。
【００２０】
この実施例を使用した回路を図４に示す。
【００２１】
サーミスタ２０の一端は半導体素子１７ｂの高電位側に接続され、一端は上アーム制御回路２２ａに接続される。この場合、サーミスタ２０は高電位となるが、高電位の上アーム制御回路２２ａからレベルシフト回路２３を経由することで低電位となり下アーム制御回路２２ｂに伝わる。
【００２２】
【実施例２】
図２において、半導体素子１及びサーミスタ２の固着されている金属層５ａと絶縁基板４とを接合しているろう材６ａうち、半導体素子１からサーミスタ２の間の部分がなく、この部分は絶縁基板４と金属層５ａは接合していない。この場合、半導体素子１の熱は絶縁基板４に放熱されることなくサーミスタ２へと伝わるため、更に半導体素子１の温度とサーミスタ２の温度の差が小さくなり、半導体素子の温度の検出精度を実施例１に比べ向上できる。
この実施例を使用した回路を図６に示す。
【００２３】
図６において、２４ａはＵ相上アームの半導体素子であるＩＧＢＴ、２４ｂはＵ相下アームＩＧＢＴ、２４ｃはＶ相上アームＩＧＢＴ、２４ｄはＶ相下アームＩＧＢＴ、２４ｅはＷ相上アームＩＧＢＴ、２４ｆはＷ相下アームＩＧＢＴであり、２５はダイオード、２６は負荷、２７ａはＵ相下アームＩＧＢＴ２４ｂの接合された金属層に接合されたサーミスタ、２７ｂはＶ相下アームＩＧＢＴ２４ｄの接合された金属層に接合されたサーミスタ、２７ｃはＷ相下アームＩＧＢＴ２４ｆの接合された金属層に接合されたサーミスタ、２８は電源、２９ａはＵ相上アームの制御回路、２９ｂはＵ相下アームの制御回路、２９ｃはＶ相上アームの制御回路、２９ｄはＶ相下アームの制御回路、２９ｅはＷ相上アームの制御回路、２９ｆはＷ相下アームの制御回路、３０ａはＵ相のレベルシフト回路、３０ｂはＶ相のレベルシフト回路、３０ｃはＷ相のレベルシフト回路である。
【００２４】
この場合、ＩＧＢＴ２４ａ、２４ｂ、２４ｃ、２４ｄ、２４ｅ、２４ｆはそれぞれ制御回路の２９ａ、２９ｂ、２９ｃ、２９ｄ、２９ｅ、２９ｆにより駆動され、負荷２６には３相の電流が流れる。 この３相電流は必ず下アームのＩＧＢＴである２４ｂ、２４ｄ、２４ｆのいずれかに流れる。過剰な電流がＩＧＢＴ２４ｂに流れた場合は、ＩＧＢＴ２４ｂの温度が上昇し、図２の方法により、サーミスタ２７ａにより、温度の上昇を検出できる。
【００２５】
また、他のＩＧＢＴ２４ｄ又は２４ｆに過剰な電流が流れた場合も同様に、それぞれサーミスタ２７ｂ、２７ｃにより温度を検出することができる。この温度がＩＧＢＴ素子の使用可能範囲を超えていた場合は、制御回路２９ａ、２９ｂ、２９ｃ、２９ｄ、２９ｅ、２９ｆにより全ＩＧＢＴ素子の駆動を停止することができる。
【００２６】
よって、本発明を採用することで、半導体装置の導体回路に過剰な電流が発生し、発熱した際も、導体回路及び半導体素子の保護ができる。
【００２７】
【発明の効果】
以上、本発明は比較的大電流容量のパッケージ型パワー半導体モジュールに好適な半導体装置において、半導体素子の接合されている絶縁基板上の金属層と同じ金属層に温度検出体を接合することで、半導体素子により発生した熱は熱伝導のよい金属層から温度検出体に伝わる為、絶縁基板への放熱を小さくでき、半導体素子の温度と温度検出体との温度差を小さくできる。また、半導体素子から温度検出体の間の金属層と絶縁基板との接合をなくすことで、半導体素子から温度検出体までの絶縁基板・支持基板への放熱を小さくして温度差をさらに小さくすることができる。更に、半導体素子の過剰な温度上昇に対し精度よく半導体素子の動作を停止するなどの対応を精度よくできる。
【図面の簡単な説明】
【図１】本発明の半導体装置の構成断面図である。
【図２】本発明の別の半導体装置の構成断面図である。
【図３】従来の内部絶縁型の半導体モジュールの半導体装置の断面構造を示す。
【図４】本発明の実施例１を使用した回路を示す。
【図５】従来の内部絶縁型の半導体モジュールの半導体装置を使用した回路を示す。
【図６】本発明の実施例２を使用した回路を示す。
【符号の説明】
１…半導体素子、２…温度検出体（サーミスタ）、３ａ…半導体素子下部のソルダー、３ｂ…サーミスタ下部のソルダー、３ｃ…絶縁基板下部のソルダー、３ｄ…配線端子下部のソルダー、４…絶縁基板、５ａ…絶縁基板上部の金属層、５ｂ…絶縁基板下部の金属層、６ａ…絶縁基板上部のろう材、６ｂ…絶縁基板下部のろう材、７…支持基板、８…樹脂体、９…金属ワイヤ、１０…ゲル、１１…実装基板、１２ａ…配線端子（電流端子）、１２ｂ…配線端子（信号端子）、１３…接着剤、１４…ドライバＩＣ、１５…外部冷却フィン、１６…・ネジ、１７ａ…上アーム半導体素子（ＩＧＢＴ）、１７ｂ…下アーム半導体素子（ＩＧＢＴ）、１８…ダイオード、１９…負荷、２０…サーミスタ、２１…電源、２２a…上アーム制御回路、２２b…下アーム制御回路、２３…レベルシフト回路、２４ａ…Ｕ相上アーム半導体素子（ＩＧＢＴ）、２４ｂ…Ｕ相下アーム半導体素子（ＩＧＢＴ）、２４ｃ…Ｖ相上アーム半導体素子（ＩＧＢＴ）、２４ｄ…Ｖ相下アーム半導体素子（ＩＧＢＴ）、２４ｅ…Ｗ相上アーム半導体素子（ＩＧＢＴ）、２４ｆ…Ｗ相下アーム半導体素子（ＩＧＢＴ）、２５…ダイオード、２６…負荷、２７ａ…Ｕ相サーミスタ、２７…ｂ：Ｖ相サーミスタ、２７ｃ…Ｗ相サーミスタ、２８…電源、２９ａ…Ｕ相上アーム制御回路、２９ｂ…Ｕ相下アーム制御回路、２９ｃ…Ｖ相上アーム制御回路、２９ｄ…Ｖ相下アーム制御回路、２９ｅ…Ｗ相上アーム制御回路、２９ｆ…Ｗ相下アーム制御回路、３０ａ…Ｕ相レベルシフト回路、３０ｂ…Ｖ相レベルシフト回路、３０ｃ…Ｗ相レベルシフト回路。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an internal insulation type semiconductor module, and more particularly to a semiconductor device suitable for a package type power semiconductor module having a relatively large current capacity.
[0002]
[Prior art]
Japanese Laid-Open Patent Publication No. 9-148523 discloses a semiconductor device that detects an increase in thermal resistance by disposing a temperature detecting element on the periphery of a semiconductor element chip.
[0003]
FIG. 3 shows a cross-sectional structure of a semiconductor device of a conventional internal insulation type semiconductor module. In this figure, an insulating substrate 4 is made of an insulating material such as alumina, and a metal layer 5a on which a wiring pattern is formed is joined to one surface by a brazing material 6a, and the other surface is soldered or the like. The metal layer 5b for enabling the joining by the brazing material 6b is joined.
[0004]
The plurality of semiconductor elements 1 are bonded to a predetermined portion of the metal layer 5a formed on one main surface of the insulating substrate 4 by a solder 3a, and the thermistor 2 is bonded to a predetermined portion of the metal layer 5a. Then, the metal layer 5b formed on the other surface of the insulating substrate 4 is laminated on the support substrate 7 by the solder 3c.
[0005]
These semiconductor elements 1 are wired with a metal wire 9 to a predetermined portion of the metal layer 5a. The support substrate 7 also serves as a heat sink that diffuses the heat generated in the semiconductor element 1.
[0006]
The resin body 8 having the current input / output wiring terminals 12a and the signal input / output wiring terminals 12b is formed of a predetermined portion of the wiring pattern formed on the metal layer 5a, the wiring terminals 12a, the mounting substrate 11, and the signal input / output. The wiring terminal 12b is connected.
[0007]
On the mounting substrate 11, a control circuit including a driver IC and a level shift circuit for raising and lowering the potential are formed, and the semiconductor element 1 is driven. At this time, a gel 10 for protecting the semiconductor element 1 is enclosed in the case. The resin body 8 and the support substrate 7 are attached to the external cooling fins 15 with screws 16.
[0008]
An example of a circuit using the semiconductor device of FIG. 3 is shown in FIG.
[0009]
In this figure, 17a is an IGBT which is a semiconductor element of the upper arm, 17b is an IGBT of the lower arm, 18 is a diode, 19 is a load, 20 is a thermistor, 21 is a power supply, 22a is a control circuit for the upper arm, and 22b is a lower arm. This is a control circuit. The semiconductor element 17a is driven by the control circuit 22a, and the semiconductor element 17b is driven by the control circuit 22b. In this case, one end of the thermistor 20 is connected to the ground side of the semiconductor element 17b, and one end is connected to the control circuit side. In this case, the temperature of the semiconductor element 17b is measured by the potential of the thermistor 20 connected to the control circuit 22b. When the temperature exceeds the usable range of the semiconductor element 17b, the control circuit 22b drives the semiconductor element 17b. The stop signal is transmitted and the driving of the semiconductor element 17b is stopped.
[0010]
However, in the above method, the heat generated by the heat generation of the semiconductor element is transferred from the semiconductor element to the metal layer to which the semiconductor element is fixed, the insulating substrate, the metal layer to which the thermistor is fixed, and the thermistor. Diffuses to the support substrate and the cooling fin under the insulating substrate. Therefore, a difference occurs between the temperature of the semiconductor element and the temperature of the thermistor, and the temperature of the semiconductor element cannot be measured accurately. For this reason, it is necessary to separately set the thermistor detection temperature corresponding to the usable temperature range of the semiconductor element.
[0011]
[Problems to be solved by the invention]
The present invention solves the above-described problems, and an object of the present invention is to provide a semiconductor device capable of accurately detecting the temperature of a semiconductor element by reducing the difference in detection temperature between the temperature of the semiconductor element and the temperature of the thermistor. .
[0012]
[Means for Solving the Problems]
The gist of the present invention is as follows.
In a semiconductor device in which an external cooling fin and an insulating substrate having a metal layer fixed to both main surfaces are joined via a support substrate fixed to one main surface of the insulating substrate, the other one side of the insulating substrate The semiconductor element and the temperature detector are electrically connected to the same metal layer fixed to the main surface, and the semiconductor element and the temperature detector of the metal layer where the semiconductor element and the temperature detector are joined are connected . The semiconductor device is characterized in that the metal layer therebetween is not bonded to the insulating substrate in the previous period.
In addition, in a semiconductor device in which an external cooling fin and an insulating substrate having a metal layer fixed to both main surfaces are bonded via a support substrate fixed to one main surface of the insulating substrate, the semiconductor element and the temperature detector on the same metal layer secured to one side main surface is electrically connected, the semiconductor element and temperature detector is connected to the mounting board and electrically mounting the driver IC, the semiconductor element of the metal layer are joined in the temperature detecting element and a metal layer between said semiconductor element and said temperature detector is a semiconductor device you characterized by not joined to the previous period insulating substrate.
[0013]
Further, the semiconductor element and the temperature detector fixed to the metal layer on the one-side main surface of the insulating substrate, and a support substrate fixed to the metal layer on the other one-side main surface of the insulating substrate, The semiconductor element of the insulating substrate and the temperature detection body are combined with the cooling fin by a resin body formed by sealing, and the semiconductor element and the temperature detection are among the metal layers bonded to the semiconductor element and the temperature detection body. The semiconductor device is characterized in that the metal layer between the bodies is not bonded to the insulating substrate in the previous period.
[0014]
The present invention is a semiconductor device in which a temperature detector is fixed to a metal layer on an insulating substrate to which a semiconductor element is fixed, and the insulating substrate, the metal layer, and the metal layer on the insulating substrate to which the semiconductor element and the temperature detector are fixed are provided. This is a semiconductor device that eliminates the junction.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the temperature difference between the temperature of the semiconductor element and the temperature detector is reduced to 1/10 to 1/1 by fixing one end of the terminal of the temperature detector (thermistor) to the metal layer on the insulating substrate to which the semiconductor element is fixed. The temperature can be reduced by 1000 ° C., and the temperature detection accuracy of the semiconductor element can be improved as compared with the conventional method.
[0016]
Furthermore, the semiconductor element and the metal layer to which the temperature detector is fixed are not bonded to the insulating substrate at the portion where the temperature detector is fixed from the semiconductor element, thereby preventing diffusion of heat to the insulating substrate. The accuracy of temperature detection can be further improved.
[0017]
Hereinafter, the present invention will be specifically described with reference to examples.
[0018]
[Example 1]
FIG. 1 is a sectional view of a semiconductor device according to the present invention. A temperature detection body (hereinafter referred to as a thermistor) 2 that is a temperature detection body has one end of an external connection terminal fixed to the same metal layer as the metal layer 5a to which the semiconductor element 1 is fixed.
[0019]
In this case, the heat generated in the semiconductor element 1 is transmitted through the metal layer 5 a having good thermal conductivity and reaches the thermistor 2. For this reason, heat radiation to the insulating substrate 4 and the support substrate 7 is small, the temperature difference between the temperature of the semiconductor element 1 and the thermistor 2 is small, and the temperature measured by the thermistor 2 is a value closer to the temperature of the semiconductor element 1 than in the prior art. It becomes.
[0020]
A circuit using this embodiment is shown in FIG.
[0021]
One end of the thermistor 20 is connected to the high potential side of the semiconductor element 17b, and one end is connected to the upper arm control circuit 22a. In this case, the thermistor 20 has a high potential, but becomes a low potential via the level shift circuit 23 from the high potential upper arm control circuit 22a and is transmitted to the lower arm control circuit 22b.
[0022]
[Example 2]
In FIG. 2, there is no part between the semiconductor element 1 and the thermistor 2 in the brazing material 6a joining the metal layer 5a to which the semiconductor element 1 and the thermistor 2 are fixed and the insulating substrate 4, and this part is insulated. The substrate 4 and the metal layer 5a are not joined. In this case, since the heat of the semiconductor element 1 is transmitted to the thermistor 2 without being radiated to the insulating substrate 4, the difference between the temperature of the semiconductor element 1 and the temperature of the thermistor 2 is further reduced, and the detection accuracy of the temperature of the semiconductor element is increased. This can be improved compared to the first embodiment.
A circuit using this embodiment is shown in FIG.
[0023]
In FIG. 6, 24a is a U-phase upper arm semiconductor element, 24b is a U-phase lower arm IGBT, 24c is a V-phase upper arm IGBT, 24d is a V-phase lower arm IGBT, 24e is a W-phase upper arm IGBT, 24f. Is a W-phase lower arm IGBT, 25 is a diode, 26 is a load, 27a is a thermistor joined to a metal layer joined to the U-phase lower arm IGBT 24b, and 27b is joined to a metal layer joined to the V-phase lower arm IGBT 24d. Bonded thermistor, 27c is a thermistor bonded to the bonded metal layer of W-phase lower arm IGBT 24f, 28 is a power supply, 29a is a control circuit for the U-phase upper arm, 29b is a control circuit for the U-phase lower arm, and 29c is V-phase upper arm control circuit, 29d is V-phase lower arm control circuit, 29e is W-phase upper arm control circuit, and 29f is W-phase lower arm control circuit Control circuit, 30a is the level shift circuit of U phase, 30b is the level shift circuit of the V-phase, 30c is the level shift circuit of the W-phase.
[0024]
In this case, the IGBTs 24a, 24b, 24c, 24d, 24e, and 24f are driven by the control circuits 29a, 29b, 29c, 29d, 29e, and 29f, respectively, and a three-phase current flows through the load 26. This three-phase current always flows to any of the lower arm IGBTs 24b, 24d, and 24f. When excessive current flows to the IGBT 24b, the temperature of the IGBT 24b rises, and the temperature rise can be detected by the thermistor 27a by the method of FIG.
[0025]
Similarly, when an excessive current flows through the other IGBT 24d or 24f, the temperature can be detected by the thermistors 27b and 27c, respectively. When this temperature exceeds the usable range of the IGBT elements, the driving of all the IGBT elements can be stopped by the control circuits 29a, 29b, 29c, 29d, 29e, and 29f.
[0026]
Therefore, by employing the present invention, the conductor circuit and the semiconductor element can be protected even when excessive current is generated in the conductor circuit of the semiconductor device and heat is generated.
[0027]
【The invention's effect】
As described above, the present invention provides a semiconductor device suitable for a package type power semiconductor module having a relatively large current capacity, by bonding the temperature detector to the same metal layer as the metal layer on the insulating substrate to which the semiconductor element is bonded. Since the heat generated by the semiconductor element is transmitted from the metal layer having good thermal conductivity to the temperature detection body, the heat radiation to the insulating substrate can be reduced, and the temperature difference between the temperature of the semiconductor element and the temperature detection body can be reduced. Further, by eliminating the bonding between the metal layer between the semiconductor element and the temperature detection body and the insulating substrate, the heat radiation from the semiconductor element to the temperature detection body to the insulating substrate and the support substrate is reduced to further reduce the temperature difference. be able to. Furthermore, it is possible to accurately cope with an excessive temperature rise of the semiconductor element, such as stopping the operation of the semiconductor element with high precision.
[Brief description of the drawings]
FIG. 1 is a structural cross-sectional view of a semiconductor device of the present invention.
FIG. 2 is a structural cross-sectional view of another semiconductor device of the present invention.
FIG. 3 shows a cross-sectional structure of a semiconductor device of a conventional internal insulation type semiconductor module.
FIG. 4 shows a circuit using Example 1 of the present invention.
FIG. 5 shows a circuit using a semiconductor device of a conventional internal insulation type semiconductor module.
FIG. 6 shows a circuit using Example 2 of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Temperature detection body (thermistor), 3a ... Solder under semiconductor element, 3b ... Solder under thermistor, 3c ... Solder under insulating substrate, 3d ... Solder under wiring terminal, 4 ... Insulating substrate, 5a: metal layer above the insulating substrate, 5b ... metal layer below the insulating substrate, 6a ... brazing material above the insulating substrate, 6b ... brazing material below the insulating substrate, 7 ... support substrate, 8 ... resin body, 9 ... metal wire DESCRIPTION OF SYMBOLS 10 ... Gel, 11 ... Mounting board, 12a ... Wiring terminal (current terminal), 12b ... Wiring terminal (signal terminal), 13 ... Adhesive, 14 ... Driver IC, 15 ... External cooling fin, 16 ... Screw, 17a ... upper arm semiconductor element (IGBT), 17b ... lower arm semiconductor element (IGBT), 18 ... diode, 19 ... load, 20 ... thermistor, 21 ... power supply, 22a ... upper arm control circuit, 22b Lower arm control circuit, 23 ... level shift circuit, 24a ... U-phase upper arm semiconductor element (IGBT), 24b ... U-phase lower arm semiconductor element (IGBT), 24c ... V-phase upper arm semiconductor element (IGBT), 24d ... V Phase lower arm semiconductor element (IGBT), 24e ... W phase upper arm semiconductor element (IGBT), 24f ... W phase lower arm semiconductor element (IGBT), 25 ... diode, 26 ... load, 27a ... U phase thermistor, 27 ... b : V phase thermistor, 27c ... W phase thermistor, 28 ... power supply, 29a ... U phase upper arm control circuit, 29b ... U phase lower arm control circuit, 29c ... V phase upper arm control circuit, 29d ... V phase lower arm control circuit 29e ... W-phase upper arm control circuit, 29f ... W-phase lower arm control circuit, 30a ... U-phase level shift circuit, 30b ... V-phase level shift circuit, 30 c: W-phase level shift circuit.

Claims (3)

外部冷却フィンと、両側主面に固着された金属層を有する絶縁基板が該絶縁基板の片側主面に固着された支持基板を介して接合されてなる半導体装置において、前記絶縁基板の他の片側主面に固着された同じ金属層に半導体素子及び温度検出体が電気的に接続し、前記半導体素子と前記温度検出体の接合されている金属層のうち、前記半導体素子と前記温度検出体の間の金属層が前期絶縁基板と接合されていないことを特徴とする半導体装置。In a semiconductor device in which an external cooling fin and an insulating substrate having a metal layer fixed to both main surfaces are joined via a support substrate fixed to one main surface of the insulating substrate, the other one side of the insulating substrate The semiconductor element and the temperature detector are electrically connected to the same metal layer fixed to the main surface, and the semiconductor element and the temperature detector of the metal layer where the semiconductor element and the temperature detector are joined are connected . A semiconductor device characterized in that a metal layer therebetween is not bonded to an insulating substrate in the previous period . 外部冷却フィンと、両側主面に固着された金属層を有する絶縁基板が該絶縁基板の片側主面に固着された支持基板を介して接合されてなる半導体装置において、前記絶縁基板の他の片側主面に固着された同じ金属層に半導体素子及び温度検出体が電気的に接続され、該半導体素子及び温度検出体がドライバＩＣを搭載した実装基板と電気的に接続し、前記半導体素子と前記温度検出体の接合されている金属層のうち、前記半導体素子と前記温度検出体の間の金属層が前期絶縁基板と接合されていないことを特徴とする半導体装置。In a semiconductor device in which an external cooling fin and an insulating substrate having a metal layer fixed to both main surfaces are joined via a support substrate fixed to one main surface of the insulating substrate, the other one side of the insulating substrate the semiconductor device and the temperature detector on the same metal layer secured to the main surface is electrically connected, the semiconductor element and temperature detector is connected to the mounting board and electrically mounting the driver IC, the said semiconductor element Of the metal layers to which the temperature detector is bonded, the metal layer between the semiconductor element and the temperature detector is not bonded to the previous insulating substrate . 絶縁基板の片側主面上の金属層に固着された半導体素子及び温度検出体と、前記絶縁基板の他の片側主面の金属層に固着された支持基板を有し、該支持基板上の絶縁基板の半導体素子及び温度検出体を封止してなる樹脂体によって冷却フィンと結合し、前記半導体素子と前記温度検出体の接合されている金属層のうち、前記半導体素子と前記温度検出体の間の金属層が前期絶縁基板と接合されていないことを特徴とする半導体装置。A semiconductor element and a temperature detector fixed to a metal layer on one main surface of the insulating substrate, and a support substrate fixed to a metal layer on the other main surface of the insulating substrate, and insulating on the support substrate The semiconductor element and the temperature detection body of the substrate are coupled to the cooling fin by a resin body formed by sealing the semiconductor element and the temperature detection body, and the semiconductor element and the temperature detection body of the metal layer bonded to the semiconductor element and the temperature detection body. A semiconductor device characterized in that a metal layer therebetween is not bonded to an insulating substrate in the previous period .
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