JP3834052B2 - 実装体 - Google Patents
実装体 Download PDFInfo
- Publication number
- JP3834052B2 JP3834052B2 JP2005197775A JP2005197775A JP3834052B2 JP 3834052 B2 JP3834052 B2 JP 3834052B2 JP 2005197775 A JP2005197775 A JP 2005197775A JP 2005197775 A JP2005197775 A JP 2005197775A JP 3834052 B2 JP3834052 B2 JP 3834052B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- wiring
- wiring film
- film
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Description
日経BP社発行「日経マイクロデバイス」1989年12月号、同年12月1日発行、P48
Claims (2)
- 半導体部品を含む複数の電子部品と、
絶縁性フィルムと該絶縁性フィルム上に形成された複数の電極と配線層とを有する可撓性配線フィルムと、
を備え、
前記複数の電子部品の電極はそれぞれ対応する前記配線フィルムの前記電極に接続され、
前記複数の電子部品は前記配線層を介して相互接続されており、
前記複数の電子部品および前記配線フィルムは、前記配線フィルムを折り曲げて積層したとき、一段に複数の電子部品が並置搭載された段と一段に一つの電子部品が搭載された段とを構成するように配置されており、
前記複数の電子部品が並置搭載された段の電子部品と前記一つの電子部品が搭載された段の電子部品は前記折り曲げられた前記配線フィルム部分に形成された配線層を介して相互接続され、
前記配線フィルムを折り曲げ積層して得られる前記複数の電子部品の積層体の実装面積は実効的に前記一段に一つの電子部品が搭載された段の実装面積となるように構成されてなることを特徴とする実装体。 - 半導体部品を含む複数の電子部品と、
配線層が形成された絶縁性フィルムよりなる可撓性配線フィルムと、
を備え、
前記複数の電子部品は前記配線層を介して電気的に相互接続されており、
前記複数の電子部品および前記配線フィルムは、前記配線フィルムを折り曲げて積層したとき、一段に複数の電子部品が並置搭載された段と一段に一つの電子部品が搭載された段とを構成するように配置されており、
前記複数の電子部品が並置搭載された段の電子部品と前記一つの電子部品が搭載された段の電子部品は前記折り曲げられた前記配線フィルム部分に形成された配線層を介して相互接続され、
前記配線フィルムを折り曲げ積層して得られる前記複数の電子部品の積層体の実装面積は実効的に前記一段に一つの電子部品が搭載された段の実装面積となるように構成されてなることを特徴とする実装体。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005197775A JP3834052B2 (ja) | 2005-07-06 | 2005-07-06 | 実装体 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005197775A JP3834052B2 (ja) | 2005-07-06 | 2005-07-06 | 実装体 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002155783A Division JP2003037246A (ja) | 2002-05-29 | 2002-05-29 | 電子部品および電子部品モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005328076A JP2005328076A (ja) | 2005-11-24 |
JP3834052B2 true JP3834052B2 (ja) | 2006-10-18 |
Family
ID=35474113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005197775A Expired - Fee Related JP3834052B2 (ja) | 2005-07-06 | 2005-07-06 | 実装体 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3834052B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100813623B1 (ko) | 2006-10-17 | 2008-03-17 | 삼성전자주식회사 | 가요성 필름, 이를 이용한 반도체 패키지 및 제조방법 |
-
2005
- 2005-07-06 JP JP2005197775A patent/JP3834052B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005328076A (ja) | 2005-11-24 |
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