JP3826651B2 - Wiring board manufacturing method - Google Patents
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【０００１】
【発明の属する技術分野】
本発明は、配線板の製造法に関する。
【０００２】
【従来の技術】
配線板は、通常、銅張り積層板にスルーホールとなる孔をあけ、その孔の内壁と銅箔表面に無電解めっきを行って、スルーホールとして必要な厚さまで電気めっきを行い、そのスルーホールめっきを保護しながら不要な銅を除去するためにエッチングレジストを形成し、例えば塩化第二銅と塩酸からなる化学エッチング液をスプレーで噴霧し、不要な銅を選択的にエッチング除去することによって製造されている。
近年では機器の小型化によって、配線板の高密度化が要求され、回路パターンの密度も、導体幅/導体間隔が３０μｍ/３０μｍ迄要求されてきている。
この要求に対応する配線板は、前記従来の製造法では非常に困難となってきているため、高密度でありながら経済的に優れた配線板の製造法が、特開平１１-５４９１０号公報に提案されている。
【０００３】
【発明が解決しようとする課題】
近年、実装方式としてチップを直接搭載する基板が要求されてきており、チップとの接続方式としてＡＣＦ(異方導電性膜)等を用いたフリップチップ方式が高密度実装として採用されてきている。
これらの実装方式に対応する基板側への要求としては、これまで以上に高密度であることが要求され、更にチップとの接続ラインに幅の高精度化、チップとの接続面の高さ(厚み)ばらつきの高精度化も必要となる。
前記公報に開示された製法は、経済的に優れており、微細配線も従来と比較して格段の向上を図ることができるが更なる高密度化の要求に対しては以下の課題がある。
【０００４】
回路パターンを形成した後、電気めっきでスルーホールを形成することから、ライン及びスルーホールに対して電気めっきリードとなるラインを接続しておかなければならない。そのめっきリードラインのために配線密度が上がらなかったり、スルーホールヘ接続するめっきリード用スルーホールが必要になると共に、スルーホール個数が多く必要となったり、そのためのライン本数が増加する等で、配線密度を向上させるには障害となっていた。また、特にチップ実装部ラインにおいて、めっきリードラインの接続が不可能な場合が発生し易く、その場合は、ラインを削除することが必要なことから、チップとの接続信頼性の低下を招く等の問題があった。また、メッキリードラインを接続しておいて後から孔で切断する等の手法をとる場合もあるが、そのためのスペースが必要になる等、更なる高密度に対しては障害となっていた。
【０００５】
一方、チップとの接続をするラインにおいては、電気めっきで形成することから、電気めっき特有の面内厚みばらつきが大きく発生し、チップとの接続面の高さ(厚さ)管理が困難になると共に、接続信頼性が悪化するという課題があった。本発明は、前記公報に開示されている微細配線レベルを損なうことなく、ラインやスルーホールにめっきリードを必要とせず、表面実装部品(例えばチップ等)との接続信頼性を損なうことなく、これまで以上に高密度回路パターンを形成でき、更に回路の高さのばらつき精度を高精度に押さえて、接続信頼性が損なわれない配線板の製造法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明の製造法は、以下の工程からなることを特徴とする。
ａ：銅張り積層板にスルーホールとなる孔をあける工程
ｂ：スルーホールとなる孔の内壁に電解めっき又は無電解めっきを受け入れる層を形成する工程
ｃ：スルーホールとなる孔及びその周囲を除いて選択的にめっきレジストを塗布する工程
ｄ：電解めっき又は無電解めっきによって少なくとも孔内壁にニッケル又はその合金のめっき層を形成する工程
ｅ：めっきレジストを剥離する工程
ｆ：スルーホール孔内壁のめっき層を保護するとともに、必要な配線を形成するためのエッチングレジストを形成する工程
ｇ：エッチングレジストの形成されていない銅箔部分を選択的にエッチング除去する工程
【０００７】
【発明の実施の形態】
前記スルーホールとして電気的に接続される、電解めっき又は無電解めっきを受け入れる層には、無電解めっき層、導電性微粒子とその導電微粒子をスルーホールとなる孔内壁に保持するための接着剤成分からなるもの、導電性モノマーを付着させ、その後、その導電性モノマーを酸化重合させて導電性を付与したもの、あるいは無電解めっきのめっき触媒によるシーダー処理を用いることができる。それぞれの実施の形態詳細については、特開平１１-５４９１０号公報に示されている。
工程ｃにおけるめっきレジストは、印刷用インク、又は露光現像タイプのドライフィルムを用いることができる。一方、材質としては、次工程のめっき時の耐久性とめっき後の剥離性を兼ね備えている必要がある。
工程ｄにおけるニッケル又はその合金めっき層の厚さは、１〜２０μｍの範囲であることが好ましく、１μｍ未満では、はんだなどの熱衝撃に対する強度が不足し、２０μｍを越えると、その後の回路形成時に大きな段差によって、エッチングレジスト密着時に気泡を巻き込み、その後のエッチングで断線する可能性があり、より好ましくは３〜１０μｍの範囲である。さらに、ニッケル又はその合金めっきを行う範囲は、スルーホールとなる孔の内壁及びスルーホールとなる孔の周囲０.０１〜１.０ｍｍの範囲とする。
工程ｆ以降については、公知技術である永久レジストを形成し、電解又は無電解めっきで導体露出部を処理する等の方法が多く用いられるが、本発明の特徴を最大に生かすためには導体露出部に対して、均一な厚みでめっきができる無電解めっきを採用することが好ましい。
【０００８】
銅張り積層板の基材には、フレキシブル基材を用いることもできる。
基材としては、ポリイミドフイルム、ポリエステルフィルム等を用いることができ、市販のものでは、ポリイミドフイルムではカプトン(デュポン社製、商品名)ユーピレックス(宇部興産（株）製、商品名)、エスパネックス(新日鉄化学（株）製、商品名)、ポリエステルフィルムでは、ルミラー(東レ（株）製、商品名)を使用することができる。
この銅張り積層板の基材には、通常の配線板に用いるガラス布エポキシ樹脂含浸の銅張り積層板、ガラス不織紙エポキシ樹脂含浸銅張り積層板、セラミック表面を粗化し該表面に銅層を形成したセラミック銅張り積層板等を用いることができる。
本発明の銅張り積層板の銅箔には、圧延銅箔、電解銅箔いずれの種類でも用いることができ、厚さは薄ければ薄いほど微細な回路を形成することができるが、取り扱い性や価格の面から、好ましい範囲は、５μｍ〜３５μｍの範囲である。銅箔の厚さが５μｍ未満のもので市販されているものはなく、自前で作製するにしてもめっき装置等を必要とし経済的ではなく、取り扱い性も極めて悪い。３５μｍを越えるものについても本発明の方法を用いることはできるが、微細な回路を形成することは困難でありメリットは少ない。
以下本発明を実施例に基づき説明するが、本発明はこれに限定されるものではない。
【０００９】
【実施例】
実施例１
工程ａ
図１(ａ)に示すように、両面に厚さ１２μｍの銅箔１を貼り合わせたガラスエポキシ樹脂含浸銅張り積層板であるＭＣＬ-Ｅ６７９(日立化成工業（株）製、商品名)の厚さ０.１ｍｍのものに、直径０.２ｍｍのスルーホールとなる孔をあけた。
工程ｂ
図１(ｂ)に示すように、孔をあけた銅張り積層板を十分に水洗いした後、コンディショナーＣＬＤ-１００(日立化成工業（株）製、商品名)に４０℃で５分間浸漬して表面処理を行い、続いて、無電解めっき用増感剤であるＣＵＳＴ-２０１Ｂ(日立化成工業（株）製、商品名)に、液温５０℃で４０分の条件で浸漬し、無電解めっき液であるＬ-５９めっき液(日立化成工業（株）製、商品名)を６０℃で３０分の条件で、厚さ０.５μｍの銅めっきを電気めっきを受け入れる層３として形成した。
工程ｃ
図１(ｃ)に示すように、スルーホール孔及びその周囲ランドを外しためっきレジスト用ドライフィルムであるフォテックＨ−Ｎ６４０(日立化成工業（株）製、商品名)をロール温度１００℃、ロール送り速度１.０ｍ/分の条件でラミネートし、フォトマスクを介して紫外線を７０ｍＪ/ｃｍ2条件で露光し、１.１重量％の炭酸ナトリウム溶液で噴霧して現像し、めっきレジスト４を形成した。
工程ｄ
図１(ｄ)に示すように、以下の電気ニッケルめっきを、液温５５℃、時間６分、電流密度４Ａ/ｄｍ2の条件で行い、厚さ５μｍのニッケルめっき層５を形成した。
(電気ニッケルめっき液の組成)
ニッケル……………６０ｇ/ｌ
塩化ニッケル………３５ｇ/ｌ
棚酸…………………３５ｇ/ｌ
工程ｅ
図１(ｅ)に示すように、めっきレジスト４を３％重量の水酸化カリウム溶液で剥離除去した。
工程ｆ
図１(ｆ)に示すように、スルーホール孔内壁のめっき層３を保護するとともに、必要な配線を形成するためのエッチングレジストを形成するために、エッチングレジスト用ドライフィルムであるフォテックＨ−Ｎ９２０(日立化成工業（株）製、商品名)をロール温度１００℃、ロール送り速度１.０ｍ/分の条件でラミネートし、フォトマスクを介して紫外線を５０ｍＪ/ｃｍ2条件で露光し、１.１重量％の炭酸ナトリウム溶液で噴霧して現像し、エッチングレジスト７を形成した。
工程ｇ
図１(ｇ)に示すように、エッチングレジスト７の形成されていない銅箔部分を、塩化第二銅/塩酸溶液をスプレー噴霧して、選択的にエッチング除去した。
工程ｈ
図１(ｈ)に示すように、エッチングレジスト７を３％重量の水酸化カリウム溶液で剥離除去した。
【００１０】
実施例２
実施例１における工程ｂに代えて、以下の工程とした。
スルーホールとなる孔の内壁に、電気めっきを受け入れる層３を、以下のようにして形成した。
孔をあけた銅張り積層板を十分に水洗いした後、ブラックホールクリーナーＳＰ-６８００(メック（株）製、商品名)に、室温で１分間浸漬けして油脂等を除去し、ブラックホールコンディショナーＳＰ-６５６０(メック（株）製、商品名)に室温で３分間浸漬してグラファイト粒子層を形成し、１０重量％硫酸で酸洗し、水洗して、均一なグラファイト層を全体に形成し、乾燥して定着し、水洗、乾燥後セパレーターＳＰ-６８００(メック（株）製、商品名)に室温で３分間浸漬し、銅表面の余分なグラファイトを除去した。
【００１１】
比較例１
工程ａ
図２(ａ)に示すように、両面に厚さ１２μｍの銅箔１を貼り合わせたガラスエポキシ樹脂含浸銅張り積層板であるＭＣＬ-Ｅ６７９(日立化成工業（株）製、商品名)の厚さ０.１ｍｍのものに、直径０.２ｍｍのスルーホールとなる孔をあけた。
工程ｂ
図２(ｂ)に示すように、孔をあけた銅張り積層板を、十分に水洗いした後、コンディショナーＣＬＤ-１００(日立化成工業（株）製、商品名)に４０℃で５分間浸漬けして表面処理を行い、続いて、無電解めっき用増感剤であるＣＵＳＴ-２０１Ｂ(日立化成工業（株）製、商品名)に、液温５０℃で４０分の条件で浸漬し、無電解めっき液であるＬ-５９めっき液(日立化成工業（株）製、商品名)を６０℃で３０分の条件で、厚さ０.５μｍの銅めっきを電気めっきを受け入れる層として形成した。
工程ｃ
図２(ｃ)に示すように、スルーホール孔内壁のめっき層３を保護するとともに、必要な配線を形成するためのエッチングレジストを形成するためにエッチングレジスト用ドライフィルムである、フォテックＨ−Ｎ９２０(日立化成工業（株）製、商品名)をロール温度１００℃、ロール送り速度１.０ｍ/分の条件でラミネートし、フォトマスクを介して紫外線を５０ｍｊ/ｃｍ2条件で露光し、１.１重量％の炭酸ナトリウム溶液で噴霧して現像し、エッチングレジスト６を形成した。
工程ｄ
図２(ｄ)に示すように、エッチングレジスト４の形成されていない胴部分を塩化第二銅/塩酸溶液をスプレー噴霧して、選択的にエッチング除去した。
工程ｅ
図２(ｅ)に示すように、以下の電気ニッケルめっきを、液温５５℃、時間６分、電流密度４Ａ/ｄｍ2の条件で行い、厚さ５μｍのニッケルめつき層５を形成した。
(電気ニッケルめっき液の組成)
ニッケル……………６０ｇ/ｌ
塩化ニッケル………３５ｇ/ｌ
棚酸…………………３５ｇ/ｌ
以上に説明した実施例と比較例のパターン配線密度及ぴ配線厚さばらつき精度について表１及び図３、図４に示す。
【００１２】
【表１】
以下に本発明の実施例に用いた測定方法と試験方法について述べる。
試料の作製
試料は、大きさ５００ｍｍ×５００ｍｍとし、２０枚の試料を作製した。
配線は図５に示す３０μｍ/３０μｍのラインに全てめっきリードを取ったものをパネルに均等に９個面付け配置し、それぞれの方法で製作した。
測定方法
導体厚みの測定には、触針式の表面粗さ測定器を用いて、基材と導体の接着されている面から導体表面迄の高さを測定した。
表１に示すように、比較例の厚みは最大５μｍものばらつきが見られるが、実施例の場合は最大でも１μｍのばらつき範囲内で製作可能である。
【００１４】
パターン配線密度において、特開平１１-５４９１０号公報記載の方法では、電気めっきのために、めっきリードが必要であることと、配線形成後にめっきをつけることから、図３に示すような設計となった場合、部品搭載ランドが近くに存在するチップ搭載エリア内接続ラインのなかには、図に示すようなメッキリード接続不可能ラインが発生し、このラインにはめっきがつかない。
この場合、このままめっきをつけない方法を採るか、または、ラインを削除するかのいずれかの方法で製作せざるを得ないこととなる。なお、無電解めっきで後からめっきすることも考えられるが、めっきが２重になり、めっきが剥がれやすくなるという問題がある。
このままめっきがつかないラインを残して、チップとの接続を行えば、接続性が極度に悪化するラインとなり、このラインを削除すれば、バランスが悪化するために、接続信頼性が悪化する。
本発明の方法によれば、無電解めっきを配線形成後に処理することによって、めっきが2重にならずにつけることができる。また、図４（ａ）に示すような設計の場合、中にあるスルーホールは表面配線側からも裏面配線からもメッキリードラインを引き延ばすことができないため、配線間隔を広げてメッキリード用スルホールを別に設置しなければなない箇所が発生する。従って図４（ｂ）に示すように、配線密度を損なうことがあったが、本発明の方法なら、配線形成前にスルーホールを形成してしまうことから、このようなめっきリード用スルーホールは必要が無く、図４（ａ）のままで製作可能である。
【００１５】
【発明の効果】
以上説明したとおり、本発明によれば、微細配線レベルを損なうことなく、ラインやスルーホーノレにめっきリードを必要とせず、チップ等の表面実装部品との接続信頼性を損なうことなく、これまで以上に高密度回路パターンを形成でき、更に回路の高さのぱらつき精度を高精度に押さえて、接続信頼性が損なわれない配線板の製造法を提供することができる。
【図面の簡単な説明】
図１(ａ)〜(ｈ)は本発明の一実施例の各工程における断面図。
図２(ａ)〜(ｆ)は従来例の各工程における断面図。
図３ 従来例を説明するための平面図。
図４本発明の効果を説明するための平面図（ａ）及び従来例を説明するための平面図（ｂ）。
図５ 本発明の効果を説明するためのめっきリードラインの部分平面図。
【符号の説明】
１.銅箔
２.基材
３.めっきを受け入れる層
４.めっきレジスト
５.ニッケルめっき層
６.孔
７.エッチングレジスト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board.
[0002]
[Prior art]
A wiring board usually has a through-hole formed in a copper-clad laminate, electrolessly plated the inner wall of the hole and the surface of the copper foil, and electroplated to the required thickness as a through-hole. Produced by forming an etching resist to remove unnecessary copper while protecting the plating, for example, spraying a chemical etching solution consisting of cupric chloride and hydrochloric acid by spraying, and selectively removing unnecessary copper by etching Has been.
In recent years, due to miniaturization of devices, it is required to increase the density of wiring boards, and the density of circuit patterns is also required to be 30 μm / 30 μm in conductor width / conductor spacing.
Since the wiring board corresponding to this requirement has become very difficult with the above-mentioned conventional manufacturing method, a manufacturing method of a wiring board that is high density and economically excellent is disclosed in Japanese Patent Laid-Open No. 11-54910. Proposed.
[0003]
[Problems to be solved by the invention]
In recent years, a substrate on which a chip is directly mounted has been required as a mounting method, and a flip-chip method using an ACF (anisotropic conductive film) or the like has been adopted as a high-density mounting as a connection method with a chip.
As a requirement on the board side corresponding to these mounting methods, it is required to have a higher density than before, and further, the width of the connection line with the chip is increased, the height of the connection surface with the chip ( It is also necessary to increase the accuracy of (thickness) variation.
The manufacturing method disclosed in the above publication is economically excellent, and the fine wiring can be remarkably improved as compared with the conventional method. However, there are the following problems with respect to the demand for higher density.
[0004]
Since the through hole is formed by electroplating after the circuit pattern is formed, the line and the line serving as the electroplating lead must be connected to the through hole. Due to the plating lead line, the wiring density does not increase, the plating lead through hole connected to the through hole is required, the number of through holes is increased, the number of lines for that increase, etc. It was an obstacle to improve the wiring density. In addition, particularly in the chip mounting part line, it is likely that the plating lead line cannot be connected. In this case, since it is necessary to delete the line, the connection reliability with the chip is reduced. There was a problem. Further, there is a case where a method of connecting a plating lead line and then cutting with a hole later is taken, but this has been an obstacle to further high density such as requiring a space for that purpose.
[0005]
On the other hand, since the line connecting to the chip is formed by electroplating, the in-plane thickness variation peculiar to electroplating is greatly generated, making it difficult to control the height (thickness) of the connection surface with the chip. At the same time, there is a problem that connection reliability deteriorates. The present invention does not impair the fine wiring level disclosed in the above publication, does not require plating leads for lines and through holes, and does not impair connection reliability with surface mount components (e.g., chips). It is an object of the present invention to provide a method for manufacturing a wiring board that can form a high-density circuit pattern more than the above, further suppresses the variation accuracy of the circuit height with high accuracy, and does not impair the connection reliability.
[0006]
[Means for Solving the Problems]
The production method of the present invention comprises the following steps.
a: opening a hole serving as a through hole in a copper-clad laminate b: forming a layer for receiving electrolytic plating or electroless plating on the inner wall of the hole serving as a through hole c: removing a hole serving as a through hole and its surroundings A step of selectively applying a plating resist d: a step of forming a plating layer of nickel or an alloy thereof at least on the inner wall of the hole by electrolytic plating or electroless plating e: a step of removing the plating resist f: plating of the inner wall of the through-hole hole Step g of forming an etching resist for protecting a layer and forming a necessary wiring g: Step of selectively etching away a copper foil portion where no etching resist is formed
DETAILED DESCRIPTION OF THE INVENTION
The layer that accepts electrolytic plating or electroless plating that is electrically connected as the through hole includes an electroless plating layer, conductive fine particles, and an adhesive component for holding the conductive fine particles on the inner wall of the hole serving as the through hole. A conductive monomer is attached, and then the conductive monomer is oxidatively polymerized to impart conductivity, or a seeder treatment with a plating catalyst for electroless plating can be used. Details of each embodiment are disclosed in Japanese Patent Laid-Open No. 11-54910.
As the plating resist in step c, printing ink or exposure and development type dry film can be used. On the other hand, as a material, it is necessary to have both the durability at the time of plating in the next step and the peelability after plating.
The thickness of the nickel or its alloy plating layer in step d is preferably in the range of 1 to 20 μm, and if it is less than 1 μm, the strength against thermal shock such as solder is insufficient. Due to the large level difference, there is a possibility that air bubbles are involved when the etching resist is in close contact, and disconnection may occur in the subsequent etching. Furthermore, the range in which nickel or an alloy plating thereof is performed is in the range of 0.01 to 1.0 mm around the inner wall of the hole to be a through hole and the hole to be a through hole.
For step f and subsequent steps, a method of forming a permanent resist, which is a known technique, and treating the exposed conductor portion by electrolysis or electroless plating is often used. However, in order to make the most of the features of the present invention, the exposed conductor It is preferable to employ electroless plating capable of plating with a uniform thickness on the part.
[0008]
A flexible substrate can be used as the substrate of the copper-clad laminate.
As the base material, polyimide film, polyester film, etc. can be used, and commercially available polyimide films include Kapton (made by DuPont, trade name) Upilex (made by Ube Industries, trade name), Espanex ( Lumirror (trade name, manufactured by Toray Industries, Inc.) can be used for Nippon Steel Chemical Co., Ltd. (trade name) and polyester film.
The base material for this copper-clad laminate is a glass-clad epoxy resin-impregnated copper-clad laminate, a glass nonwoven paper epoxy resin-impregnated copper-clad laminate used for ordinary wiring boards, a roughened ceramic surface, and a copper layer on the surface. A ceramic copper-clad laminate or the like on which is formed can be used.
As the copper foil of the copper-clad laminate of the present invention, any kind of rolled copper foil and electrolytic copper foil can be used. The thinner the thickness, the finer the circuit can be formed. In terms of price, a preferable range is 5 μm to 35 μm. There is no commercially available copper foil having a thickness of less than 5 μm, and even if it is produced in-house, a plating apparatus or the like is required, which is not economical, and the handling property is extremely poor. Although the method of the present invention can be used for a film having a thickness exceeding 35 μm, it is difficult to form a fine circuit and there are few merits.
Hereinafter, the present invention will be described based on examples, but the present invention is not limited thereto.
[0009]
【Example】
Example 1
Step a
As shown in FIG. 1 (a), the thickness of MCL-E679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a glass epoxy resin-impregnated copper-clad laminate with 12 μm
Step b
As shown in FIG. 1 (b), the perforated copper-clad laminate was washed thoroughly with water, and then immersed in a conditioner CLD-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 40 ° C. for 5 minutes. Surface treatment is performed, followed by immersion in CUST-201B (trade name, manufactured by Hitachi Chemical Co., Ltd.), a sensitizer for electroless plating, at a liquid temperature of 50 ° C. for 40 minutes. An L-59 plating solution (trade name, manufactured by Hitachi Chemical Co., Ltd.) as a solution was formed at a temperature of 60 ° C. for 30 minutes as a layer 3 for receiving electroplating with a thickness of 0.5 μm.
Process c
As shown in FIG. 1 (c), a photech H-N640 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for plating resist with the through-holes and surrounding lands removed, is rolled at a roll temperature of 100 ° C. Lamination is performed at a feed rate of 1.0 m / min, UV light is exposed through a photomask at 70 mJ / cm 2 , sprayed with a 1.1 wt% sodium carbonate solution and developed to form a plating resist 4 did.
Step d
As shown in FIG. 1D, the following nickel electroplating was performed under the conditions of a liquid temperature of 55 ° C., a time of 6 minutes, and a current density of 4 A / dm 2 to form a nickel plating layer 5 having a thickness of 5 μm.
(Composition of electro nickel plating solution)
Nickel ............ 60g / l
Nickel chloride ... 35g / l
Shelf acid ... 35g / l
Process e
As shown in FIG. 1 (e), the plating resist 4 was peeled off with a 3% weight potassium hydroxide solution.
Process f
As shown in FIG. 1 (f), in order to protect the plating layer 3 on the inner wall of the through-hole hole and to form an etching resist for forming necessary wiring, Photec H-N920, which is a dry film for etching resist, is used. (Trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated at a roll temperature of 100 ° C. and a roll feed speed of 1.0 m / min, and exposed to ultraviolet rays at 50 mJ / cm 2 through a photomask. An etching resist 7 was formed by spraying with a 1 wt% sodium carbonate solution and developing.
Process g
As shown in FIG. 1 (g), the copper foil portion where the etching resist 7 was not formed was selectively removed by spraying a cupric chloride / hydrochloric acid solution.
Process h
As shown in FIG. 1 (h), the etching resist 7 was peeled off with a 3% weight potassium hydroxide solution.
[0010]
Example 2
Instead of step b in Example 1, the following steps were used.
A layer 3 for receiving electroplating was formed on the inner wall of the hole to be a through hole as follows.
After thoroughly washing the perforated copper-clad laminate with black hole cleaner SP-6800 (trade name, manufactured by MEC Co., Ltd.) for 1 minute at room temperature to remove oils and fats, black hole conditioner SP -6560 (MEC Co., Ltd., trade name) soaked at room temperature for 3 minutes to form a graphite particle layer, pickled with 10 wt% sulfuric acid, washed with water to form a uniform graphite layer as a whole, After drying and fixing, washing with water and drying, the product was immersed in separator SP-6800 (trade name, manufactured by MEC Co., Ltd.) for 3 minutes at room temperature to remove excess graphite on the copper surface.
[0011]
Comparative Example 1
Step a
As shown in FIG. 2 (a), the thickness of MCL-E679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a glass epoxy resin-impregnated copper-clad laminate with 12 μm
Step b
As shown in Fig. 2 (b), the perforated copper-clad laminate was thoroughly washed with water, and then immersed in conditioner CLD-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 40 ° C for 5 minutes. Surface treatment, and then immersed in CUST-201B (trade name, manufactured by Hitachi Chemical Co., Ltd.), a sensitizer for electroless plating, at a liquid temperature of 50 ° C. for 40 minutes. An L-59 plating solution (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating solution, was formed at a temperature of 60 ° C. for 30 minutes to form a 0.5 μm thick copper plating as a layer for receiving electroplating.
Process c
As shown in FIG. 2 (c), Photec H-N920, which is a dry film for etching resist, is used to protect the plating layer 3 on the inner wall of the through-hole hole and to form an etching resist for forming necessary wiring. (Trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated at a roll temperature of 100 ° C. and a roll feed rate of 1.0 m / min, and exposed to UV light at 50 mj / cm 2 through a photomask. An etching resist 6 was formed by spraying with a 1% by weight sodium carbonate solution and developing.
Step d
As shown in FIG. 2 (d), the barrel portion where the etching resist 4 was not formed was selectively removed by spraying a cupric chloride / hydrochloric acid solution.
Process e
As shown in FIG. 2 (e), the following nickel electroplating was performed under conditions of a liquid temperature of 55 ° C., a time of 6 minutes, and a current density of 4 A / dm 2 to form a nickel plating layer 5 having a thickness of 5 μm.
(Composition of electro nickel plating solution)
Nickel ............ 60g / l
Nickel chloride ... 35g / l
Shelf acid ... 35g / l
Table 1 and FIGS. 3 and 4 show the pattern wiring density and the wiring thickness variation accuracy of the example and the comparative example described above.
[0012]
[Table 1]
The measurement method and test method used in the examples of the present invention will be described below.
Sample preparation Samples were 500 mm × 500 mm in size, and 20 samples were prepared.
Wiring was prepared by placing each of the 30 μm / 30 μm lines shown in FIG. 5 with plating leads all evenly arranged on the panel and by each method.
Measurement Method For measuring the conductor thickness, the height from the surface where the base material and the conductor were bonded to the conductor surface was measured using a stylus type surface roughness measuring instrument.
As shown in Table 1, the thickness of the comparative example varies as much as 5 μm, but in the case of the example, it can be manufactured within a variation range of 1 μm at the maximum.
[0014]
With respect to the pattern wiring density, the method described in Japanese Patent Laid-Open No. 11-54910 requires a plating lead for electroplating, and plating is performed after the wiring is formed. In this case, a plating lead connection impossible line as shown in the figure is generated in a chip mounting area connection line in which a component mounting land exists nearby, and this line cannot be plated.
In this case, it is inevitably produced by either a method in which plating is not applied as it is or a method in which a line is deleted. In addition, although it is also conceivable to perform plating later by electroless plating, there is a problem that the plating becomes double and the plating is easily peeled off.
If the line is left unplated and the connection with the chip is made, the connection will be extremely deteriorated. If this line is deleted, the balance will deteriorate, and the connection reliability will deteriorate.
According to the method of the present invention, the electroless plating can be applied without forming a double layer by treating after the wiring is formed. In addition, in the case of the design shown in FIG. 4A, since the plated lead line cannot be extended from the front surface wiring side or the back surface wiring in the through hole inside, the wiring interval is widened and the through hole for the plating lead is formed. There are places that must be installed separately. Therefore, as shown in FIG. 4B, the wiring density may be impaired. However, according to the method of the present invention, a through hole is formed before the wiring is formed. It is not necessary and can be manufactured as shown in FIG.
[0015]
【The invention's effect】
As described above, according to the present invention, without losing the fine wiring level, no plating lead is required for the line or through hole, and the connection reliability with the surface mounting component such as a chip is not deteriorated. A high-density circuit pattern can be formed, and furthermore, a circuit board manufacturing method that does not impair the connection reliability can be provided by suppressing the fluctuation accuracy of the circuit height with high accuracy.
[Brief description of the drawings]
1A to 1H are cross-sectional views in each step of an embodiment of the present invention.
2A to 2F are cross-sectional views in each process of the conventional example.
FIG. 3 is a plan view for explaining a conventional example.
4 is a plan view for explaining the effect of the present invention (a) and a plan view for explaining a conventional example (b).
FIG. 5 is a partial plan view of a plating lead line for explaining the effect of the present invention.
[Explanation of symbols]
1. Copper foil 2. Base material 3. Layer for receiving plating 4. Plating resist 5. Nickel plating layer 6. Hole 7. Etching resist
Claims (7)
ａ：銅張り積層板にスルーホールとなる孔をあける工程
ｂ：スルーホールとなる孔の内壁に電解めっき又は無電解めっきを受け入れる層を形成する工程
ｃ：スルーホールとなる孔及びその周囲を除いて選択的にめっきレジストを塗布する工程
ｄ：電解めっき又は無電解めっきによって少なくとも孔内壁にニッケル又はその合金のめっき層を形成する工程
ｅ：めっきレジストを剥離する工程
ｆ：スルーホール孔内壁のめっき層を保護するとともに、必要な配線を形成するためのエッチングレジストを形成する工程
ｇ：エッチングレジストの形成されていない銅箔部分を選択的にエッチング除去する工程The manufacturing method of the wiring board characterized by consisting of the process of the procedure of the following ag .
a: opening a hole serving as a through hole in a copper-clad laminate b: forming a layer for receiving electrolytic plating or electroless plating on the inner wall of the hole serving as a through hole c: removing a hole serving as a through hole and its surroundings A step of selectively applying a plating resist d: a step of forming a plating layer of nickel or an alloy thereof at least on the inner wall of the hole by electrolytic plating or electroless plating e: a step of removing the plating resist f: plating of the inner wall of the through-hole hole A step of forming an etching resist for forming the necessary wiring while protecting the layer g: a step of selectively etching away a copper foil portion where the etching resist is not formed
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000027175A JP3826651B2 (en) | 2000-01-31 | 2000-01-31 | Wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000027175A JP3826651B2 (en) | 2000-01-31 | 2000-01-31 | Wiring board manufacturing method |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004323559A Division JP2005039302A (en) | 2004-11-08 | 2004-11-08 | Method of manufacturing wiring board |
| JP2004323558A Division JP2005039301A (en) | 2004-11-08 | 2004-11-08 | Wiring board |
| JP2004323560A Division JP2005039303A (en) | 2004-11-08 | 2004-11-08 | Method of manufacturing wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001217539A JP2001217539A (en) | 2001-08-10 |
| JP3826651B2 true JP3826651B2 (en) | 2006-09-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000027175A Expired - Fee Related JP3826651B2 (en) | 2000-01-31 | 2000-01-31 | Wiring board manufacturing method |
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| JP (1) | JP3826651B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281711A (en) * | 2010-06-09 | 2011-12-14 | 富士通株式会社 | Laminated circuit board and board producing method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3770895B2 (en) * | 2003-12-09 | 2006-04-26 | 新光電気工業株式会社 | Manufacturing method of wiring board using electrolytic plating |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281711A (en) * | 2010-06-09 | 2011-12-14 | 富士通株式会社 | Laminated circuit board and board producing method |
| US8669481B2 (en) | 2010-06-09 | 2014-03-11 | Fujitsu Limited | Laminated circuit board and board producing method |
Also Published As
| Publication number | Publication date |
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| JP2001217539A (en) | 2001-08-10 |
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