JP3808866B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP3808866B2 JP3808866B2 JP2003407888A JP2003407888A JP3808866B2 JP 3808866 B2 JP3808866 B2 JP 3808866B2 JP 2003407888 A JP2003407888 A JP 2003407888A JP 2003407888 A JP2003407888 A JP 2003407888A JP 3808866 B2 JP3808866 B2 JP 3808866B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- film
- semiconductor device
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1乃至図10を用いて、この発明の第1の実施形態に係る半導体装置及びその製造方法について説明する。図1は、第1の実施形態に係る半導体装置を模式的に示す断面構造図であり、半導体基板11の主表面上に4層の多層配線を設けた場合を例に挙げて示している。
n)、パラジウム(Pb)、ルテニウム(Ru)、ロジウム(Rh)、クロム(Cr)、銀(Ag)、コバルト(Co)、インジウム(In)、銅(Cu)等がある。
次に、この発明の第2の実施形態に係る半導体装置およびその製造方法について、図11乃至図15を用いて説明する。以下の説明において、第1の実施形態と重複する部分の説明を省略する。
次に、この発明の第3の実施形態に係る半導体装置およびその製造方法について、図16乃至図19を用いて説明する。図16は、第3の実施形態に係る半導体装置を模式的に示す断面構造図である。
本実施形態では上部拡散防止層61として、配線間絶縁層(キャップ絶縁層26及び絶縁層25)に対して比誘電率の高い絶縁体を用いることなく、各導電層27上、シード層28上、および下部拡散防止層29上のみに導体が形成されている。その結果、上部拡散防止層61による配線間容量の上昇を抑え、信号遅延をさらに低減することができる。
Claims (6)
- 半導体基板と、
前記半導体基板の主表面上に交互に積層された絶縁層と配線層とを備える同一のベース金属からなる多層配線構造において、
前記同一のベース金属からなる配線層の少なくとも1層は濃度が高いほど前記配線層の電流密度を低減させる添加元素を含み、前記添加元素の濃度は、前記配線層の下層側よりも上層側の方が低いこと
を特徴とする半導体装置。 - 前記添加元素の濃度は、前記ベース金属における断面積あたりの界面の長さが大きいほど高いこと
を特徴とする請求項1に記載の半導体装置。 - 前記ベース金属は、銅,アルミニウム,銀の少なくとも1つを含むこと
を特徴とする請求項1または2に記載の半導体装置。 - 前記添加元素は、Mg,Ti,Al,Sn,Pb,Ru,Rh,Cr,Ag,Co,In,Cuの少なくとも1つを含むこと
を特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。 - 前記半導体基板上に設けられ、前記多層配線中の前記配線層に選択的に接続される絶縁ゲート型電界効果トランジスタを更に具備すること
を特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。 - 前記絶縁層と配線層の間に設けられたシード層と、前記シード層の界面拡散を防止する添加元素とを更に備え、
前記添加元素の濃度は、最下層より最上層の方が低いこと
を特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003407888A JP3808866B2 (ja) | 2003-12-05 | 2003-12-05 | 半導体装置 |
US10/778,180 US6972491B2 (en) | 2003-12-05 | 2004-02-17 | Semiconductor device including multi-layered interconnection and method of manufacturing the device |
US11/250,530 US7768127B2 (en) | 2003-12-05 | 2005-10-17 | Semiconductor device including multi-layered interconnection and method of manufacturing the device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003407888A JP3808866B2 (ja) | 2003-12-05 | 2003-12-05 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005167160A JP2005167160A (ja) | 2005-06-23 |
JP3808866B2 true JP3808866B2 (ja) | 2006-08-16 |
Family
ID=34631768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003407888A Expired - Fee Related JP3808866B2 (ja) | 2003-12-05 | 2003-12-05 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US6972491B2 (ja) |
JP (1) | JP3808866B2 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI285938B (en) * | 2003-08-28 | 2007-08-21 | Fujitsu Ltd | Semiconductor device |
JP3808866B2 (ja) * | 2003-12-05 | 2006-08-16 | 株式会社東芝 | 半導体装置 |
KR100613388B1 (ko) * | 2004-12-23 | 2006-08-17 | 동부일렉트로닉스 주식회사 | 다마신법을 이용한 구리 배선층을 갖는 반도체 소자 및 그형성 방법 |
JP2007165505A (ja) * | 2005-12-13 | 2007-06-28 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US20070187828A1 (en) * | 2006-02-14 | 2007-08-16 | International Business Machines Corporation | Ild layer with intermediate dielectric constant material immediately below silicon dioxide based ild layer |
JP2012094928A (ja) * | 2006-03-07 | 2012-05-17 | Renesas Electronics Corp | 半導体装置 |
JP4959267B2 (ja) * | 2006-03-07 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置および電気ヒューズの抵抗値の増加方法 |
JP5065695B2 (ja) * | 2007-02-01 | 2012-11-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5628470B2 (ja) | 2007-12-04 | 2014-11-19 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP5253872B2 (ja) * | 2008-04-17 | 2013-07-31 | 株式会社東芝 | 半導体集積回路装置 |
JP5502339B2 (ja) * | 2009-02-17 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5485333B2 (ja) * | 2012-05-10 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8765602B2 (en) | 2012-08-30 | 2014-07-01 | International Business Machines Corporation | Doping of copper wiring structures in back end of line processing |
US20140061915A1 (en) * | 2012-08-30 | 2014-03-06 | International Business Machines Corporation | Prevention of thru-substrate via pistoning using highly doped copper alloy seed layer |
US10211097B2 (en) * | 2015-12-30 | 2019-02-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
KR102331763B1 (ko) * | 2017-06-22 | 2021-11-26 | 현대자동차주식회사 | 내비게이션 장치와 연동하여 자율 주차와 자율 주행을 제어하는 장치 및 방법 |
EP3514828B1 (en) | 2018-01-19 | 2021-08-25 | Socionext Inc. | Semiconductor integrated circuitry |
KR102627459B1 (ko) * | 2018-08-31 | 2024-01-22 | 삼성전자주식회사 | 다층 도선을 포함하는 집적 회로 |
US11532550B2 (en) * | 2019-07-31 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure having a multi-layer conductive feature and method making the same |
US11113443B1 (en) * | 2020-06-12 | 2021-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with thicker metal lines on lower metallization layer |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11186273A (ja) | 1997-12-19 | 1999-07-09 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
DE60125338T2 (de) * | 2000-03-07 | 2007-07-05 | Asm International N.V. | Gradierte dünne schichten |
JP4117101B2 (ja) * | 2000-08-30 | 2008-07-16 | 株式会社ルネサステクノロジ | 半導体装置とその製造方法 |
JP4118029B2 (ja) * | 2001-03-09 | 2008-07-16 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
JP2003257979A (ja) | 2001-12-25 | 2003-09-12 | Nec Electronics Corp | 銅配線構造およびその製造方法 |
JP4230334B2 (ja) | 2003-10-31 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7244673B2 (en) * | 2003-11-12 | 2007-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration film scheme for copper / low-k interconnect |
JP3808866B2 (ja) * | 2003-12-05 | 2006-08-16 | 株式会社東芝 | 半導体装置 |
-
2003
- 2003-12-05 JP JP2003407888A patent/JP3808866B2/ja not_active Expired - Fee Related
-
2004
- 2004-02-17 US US10/778,180 patent/US6972491B2/en not_active Expired - Fee Related
-
2005
- 2005-10-17 US US11/250,530 patent/US7768127B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050121791A1 (en) | 2005-06-09 |
US7768127B2 (en) | 2010-08-03 |
JP2005167160A (ja) | 2005-06-23 |
US20060244144A1 (en) | 2006-11-02 |
US6972491B2 (en) | 2005-12-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3808866B2 (ja) | 半導体装置 | |
US8178437B2 (en) | Barrier material and process for Cu interconnect | |
US8450200B2 (en) | Method for stacked contact with low aspect ratio | |
EP1780788A1 (en) | Semiconductor device and method for manufacturing same | |
US7214594B2 (en) | Method of making semiconductor device using a novel interconnect cladding layer | |
US7470609B2 (en) | Semiconductor device and method for manufacturing the same | |
US20080232025A1 (en) | Mim capacitor and method of making same | |
JP2004527909A (ja) | 誘電体バリアフィルムを用いたダマシンプロセス | |
US7816256B2 (en) | Process for improving the reliability of interconnect structures and resulting structure | |
US20060043589A1 (en) | Electronic device and method for fabricating the same | |
US20060154464A1 (en) | Semiconductor device and a method of fabricating a semiconductor device | |
US20050023701A1 (en) | Semiconductor device and method of manufacturing the same | |
US6680542B1 (en) | Damascene structure having a metal-oxide-metal capacitor associated therewith | |
US7659626B2 (en) | Semiconductor device including a barrier metal film | |
US7932187B2 (en) | Method for fabricating a semiconductor device | |
JP2003282728A (ja) | 半導体素子及びその製造方法 | |
JP4034482B2 (ja) | 多層配線構造体及び半導体装置の製造方法 | |
KR100538748B1 (ko) | 집적 회로에서의 구리 상호 접속부 형성 방법 | |
JP2001135723A (ja) | 半導体装置及びその製造方法 | |
US20020036348A1 (en) | Semiconductor device having multi-layered wiring structure | |
KR101153224B1 (ko) | 다마신 공정에 의해 형성된 캐패시터와 금속 배선을 갖는 반도체 소자 제조방법 | |
JP2004296802A (ja) | 半導体装置およびその製造方法 | |
JP2004247337A (ja) | 半導体装置及びその製造方法 | |
JP4108189B2 (ja) | 配線構造、及びその形成方法 | |
US20230187341A1 (en) | Barrier liner free interface for metal via |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051019 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051025 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051226 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060221 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060419 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060516 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060518 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090526 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100526 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110526 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110526 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120526 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120526 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130526 Year of fee payment: 7 |
|
LAPS | Cancellation because of no payment of annual fees |