JP3727455B2 - Correlation calculation method, correlation calculation circuit, and coherent DLL circuit - Google Patents

Description

【０００１】
【発明の属する技術分野】
本発明は、ＤＳ−ＣＤＭＡ（Direct Sequence - Code Division Multiple Access:直接拡散−符号分割多元接続）方式の受信機における同期追跡回路で用いられる相関演算方法及び相関演算回路及びコヒーレントＤＬＬ回路に係り、特に伝送路推定精度が劣化した場合でも伝送品質の劣化を抑えることができる相関演算方法及び相関演算回路及びコヒーレントＤＬＬ回路に関する。
【０００２】
【従来の技術】
一般的に、ＤＳ−ＣＤＭＡ（Direct Sequence - Code Division Multiple Access:直接拡散−符号分割多元接続）方式では、受信信号の拡散符号位相と受信機の拡散符号位相との同期を保持することが重要であり、その同期を保持するための同期追跡回路としてコヒーレントＤＬＬ（Coherent Delay Locked Loop）回路が既に公知である。
【０００３】
なお、コヒーレントＤＬＬ回路の詳細は、「“ＤＳ−ＣＤＭＡ逆変調型coherent ＤＬＬ”佐和橋 衛、1995年信学会総合大会、Ｂ−４０７」に詳しく記されている。
【０００４】
まず、従来のコヒーレントＤＬＬ回路について、図５を使って説明する。図５は、従来のコヒーレントＤＬＬ回路のブロック図である。
従来のコヒーレントＤＬＬ回路は、図５に示すように、第１の相関器１と、伝送路推定器２と、第１の共役複素乗算回路３と、判定器４と、第２の相関器５と、第３の相関器６と、第１の逆変調回路７と、第２の逆変調回路８と、第２の共役複素乗算回路９と、第３の共役複素乗算回路１０と、減算器１１と、平均化回路１２と、拡散符号発生回路１３と、第１の遅延器１４と、第２の遅延器１５とから構成されている。
【０００５】
次に、従来のコヒーレントＤＬＬ回路の各部について説明する。
第１の相関器１は、受信した複素受信ベースバンド信号と、受信機が持つ拡散符号とを入力し、相関を取って相関信号を出力するものであり、この相関信号はフェージング変動による伝送路歪みを受けている可能性が高い。
【０００６】
伝送路推定器２は、第１の相関器１からの相関信号を入力し、相関信号に含まれる伝送路歪みを推定し、伝送路推定値を出力するものである。
推定方法としては、例えばフレーム内に定期的に挿入された既知のシンボルから伝送路歪みを測定し、その時系列を内挿補間することによって、全シンボルにおける伝送路歪みを推定する。
【０００７】
第１の共役複素乗算回路３は、伝送路推定器２からの推定値と、第１の相関器１からの相関信号とを入力し、双方を共役複素乗算することによって相関信号の伝送路歪みを補償し、伝送路歪みを補償した相関信号を出力するものである。
【０００８】
判定器４は、第１の共役複素乗算回路３からの伝送路歪みを補償した相関信号を入力し、予め設定されたしきい値に対する大小を判定して受信データを出力するものである。
【０００９】
第２の相関器５は、受信した複素受信ベースバンド信号と、第１の相関器１へ与えられる拡散符号位相よりもＴｃ／２（Ｔｃ：拡散符号１ビット周期）進んでいる拡散符号（以下、Ｅａｒｌｙ信号と呼ぶ）とを入力し、相関を取って相関信号を出力するものである。
【００１０】
第３の相関器６は、受信した複素受信ベースバンド信号と、第１の相関器１へ与えられる拡散符号位相よりもＴｃ／２遅れている拡散符号（以下、Ｌａｔｅ信号と呼ぶ）とを入力し、相関を取って相関信号を出力するものである。
【００１１】
第１の逆変調回路７は、第２の相関器５からの相関信号を判定器４からの判定データ（受信データ）で逆変調することにより変調成分を除去するものである。第２の逆変調回路８は、第３の相関器６からの相関信号を判定器４からの判定データ（受信データ）で逆変調することにより変調成分を除去するものである。
【００１２】
第２の共役複素乗算回路９は、伝送路推定器２からの伝送路推定値と、第１の逆変調回路７からの出力を共役複素乗算することにより、伝送路歪みを除去するものである。
第３の共役複素乗算回路１０は、伝送路推定器２からの伝送路推定値と、第２の逆変調回路８からの出力を共役複素乗算することにより、伝送路歪みを除去するものである。
【００１３】
ここで、第２の共役複素乗算回路９及び第３の共役複素乗算回路１０の構成について、図６を使って説明するが、両回路の内部構成は全く同様であるので、単に共役複素乗算回路として説明する。図６は、従来の共役複素乗算回路の構成例を示すブロック図である。
【００１４】
従来の共役複素乗算回路は、第１の乗算器２１と、第２の乗算器２２と、第３の乗算器２３と、第４の乗算器２４と、加算器２５と、加算器２６とから構成されており、いずれも乗算器及び加算器として一般的な動作を行うものである。
【００１５】
従来の共役複素乗算回路では、複素相関信号の同相成分（Ｉ成分）が第１の乗算器２１と第２の乗算器２２とに入力され、それぞれ伝送路推定値のＩ成分と直交成分（Ｑ成分）とで乗算される。
また複素相関信号のＱ成分は、第３の乗算器２３と第４の乗算器２４とに入力され、それぞれ伝送路推定値のＩ成分とＱ成分とで乗算される。
【００１６】
そして、第１の乗算器２１の出力と第４の乗算器２４の出力とが、第１の加算器２５で加算されることによって伝送路歪みを補償した相関信号のＩ成分が得られ、第３の乗算器２３の出力と第２の乗算器２２の出力が第２の加算器２６で減算されることによって伝送路歪み補償した相関信号のＱ成分が得られる。
【００１７】
このときＱ成分には相関信号が存在しないため、共役複素乗算回路からはＩ成分だけが相関信号として出力されることになる。
よって、図５では、第２の共役複素乗算回路９及び第３の共役複素乗算回路１０からの出力が複素信号ではなく実信号になっている。
【００１８】
ここで、共役複素乗算回路の作用の流れを図７，図８を用いて説明する。図７は、従来のコヒーレントＤＬＬ回路における、推定誤差がない場合の伝送路歪み補償の動作過程を示す説明図であり、図８は、従来のコヒーレントＤＬＬ回路における、推定誤差がある場合の伝送路歪み補償の動作過程を示す説明図である。
【００１９】
従来の共役複素乗算回路において、伝送路歪みがないとき、第１の逆変調回路７又は第２の逆変調回路８から出力される信号の相関ベクトルは、図７（Ａ）のように複素平面上のＩ軸上の正方向にのみ存在する。
【００２０】
これに伝送路歪みによる位相回転が加わると、逆変調回路出力の相関ベクトルは図７（Ｂ）のように位相回転量分だけ回転する。ここで位相回転量はθとする。
そして、伝送路推定器２において既知のシンボルから伝送路歪みを測定し内挿補間して得た推定誤差のない伝送路推定値（位相回転量θ）を、共役複素乗算回路で共役複素乗算すると、図７（Ｃ）のように伝送路歪みによる位相回転が補償され、相関ベクトルはＩ軸上の正方向にのみ存在することになる。
【００２１】
減算器１１は、第２の共役複素乗算回路９からのＩ成分の出力と、第３の共役複素乗算回路１０からのＩ成分の出力を減算し、受信ベースバンド信号の拡散符号位相と受信機の拡散符号位相との位相差を出力するものである。
【００２２】
平均化回路１２は、減算器１１から出力される位相差を平均化することにより、雑音による急激な変動を低減するものである。
【００２３】
拡散符号発生回路１３は、平均化回路１２から得られた平均化された位相差を入力して、当該位相差がなくなるように、拡散符号を発生させるクロックタイミングを調整しながら拡散符号を発生させるものであり、この信号が前述したＥａｒｌｙ信号に相当する。
【００２４】
第１の遅延器１４は、拡散符号発生回路１３から出力された拡散符号をＴｃ／２遅らせて出力するものである。
第２の遅延器１５は、第１の遅延器１４から出力されたＴｃ／２遅延した拡散符号を更にＴｃ／２遅延させて出力するものであり、この信号が前述したＬａｔｅ信号に相当する。
【００２５】
次に、従来のコヒーレントＤＬＬ回路の動作について、図５を使って説明する。
従来のコヒーレントＤＬＬ回路の動作は、受信した複素受信ベースバンド信号が、第１の相関器１及び第２の相関器５及び第３の相関器６に入力される。
【００２６】
そして、第１の相関器１において複素受信ベースバンド信号は、第１の遅延器１４から出力された拡散符号との相関がとられ、相関信号が伝送路推定器２及び第１の共役複素乗算回路３に入力される。
【００２７】
そして、第１の相関器１からの相関信号は、フェージング変動による伝送路歪みを受けており、伝送路推定器２で伝送路歪みが推定され、伝送路推定値が第１の共役複素乗算回路３及び第２の共役複素乗算回路９及び第３の共役複素乗算回路１０に入力される。
【００２８】
そして、第１の共役複素乗算回路３で伝送路推定器２からの伝送路推定値と、第１の相関器からの相関信号とが共役複素乗算され、相関信号の伝送路歪みを補償した相関信号が判定器４で判定されて受信データが出力される。
【００２９】
一方、複素受信ベースバンド信号は、第２の相関器５で、拡散符号発生回路１３から出力されたＥａｒｌｙ信号（第１の相関器１へ与えられる拡散符号位相よりもＴｃ／２進んでいる拡散符号）と相関がとられ、この相関信号には、位相変調成分と伝送路歪みによる位相回転が生じているために、第１の逆変調回路７において判定器４からの判定データで逆変調することにより変調成分が除去され、更に第２の共役複素乗算回路９で伝送路推定器２からの伝送路推定値と共役複素乗算することにより、伝送路歪みを除去したＩ成分の信号が出力される。
【００３０】
また、同様に複素受信ベースバンド信号は、第３の相関器６で第２の遅延器１５から出力されたＬａｔｅ信号（第１の相関器１へ与えられる拡散符号位相よりもＴｃ／２遅れている拡散符号）と相関がとられ、この相関信号には、位相変調成分と伝送路歪みによる位相回転が生じているために、第２の逆変調回路８において判定器４からの判定データで逆変調することにより変調成分を除去し、更に第３の共役複素乗算回路１０で伝送路推定器２からの伝送路推定値と共役複素乗算することにより、伝送路歪みを除去したＩ成分の信号が出力される。
【００３１】
そして、減算器１１で第２の共役複素乗算回路９からのＩ成分の出力と、第３の共役複素乗算回路１０からのＩ成分の出力とが減算され、受信ベースバンド信号の拡散符号位相と受信機の拡散符号位相との位相差が出力される。この位相差には雑音による誤差が含まれているため、平均化回路１２で平均化されて雑音による急激な変動が低減され、拡散符号発生回路１３では、平均化回路１２から得られた位相差により、位相差がなくなる様に発生のクロックタイミングが調整されて、拡散符号が発生される。
【００３２】
そして、拡散符号発生回路１３で発生されて出力された拡散符号は、Ｅａｒｌｙ信号として第２の相関器５に入力されて相関に用いられると共に、第１の遅延器１４でＴｃ／２遅らされ、当該拡散符号が受信機が持つ拡散符号として第１の相関器１に入力されて相関に用いられると共に、第２の遅延器１５で更にＴｃ／２遅らされ、当該拡散符号がＬａｔｅ信号として第３の相関器６に入力されて相関に用いられることになる。
【００３３】
【発明が解決しようとする課題】
しかしながら、上記従来のコヒーレントＤＬＬ回路では、伝送路推定精度が劣化したとき、補償誤りが生じるため、伝送品質が劣化するいう問題点があった。
【００３４】
例えば、図８（Ａ）のようにフェージング変動による位相回転量（伝送路推定値）を誤ってφと推定したとき、その伝送路歪み補償は図８（Ｂ）のようになり、補償結果は図８（Ｃ）のようになり、伝送路補償した相関信号のベクトルはＩ軸上だけでなくＱ軸上にも漏れ込んでしまう。
【００３５】
このため相関信号のＩ成分だけで位相差を求めると、図７（Ｃ）のような本来の相関信号エネルギーが得られないため位相差に誤差が生じる。このため拡散符号発生回路で発生する拡散符号の位相が、受信ベースバンド信号のチップタイミングに対して誤差を有し、逆拡散の際のジッタが大きくなり、復調後の受信データの品質が劣化するという問題点があった。
【００３６】
本発明は上記実情に鑑みて為されたもので、伝送路推定精度が劣化したときの伝送品質を改善できる相関演算方法及び相関演算回路及びコヒーレントＤＬＬ回路を提供することを目的とする。
【００３７】
【課題を解決するための手段】
上記従来例の問題点を解決するための請求項１記載の発明は、相関演算方法において、複素相関信号の同相成分と、前記複素相関信号の直交成分の絶対値若しくは自乗値とを加算した信号を相関出力信号とすることを特徴としており、相関信号の同相成分に、当該相関信号の直交成分の絶対値若しくは自乗値を加算することによって、推定誤差により発生する相関信号の直交成分を同相成分に盛り込むことになり、推定誤差を補償できる。
【００３８】
上記従来例の問題点を解決するための請求項２記載の発明は、相関演算回路において、
受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の同相成分とを乗算する第１の乗算器と、
受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の直交成分とを乗算する第２の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の同相成分とを乗算する第３の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の直交成分とを乗算する第４の乗算器と、
前記第１の乗算器の出力と前記第４の乗算器の出力とを加算する第１の加算器と、
前記第２の乗算器の出力と前記第３の乗算器の出力との差を演算する第２の加算器と、
前記第２の加算器の出力を絶対値化する絶対値回路と、
前記第１の加算器の出力と前記絶対値回路の出力とを加算し、相関信号として出力する第３の加算器とを有することを特徴としており、
第１の加算器から出力される伝送路歪みを補償した相関信号の同相成分に、絶対値回路のから出力される当該相関信号の直交成分の絶対値を加算することによって、推定誤差により発生する相関信号の直交成分を同相成分に盛り込むことになり、推定誤差を補償できる。
【００３９】
上記従来例の問題点を解決するための請求項３記載の発明は、相関演算回路において、
受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の同相成分とを乗算する第１の乗算器と、
受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の直交成分とを乗算する第２の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の同相成分とを乗算する第３の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の直交成分とを乗算する第４の乗算器と、
前記第１の乗算器の出力と前記第４の乗算器の出力とを加算する第１の加算器と、
前記第２の乗算器の出力と前記第３の乗算器の出力との差を演算する第２の加算器と、
前記第２の加算器の出力を自乗する自乗演算回路と、
前記第１の加算器の出力と前記自乗演算回路の出力とを加算し、相関信号として出力する第３の加算器とを有することを特徴としており、
第１の加算器から出力される伝送路歪みを補償した相関信号の同相成分に、自乗演算回路のから出力される当該相関信号の直交成分の自乗値を加算することによって、推定誤差により発生する相関信号の直交成分を同相成分に盛り込むことになり、推定誤差を補償できる。
【００４０】
上記従来例の問題点を解決するための請求項４記載の発明は、コヒーレントＤＬＬ回路において、
受信ベースバンド信号と受信機の拡散符号との相関をとって相関信号を出力する第１の相関器と、
前記相関信号から伝送路歪みを推定し、伝送路推定値を出力する伝送路推定器と、
前記相関信号と前記伝送路推定値とを共役複素乗算して出力する共役複素乗算回路と、
前記共役複素乗算回路からの出力を判定して受信データを出力する判定器と、
前記受信ベースバンド信号と前記拡散符号より１／２周期進んでいる拡散符号との相関をとって相関信号を出力する第２の相関器と、
前記第２の相関器からの相関信号を前記受信データで逆変調する第１の逆変調回路と、
前記第１の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第１の相関演算回路と、
前記受信ベースバンド信号と前記拡散符号より１／２周期遅れている拡散符号との相関をとって相関信号を出力する第３の相関器と、
前記第３の相関器からの相関信号を前記受信データで逆変調する第２の逆変調回路と、
前記第２の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第２の相関演算回路と、
前記第１の相関演算回路の出力と、前記第２の相関演算回路の出力とを減算して位相差を出力する減算器と、
前記位相差を平均化する平均化回路と、
前記平均化回路から出力される位相差に従って、前記位相差が無くなるように発生タイミングを調整しながら拡散符号を発生させ、前記第２の相関器に１／２周期進んでいる拡散符号として供給する拡散符号発生回路と、
前記拡散符号発生回路からの拡散符号を１／２周期遅らせ、前記第１の相関器に受信機の拡散符号として供給する第１の遅延器と、
前記第１の遅延器からの拡散符号を１／２周期遅らせ、前記第３の相関器に１／２周期遅れている拡散符号として供給する第２の遅延器とを備え、
前記第１の相関演算回路と前記第２の相関演算回路を、請求項１記載の相関演算回路で構成したことを特徴としており、
受信ベースバンド信号と１／２周期進んだ拡散符号との相関信号、及び受信ベースバンド信号と１／２周期遅れた拡散符号との相関信号に含まれる推定誤差を、相関信号の同相成分に直交成分の絶対値を加算することによって補償できる。
【００４１】
上記従来例の問題点を解決するための請求項５記載の発明は、コヒーレントＤＬＬ回路において、
受信ベースバンド信号と受信機の拡散符号との相関をとって相関信号を出力する第１の相関器と、
前記相関信号から伝送路歪みを推定し、伝送路推定値を出力する伝送路推定器と、
前記相関信号と前記伝送路推定値とを共役複素乗算して出力する共役複素乗算回路と、
前記共役複素乗算回路からの出力を判定して受信データを出力する判定器と、
前記受信ベースバンド信号と前記拡散符号より１／２周期進んでいる拡散符号との相関をとって相関信号を出力する第２の相関器と、
前記第２の相関器からの相関信号を前記受信データで逆変調する第１の逆変調回路と、
前記第１の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第１の相関演算回路と、
前記受信ベースバンド信号と前記拡散符号より１／２周期遅れている拡散符号との相関をとって相関信号を出力する第３の相関器と、
前記第３の相関器からの相関信号を前記受信データで逆変調する第２の逆変調回路と、
前記第２の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第２の相関演算回路と、
前記第１の相関演算回路の出力と、前記第２の相関演算回路の出力とを減算して位相差を出力する減算器と、
前記位相差を平均化する平均化回路と、
前記平均化回路から出力される位相差に従って、前記位相差が無くなるように発生タイミングを調整しながら拡散符号を発生させ、前記第２の相関器に１／２周期進んでいる拡散符号として供給する拡散符号発生回路と、
前記拡散符号発生回路からの拡散符号を１／２周期遅らせ、前記第１の相関器に受信機の拡散符号として供給する第１の遅延器と、
前記第１の遅延器からの拡散符号を１／２周期遅らせ、前記第３の相関器に１／２周期遅れている拡散符号として供給する第２の遅延器とを備え、
前記第１の相関演算回路と前記第２の相関演算回路を、請求項２記載の相関演算回路で構成したことを特徴としており、
受信ベースバンド信号と１／２周期進んだ拡散符号との相関信号、及び受信ベースバンド信号と１／２周期遅れた拡散符号との相関信号に含まれる推定誤差を、相関信号の同相成分に直交成分の自乗値を加算することによって補償できる。
【００４２】
【発明の実施の形態】
請求項に係る発明について、その実施の形態を図面を参照しながら説明する。
本発明に係る相関演算方法及び相関演算回路及びコヒーレントＤＬＬ回路は、受信ベースバンド信号の複素相関信号と伝送路推定値との共役複素乗算後に、演算結果の同相成分と、直交成分の絶対値又は自乗値とを加算して伝送路推定値の推定誤差を補償し、受信ベースバンド信号の拡散符号位相と受信機の拡散符号位相との位相差を求めるものなので、伝送路推定精度が劣化したときの伝送品質を改善できるものである。
【００４３】
まず、本発明に係るコヒーレントＤＬＬ回路の構成について図１を使って説明する。図１は、本発明に係るコヒーレントＤＬＬ回路の構成ブロック図である。尚、図５と同様の構成をとる部分については同一の符号を付して説明する。
【００４４】
本発明のコヒーレントＤＬＬ回路（本回路）は、従来のコヒーレントＤＬＬ回路と同様の部分として、第１の相関器１と、伝送路推定器２と、第１の共役複素乗算回路（但し、本回路では共役複素乗算回路が１つであるので単に共役複素乗算回路と呼ぶ）３と、判定器４と、第２の相関器５と、第３の相関器６と、第１の逆変調回路７と、第２の逆変調回路８と、減算器１１と、平均化回路１２と、拡散符号発生回路１３と、第１の遅延器１４と、第２の遅延器１５とから構成され、更に本発明の特徴部分として、従来の第２の共役複素乗算回路９の代わりに第１の相関演算回路１６が、また従来の第３の共役複素乗算回路１０の代わりに第２の相関演算回路１７が設けられている。
【００４５】
次に、本回路の各部について説明するが、従来と同様の構成部分はその詳細も従来と全く同様であるので説明を省略し、本回路における特徴部分である第１の相関演算回路１６及び第２の相関演算回路１７だけについて説明する。
【００４６】
第１の相関演算回路１６及び第２の相関演算回路１７は、各々第１の逆変調回路７及び第２の逆変調回路８からの出力と、伝送路推定器２から出力された伝送路推定値とを共役複素乗算し、更に演算結果のＩ成分と、Ｑ成分の絶対値又は自乗値との加算結果を出力するものである。
【００４７】
ここで、第１の相関演算回路１６及び第２の相関演算回路１７の第１の構成例について、図２を使って説明するが、両回路の構成は全く同様であるので、単に相関演算回路として説明する。図２は、本発明の相関演算回路の第１の構成例を示すブロック図である。尚、図６と同様の構成をとる部分については同一の符号を付して説明する。
【００４８】
本発明の相関演算回路の第１の構成例は、図２に示すように、従来の第２の共役複素乗算回路９及び第３の共役複素乗算回路１０と同様の部分として、第１の乗算器２１と、第２の乗算器２２と、第３の乗算器２３と、第４の乗算器２４と、加算器２５と、加算器２６とから構成されており、更に本発明の特徴部分として、新たに第３の加算器２７と、絶対値回路２８とが設けられている。
【００４９】
ここで、従来の共役複素乗算回路と同様の構成部分はその内容も従来と全く同様であるので説明を省略し、特徴部分についてのみ説明する。
【００５０】
絶対値回路２８は、第２の加算器２６の出力である伝送路歪み補償後の相関信号のＱ成分を絶対値化して出力する一般的な絶対値回路である。
【００５１】
第３の加算器２７は、第１の加算器２５の出力である伝送路歪み補償後の相関信号のＩ成分と、絶対値回路２７の出力である伝送路歪み補償後の相関信号のＱ成分の絶対値とを加算（合成）する一般的な加算器である。
【００５２】
次に、本発明の相関演算回路の第１の構成例における動作について、図２を用いて説明する。
図２において、相関信号のＩ成分は、第１の乗算器２１と第２の乗算器２２とに入力され、それぞれ伝送路推定値のＩ成分とＱ成分とで乗算され、また相関信号のＱ成分は、第３の乗算器２３と第４の乗算器２４とに入力され、それぞれ伝送路推定値のＩ成分とＱ成分とで乗算される点は、従来の共役複素乗算回路と同様である。
【００５３】
そして、第１の乗算器２１の出力と第４の乗算器２４の出力が第１の加算器２５で加算されて伝送路歪み補償した相関信号のＩ成分が得られ、第３の乗算器２３の出力と第２の乗算器２２の出力が第２の加算器２６で減算されて伝送路歪み補償した相関信号のＱ成分が得られ、更に本発明の特徴部分として絶対値回路２８でＱ成分が絶対値化される。
【００５４】
そして、第３の加算器２７で伝送路歪み補償した相関信号のＩ成分に絶対値化された伝送路歪み補償した相関信号のＱ成分が加えられることにより、伝送路推定値の推定誤差が補償され、本来の伝送路歪み補償した相関信号エネルギーが得られることになる。
【００５５】
次に、本発明の相関演算回路の第２の構成例について、図３を使って説明する。図３は、本発明の相関演算回路の第２の構成例を示すブロック図である。尚、図２と同様の構成をとる部分については同一の符号を付して説明する。
【００５６】
本発明の相関演算回路の第２の構成例は、図３に示すように、第１の構成例と同様の部分として、第１の乗算器２１と、第２の乗算器２２と、第３の乗算器２３と、第４の乗算器２４と、加算器２５と、加算器２６と、第３の加算器２７とから構成されており、更に本発明の特徴部分として、第１の構成例の絶対値回路２８の代わりに自乗演算回路２９が設けられている。
【００５７】
ここで、第１の構成例と同様の構成部分は従来と全く同様であるので説明を省略し、特徴部分についてのみ説明する。
自乗演算回路２９は、第２の加算器２６の出力である伝送路歪み補償後の相関信号のＱ成分を自乗して出力する一般的な自乗演算回路である。
【００５８】
尚、第３の加算器２７では、第１の加算器２５の出力である伝送路歪み補償後の相関信号のＩ成分と、自乗演算回路２９の出力である伝送路歪み補償後の相関信号のＱ成分の自乗値とを加算（合成）するようになっている。
【００５９】
次に、本発明の相関演算回路の第２の構成例における動作について、図３を用いて説明するが、動作は第１の構成例とほぼ同様であり、異なる点は、第２の加算器２６から得られる伝送路歪み補償した相関信号のＱ成分が自乗演算回路２９で自乗される点であり、第３の加算器２７で伝送路歪み補償した相関信号のＩ成分に伝送路歪み補償した相関信号のＱ成分の自乗値が加えられることにより、伝送路推定値の推定誤差が補償され、本来の伝送路歪み補償した相関信号エネルギーが得られることになる。
【００６０】
次に、本発明の相関演算回路の作用の流れを図４を用いて説明する。図４は、本発明における推定誤差がある場合の伝送路歪み補償の動作過程を示す説明図である。
【００６１】
図８で説明したように、推定精度が劣化すると、伝送路歪みを補償した相関信号は、図８（Ｃ）のように本来のＩ成分に存在するだけでなく、Ｑ成分にも相関信号が漏れ込んでしまうので、本発明では、図４（Ｃ）のように、漏れ込んだＱ成分の絶対値又は自乗値をＩ成分に加えることで、推定誤差による劣化を補償している。
【００６２】
ここで、Ｑ成分の絶対値を加算するのは、Ｑ成分が図８（Ｃ）のように負の値であるとき、そのままＱ成分をＩ成分に加えると、合成後のＩ成分が合成前に比べて小さくなり、かえって劣化してしまうからであり、自乗値の場合はこの心配がない。
【００６３】
次に、本発明のコヒーレントＤＬＬ回路の動作について、図１を使って説明するが、受信した複素受信ベースバンド信号が、第１の相関器１で相関が取られ、伝送路推定器２で伝送路歪みが推定され、第１の共役複素乗算回路３で伝送路推定器２からの伝送路推定値と、第１の相関器からの相関信号とが共役複素乗算され、相関信号の伝送路歪みを補償した相関信号が判定器４で判定されて受信データが出力される点は従来と同様である。
【００６４】
また、複素受信ベースバンド信号が、第２の相関器５で、拡散符号発生回路１３から出力されたＥａｒｌｙ信号（第１の相関器１へ与えられる拡散符号位相よりもＴｃ／２進んでいる拡散符号）と相関がとられ、第１の逆変調回路７において判定器４からの判定データで逆変調することにより変調成分が除去される点も従来と同様である。
【００６５】
また、同様に複素受信ベースバンド信号が、第３の相関器６で第２の遅延器１５から出力されたＬａｔｅ信号（第１の相関器１へ与えられる拡散符号位相よりもＴｃ／２遅れている拡散符号）と相関がとられ、第２の逆変調回路８において判定器４からの判定データで逆変調することにより変調成分が除去される点も従来と同様である。
【００６６】
そして、本発明のコヒーレントＤＬＬ回路の動作の特徴部分として、第１の逆変調回路７において判定器４からの判定データで逆変調された相関信号は、第１の相関演算回路１６で伝送路推定値と共役複素乗算して伝送路歪みが除去され、更にＩ成分とＱ成分の絶対値（第１の構成例）又は自乗値（第２の構成例）とが加算されて相関出力とすることにより伝送路歪み推定誤差分を補償した出力が為される。
【００６７】
同様に、本発明のコヒーレントＤＬＬ回路の動作の特徴部分として、第２の逆変調回路８において判定器４からの判定データで逆変調された相関信号は、第２の相関演算回路１７で伝送路推定値と共役複素乗算して伝送路歪みが除去され、更にＩ成分とＱ成分の絶対値（第１の構成例）又は自乗値（第２の構成例）とが加算されて相関出力とすることにより伝送路歪み推定誤差分を補償した出力が為される。
【００６８】
そして、図１において、減算器１１は第１の相関演算回路１６と、第２の相関演算回路１７とからの出力を減算し、受信ベースバンド信号の拡散符号位相と受信機の拡散符号位相との位相差を出力し、平均化回路１２にて平均化して雑音による急激な変動を低減され、拡散符号発生回路１３では、平均化回路１２から得られた位相差により、位相差がなくなる様に発生のクロックタイミングが調整されて、拡散符号が発生される。
【００６９】
そして、拡散符号発生回路１３で発生されて出力された拡散符号は、Ｅａｒｌｙ信号として第２の相関器５に入力されて相関に用いられると共に、第１の遅延器１４でＴｃ／２遅らされ、当該拡散符号が受信機が持つ拡散符号として第１の相関器１に入力されて相関に用いられると共に、第２の遅延器１５で更にＴｃ／２遅らされ、当該拡散符号がＬａｔｅ信号として第３の相関器６に入力されて相関に用いられることになる。
【００７０】
本発明の相関演算方法では、複素受信ベースバンド信号の複素相関信号の同相成分に、当該複素相関信号の直交成分の絶対値若しくは自乗値を加算するので、推定誤差により発生した直交成分を盛り込むことにより、推定誤差を補償できる効果がある。
【００７１】
尚、直交成分の絶対値を加算する方が、自乗値を加算する場合に比べて自乗誤差が無く、特性の向上が期待できる。
【００７２】
本発明の相関演算回路の第１の構成例では、複素受信ベースバンド信号の複素相関信号と、伝送路推定器２からの伝送路推定値との共役複素乗算により、伝送路歪みを補償し、更に、絶対値回路２８で伝送路歪み補償後のＱ成分の絶対値を求め、第３の加算器２７で伝送路歪み補償後のＩ成分とＱ成分の絶対値とを加算するので、推定誤差により発生した伝送路歪み補償後のＱ成分を盛り込むことにより、推定誤差を補償できる効果がある。
【００７３】
本発明の相関演算回路の第２の構成例では、複素受信ベースバンド信号の複素相関信号と、伝送路推定器２からの伝送路推定値との共役複素乗算により、伝送路歪みを補償し、更に、絶対値回路２８で伝送路歪み補償後のＱ成分の自乗値を求め、第３の加算器２７で伝送路歪み補償後のＩ成分とＱ成分の自乗値とを加算するので、推定誤差により発生した伝送路歪み補償後のＱ成分を盛り込むことにより、推定誤差を補償できる効果がある。
【００７４】
本発明のコヒーレントＤＬＬ回路では、複素受信ベースバンド信号が、第２の相関器５で拡散符号のＥａｒｌｙ信号と相関がとられ、第１の逆変調回路７で変調成分が除去され、更に第１の相関演算回路１６で伝送路推定器２からの伝送路推定値と共役複素乗算後に、相関信号のＩ成分にＱ成分絶対値又は自乗値が加算されて推定誤差が補償され、一方、複素受信ベースバンド信号は、第３の相関器６で拡散符号のＬａｔｅ信号と相関がとられ、第２の逆変調回路８で変調成分が除去され、更に第２の相関演算回路１７で伝送路推定器２からの伝送路推定値と共役複素乗算後に、相関信号のＩ成分にＱ成分絶対値又は自乗値が加算されて推定誤差が補償され、各々推定誤差が補償された相関信号で受信ベースバンド信号の拡散符号位相と受信機の拡散符号位相との位相差が求められて、当該位相差に従って拡散符号発生タイミングが図られるので、伝送路推定値の推定誤差が発生して伝送路推定精度が劣化しても、当該誤差を補償して拡散符号を発生するため、受信データの品質の劣化を抑え、伝送品質を改善できる効果がある。
【００７５】
【発明の効果】
請求項１記載の発明によれば、複素相関信号の同相成分と、複素相関信号の直交成分の絶対値若しくは自乗値とを加算した信号を相関出力信号とする相関演算方法としているので、推定誤差により発生する相関信号の直交成分を同相成分に盛り込むことにより推定誤差を補償でき、伝送路推定精度が劣化した場合にも、伝送品質を改善できる効果がある。
【００７６】
請求項２記載の発明によれば、
第１の乗算器で受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の同相成分とを乗算した結果と、第４の乗算器で受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の直交成分とを乗算した結果とを、第１の加算器で加算して伝送路歪みを補償した相関信号の同相成分を出力し、
第２の乗算器で受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の直交成分とを乗算した結果と、第３の乗算器で受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の同相成分とを乗算した結果との差を、第２の加算器で演算して伝送路歪みを補償した相関信号の直交成分を出力し、当該直交成分を絶対値回路で絶対値化し、
第３の加算回路で第１の加算器から出力される伝送路歪みを補償した相関信号の同相成分に、絶対値回路から出力される当該相関信号の直交成分の絶対値を加算して相関信号として出力する相関演算回路としているので、
推定誤差により発生する相関信号の直交成分を同相成分に盛り込むことにより推定誤差を補償でき、伝送路推定精度が劣化した場合にも、伝送品質を改善できる効果がある。
【００７７】
請求項３記載の発明によれば、
第１の乗算器で受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の同相成分とを乗算した結果と、第４の乗算器で受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の直交成分とを乗算した結果とを、第１の加算器で加算して伝送路歪みを補償した相関信号の同相成分を出力し、
第２の乗算器で受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の直交成分とを乗算した結果と、第３の乗算器で受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の同相成分とを乗算した結果との差を、第２の加算器で演算して伝送路歪みを補償した相関信号の直交成分を出力し、当該直交成分を自乗演算回路で自乗し、
第３の加算回路で第１の加算器から出力される伝送路歪みを補償した相関信号の同相成分に、自乗演算回路から出力される当該相関信号の直交成分の自乗値を加算して相関信号として出力する相関演算回路としているので、推定誤差により発生する相関信号の直交成分を同相成分に盛り込むことにより推定誤差を補償でき、伝送路推定精度が劣化した場合にも、伝送品質を改善できる効果がある。
【００７８】
請求項４記載の発明によれば、
第１の相関器で受信ベースバンド信号と受信機の拡散符号との相関をとって相関信号を出力し、伝送路推定器で相関信号から伝送路歪みを推定し、共役複素乗算回路で相関信号と伝送路推定値とを共役複素乗算し、判定器で判定して受信データを出力し、
第２の相関器で受信ベースバンド信号と当該拡散符号より１／２周期進んでいる拡散符号との相関をとり、第１の逆変調回路で受信データを用いて逆変調し、第１の相関演算回路で、請求項１記載の相関演算回路を用いて伝送路推定値との共役複素乗算を行い、更に演算結果の同相成分に直交成分の絶対値を加算し、
第３の相関器で受信ベースバンド信号と当該拡散符号より１／２周期遅れている拡散符号との相関をとり、第２の逆変調回路で受信データを用いて逆変調し、第２の相関演算回路で、請求項１記載の相関演算回路を用いて伝送路推定値との共役複素乗算を行い、更に演算結果の同相成分に直交成分の絶対値を加算し、
減算器で第１の相関演算回路の出力と第２の相関演算回路の出力とを減算して位相差を出力し、平均化回路で平均化し、拡散符号発生回路で平均化された位相差が無くなるように発生タイミングを調整しながら拡散符号を発生させて第２の相関器に１／２周期進んでいる拡散符号として供給し、第１の遅延器で１／２周期遅らせて第１の相関器に受信機の拡散符号として供給し、更に第２の遅延器で１／２周期遅らせて第３の相関器に１／２周期遅れている拡散符号として供給するコヒーレントＤＬＬ回路としているので、
受信ベースバンド信号と１／２周期進んだ拡散符号との相関信号、及び受信ベースバンド信号と１／２周期遅れた拡散符号との相関信号に含まれる推定誤差を、相関信号の同相成分に直交成分の絶対値を加算することによって補償でき、伝送路推定精度が劣化した場合にも、伝送品質を改善できる効果がある。
【００７９】
請求項５記載の発明によれば、
第１の相関器で受信ベースバンド信号と受信機の拡散符号との相関をとって相関信号を出力し、伝送路推定器で相関信号から伝送路歪みを推定し、共役複素乗算回路で相関信号と伝送路推定値とを共役複素乗算し、判定器で判定して受信データを出力し、
第２の相関器で受信ベースバンド信号と当該拡散符号より１／２周期進んでいる拡散符号との相関をとり、第１の逆変調回路で受信データを用いて逆変調し、第１の相関演算回路で、請求項２記載の相関演算回路を用いて伝送路推定値との共役複素乗算を行い、更に演算結果の同相成分に直交成分の自乗値を加算し、
第３の相関器で受信ベースバンド信号と当該拡散符号より１／２周期遅れている拡散符号との相関をとり、第２の逆変調回路で受信データを用いて逆変調し、第２の相関演算回路で、請求項２記載の相関演算回路を用いて伝送路推定値との共役複素乗算を行い、更に演算結果の同相成分に直交成分の自乗値を加算し、
減算器で第１の相関演算回路の出力と第２の相関演算回路の出力とを減算して位相差を出力し、平均化回路で平均化し、拡散符号発生回路で平均化された位相差が無くなるように発生タイミングを調整しながら拡散符号を発生させて第２の相関器に１／２周期進んでいる拡散符号として供給し、第１の遅延器で１／２周期遅らせて第１の相関器に受信機の拡散符号として供給し、更に第２の遅延器で１／２周期遅らせて第３の相関器に１／２周期遅れている拡散符号として供給するコヒーレントＤＬＬ回路としているので、
受信ベースバンド信号と１／２周期進んだ拡散符号との相関信号、及び受信ベースバンド信号と１／２周期遅れた拡散符号との相関信号に含まれる推定誤差を、相関信号の同相成分に直交成分の自乗値を加算することによって補償でき、伝送路推定精度が劣化した場合にも、伝送品質を改善できる効果がある。
【図面の簡単な説明】
【図１】本発明に係るコヒーレントＤＬＬ回路の構成ブロック図である。
【図２】本発明の相関演算回路の第１の構成例を示すブロック図である。
【図３】本発明の相関演算回路の第２の構成例を示すブロック図である。
【図４】本発明における推定誤差がある場合の伝送路歪み補償の動作過程を示す説明図である。
【図５】従来のコヒーレントＤＬＬ回路のブロック図である。
【図６】従来の共役複素乗算回路の構成例を示すブロック図である。
【図７】従来のコヒーレントＤＬＬ回路における、推定誤差がない場合の伝送路歪み補償の動作過程を示す説明図である。
【図８】従来のコヒーレントＤＬＬ回路における、推定誤差がある場合の伝送路歪み補償の動作過程を示す説明図である。
【符号の説明】
１…第１の相関器、 ２…伝送路推定器、 ３…（第１の）共役複素乗算回路、 ４…判定器、 ５…第２の相関器、 ６…第３の相関器、 ７…第１の逆変調回路、 ８…第２の逆変調回路、 ９…第２の共役複素乗算回路、 １０…第３の共役複素乗算回路、 １１…加算器、 １２…平均化回路、 １３…拡散符号発生回路、 １４…第１の遅延器、 １５…第２の遅延器、 １６…第１の相関演算回路、 １７…第２の相関演算回路、 ２１…第１の乗算器、 ２２…第２の乗算器、 ２３…第３の乗算器、 ２４…第４の乗算器、 ２５…第１の加算器、 ２６…第２の加算器、 ２７…第３の加算器、 ２８…絶対値回路、 ２９…自乗演算回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a correlation calculation method, a correlation calculation circuit, and a coherent DLL circuit used in a synchronization tracking circuit in a DS-CDMA (Direct Sequence-Code Division Multiple Access) receiver. The present invention relates to a correlation calculation method, a correlation calculation circuit, and a coherent DLL circuit that can suppress deterioration in transmission quality even when transmission path estimation accuracy deteriorates.
[0002]
[Prior art]
In general, in DS-CDMA (Direct Sequence-Code Division Multiple Access), it is important to maintain synchronization between the spread code phase of the received signal and the spread code phase of the receiver. There is already known a coherent DLL (Coherent Delay Locked Loop) circuit as a synchronization tracking circuit for maintaining the synchronization.
[0003]
Details of the coherent DLL circuit are described in detail in ““ DS-CDMA Inverse Modulation Coherent DLL ”Mamoru Sawahashi, 1995 Shinsei Conference, B-407”.
[0004]
First, a conventional coherent DLL circuit will be described with reference to FIG. FIG. 5 is a block diagram of a conventional coherent DLL circuit.
As shown in FIG. 5, the conventional coherent DLL circuit includes a first correlator 1, a transmission path estimator 2, a first conjugate complex multiplier circuit 3, a determiner 4, and a second correlator 5. A third correlator 6, a first inverse modulation circuit 7, a second inverse modulation circuit 8, a second conjugate complex multiplier circuit 9, a third conjugate complex multiplier circuit 10, and a subtractor 11, an averaging circuit 12, a spread code generation circuit 13, a first delay device 14, and a second delay device 15.
[0005]
Next, each part of the conventional coherent DLL circuit will be described.
The first correlator 1 inputs the received complex reception baseband signal and the spreading code of the receiver, outputs a correlation signal by taking a correlation, and this correlation signal is a transmission path due to fading fluctuation. There is a high possibility of being distorted.
[0006]
The transmission path estimator 2 receives the correlation signal from the first correlator 1, estimates transmission path distortion included in the correlation signal, and outputs a transmission path estimation value.
As an estimation method, for example, channel distortion is measured from known symbols periodically inserted in a frame, and the channel distortion in all symbols is estimated by interpolating the time series.
[0007]
The first conjugate complex multiplication circuit 3 receives the estimated value from the transmission path estimator 2 and the correlation signal from the first correlator 1 and performs conjugate complex multiplication on both to perform transmission path distortion of the correlation signal. And a correlation signal with compensated transmission path distortion is output.
[0008]
The determination unit 4 receives the correlation signal compensated for the transmission path distortion from the first conjugate complex multiplication circuit 3, determines the magnitude with respect to a preset threshold value, and outputs received data.
[0009]
The second correlator 5 receives the received complex reception baseband signal and a spreading code (Tc: spreading code 1 bit period) ahead of the spreading code phase given to the first correlator 1 (hereinafter referred to as the spreading code phase). , Referred to as an Early signal), a correlation is obtained and a correlation signal is output.
[0010]
The third correlator 6 inputs the received complex reception baseband signal and a spread code (hereinafter referred to as a Late signal) delayed by Tc / 2 from the spread code phase applied to the first correlator 1. Then, the correlation is obtained and a correlation signal is output.
[0011]
The first inverse modulation circuit 7 removes a modulation component by inversely modulating the correlation signal from the second correlator 5 with the decision data (received data) from the decision unit 4. The second inverse modulation circuit 8 removes a modulation component by inversely modulating the correlation signal from the third correlator 6 with the determination data (received data) from the determiner 4.
[0012]
The second conjugate complex multiplication circuit 9 removes transmission path distortion by conjugate complex multiplication of the transmission path estimation value from the transmission path estimator 2 and the output from the first inverse modulation circuit 7. .
The third conjugate complex multiplication circuit 10 removes transmission path distortion by conjugate complex multiplication of the transmission path estimation value from the transmission path estimator 2 and the output from the second inverse modulation circuit 8. .
[0013]
Here, the configurations of the second conjugate complex multiplier circuit 9 and the third conjugate complex multiplier circuit 10 will be described with reference to FIG. 6. However, since the internal configurations of both circuits are exactly the same, the conjugate complex multiplier circuit is simply used. Will be described. FIG. 6 is a block diagram showing a configuration example of a conventional conjugate complex multiplication circuit.
[0014]
The conventional conjugate complex multiplication circuit includes a first multiplier 21, a second multiplier 22, a third multiplier 23, a fourth multiplier 24, an adder 25, and an adder 26. Both are configured to perform general operations as a multiplier and an adder.
[0015]
In the conventional conjugate complex multiplication circuit, the in-phase component (I component) of the complex correlation signal is input to the first multiplier 21 and the second multiplier 22, and the I component and the quadrature component (Q Component).
The Q component of the complex correlation signal is input to the third multiplier 23 and the fourth multiplier 24, and is multiplied by the I component and the Q component of the transmission path estimation value, respectively.
[0016]
Then, the output of the first multiplier 21 and the output of the fourth multiplier 24 are added by the first adder 25 to obtain the I component of the correlation signal compensated for the transmission path distortion. The output of the third multiplier 23 and the output of the second multiplier 22 are subtracted by the second adder 26 to obtain the Q component of the correlation signal compensated for the transmission path distortion.
[0017]
At this time, since no correlation signal exists in the Q component, only the I component is output as a correlation signal from the conjugate complex multiplication circuit.
Therefore, in FIG. 5, the outputs from the second conjugate complex multiplier circuit 9 and the third conjugate complex multiplier circuit 10 are not complex signals but real signals.
[0018]
Here, the flow of the operation of the conjugate complex multiplication circuit will be described with reference to FIGS. FIG. 7 is an explanatory diagram showing an operation process of transmission path distortion compensation when there is no estimation error in the conventional coherent DLL circuit, and FIG. 8 is a transmission path when there is an estimation error in the conventional coherent DLL circuit. It is explanatory drawing which shows the operation | movement process of distortion compensation.
[0019]
In the conventional conjugate complex multiplication circuit, when there is no transmission path distortion, the correlation vector of the signal output from the first inverse modulation circuit 7 or the second inverse modulation circuit 8 is a complex plane as shown in FIG. It exists only in the positive direction on the upper I-axis.
[0020]
When phase rotation due to transmission path distortion is added to this, the correlation vector of the inverse modulation circuit output is rotated by the amount of phase rotation as shown in FIG. Here, the amount of phase rotation is θ.
Then, when the transmission path estimator 2 measures the transmission path distortion from a known symbol and interpolates, the transmission path estimation value (phase rotation amount θ) having no estimation error is conjugate complex multiplied by the conjugate complex multiplication circuit. As shown in FIG. 7C, the phase rotation due to the transmission path distortion is compensated, and the correlation vector exists only in the positive direction on the I axis.
[0021]
The subtractor 11 subtracts the output of the I component from the second conjugate complex multiplier circuit 9 and the output of the I component from the third conjugate complex multiplier circuit 10 to obtain the spread code phase of the received baseband signal and the receiver The phase difference from the spread code phase is output.
[0022]
The averaging circuit 12 averages the phase difference output from the subtractor 11 to reduce abrupt fluctuation due to noise.
[0023]
The spreading code generation circuit 13 receives the averaged phase difference obtained from the averaging circuit 12, and generates a spreading code while adjusting the clock timing for generating the spreading code so that the phase difference is eliminated. This signal corresponds to the aforementioned Early signal.
[0024]
The first delay unit 14 delays the spreading code output from the spreading code generation circuit 13 by Tc / 2 and outputs the delayed code.
The second delay unit 15 outputs the spread code delayed by Tc / 2 output from the first delay unit 14 by further delaying by Tc / 2, and this signal corresponds to the above-mentioned Late signal.
[0025]
Next, the operation of the conventional coherent DLL circuit will be described with reference to FIG.
In the operation of the conventional coherent DLL circuit, the received complex reception baseband signal is input to the first correlator 1, the second correlator 5, and the third correlator 6.
[0026]
Then, in the first correlator 1, the complex reception baseband signal is correlated with the spreading code output from the first delay unit 14, and the correlation signal is the transmission path estimator 2 and the first conjugate complex multiplication. Input to the circuit 3.
[0027]
The correlation signal from the first correlator 1 is subjected to transmission path distortion due to fading fluctuation, the transmission path distortion is estimated by the transmission path estimator 2, and the transmission path estimated value is the first conjugate complex multiplication circuit. 3 and the second conjugate complex multiplier circuit 9 and the third conjugate complex multiplier circuit 10.
[0028]
Then, the first conjugate complex multiplication circuit 3 performs conjugate complex multiplication of the transmission path estimation value from the transmission path estimator 2 and the correlation signal from the first correlator to compensate the transmission path distortion of the correlation signal. The signal is determined by the determiner 4 and the received data is output.
[0029]
On the other hand, the complex reception baseband signal is transmitted by the second correlator 5 to the Early signal output from the spread code generation circuit 13 (spread advanced by Tc / 2 from the spread code phase given to the first correlator 1). The correlation signal is subjected to phase modulation due to the phase modulation component and transmission path distortion. Therefore, the first inverse modulation circuit 7 inversely modulates with the determination data from the determination unit 4. As a result, the modulation component is removed, and the second conjugate complex multiplication circuit 9 performs conjugate complex multiplication with the transmission channel estimation value from the transmission channel estimator 2 to output an I component signal from which transmission channel distortion has been removed. The
[0030]
Similarly, the complex reception baseband signal is delayed by Tc / 2 from the Late signal output from the second delay unit 15 by the third correlator 6 (spread code phase applied to the first correlator 1). The correlation signal has a phase rotation due to the phase modulation component and the transmission path distortion. Therefore, the second inverse modulation circuit 8 reverses the correlation signal with the determination data from the determination unit 4. The modulation component is removed by modulation, and further, the third conjugate complex multiplication circuit 10 performs conjugate complex multiplication with the transmission channel estimation value from the transmission channel estimator 2, so that the I component signal from which transmission channel distortion has been removed is obtained. Is output.
[0031]
The subtractor 11 subtracts the output of the I component from the second conjugate complex multiplier circuit 9 and the output of the I component from the third conjugate complex multiplier circuit 10 to obtain the spreading code phase of the received baseband signal and The phase difference with the spreading code phase of the receiver is output. Since this phase difference includes an error due to noise, it is averaged by the averaging circuit 12 and abrupt fluctuation due to noise is reduced. In the spread code generating circuit 13, the phase difference obtained from the averaging circuit 12 is reduced. Thus, the generated clock timing is adjusted so that the phase difference is eliminated, and a spread code is generated.
[0032]
The spread code generated and output by the spread code generation circuit 13 is input to the second correlator 5 as an Early signal and used for correlation, and is delayed by Tc / 2 by the first delay unit 14. The spreading code is input to the first correlator 1 as a spreading code of the receiver and used for correlation, and further delayed by Tc / 2 by the second delay unit 15, and the spreading code is converted into a Late signal. It is input to the third correlator 6 and used for correlation.
[0033]
[Problems to be solved by the invention]
However, the conventional coherent DLL circuit has a problem that transmission quality deteriorates because a compensation error occurs when the transmission path estimation accuracy deteriorates.
[0034]
For example, when the phase rotation amount (transmission channel estimation value) due to fading fluctuation is erroneously estimated as shown in FIG. 8A, the transmission channel distortion compensation is as shown in FIG. 8B, and the compensation result is As shown in FIG. 8C, the vector of the correlation signal compensated for the transmission path leaks not only on the I axis but also on the Q axis.
[0035]
For this reason, if the phase difference is obtained only from the I component of the correlation signal, the original correlation signal energy as shown in FIG. For this reason, the phase of the spread code generated by the spread code generation circuit has an error with respect to the chip timing of the received baseband signal, the jitter at the time of despreading increases, and the quality of the received data after demodulation deteriorates There was a problem.
[0036]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a correlation calculation method, a correlation calculation circuit, and a coherent DLL circuit that can improve transmission quality when transmission channel estimation accuracy is deteriorated.
[0037]
[Means for Solving the Problems]
The invention according to claim 1 for solving the problems of the conventional example is a signal obtained by adding the in-phase component of the complex correlation signal and the absolute value or square value of the quadrature component of the complex correlation signal in the correlation calculation method. Is used as a correlation output signal, and by adding the absolute value or square value of the quadrature component of the correlation signal to the in-phase component of the correlation signal, the quadrature component of the correlation signal generated by the estimation error is added to the in-phase component. Therefore, the estimation error can be compensated.
[0038]
The invention according to claim 2 for solving the problems of the conventional example is as follows.
A first multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A second multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the quadrature component of the transmission path estimation value;
A third multiplier that multiplies the quadrature component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A fourth multiplier for multiplying the orthogonal component of the complex correlation signal of the received baseband signal by the orthogonal component of the transmission path estimation value;
A first adder for adding the output of the first multiplier and the output of the fourth multiplier;
A second adder for computing a difference between the output of the second multiplier and the output of the third multiplier;
An absolute value circuit for converting the output of the second adder into an absolute value;
A third adder that adds the output of the first adder and the output of the absolute value circuit and outputs a correlation signal;
Generated by an estimation error by adding the absolute value of the quadrature component of the correlation signal output from the absolute value circuit to the in-phase component of the correlation signal compensated for the transmission path distortion output from the first adder. Since the quadrature component of the correlation signal is included in the in-phase component, the estimation error can be compensated.
[0039]
The invention according to claim 3 for solving the problems of the conventional example, in the correlation operation circuit,
A first multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A second multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the quadrature component of the transmission path estimation value;
A third multiplier that multiplies the quadrature component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A fourth multiplier for multiplying the orthogonal component of the complex correlation signal of the received baseband signal by the orthogonal component of the transmission path estimation value;
A first adder for adding the output of the first multiplier and the output of the fourth multiplier;
A second adder for computing a difference between the output of the second multiplier and the output of the third multiplier;
A square operation circuit that squares the output of the second adder;
A third adder that adds the output of the first adder and the output of the square calculation circuit and outputs a correlation signal;
Generated by an estimation error by adding the square value of the quadrature component of the correlation signal output from the square calculation circuit to the in-phase component of the correlation signal compensated for the transmission path distortion output from the first adder. Since the quadrature component of the correlation signal is included in the in-phase component, the estimation error can be compensated.
[0040]
The invention according to claim 4 for solving the problems of the conventional example is a coherent DLL circuit.
A first correlator that correlates the received baseband signal and the spreading code of the receiver and outputs a correlation signal;
A channel estimator that estimates channel distortion from the correlation signal and outputs a channel estimation value;
A conjugate complex multiplier circuit that conjugate-multiplies and outputs the correlation signal and the channel estimation value;
A determiner for determining an output from the conjugate complex multiplication circuit and outputting received data;
A second correlator that outputs a correlation signal by correlating the received baseband signal with a spreading code that is a half cycle ahead of the spreading code;
A first inverse modulation circuit that inversely modulates a correlation signal from the second correlator with the received data;
A first correlation operation circuit that outputs a conjugate complex multiplication of the output from the first inverse modulation circuit and the transmission path estimation value;
A third correlator that outputs a correlation signal by correlating the received baseband signal with a spreading code that is ½ cycle delayed from the spreading code;
A second inverse modulation circuit for inversely modulating the correlation signal from the third correlator with the received data;
A second correlation operation circuit that outputs a conjugate complex multiplication of the output from the second inverse modulation circuit and the transmission path estimation value;
A subtractor that subtracts the output of the first correlation calculation circuit and the output of the second correlation calculation circuit to output a phase difference;
An averaging circuit for averaging the phase difference;
In accordance with the phase difference output from the averaging circuit, a spreading code is generated while adjusting the generation timing so that the phase difference is eliminated, and the spreading code is supplied to the second correlator as a spreading code that is advanced by ½ cycle. A spreading code generation circuit;
A first delay unit that delays the spreading code from the spreading code generation circuit by a half period and supplies the delayed code to the first correlator as a spreading code of a receiver;
A second delay unit that delays the spreading code from the first delay unit by 1/2 cycle and supplies the third correlator as a spreading code delayed by 1/2 cycle;
The first correlation calculation circuit and the second correlation calculation circuit are configured by the correlation calculation circuit according to claim 1,
The estimation error included in the correlation signal between the received baseband signal and the spread code advanced by ½ period and the correlation signal between the received baseband signal and the spread code delayed by ½ period are orthogonal to the in-phase component of the correlation signal. Compensation can be achieved by adding the absolute values of the components.
[0041]
The invention according to claim 5 for solving the problems of the conventional example is a coherent DLL circuit.
A first correlator that correlates the received baseband signal and the spreading code of the receiver and outputs a correlation signal;
A channel estimator that estimates channel distortion from the correlation signal and outputs a channel estimation value;
A conjugate complex multiplier circuit that conjugate-multiplies and outputs the correlation signal and the channel estimation value;
A determiner for determining an output from the conjugate complex multiplication circuit and outputting received data;
A second correlator that outputs a correlation signal by correlating the received baseband signal with a spreading code that is a half cycle ahead of the spreading code;
A first inverse modulation circuit that inversely modulates a correlation signal from the second correlator with the received data;
A first correlation operation circuit that outputs a conjugate complex multiplication of the output from the first inverse modulation circuit and the transmission path estimation value;
A third correlator that outputs a correlation signal by correlating the received baseband signal with a spreading code that is ½ cycle delayed from the spreading code;
A second inverse modulation circuit for inversely modulating the correlation signal from the third correlator with the received data;
A second correlation operation circuit that outputs a conjugate complex multiplication of the output from the second inverse modulation circuit and the transmission path estimation value;
A subtractor that subtracts the output of the first correlation calculation circuit and the output of the second correlation calculation circuit to output a phase difference;
An averaging circuit for averaging the phase difference;
In accordance with the phase difference output from the averaging circuit, a spreading code is generated while adjusting the generation timing so that the phase difference is eliminated, and the spreading code is supplied to the second correlator as a spreading code that is advanced by ½ cycle. A spreading code generation circuit;
A first delay unit that delays the spreading code from the spreading code generation circuit by a half period and supplies the delayed code to the first correlator as a spreading code of a receiver;
A second delay unit that delays the spreading code from the first delay unit by 1/2 cycle and supplies the third correlator as a spreading code delayed by 1/2 cycle;
The first correlation calculation circuit and the second correlation calculation circuit are configured by the correlation calculation circuit according to claim 2,
The estimation error included in the correlation signal between the received baseband signal and the spread code advanced by 1/2 period and the correlation signal between the received baseband signal and the spread code delayed by 1/2 period are orthogonal to the in-phase component of the correlation signal. Compensation can be achieved by adding the square values of the components.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the claimed invention will be described with reference to the drawings.
The correlation calculation method, the correlation calculation circuit, and the coherent DLL circuit according to the present invention, after conjugate complex multiplication of the complex correlation signal of the received baseband signal and the transmission path estimation value, the in-phase component of the calculation result and the absolute value of the quadrature component or When the transmission path estimation accuracy deteriorates because the sum of the square value is added to compensate for the estimation error of the transmission path estimation value and the phase difference between the spreading code phase of the received baseband signal and the spreading code phase of the receiver is obtained. The transmission quality can be improved.
[0043]
First, the configuration of the coherent DLL circuit according to the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a coherent DLL circuit according to the present invention. In addition, the same code | symbol is attached | subjected and demonstrated about the part which has the structure similar to FIG.
[0044]
The coherent DLL circuit (this circuit) of the present invention includes a first correlator 1, a transmission path estimator 2, and a first conjugate complex multiplier circuit (provided that this circuit is the same as the conventional coherent DLL circuit). In this case, since there is only one conjugate complex multiplier circuit, it is simply called a conjugate complex multiplier circuit) 3, a determiner 4, a second correlator 5, a third correlator 6, and a first inverse modulation circuit 7. And a second inverse modulation circuit 8, a subtractor 11, an averaging circuit 12, a spread code generation circuit 13, a first delay device 14, and a second delay device 15, As a feature of the invention, a first correlation operation circuit 16 is used instead of the conventional second conjugate complex multiplication circuit 9, and a second correlation operation circuit 17 is used instead of the conventional third conjugate complex multiplication circuit 10. Is provided.
[0045]
Next, each part of this circuit will be described. However, since the details of the same components as those in the prior art are the same as those in the prior art, the description thereof will be omitted, and the first correlation operation circuit 16 and the first feature which are characteristic parts of this circuit will be omitted. Only the second correlation calculation circuit 17 will be described.
[0046]
The first correlation calculation circuit 16 and the second correlation calculation circuit 17 are respectively output from the first inverse modulation circuit 7 and second inverse modulation circuit 8 and the transmission path estimation output from the transmission path estimator 2. The value is conjugate complex-multiplied, and the addition result of the I component of the operation result and the absolute value or square value of the Q component is output.
[0047]
Here, the first configuration example of the first correlation calculation circuit 16 and the second correlation calculation circuit 17 will be described with reference to FIG. 2, but the configuration of both circuits is exactly the same. Will be described. FIG. 2 is a block diagram showing a first configuration example of the correlation calculation circuit of the present invention. Parts having the same configuration as in FIG. 6 will be described with the same reference numerals.
[0048]
As shown in FIG. 2, the first configuration example of the correlation calculation circuit according to the present invention includes the first multiplication as a part similar to the second conjugate complex multiplication circuit 9 and the third conjugate complex multiplication circuit 10 of the related art. 21, a second multiplier 22, a third multiplier 23, a fourth multiplier 24, an adder 25, and an adder 26, and further as a characteristic part of the present invention. A third adder 27 and an absolute value circuit 28 are newly provided.
[0049]
Here, since the same components as those of the conventional conjugate complex multiplication circuit are the same as those of the prior art, the description thereof will be omitted and only the characteristic portions will be described.
[0050]
The absolute value circuit 28 is a general absolute value circuit that converts the Q component of the correlation signal after the transmission path distortion compensation, which is the output of the second adder 26, into an absolute value and outputs it.
[0051]
The third adder 27 includes an I component of the correlation signal after transmission path distortion compensation, which is an output of the first adder 25, and a Q component of the correlation signal after transmission path distortion compensation, which is an output of the absolute value circuit 27. It is a general adder that adds (synthesizes) the absolute value of.
[0052]
Next, the operation in the first configuration example of the correlation calculation circuit of the present invention will be described with reference to FIG.
In FIG. 2, the I component of the correlation signal is input to the first multiplier 21 and the second multiplier 22, and is multiplied by the I component and the Q component of the transmission path estimation value, respectively. The components are input to the third multiplier 23 and the fourth multiplier 24, and are multiplied by the I component and the Q component of the transmission path estimation value, respectively, as in the conventional conjugate complex multiplier circuit. .
[0053]
Then, the output of the first multiplier 21 and the output of the fourth multiplier 24 are added by the first adder 25 to obtain the I component of the correlation signal compensated for the transmission path distortion, and the third multiplier 23. And the output of the second multiplier 22 are subtracted by the second adder 26 to obtain the Q component of the correlation signal compensated for the transmission path distortion. Further, as the characteristic part of the present invention, the Q component is obtained by the absolute value circuit 28. Is converted to an absolute value.
[0054]
Then, by adding the Q component of the correlation signal compensated for the transmission path distortion, which is absolute value, to the I component of the correlation signal compensated for the transmission path distortion by the third adder 27, the estimation error of the transmission path estimation value is compensated. Thus, the correlation signal energy compensated for the original transmission path distortion can be obtained.
[0055]
Next, a second configuration example of the correlation calculation circuit of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing a second configuration example of the correlation calculation circuit of the present invention. Parts having the same configuration as in FIG. 2 will be described with the same reference numerals.
[0056]
As shown in FIG. 3, the second configuration example of the correlation operation circuit of the present invention includes a first multiplier 21, a second multiplier 22, and a third portion as parts similar to the first configuration example. The multiplier 23, the fourth multiplier 24, the adder 25, the adder 26, and the third adder 27, and the first configuration example as a characteristic part of the present invention. Instead of the absolute value circuit 28, a square calculation circuit 29 is provided.
[0057]
Here, the same components as those in the first configuration example are exactly the same as those in the prior art, so the description thereof will be omitted and only the characteristic portions will be described.
The square calculation circuit 29 is a general square calculation circuit that squares and outputs the Q component of the correlation signal after transmission path distortion compensation, which is the output of the second adder 26.
[0058]
In the third adder 27, the I component of the correlation signal after transmission path distortion compensation, which is the output of the first adder 25, and the correlation signal after transmission path distortion compensation, which is the output of the square calculation circuit 29, are output. The square value of the Q component is added (synthesized).
[0059]
Next, the operation of the second configuration example of the correlation operation circuit of the present invention will be described with reference to FIG. 3, but the operation is substantially the same as that of the first configuration example. The difference is that the second adder 26, the Q component of the correlation signal compensated for transmission path distortion is squared by the square calculation circuit 29, and the transmission path distortion compensation is performed on the I component of the correlation signal compensated for transmission path distortion by the third adder 27. By adding the square value of the Q component of the correlation signal, the estimation error of the channel estimation value is compensated, and the correlation signal energy compensated for the original channel distortion is obtained.
[0060]
Next, the flow of the operation of the correlation calculation circuit of the present invention will be described with reference to FIG. FIG. 4 is an explanatory diagram showing an operation process of channel distortion compensation when there is an estimation error in the present invention.
[0061]
As described with reference to FIG. 8, when the estimation accuracy deteriorates, the correlation signal compensated for the transmission path distortion exists not only in the original I component as shown in FIG. 8C, but also in the Q component. In the present invention, as shown in FIG. 4C, the absolute value or square value of the leaked Q component is added to the I component to compensate for the degradation due to the estimation error.
[0062]
Here, the absolute value of the Q component is added when the Q component is a negative value as shown in FIG. 8C and the Q component is added to the I component as it is before the synthesis. This is because it is smaller than the above and deteriorates.
[0063]
Next, the operation of the coherent DLL circuit of the present invention will be described with reference to FIG. 1. The received complex reception baseband signal is correlated by the first correlator 1 and transmitted by the transmission path estimator 2. The path distortion is estimated, and the first conjugate complex multiplication circuit 3 performs conjugate complex multiplication of the transmission path estimation value from the transmission path estimator 2 and the correlation signal from the first correlator, and the transmission path distortion of the correlation signal. The correlation signal compensated for is determined by the determiner 4 and the received data is output as in the conventional case.
[0064]
In addition, the complex reception baseband signal is transmitted from the early correlator 5 by the second correlator 5 to the Early signal (spread which is advanced by Tc / 2 from the spread code phase given to the first correlator 1). In the same way as in the prior art, the first inverse modulation circuit 7 demodulates with the decision data from the decision unit 4 and removes the modulation component.
[0065]
Similarly, the complex reception baseband signal is delayed by Tc / 2 from the Late signal output from the second delay unit 15 by the third correlator 6 (spread code phase applied to the first correlator 1). In the same manner as in the prior art, the second demodulation circuit 8 removes the modulation component by performing demodulation with the decision data from the decision unit 4.
[0066]
As a characteristic part of the operation of the coherent DLL circuit of the present invention, the correlation signal inversely modulated by the determination data from the determination unit 4 in the first inverse modulation circuit 7 is subjected to transmission path estimation by the first correlation calculation circuit 16. The transmission path distortion is removed by conjugate complex multiplication with the value, and the absolute value (first configuration example) or square value (second configuration example) of the I component and Q component is added to obtain a correlation output. Thus, an output compensated for the transmission path distortion estimation error is made.
[0067]
Similarly, as a characteristic part of the operation of the coherent DLL circuit according to the present invention, the correlation signal that is inversely modulated by the determination data from the determination unit 4 in the second inverse modulation circuit 8 is transmitted through the second correlation calculation circuit 17. Transmission path distortion is removed by conjugate complex multiplication with the estimated value, and the absolute value (first configuration example) or square value (second configuration example) of the I component and Q component is added to obtain a correlation output. As a result, an output compensated for the transmission path distortion estimation error is made.
[0068]
In FIG. 1, the subtractor 11 subtracts the outputs from the first correlation calculation circuit 16 and the second correlation calculation circuit 17 to obtain the spread code phase of the received baseband signal and the spread code phase of the receiver. The phase difference is output and averaged by the averaging circuit 12 to reduce abrupt fluctuation due to noise so that the spread code generation circuit 13 eliminates the phase difference due to the phase difference obtained from the averaging circuit 12. The generated clock timing is adjusted to generate a spread code.
[0069]
The spread code generated and output by the spread code generation circuit 13 is input to the second correlator 5 as an Early signal and used for correlation, and is delayed by Tc / 2 by the first delay unit 14. The spreading code is input to the first correlator 1 as a spreading code of the receiver and used for correlation, and further delayed by Tc / 2 by the second delay unit 15, and the spreading code is converted into a Late signal. It is input to the third correlator 6 and used for correlation.
[0070]
In the correlation calculation method of the present invention, the absolute value or square value of the quadrature component of the complex correlation signal is added to the in-phase component of the complex correlation signal of the complex reception baseband signal, so that the quadrature component generated due to the estimation error is included. Thus, there is an effect that the estimation error can be compensated.
[0071]
Note that the addition of the absolute value of the orthogonal component has no square error compared to the case of adding the square value, and an improvement in characteristics can be expected.
[0072]
In the first configuration example of the correlation operation circuit of the present invention, the transmission line distortion is compensated by conjugate complex multiplication of the complex correlation signal of the complex reception baseband signal and the transmission path estimation value from the transmission path estimator 2; Further, the absolute value circuit 28 calculates the absolute value of the Q component after the transmission line distortion compensation, and the third adder 27 adds the I component and the absolute value of the Q component after the transmission line distortion compensation. Incorporating the Q component after compensation for the transmission path distortion generated by the method has the effect of compensating the estimation error.
[0073]
In the second configuration example of the correlation operation circuit of the present invention, the transmission line distortion is compensated by conjugate complex multiplication of the complex correlation signal of the complex reception baseband signal and the transmission path estimation value from the transmission path estimator 2; Further, the square value of the Q component after the transmission line distortion compensation is obtained by the absolute value circuit 28, and the I component and the square value of the Q component after the transmission line distortion compensation are added by the third adder 27. Incorporating the Q component after compensation for the transmission path distortion generated by the method has the effect of compensating the estimation error.
[0074]
In the coherent DLL circuit of the present invention, the complex reception baseband signal is correlated with the early signal of the spread code by the second correlator 5, the modulation component is removed by the first inverse modulation circuit 7, and the first After the complex complex multiplication with the transmission path estimation value from the transmission path estimator 2 in the correlation calculation circuit 16, the Q component absolute value or square value is added to the I component of the correlation signal to compensate for the estimation error, while the complex reception The baseband signal is correlated with the spread code Late signal by the third correlator 6, the modulation component is removed by the second inverse modulation circuit 8, and further the transmission path estimator by the second correlation calculation circuit 17. After the conjugate complex multiplication with the channel estimation value from 2, the Q component absolute value or the square value is added to the I component of the correlation signal to compensate the estimation error, and the received baseband signal is a correlation signal in which each estimation error is compensated. Spreading code phase and reception Therefore, even if the estimation error of the transmission channel estimation value occurs and the transmission channel estimation accuracy deteriorates, the error is calculated. Since the spreading code is generated by compensation, there is an effect that the deterioration of the quality of the received data can be suppressed and the transmission quality can be improved.
[0075]
【The invention's effect】
According to the first aspect of the invention, since the correlation calculation method uses the signal obtained by adding the in-phase component of the complex correlation signal and the absolute value or square value of the quadrature component of the complex correlation signal as the correlation output signal, the estimation error By incorporating the quadrature component of the correlation signal generated by the above into the in-phase component, the estimation error can be compensated, and the transmission quality can be improved even when the transmission path estimation accuracy deteriorates.
[0076]
According to invention of Claim 2,
The result of multiplying the in-phase component of the complex correlation signal of the received baseband signal by the first multiplier and the in-phase component of the transmission path estimation value, and the quadrature component of the complex correlation signal of the received baseband signal by the fourth multiplier The result of multiplying the quadrature component of the transmission path estimation value is added by the first adder to output the in-phase component of the correlation signal compensated for the transmission path distortion,
The result of multiplying the in-phase component of the complex correlation signal of the received baseband signal by the second multiplier and the orthogonal component of the transmission path estimation value, and the quadrature component of the complex correlation signal of the received baseband signal by the third multiplier The quadrature component of the correlation signal, which is calculated by the second adder and compensates for the channel distortion, is calculated by the difference between the result of multiplying the in-phase component of the channel estimation value by the second adder, and the quadrature component is absolute by the absolute value circuit. Valuation,
A correlation signal obtained by adding the absolute value of the quadrature component of the correlation signal output from the absolute value circuit to the in-phase component of the correlation signal compensated for the transmission path distortion output from the first adder by the third addition circuit. As a correlation calculation circuit that outputs as
By incorporating the quadrature component of the correlation signal generated by the estimation error into the in-phase component, the estimation error can be compensated, and the transmission quality can be improved even when the transmission path estimation accuracy deteriorates.
[0077]
According to invention of Claim 3,
The result of multiplying the in-phase component of the complex correlation signal of the received baseband signal by the first multiplier and the in-phase component of the transmission path estimation value, and the quadrature component of the complex correlation signal of the received baseband signal by the fourth multiplier The result of multiplying the quadrature component of the transmission path estimation value is added by the first adder to output the in-phase component of the correlation signal compensated for the transmission path distortion,
The result of multiplying the in-phase component of the complex correlation signal of the received baseband signal by the second multiplier and the orthogonal component of the transmission path estimation value, and the quadrature component of the complex correlation signal of the received baseband signal by the third multiplier The difference between the result of multiplying the in-phase component of the channel estimation value by the second adder is calculated by the second adder and the quadrature component of the correlation signal compensated for the channel distortion is output, and the quadrature component is squared by the square calculation circuit. And
A correlation signal obtained by adding the square value of the quadrature component of the correlation signal output from the square calculation circuit to the in-phase component of the correlation signal output from the first adder compensated for by the third addition circuit. Since the correlation calculation circuit that outputs the signal is used, it is possible to compensate for the estimation error by incorporating the quadrature component of the correlation signal caused by the estimation error into the in-phase component, and the transmission quality can be improved even when the channel estimation accuracy is degraded. There is.
[0078]
According to invention of Claim 4,
The first correlator correlates the received baseband signal with the spread code of the receiver and outputs a correlation signal. The transmission path estimator estimates the transmission path distortion from the correlation signal. The conjugate complex multiplication circuit correlates the correlation signal. And the transmission path estimation value are conjugate complex multiplied, and determined by the determiner to output the received data,
The second correlator correlates the received baseband signal with the spread code that is ½ cycle ahead of the spread code, and the first inverse modulation circuit performs demodulation using the received data, and the first correlation The arithmetic circuit performs conjugate complex multiplication with the transmission path estimation value using the correlation arithmetic circuit according to claim 1, and further adds the absolute value of the quadrature component to the in-phase component of the operation result,
The third correlator correlates the received baseband signal with the spreading code delayed by 1/2 cycle from the spreading code, and the second inverse modulation circuit performs inverse modulation using the received data, and the second correlation. The arithmetic circuit performs conjugate complex multiplication with the transmission path estimation value using the correlation arithmetic circuit according to claim 1, and further adds the absolute value of the quadrature component to the in-phase component of the arithmetic result,
The output of the first correlation operation circuit and the output of the second correlation operation circuit are subtracted by the subtracter to output the phase difference, averaged by the averaging circuit, and the phase difference averaged by the spreading code generation circuit is A spreading code is generated while adjusting the generation timing so as to be eliminated, supplied to the second correlator as a spreading code that is advanced by 1/2 period, and delayed by 1/2 period by the first delay unit, and the first correlation. The coherent DLL circuit is supplied as a spreading code of the receiver to the receiver, further delayed by 1/2 cycle by the second delay unit and supplied as a spreading code delayed by 1/2 cycle to the third correlator,
The estimation error included in the correlation signal between the received baseband signal and the spread code advanced by 1/2 period and the correlation signal between the received baseband signal and the spread code delayed by 1/2 period are orthogonal to the in-phase component of the correlation signal. Compensation can be achieved by adding the absolute values of the components, and transmission quality can be improved even when transmission path estimation accuracy is degraded.
[0079]
According to invention of Claim 5,
The first correlator correlates the received baseband signal with the spread code of the receiver and outputs a correlation signal. The transmission path estimator estimates the transmission path distortion from the correlation signal. The conjugate complex multiplication circuit correlates the correlation signal. And the transmission path estimation value are conjugate complex multiplied, and determined by the determiner to output the received data,
The second correlator correlates the received baseband signal with the spread code that is ½ cycle ahead of the spread code, and the first inverse modulation circuit performs demodulation using the received data, and the first correlation The arithmetic circuit performs conjugate complex multiplication with the transmission path estimation value using the correlation arithmetic circuit according to claim 2, and further adds the square value of the quadrature component to the in-phase component of the operation result,
The third correlator correlates the received baseband signal with the spreading code delayed by 1/2 cycle from the spreading code, and the second inverse modulation circuit performs inverse modulation using the received data, and the second correlation. The arithmetic circuit performs conjugate complex multiplication with the transmission path estimation value using the correlation arithmetic circuit according to claim 2, and further adds the square value of the quadrature component to the in-phase component of the operation result,
The output of the first correlation operation circuit and the output of the second correlation operation circuit are subtracted by the subtracter to output the phase difference, averaged by the averaging circuit, and the phase difference averaged by the spreading code generation circuit is A spreading code is generated while adjusting the generation timing so as to be eliminated, supplied to the second correlator as a spreading code that is advanced by 1/2 period, and delayed by 1/2 period by the first delay unit, and the first correlation. The coherent DLL circuit is supplied as a spreading code of the receiver to the receiver, further delayed by 1/2 cycle by the second delay unit and supplied as a spreading code delayed by 1/2 cycle to the third correlator,
The estimation error included in the correlation signal between the received baseband signal and the spread code advanced by 1/2 period and the correlation signal between the received baseband signal and the spread code delayed by 1/2 period are orthogonal to the in-phase component of the correlation signal. Compensation can be achieved by adding the square values of the components, and the transmission quality can be improved even when the transmission path estimation accuracy deteriorates.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of a coherent DLL circuit according to the present invention.
FIG. 2 is a block diagram showing a first configuration example of a correlation calculation circuit according to the present invention.
FIG. 3 is a block diagram showing a second configuration example of the correlation calculation circuit of the present invention.
FIG. 4 is an explanatory diagram showing an operation process of channel distortion compensation when there is an estimation error in the present invention.
FIG. 5 is a block diagram of a conventional coherent DLL circuit.
FIG. 6 is a block diagram illustrating a configuration example of a conventional conjugate complex multiplication circuit.
FIG. 7 is an explanatory diagram showing an operation process of channel distortion compensation when there is no estimation error in a conventional coherent DLL circuit.
FIG. 8 is an explanatory diagram showing an operation process of channel distortion compensation when there is an estimation error in a conventional coherent DLL circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... 1st correlator, 2 ... Transmission path estimator, 3 ... (1st) conjugate complex multiplication circuit, 4 ... Determinator, 5 ... 2nd correlator, 6 ... 3rd correlator, 7 ... DESCRIPTION OF SYMBOLS 1st inverse modulation circuit, 8 ... 2nd inverse modulation circuit, 9 ... 2nd conjugate complex multiplication circuit, 10 ... 3rd conjugate complex multiplication circuit, 11 ... Adder, 12 ... Averaging circuit, 13 ... Spreading Code generation circuit, 14 ... first delay, 15 ... second delay, 16 ... first correlation calculation circuit, 17 ... second correlation calculation circuit, 21 ... first multiplier, 22 ... second 23 ... 3rd multiplier 24 ... 4th multiplier 25 ... 1st adder 26 ... 2nd adder 27 ... 3rd adder 28 ... Absolute value circuit, 29 ... Square calculation circuit

Claims (5)

複素相関信号の同相成分と、前記複素相関信号の直交成分の絶対値若しくは自乗値とを加算した信号を相関出力信号とすることを特徴とする相関演算方法。A correlation calculation method characterized in that a signal obtained by adding an in-phase component of a complex correlation signal and an absolute value or square value of a quadrature component of the complex correlation signal is used as a correlation output signal. 受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の同相成分とを乗算する第１の乗算器と、
受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の直交成分とを乗算する第２の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の同相成分とを乗算する第３の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の直交成分とを乗算する第４の乗算器と、
前記第１の乗算器の出力と前記第４の乗算器の出力とを加算する第１の加算器と、
前記第２の乗算器の出力と前記第３の乗算器の出力との差を演算する第２の加算器と、
前記第２の加算器の出力を絶対値化する絶対値回路と、
前記第１の加算器の出力と前記絶対値回路の出力とを加算し、相関信号として出力する第３の加算器とを有することを特徴とする相関演算回路。A first multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A second multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the quadrature component of the transmission path estimation value;
A third multiplier that multiplies the quadrature component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A fourth multiplier for multiplying the orthogonal component of the complex correlation signal of the received baseband signal by the orthogonal component of the transmission path estimation value;
A first adder for adding the output of the first multiplier and the output of the fourth multiplier;
A second adder for computing a difference between the output of the second multiplier and the output of the third multiplier;
An absolute value circuit for converting the output of the second adder into an absolute value;
A correlation operation circuit comprising: a third adder that adds the output of the first adder and the output of the absolute value circuit and outputs the result as a correlation signal. 受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の同相成分とを乗算する第１の乗算器と、
受信ベースバンド信号の複素相関信号の同相成分と伝送路推定値の直交成分とを乗算する第２の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の同相成分とを乗算する第３の乗算器と、
受信ベースバンド信号の複素相関信号の直交成分と伝送路推定値の直交成分とを乗算する第４の乗算器と、
前記第１の乗算器の出力と前記第４の乗算器の出力とを加算する第１の加算器と、
前記第２の乗算器の出力と前記第３の乗算器の出力との差を演算する第２の加算器と、
前記第２の加算器の出力を自乗する自乗演算回路と、
前記第１の加算器の出力と前記自乗演算回路の出力とを加算し、相関信号として出力する第３の加算器とを有することを特徴とする相関演算回路。A first multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A second multiplier that multiplies the in-phase component of the complex correlation signal of the received baseband signal by the quadrature component of the transmission path estimation value;
A third multiplier that multiplies the quadrature component of the complex correlation signal of the received baseband signal by the in-phase component of the transmission path estimation value;
A fourth multiplier for multiplying the orthogonal component of the complex correlation signal of the received baseband signal by the orthogonal component of the transmission path estimation value;
A first adder for adding the output of the first multiplier and the output of the fourth multiplier;
A second adder for computing a difference between the output of the second multiplier and the output of the third multiplier;
A square operation circuit that squares the output of the second adder;
A correlation operation circuit comprising: a third adder that adds the output of the first adder and the output of the square operation circuit and outputs the result as a correlation signal. 受信ベースバンド信号と受信機の拡散符号との相関をとって相関信号を出力する第１の相関器と、
前記相関信号から伝送路歪みを推定し、伝送路推定値を出力する伝送路推定器と、
前記相関信号と前記伝送路推定値とを共役複素乗算して出力する共役複素乗算回路と、
前記共役複素乗算回路からの出力を判定して受信データを出力する判定器と、前記受信ベースバンド信号と前記拡散符号より１／２周期進んでいる拡散符号との相関をとって相関信号を出力する第２の相関器と、
前記第２の相関器からの相関信号を前記受信データで逆変調する第１の逆変調回路と、
前記第１の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第１の相関演算回路と、
前記受信ベースバンド信号と前記拡散符号より１／２周期遅れている拡散符号との相関をとって相関信号を出力する第３の相関器と、
前記第３の相関器からの相関信号を前記受信データで逆変調する第２の逆変調回路と、
前記第２の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第２の相関演算回路と、
前記第１の相関演算回路の出力と、前記第２の相関演算回路の出力とを減算して位相差を出力する減算器と、
前記位相差を平均化する平均化回路と、
前記平均化回路から出力される位相差に従って、前記位相差が無くなるように発生タイミングを調整しながら拡散符号を発生させ、前記第２の相関器に１／２周期進んでいる拡散符号として供給する拡散符号発生回路と、
前記拡散符号発生回路からの拡散符号を１／２周期遅らせ、前記第１の相関器に受信機の拡散符号として供給する第１の遅延器と、
前記第１の遅延器からの拡散符号を１／２周期遅らせ、前記第３の相関器に１／２周期遅れている拡散符号として供給する第２の遅延器とを備え、
前記第１の相関演算回路と前記第２の相関演算回路を、請求項１記載の相関演算回路で構成したことを特徴とするコヒーレントＤＬＬ回路。A first correlator that correlates the received baseband signal and the spreading code of the receiver and outputs a correlation signal;
A channel estimator that estimates channel distortion from the correlation signal and outputs a channel estimation value;
A conjugate complex multiplier circuit that conjugate-multiplies and outputs the correlation signal and the channel estimation value;
Determines the output from the conjugate complex multiplication circuit and outputs received data, and outputs a correlation signal by correlating the received baseband signal with a spreading code that is ½ cycle ahead of the spreading code A second correlator that
A first inverse modulation circuit that inversely modulates a correlation signal from the second correlator with the received data;
A first correlation operation circuit that outputs a conjugate complex multiplication of the output from the first inverse modulation circuit and the transmission path estimation value;
A third correlator that outputs a correlation signal by correlating the received baseband signal with a spreading code that is ½ cycle delayed from the spreading code;
A second inverse modulation circuit for inversely modulating the correlation signal from the third correlator with the received data;
A second correlation operation circuit that outputs a conjugate complex multiplication of the output from the second inverse modulation circuit and the transmission path estimation value;
A subtractor that subtracts the output of the first correlation calculation circuit and the output of the second correlation calculation circuit to output a phase difference;
An averaging circuit for averaging the phase difference;
In accordance with the phase difference output from the averaging circuit, a spreading code is generated while adjusting the generation timing so that the phase difference is eliminated, and the spreading code is supplied to the second correlator as a spreading code that is advanced by ½ cycle. A spreading code generation circuit;
A first delay unit that delays the spreading code from the spreading code generation circuit by a half period and supplies the delayed code to the first correlator as a spreading code of a receiver;
A second delay unit that delays the spreading code from the first delay unit by 1/2 cycle and supplies the third correlator as a spreading code delayed by 1/2 cycle;
The coherent DLL circuit according to claim 1, wherein the first correlation calculation circuit and the second correlation calculation circuit are configured by the correlation calculation circuit according to claim 1. 受信ベースバンド信号と受信機の拡散符号との相関をとって相関信号を出力する第１の相関器と、
前記相関信号から伝送路歪みを推定し、伝送路推定値を出力する伝送路推定器と、
前記相関信号と前記伝送路推定値とを共役複素乗算して出力する共役複素乗算回路と、
前記共役複素乗算回路からの出力を判定して受信データを出力する判定器と、前記受信ベースバンド信号と前記拡散符号より１／２周期進んでいる拡散符号との相関をとって相関信号を出力する第２の相関器と、
前記第２の相関器からの相関信号を前記受信データで逆変調する第１の逆変調回路と、
前記第１の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第１の相関演算回路と、
前記受信ベースバンド信号と前記拡散符号より１／２周期遅れている拡散符号との相関をとって相関信号を出力する第３の相関器と、
前記第３の相関器からの相関信号を前記受信データで逆変調する第２の逆変調回路と、
前記第２の逆変調回路からの出力と前記伝送路推定値とを共役複素乗算して出力する第２の相関演算回路と、
前記第１の相関演算回路の出力と、前記第２の相関演算回路の出力とを減算して位相差を出力する減算器と、
前記位相差を平均化する平均化回路と、
前記平均化回路から出力される位相差に従って、前記位相差が無くなるように発生タイミングを調整しながら拡散符号を発生させ、前記第２の相関器に１／２周期進んでいる拡散符号として供給する拡散符号発生回路と、
前記拡散符号発生回路からの拡散符号を１／２周期遅らせ、前記第１の相関器に受信機の拡散符号として供給する第１の遅延器と、
前記第１の遅延器からの拡散符号を１／２周期遅らせ、前記第３の相関器に１／２周期遅れている拡散符号として供給する第２の遅延器とを備え、
前記第１の相関演算回路と前記第２の相関演算回路を、請求項２記載の相関演算回路で構成したことを特徴とするコヒーレントＤＬＬ回路。A first correlator that correlates the received baseband signal and the spreading code of the receiver and outputs a correlation signal;
A channel estimator that estimates channel distortion from the correlation signal and outputs a channel estimation value;
A conjugate complex multiplier circuit that conjugate-multiplies and outputs the correlation signal and the channel estimation value;
Determines the output from the conjugate complex multiplication circuit and outputs received data, and outputs a correlation signal by correlating the received baseband signal with a spreading code that is ½ cycle ahead of the spreading code A second correlator that
A first inverse modulation circuit that inversely modulates a correlation signal from the second correlator with the received data;
A first correlation operation circuit that outputs a conjugate complex multiplication of the output from the first inverse modulation circuit and the transmission path estimation value;
A third correlator that outputs a correlation signal by correlating the received baseband signal with a spreading code that is ½ cycle delayed from the spreading code;
A second inverse modulation circuit for inversely modulating the correlation signal from the third correlator with the received data;
A second correlation operation circuit that outputs a conjugate complex multiplication of the output from the second inverse modulation circuit and the transmission path estimation value;
A subtractor that subtracts the output of the first correlation calculation circuit and the output of the second correlation calculation circuit to output a phase difference;
An averaging circuit for averaging the phase difference;
In accordance with the phase difference output from the averaging circuit, a spreading code is generated while adjusting the generation timing so that the phase difference is eliminated, and the spreading code is supplied to the second correlator as a spreading code that is advanced by ½ cycle. A spreading code generation circuit;
A first delay unit that delays the spreading code from the spreading code generation circuit by a half period and supplies the delayed code to the first correlator as a spreading code of a receiver;
A second delay unit that delays the spreading code from the first delay unit by 1/2 cycle and supplies the third correlator as a spreading code delayed by 1/2 cycle;
3. A coherent DLL circuit, wherein the first correlation calculation circuit and the second correlation calculation circuit are constituted by the correlation calculation circuit according to claim 2.

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