JP3658162B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3658162B2
JP3658162B2 JP32758097A JP32758097A JP3658162B2 JP 3658162 B2 JP3658162 B2 JP 3658162B2 JP 32758097 A JP32758097 A JP 32758097A JP 32758097 A JP32758097 A JP 32758097A JP 3658162 B2 JP3658162 B2 JP 3658162B2
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semiconductor element
insulating film
wiring
semiconductor device
conductive wiring
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JPH11163201A (en
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昭弘 矢口
誠 北野
順一 有田
健二 氏家
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

PROBLEM TO BE SOLVED: To prevent disconnection of a conductive wiring for improved reliability by, making a width at a position facing an outer edge of a semiconductor element to be wider than that at a position facing outside and/or inside of the outer edge of the semiconductor element. SOLUTION: A conductive wiring comprises a surface wiring 2, a through hole, and an internal wiring, etc. A semiconductor element 1 is fixed to a semiconductor element fixing surface 4a of a printed wiring board 4, while jointed to a bonding pad 2a by a metal thin line. In surface wiring, a wide part 13 is provided at a surface wiring part 12 crossing just below a semiconductor element outer edge (end part) 1a so as to cross an profile line of the semiconductor element 1. Related to the wide part 13, wiring width between through holes is formed wider from the end part 1a. The deformation amount of an insulating film is minimum at the center of the semiconductor element 1 while maximum at the end 1a, and deformation of the insulating film is suppressed at the end 1a for suppressing cracks at the insulating film from occurring.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子と外部端子を電気的に接続する導電性配線を備えた半導体装置に係り、特に導電性配線の信頼性を高めた半導体装置に関する。
【０００２】
【従来の技術】
半導体装置の高密度実装化に対応するため、多ピン化、小型化および高速化に適したボールグリッドアレイ（ＢＧＡ）型の半導体装置が実用化されている。ＢＧＡ型半導体装置は、半導体装置のパッケージの面内にはんだバンプなどから外部端子を２次元配置した構造となっている。ＢＧＡ型半導体装置では、半導体素子と外部端子との電気的接続のため、表面、あるいは表面および内部に導電性配線が形成されているインターポーザと呼ばれる部材が用いられている。インターポーザにはガラス／エポキシなどを基材とするプリント配線基板や、テープ・オートメイティド・ボンディング（ＴＡＢ）技術による半導体装置で用いられているポリイミドなどを基材として表面などに導電性配線を形成した絶縁性テープなどが使用されている。
【０００３】
インターポーザにプリント配線基板を用いた従来の半導体装置の例が米国特許ＮＯ．５２１６２７８および特表平６−５０６３１９号公報などに開示されている。これら従来技術によるＢＧＡ型半導体装置の例を図３０および図３１に示す。なお、図３０は従来のＢＧＡ型半導体装置の断面図、図３１は図３０に示した従来の半導体装置の半導体素子と封止樹脂と絶縁膜を取り除いた状態での平面図である。
【０００４】
従来のＢＧＡ型半導体装置は半導体素子１と、表面および内部に導電性配線が形成され、導電性配線の一部を開口するように形成された絶縁膜３を有するプリント配線基板４と、半導体素子１をプリント配線基板表面に固着する接着部材５と、半導体素子１とプリント配線基板の導電性配線とを電気的に接続する金属細線６と、半導体素子１と金属細線６とプリント配線基板４の半導体素子固着面４ａを封止する封止樹脂７と、外部端子８とから構成されている。導電性配線は、表面配線２とボンディングパッド２ａとスルーホール２ｂと内部配線２ｃとランド２ｄとから構成されている。絶縁膜３はソルダーレジストあるいはフォトレジストなどと呼ばれており、スクリーン印刷法、フォト法などによって形成される。絶縁膜にはエポキシ、ポリイミド、ポリブタジエンなどの材料が用いられる。
【０００５】
金属細線６とプリント配線基板４の導電性配線とは、半導体素子１の面外に配置されているボンディングパッド２ａで接続されている。ボンディングパッド２ａ部分では、絶縁膜３に開口部３ａが形成されており、金属細線６とボンディングパッド２ａが接合できるようになっている。外部端子８はプリント配線基板の外部端子接合面４ｂに格子状に設けられており、半導体素子１の面外および面内の両方に配置されている。半導体素子１面内に配置される外部端子８と半導体素子１とを電気的に接続するため、表面配線２はボンディングパッド２ａから半導体素子１の面内に向かって半導体素子１の外形線と交差するように連続して形成されており、表面配線に連なるスルーホール２ｂあるいは内部配線２ｃを経て外部端子８が接合されるプリント配線基板の外部端子接合面４ｂに形成されたランド２ｄまで形成されている。ランド２ｄ部は、プリント配線基板の外部端子接合面４ｂに設けられた絶縁膜９に開口部９ａが形成されており、ランド２ｄと外部端子８が接合できるようになっている。
【０００６】
【発明が解決しようとする課題】
従来の半導体装置では、半導体素子１の線膨張係数が２〜３×１０- 6／℃、プリント配線基板の線膨張係数が１６×１０- 6／℃程度であり、両者の線膨張係数に大きな差異がる。このような構成の半導体装置に温度変化が加わると、両者の線膨張係数差に起因した熱応力が両者の界面に発生するようになり、接着部材５にき裂やはく離などが発生する。接着部材５にき裂などが発生すると、両者の界面に発生する熱応力は半導体素子１の端部１ａに集中してさらに大きくなる。このような状況で温度変化が繰り返し加わると、図３２（従来のＢＧＡ型半導体装置の絶縁膜のき裂の状態を示す断面図）に示すように、半導体素子の端部１ａ部分から絶縁膜３のき裂１１が発生するようになる。
【０００７】
次に絶縁膜３のき裂１１の発生と成長のメカニズムを説明する。半導体素子１とプリント配線基板４の線膨張係数差により発生する熱応力は両者の界面全体で分担するが、接着部材５にき裂１０が発生すると、このき裂１０の部分は応力を負担できなくなるため、半導体素子の端部１ａに応力が集中するようになる。この応力集中によって絶縁膜３にき裂１１が発生する。絶縁膜３の線膨張係数が比較的大きいことと、接着部材５にき裂が生じていることから、絶縁膜３は温度変化によって自由に変形できるようになる。温度変化の繰り返しに伴って、絶縁膜３のき裂１１は開口と閉口を繰り返しながら徐々に進行していき、いずれは絶縁膜３を横断したき裂に成長するようになる。
【０００８】
表面配線２が上記絶縁膜３のき裂１１の発生個所である半導体素子端部１ａを横切るように、半導体素子１の外縁部の内側（以下、内面ともいう）と外側（以下、外面ともいう）とに連続して形成されていると、き裂１１は表面配線２内部へも進行し、いずれは表面配線２に断線が発生する可能性が大きくなる。表面配線が断線すると半導体装置が正常に機能しなくなり、半導体装置の信頼性を著しく低下させることになる。
【０００９】
同様の問題は、インターポーザとして表面に導電性配線が形成されたＴＡＢ技術で用いられる絶縁テープを使用した半導体装置においても発生する。
【００１０】
本発明は、半導体素子の外縁部（以下、外形線ともいう）と交差するように半導体素子の面内と面外とに連続して形成されている導電性配線の断線を防止・抑制し、信頼性の高い半導体装置を提供することを目的とする。
【００１１】
【課題を解決するための手段】
上記の課題は、接着部材にき裂などが発生したことによって生じる、温度変化が加わった際の絶縁膜の大きな変形を低減もしくは拘束する手段を採用することによって解決することができる。
【００１２】
本発明は、一主面を有する基板と、この基板の一主面に形成された導電性配線と、前記基板の一主面と前記導電性配線との所望の領域に形成された絶縁膜と、この絶縁膜の前記基板とは反対側に接着層を介して配設された半導体素子とを備え、前記導電性配線が前記半導体素子の外縁部より外側と前記半導体素子の外縁部より内側とを結ぶように形成された半導体装置において、以下の構成を備えたことを特徴とする。
【００１３】
（Ａ）前記導電性配線は前記半導体素子の外縁部と対向する位置の幅が前記半導体素子の外縁部より外側および／または内側と対向する位置の幅よりも広くなるように形成されていること。
【００１４】
（Ｂ）前記導電性配線のうち前記半導体の外縁部を構成する各辺の中央部と対向する領域に形成された導電性配線は前記半導体素子の外縁部と対向する位置の幅が前記半導体素子の外縁部より外側および／または内側と対向する位置の幅よりも広くなるように形成されていること。
【００１５】
本発明が対象とする半導体装置では、基板表面の導電性配線が一部の開口部を除いて絶縁膜により被覆された状態になっている。導電性配線は銅（Ｃｕ）もしくは銅の表面にめっきを施した材料によって形成される。導電性配線に用いる材料は絶縁膜の材料より通常弾性係数が大きいため、温度変化時の絶縁膜の変形は、導電性配線によって拘束されるようになっている。したがって、導電性配線の配線幅を広くして絶縁膜内での導電性配線が占める割合を多くすることにより、絶縁膜の変形量を低減することができる。
【００１６】
図３３はＢＧＡ型半導体装置の１／４部分を取り出し、半導体素子面内に導電性配線を１本形成したモデルで、導電性配線の周囲にき裂を導入し、半導体装置を冷却した場合の導電性配線表面の応力と配線幅の関係を有限要素法により解析した結果である。図３３より配線幅増加による応力低減効果は明らかであり、実際の半導体装置では、複数の導電性配線の配線幅を広くすることによって、さらに応力低減を図ることが可能となる。
【００１７】
また、導電性配線の断線が発生する半導体素子端部（外縁部）の直下部分において、導電性配線の配線幅を広くすることにより、絶縁膜の変形量減少による応力低減効果の他に、導電性配線にき裂が発生しても断線に至るまでの寿命（温度変化の繰り返し回数）を長くできる効果も得られる。
【００１８】
さらにまた、方形の半導体素子を搭載した半導体装置では、半導体素子の外形線を構成する４辺の中央部分が平面ひずみ状態となり、発生する熱応力が大きくなるため,この部分で導電性配線が断線する確率が高くなる。また、配線幅を必要以上に広くすると半導体装置内での配線容量が増大してノイズが発生し、半導体素子の高速動作が阻害される要因となる。したがって、少なくとも断線発生確率が大きくなる半導体素子の辺の中央部分で、半導体素子の外形線と交差するように形成された導電性配線の配線幅を広くすることによって、断線を防止でき、半導体装置の特性も考慮した半導体装置をえることができる。
【００１９】
（Ｃ）前記導電性配線は群を成して形成されており、この群を成して形成された導電性配線の両端に位置する導電性配線は前記半導体素子の外縁部と対向する位置の幅が前記半導体素子の外縁部より外側および／または内側と対向する位置の幅よりも広くなるように形成されていること。
【００２０】
本発明によっても、弾性係数の大きな導電性配線が絶縁膜に対してプリント配線基板表面を占める割合を大きくでき、絶縁膜の変形を拘束することができる。また、半導体装置の端子数が多く、導電性配線どうしが接近して略平行に配置されている導電性配線群では、すべての導電性配線の配線幅を広くするのが困難な場合がある。また、ＢＧＡ型半導体装置は高速動作が要求される半導体素子を搭載する場合が多く、導電性配線幅を必要以上に広くすると配線容量（インダクタンス）が増大し、これによって高速動作が阻害されることがある。そのため、配線幅を広げるのは最小限にとどめることが必要となる。前記導電性配線群では、少なくともその端部に位置する導電性配線を内部の配線より広くすることによって、絶縁膜の変形を両端部でピン止めすることができ、絶縁膜の変形量を低減できる。
【００２１】
（Ｄ）前記導電性配線は前記半導体の外縁部を構成する各辺の中央部以外の領域と対向する前記基板の領域に形成されていること。
【００２２】
方形の半導体素子を搭載した半導体装置では、半導体素子の外形線を構成する辺の中央部分が平面ひずみ状態となり、発生する熱応力が大きくなるため,この部分で導電性配線が断線する確率が高くなる。したがって、上記中央部分には半導体素子の外形線と交差して端部を横切るような導電性配線が配置されないように、導電性配線パターンを形成することで、断線発生の可能性を小さくすることができる。
【００２３】
（Ｅ）前記導電性配線は前記半導体素子の外縁部を斜めに横切るように形成されていること。
【００２４】
導電性配線を半導体素子の外形線を斜めに横切るように形成することによって、半導体素子の面内において、導電性配線２が占める割合を大きくすることができ、絶縁膜の変形拘束効果が大きくなる。また、半導体素子の外形線上での導電性配線の断面積が見掛け上増加することから、配線にき裂が発生してから断線するまでの寿命が延びる効果も得ることができる。
【００２５】
（Ｆ）前記絶縁膜の弾性係数Ｅ１と前記接着層の弾性係数Ｅ２との関係がＥ１≦Ｅ２となるように構成したこと。
【００２６】
絶縁膜のき裂は、線膨張係数の大きな絶縁膜自体が温度変化により収縮と膨張を繰り返すことによって発生、成長する。絶縁膜に用いられる材料はエポキシ樹脂、ポリイミド樹脂またはポリブタジエン樹脂などであり、これらの材料の弾性係数は、通常接着部材の弾性係数より大きくなっている。絶縁膜の弾性係数が大きいとき裂の先端に発生する応力が緩和されないため、き裂の成長はき裂が長くなるに従って加速されていく。絶縁膜の弾性係数を小さくすると、き裂先端での変形が容易となり、き裂先端の応力が緩和され、き裂の成長を抑止することができる。
【００２７】
図３４はＢＧＡ型半導体装置の１／４部分を取り出し、半導体素子面内に導電性配線を１本形成したモデルで、導電性配線の周囲にき裂を導入し、半導体装置を冷却した場合のき裂先端の導電性配線表面の応力と絶縁膜の弾性係数の関係を有限要素法により解析した結果である。図から絶縁膜の弾性係数を小さくするとき裂先端の応力も低減することが実証されている。
【００２８】
（Ｇ）前記絶縁膜の弾性係数が１０Ｇｐａ以上であること。
【００２９】
導電性配線の断線発生の原因となる絶縁膜のき裂は、接着部材にき裂やはく離が発生したことによって、絶縁膜の変形が自由になることで発生する。同様に接着部材の弾性係数が小さいと、絶縁膜の変形を拘束できなくなるため、絶縁膜にき裂が発生し易くなる。したがって、接着部材の弾性係数を大きくすることによって温度変化時の絶縁膜の変形を拘束してやれば、絶縁膜のき裂発生を抑止することが可能となる。
【００３０】
図３５は、ＢＧＡ型半導体装置の断面を取り出したモデルで、半導体装置を冷却した際の半導体素子端部での絶縁膜表面応力を、接着部材の弾性係数を変えて有限要素法により解析した結果である。この解析では絶縁膜の弾性係数を２．５ＧＰａとしている。図から接着部材の弾性係数を大きくしていくと絶縁膜の応力が次第に低下していくのが明らかであるが、１０ＧＰａ程度から応力の低下割合が小さくなっており、ほぼ一定の値となっている。この結果から接着部材の弾性係数を１０ＧＰａ以上に設定すれば絶縁膜の応力を低い値に維持することができる。
【００３１】
また、発明者らが行った試作評価では、接着部材の弾性係数を１ＧＰａとした半導体装置には温度変化の繰り返し１００回で絶縁膜にき裂が発生した。しかしながら弾性係数を１７ＧＰａとしたものでは４００回でも絶縁膜のき裂は発生しておらず、効果を確認することができた。
【００３２】
なお、接着部材の弾性係数を大きくしていくと、半導体素子とプリント配線基板の線膨張係数差によって半導体素子に発生する応力も大きくなり、半導体素子に割れが発生する可能性が増大する。したがって、接着部材に使用する弾性係数の範囲は１０ＧＰａを下限とし、半導体素子に割れを発生させない値が上限となる。
【００３３】
また本発明の半導体装置は、一主面を有する絶縁性テープと、この絶縁性テープの一主面に形成された導電性配線と、前記絶縁性テープの一主面と前記導電性配線との所望の領域に形成された絶縁膜と、この絶縁膜の前記絶縁性テープとは反対側に接着層を介して配設された半導体素子とを備え、前記導電性配線は前記半導体素子の外縁部より外側と前記半導体素子の外縁部より内側とを結ぶように形成された半導体装置において、以下の構成を備えたことを特徴とする。
【００３４】
（Ｈ）前記半導体素子の端部の前記絶縁性テープ側には前記導電性配線が露出していること。
【００３５】
すなわち、熱応力が集中する半導体素子端部の直下部分からき裂が発生しやすい絶縁膜を取り除き、この部分を絶縁膜よりじん性の大きな封止樹脂で覆うことにより、き裂の発生と成長を抑制することができる。
【００３６】
（Ｉ）前記半導体素子の外縁部よりも内側では前記導電性配線との絶縁を要する領域に前記絶縁膜が形成されていること。
【００３７】
絶縁膜は導電性配線が他の導体部材などに接触して短絡などを起こさないように保護するために設けられている。したがって、絶縁膜を導電性配線の周囲のみを覆うようにして半導体素子面内での絶縁膜の体積を減らすことにより、温度変化時の絶縁膜の変形量を低減することができる。
【００３８】
（Ｊ）前記絶縁性テープの前記半導体素子の外縁部よりも内側の領域と対向する領域には前記絶縁膜の変形を拘束する部材が形成されていること。
【００３９】
変形拘束用の部材は箔状部材で形成するのが望ましく、導電性材料と同じ材料で形成するのが良い。また、方形の半導体素子を搭載した半導体装置では、半導体素子の外形線を構成する辺の中央部分が平面ひずみ状態となり、発生する熱応力が大きくなるためこの部分で導電性配線が断線する確率が高くなる。したがって、最低限半導体素子の辺の中央部分での絶縁膜の変形を拘束すれば良い。
【００４０】
また、前絶縁膜の弾性係数を、前記接着部材の弾性係数と同等もしくはそれ以下とすることも有効である。
【００４１】
絶縁膜のき裂は、線膨張係数が大きい絶縁膜自体が、温度変化により収縮と膨張を繰り返すことによって発生、成長する。絶縁膜に用いられる材料はエポキシ樹脂、ポリイミド樹脂またはポリブタジエン樹脂などであり、これらの材料の弾性係数は、通常接着部材の弾性係数より大きくなっている。絶縁膜の弾性係数が大きいとき裂の先端に発生する応力が緩和されないため、き裂の成長はき裂が長くなるに従って加速されていく。絶縁膜の弾性係数を小さくすると、き裂先端での塑性変形領域が拡大するためき裂先端の応力が緩和され、き裂の成長を抑止することができる。
【００４２】
【発明の実施の形態】
以下、本発明の実施形態を図面にしめした実施例用いて詳細に説明する。
〔第１実施例〕
図１は、本発明の第１実施例による半導体装置の半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図２は図１に示した半導体装置の断面図である。
【００４３】
図において、プリント配線基板４の表面および内部には導電性配線が形成されており、導電性配線は表面配線２、ボンディングパッド２ａ、スルーホール２ｂ、内部配線２ｃ、およびランド２ｄとから構成されている。プリント配線基板４の表面４ａと４ｂには開口部３ａおよび９ａが設けられた絶縁膜３および９が形成されている。方形の半導体素子１はプリント配線基板の半導体素子固着面４ａに接着部材５によって固着されている。半導体素子１と導電性配線は金属細線６によって電気的に接続されており、金属細線６は半導体素子１の面外に設けられているボンディングパッド２ａに接合されている。ボンディングパッド２ａ部分では絶縁膜３に開口部３ａが設けられており、金属細線６が接合できるようになっている。導電性配線はボンディングパッド２ａからプリント配線基板表面の表面配線２、プリント配線基板４内部のスルーホール２ｂや内部配線２ｃを経てプリント配線基板の外部端子接合面４ｂのランド２ｄまで延びている。ランド２ｄに外部端子８が接合されることにより、半導体素子と外部端子は導電性配線によって電気的に接続される。ランド２ｄ部分では、絶縁膜９に開口部９ａが設けられており、外部端子８がランド２ｄに接合できるようになっている。半導体素子１と金属細線６およびプリント配線基板の半導体素子固着面４ａは封止樹脂７によって覆われている。
【００４４】
プリント配線基板の半導体素子固着面４ａに形成された表面配線２のうち、半導体素子１の外形線と交差するように半導体素子端部１ａの直下部を横切る表面配線１２には幅広部１３が設けられている。図１に示した表面配線の幅広部１３は、半導体素子端部１ａ部分からスルーホール２ｂ間の配線幅を広くすることによって形成されている。
【００４５】
表面配線２には、銅（Ｃｕ）箔、あるいは表面に金（Ａｕ）、ニッケル（Ｎｉ）などのメッキを施した銅箔などを用いる。プリント配線基板４はガラス／エポキシなどを基材とする材料から構成される。金属細線６には金（Ａｕ）、銀（Ａｇ）、あるいはアルミ（Ａｌ）などの材料を用いる。封止樹脂７には、例えばシリカ粒子を充てんしたエポキシ樹脂を用いる。外部端子８には、半導体装置を実装する際に広く用いられているはんだ（例えばＰｂ−Ｓｎ系共晶はんだ）を用いる。
【００４６】
本実施例の半導体装置によれば、温度変化が加わった際の絶縁膜の変形を、幅広部を設けた表面配線によって拘束することができ、絶縁膜のき裂の発生および成長を抑止することができる。
【００４７】
図１に示した実施例では、幅広部１３を、半導体素子端部１ａの直下部分からスルーホール２ｂ間の表面配線２に形成する例を示した。絶縁膜３の変形量は半導体素子１の中心で最小,端部で最大となり,端部１ａの直下部で最大応力が発生するため、絶縁膜３のき裂は半導体素子端部１ａ部分で発生する。このため、半導体素子端部１ａ部分で絶縁膜の変形を拘束すれば,最低限必要な効果が得られる。したがって,幅広部１３は図３のように少なくとも半導体素子端部１ａの直下部分に形成されていれば良い。図３のような実施例は、高速動作の要求から配線容量を大きくできない半導体装置の場合、特に有効となる。
【００４８】
〔第２実施例〕
図４は、本発明の第２実施例による半導体装置の半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図５は図４に示した半導体装置の断面図である。
【００４９】
半導体装置としての基本構成は第１実施例と共通しているので説明を省略する。
本実施例では、表面配線２のうち、プリント配線基板の半導体素子固着面４ａに形成され、半導体素子１の外形線と交差するように半導体素子端部１ａの直下部を横切る表面配線１２であって、半導体素子長辺の中央部分１ｂに配置されている表面配線１２ａには、幅広部１３が設けられている。図４に示した表面配線１２の幅広部１３は、半導体素子端部１ａの直下部分からスルーホール２ｂ間の配線幅を広くすることによって形成されている。
【００５０】
本実施例のように方形の半導体素子１を搭載した半導体装置では、例えば半導体素子長辺の中央部分１ｂが平面ひずみ状態となり、中央部分１ｂの半導体素子端部１ａの直下部に発生する応力が、半導体素子コーナー部１ｃに発生する応力より大きくなる。したがって、表面配線の断線は半導体素子長辺側の中央部分１ｂの端部１ａで発生する確率が大きいため、この部分の表面配線２を幅広にして絶縁膜３の変形を拘束することで、表面配線の断線を防止することができる。
【００５１】
本実施例では、表面配線が半導体素子の長辺側端部を横切る例を示している。しかしながら、導電性配線が半導体素子の短辺側端部を横切るように配置されているような半導体装置では、短辺側の表面配線にも幅広部１３を形成しても良い。
【００５２】
図４に示した実施例では、幅広部１３を、半導体素子端部１ａの直下部分からスルーホール２ｂ間の表面配線２に形成する例を示した。絶縁膜３の変形量は半導体素子１の中心で最小,端部で最大となり、端部１ａの直下部で最大応力が発生するため、絶縁膜３のき裂は半導体素子端部１ａ部分で発生する。このため、半導体素子端部１ａ部分で絶縁膜の変形を拘束すれば,最低限必要な効果が得られる。したがって,幅広部１３は図６のように少なくとも半導体素子端部１ａの直下部分に形成されていれば良い。図６のような実施例は、高速動作の要求から配線容量を大きくできない半導体装置の場合、特に有効となる。
【００５３】
〔第３実施例〕
図７は、本発明の第３実施例による半導体装置の半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図８は図７に示した半導体装置の断面図である。
【００５４】
半導体装置としての基本構成は第１実施例と共通しているので説明を省略する。
本実施例では、プリント配線基板の半導体素子固着面４ａに形成されている表面配線２のうち、複数の表面配線どうしが略平行に半導体素子１の外形線と交差するように端部１ａを横切る表面配線群１４では、表面配線群の端部１４ａに位置する表面配線に幅広部１３が設けられており、表面配線群の内部１４ｂに位置する表面配線より配線幅が広くなっている。図７に示した導電性配線の幅広部１３は、半導体素子端部１ａ部分からスルーホール２ｂ間の配線幅を広くすることによって形成されている。
【００５５】
本実施例に示した半導体装置によれば、前記表面配線群の少なくとも端部に位置する表面配線に幅広部を形成することにより、温度変化が加わった際の絶縁膜の変形を両端部の幅広部を設けた表面配線によってピン止めすることができ、絶縁膜のき裂の発生および成長を抑止することができる。また、図７の実施例は、配線容量の増加を最小限にすることができるため、特に高速動作が要求される半導体装置で有効となる。
【００５６】
図７に示した実施例では、幅広部１３を、表面配線群１４の端部１４ａに位置する表面配線２の半導体素子端部１ａ直下部分からスルーホール２ｂ間に形成する例を示した。絶縁膜３の変形量は半導体素子１の端部で最大となるため,絶縁膜３のき裂は半導体素子端部１ａの直下部分で発生するようになる。このため、半導体素子端部１ａ部分で絶縁膜の変形を拘束すれば,最低限必要な効果が得られる。したがって,幅広部１３は図９のように少なくとも半導体素子端部１ａの直下部分に形成されていれば良い。図９のような実施例は、高速動作の要求から配線容量を大きくできない半導体装置の場合、特に有効となる。
【００５７】
〔第４実施例〕
図１０は、本発明の第４実施例による半導体装置の半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図１１は図１０に示した半導体装置の断面図である。
【００５８】
半導体装置としての基本構成は第１実施例と共通しているので説明を省略する。
本実施例では、プリント配線基板の半導体素子固着面４ａにおいて、半導体素子の長辺側中央部分１ｂでは、半導体素子１の外形線と交差するように端部１ａを横切る表面配線２が設けられていない。この部分の表面配線２は、ボンディングパッド２ａからプリント配線基板４の外方に向かって延びており,スルーホール２ｂと内部配線２ｃを経てランド２ｄへ接続されている。したがって、中央部分１ｂの半導体素子端部１ａの直下部分では、プリント配線基板の半導体素子固着面４ａに絶縁膜３と接着部材５のみが設けられている。一方、半導体素子のコーナー１ｃの近傍部分では、半導体素子端部１ａを横切るように表面配線２が形成されている。
【００５９】
本実施例のように方形の半導体素子１を搭載した半導体装置では、例えば半導体素子長辺側の中央部分１ｂが平面ひずみ状態となり、中央部分１ｂの半導体素子端部１ａ直下部分に発生する応力が、半導体素子コーナー部１ｃに発生する応力より大きくなる。このため導電性配線の断線は半導体素子長辺側の中央部分１ｂの端部１ａ直下部分で発生する確率が大きくなる。したがって、半導体素子長辺側の中央部分１ｂでは、表面配線２が半導体素子端部１ａを横切らないように引き回すことにより、絶縁膜３のき裂に起因する導電性配線の断線を防止することができる。
【００６０】
〔第５実施例〕
図１２は本発明の第５実施例による半導体装置の半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図１３は図１２に示した半導体装置の断面図である。
【００６１】
半導体装置としての基本構成は第１実施例と共通しているので説明を省略する。
本実施例では、プリント配線基板の半導体素子固着面４ａに形成された表面配線２であって、半導体素子１の外形線と交差して半導体素子端部１ａを横切るように形成される表面配線１２のうち、半導体素子長辺側の中央部分１ｂに配置された表面配線１２は、半導体素子１の外形線に対して斜めに半導体素子端部１ａを横切るように形成されている。
【００６２】
表面配線１２を半導体素子の端部１ａを斜めに横切るように形成することによって、直角に横切る場合よりも半導体素子１の面内での表面配線２が占める割合を大きくすることができ、絶縁膜の変形拘束効果が大きくなる。また、半導体素子外形線上での表面配線の断面積が見掛け上増加することから、配線にき裂が発生してから断線するまでの寿命が延びる効果も得ることができる。
【００６３】
本実施例のように方形の半導体素子１を搭載した半導体装置では、例えば半導体素子長辺側の中央部分１ｂが平面ひずみ状態となり、この部分の半導体素子端部１ａの直下部分に発生する応力が大きくなる。このため導電性配線の断線は半導体素子長辺側の中央部分１ｂで発生する確率が大きくなっている。したがって、少なくとも中央部分１ｂでの絶縁膜３の変形を拘束して変形量を低減することが必要となる。
【００６４】
〔第６実施例〕
図１４は本発明の第６実施例による半導体装置の断面図である。
【００６５】
半導体装置としての基本構成は第１実施例と共通しているので説明を省略する。
本実施例の半導体装置では、絶縁膜３を、接着部材５の弾性係数と同等かそれ以下の弾性係数を有する材料で形成する。絶縁膜３を低弾性化することによって、絶縁膜３にき裂が発生した場合でも、絶縁膜自体の変形が容易となるため、き裂の先端に発生する応力を変形によって緩和することができる。そのため、温度変化の繰り返しによるき裂の成長を抑制する効果を得ることができ、表面配線の断線を防止することができる。
【００６６】
接着部材５には通常弾性係数が１ＧＰａ程度の材料が使用される。したがって、絶縁膜３には、弾性係数が１ＧＰａ以下の材料を選択して使用するのが望ましい。
【００６７】
上記したように絶縁膜３の低弾性化によって絶縁膜３のき裂発生および成長を抑止できるようになるが、プリント配線基板４の製作上の制約などから、絶縁膜３の弾性係数を低くできない場合がある。このような場合は、接着部材５の弾性係数を大きくすることによって絶縁膜３に発生する応力を低減し、絶縁膜３のき裂発生を抑止するのが望ましい。通常使用される絶縁膜３の弾性係数は２．５ＧＰａ程度であり、この絶縁膜３を使用する場合は、接着部材５の弾性係数を１０ＧＰａ以上に設定する。接着部材５に弾性係数の大きな材料を用いることによって絶縁膜３の温度変化時の変形を拘束でき、絶縁膜３のき裂発生を抑止することが可能となる。
【００６８】
〔第７実施例〕
図１５は本発明の第７実施例による半導体装置の封止樹脂と接着部材と絶縁膜とを取り除いた状態での平面図であり、図１６は図１５に示した半導体装置の断面図である。
【００６９】
図において、絶縁性テープ１５の半導体素子固着面１５ａには導電性配線と絶縁膜３が形成されており、導電性配線は表面配線２とボンディングパッド２ａとランド２ｄとから構成されている。絶縁膜３にはボンディングパッド２ａを露出させる開口部３ａが設けられている。方形の半導体素子１は絶縁性テープ１５の半導体素子固着面１５ａに接着部材５によって固着されている。半導体素子１と導電性配線は金属細線６によって電気的に接続されており、金属細線６は半導体素子１の面外に位置するボンディングパッド２ａに接合されている。ボンディングパッド２ａ部分では絶縁膜３に開口部３ａが設けられており、金属細線６が接合できるようになっている。表面配線２はボンディングパッド２ａから半導体素子１の面内に配置されているランド２ｄまで半導体素子１の外形線と交差して端部１ａを横切るように形成されている。ランド２ｄが設けられている部分では絶縁性テープ１５に開口部１６が形成されており、外部端子８が開口部１６の内部でランド２ｄに接合されている。外部端子８は絶縁性テープ１５の半導体素子固着面１５ａとは反対側の外部端子接合面１５ｂに設けられており、半導体装置を実装する場合に、実装基板の所定の位置に接合される。半導体素子１と金属細線６および絶縁性テープの半導体素子固着面１５ａは封止樹脂７によって覆われている。
【００７０】
半導体素子端部１ａを横切る表面配線２のうち、半導体素子１各辺の中央部分１ｂに配置されている表面配線２には、幅広部１３が形成されている。図１５に示した表面配線２の幅広部１３は、半導体素子端部１ａ部分からランド２ｄ間の配線幅を広くすることによって形成されている。
【００７１】
表面配線２などの導電性配線には、銅（Ｃｕ）箔、あるいは表面に金（Ａｕ）、ニッケル（Ｎｉ）などのメッキを施した銅箔などを用いる。絶縁性テープ１５はポリイミド、ガラス／エポキシなどの材料から構成される。金属細線６には金（Ａｕ）、銀（Ａｇ）あるいはアルミ（Ａｌ）などの材料を用いる。接着部材５には例えばエポキシ樹脂を基材とする材料を用いる。封止樹脂７には、例えばシリカ粒子を充てんしたエポキシ樹脂を用いる。外部端子８には、半導体装置を実装する際に広く用いられているはんだ（例えばＰｂ−Ｓｎ系共晶はんだ）を用いる。
【００７２】
本実施例の半導体装置によれば、温度変化が加わった際の絶縁膜の変形を、幅広部を設けた表面配線によって拘束することができ、絶縁膜のき裂の発生および成長を抑止することができる。
【００７３】
幅広部１３は、少なくとも図１５のように半導体素子１の各辺の中央部分１ｂに配置されている表面配線２に形成されていれば良い。本実施例のように方形の半導体素子１を搭載した半導体装置では、半導体素子各辺の中央部分１ｂが平面ひずみ状態となり、半導体素子端部１ａの直下部に発生する応力が大きくなる。したがって、表面配線２の断線はこの位置で発生する確率が大きくなるため、この部分での絶縁膜３の変位を拘束することで、表面配線の断線を防止することができる。
【００７４】
図１５に示した実施例では、半導体素子１と導電性配線との電気的接続に金属細線６を用いる例を示している。両者の接続は金属細線以外の方法で行っても良く、例えばＴＡＢ技術で用いる箔状リードやフリップチップ技術による微細なバンプを用いた接続を行う。
【００７５】
また、図１５に示した実施例では、幅広部１３を、半導体素子端部１ａ部分からランド２ｄ間の表面配線２に形成する例を示した。絶縁膜３の変形量は半導体素子１の中心で最小、端部１ａで最大となるため、絶縁膜３のき裂は半導体素子端部１ａ部分で発生する。このため半導体素子端部１ａ部分で絶縁膜３の変形を拘束すれば、最低限必要な効果を得ることができる。したがって,幅広部１３は図１７の平面図に示すように、少なくとも半導体素子端部１ａの直下部分に形成されていれば良い。なお、図１８は図１７に示した半導体装置の断面図である。図１７のような実施例は、高速動作の要求から配線容量を大きくできない半導体装置の場合、特に有効となる。
【００７６】
〔第８実施例〕
図１９は本発明の第８実施例による半導体装置を半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図２０は図１９に示した半導体装置の断面図である。
【００７７】
半導体装置としての基本構成は第７実施例と共通しているので説明を省略する。
本実施例では、表面配線２のうち、複数の表面配線２どうしが略平行に配置されている表面配線群１４では、表面配線群の端部１４ａに位置する表面配線に幅広部１３が設けられており、表面配線群の内部１４ｂに位置する表面配線より配線幅が広くなっている。図１９に示した表面配線の幅広部１３は、半導体素子端部１ａ部分からランド２ｄ間の配線幅を広くすることによって形成されている。
【００７８】
本実施例に示した半導体装置によれば、前記表面配線群の少なくとも端部に位置する表面配線に幅広部を形成することにより、温度変化が加わった際の絶縁膜の変形を両端部の幅広部を設けた導電性配線によってピン止めすることができ、絶縁膜のき裂の発生および成長を抑止することができる。
【００７９】
図１９に示した実施例では、幅広部１３を表面配線群１４の両端部１４ａに位置する表面配線２の半導体素子端部１ａ部分からランド２ｄまでに形成する例を示した。絶縁膜３の変形量は半導体素子端部１ａで最大となるため、絶縁膜３のき裂は端部１ａ部分で発生する。このため、半導体素子端部１ａ部分で絶縁膜の変形を拘束すれば、最低限必要な効果が得られる。したがって、幅広部１３は半導体素子端部１ａの直下部分に少なくとも形成されていれば良い。このように幅広部の形成範囲を小さくするのは、高速動作の要求から配線容量を大きくすることができない半導体装置の場合有効となる。
【００８０】
〔第９実施例〕
図２１は本発明の第９実施例による半導体装置を半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図２２は図２１に示した半導体装置の断面図である。
【００８１】
半導体装置としての基本構成は第７実施例と共通しているので説明を省略する。
本実施例では、表面配線２のうち、半導体素子の端部１ａを横切るように引き延ばされている表面配線１２の配線幅は、これ以外の表面配線２より広くなっている。図２１に示した半導体素子端部１ａを横切る表面配線１２は、ボンディングパッド２ａからランド２ｄ間の全配線の幅が広くなっている。
【００８２】
本実施例の半導体装置によれば、温度変化が加わった際の絶縁膜の変形を、幅広部を設けた表面配線によって拘束することができ、絶縁膜のき裂の発生および成長を抑止することができる。
【００８３】
図２１に示した実施例では、半導体素子端部１ａを横切る表面配線１２をこれ以外の表面配線より幅広にする例を示した。絶縁膜３の変形量は半導体素子１の中心で最小、端部１ａで最大となるため、絶縁膜３のき裂は半導体素子端部１ａ部分で発生する。このため半導体素子端部１ａ部分で絶縁膜３の変形を拘束すれば、最低限必要な効果を得ることができる。したがって,配線幅を広くする個所は、少なくとも半導体素子端部１ａの直下部分であれば良い。
【００８４】
〔第１０実施例〕
図２３は本発明の第１０実施例による半導体装置を半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図であり、図２４は図２３に示した半導体装置の断面図である。
【００８５】
半導体装置としての基本構成は第７実施例と共通しているので説明を省略する。
本実施例では、絶縁性テープの半導体素子固着面１５ａであって、ランド２ｄが形成されていない半導体素子１面内の中央部分１５ｃには、方形の変形拘束部材１７が設けられている。変形拘束部材１７は表面配線２と同じ材料で構成するのが望ましく、銅（Ｃｕ）などを箔状にした材料を用いる。半導体素子面内の絶縁性テープ表面に銅などの剛性の大きな材料で構成した板状の部材を設けることによって、温度変化による絶縁膜の変形を拘束する効果を得ることができる。
【００８６】
本実施例に示した半導体装置によれば、変形拘束部材によって絶縁膜の変形を拘束し、変形量を小さくすることができる。これによって、絶縁膜のき裂の発生および成長を抑制することができる。
【００８７】
図２３に示した実施例では、変形拘束部材１７を半導体素子１の形状と同じ方形に形成する例を示した。本実施例のように方形の半導体素子１を搭載した半導体装置では、半導体素子の各辺中央部分が平面ひずみ状態となり、この部分で半導体素子端部１ａ直下部に発生する応力が大きくなる。したがって、表面配線の断線はこの位置で発生する確率が大きくなるため、少なくともこの部分での絶縁膜３の変位を拘束すれば、表面配線の断線を防止することができる。図２５は半導体素子各辺の中央部分での絶縁膜の変形量を低減するために、半導体素子の対向する２辺を通る中心線と一致する十字型の変形拘束部材１７を形成した例である。変形拘束部材１７を図２５のような形状にすることによって、半導体素子各辺の中央部分での絶縁膜の変形を拘束することができる。また、銅箔の使用量を低減することによって絶縁性テープの反り量を低減でき、半導体素子を絶縁性テープに固着する作業などを容易にすることができる。
【００８８】
〔第１１実施例〕
図２６は、本発明の第１１実施例による半導体装置の断面図である。
【００８９】
半導体装置としての基本構成は第７実施例と共通しているので説明を省略する。
本実施例では、半導体素子端部１ａの直下部分には、絶縁膜３に開口部３ｂが設けられていることから、この部分では絶縁膜３が存在しておらず、封止樹脂７が半導体素子１と絶縁性テープ１５との間に介在している。半導体素子端部１ａの直下部分に絶縁膜３に用いる材料よりじん性の大きな封止樹脂を介在させることによって、半導体素子端部１ａからのき裂の発生を抑制することができる。
【００９０】
〔第１２実施例〕
図２７は本発明の第１２実施例による半導体装置の断面図であり、図２８は図２７に示した半導体装置の半導体素子と封止樹脂と絶縁膜とを取り除いた状態での平面図である。
【００９１】
半導体装置としての基本構成は第７実施例と共通しているので説明を省略する。
本実施例では、絶縁性テープの半導体素子固着面１５ａであって、ランド２ｄが形成されていない半導体素子１面内の中央部分１５ｃには、絶縁膜３に開口部１８が設けられており、中央部分１５ｃでは絶縁性テープの半導体素子固着面１５ａは接着部材５が覆っている。すなわち絶縁膜３は半導体素子１面外ではボンディングパッド２ａ以外の部分、面内では表面配線２とランド２ｄが形成されている部分に設けられている。
【００９２】
半導体素子面内の中央部分１５ｃに絶縁膜３を設けないことによって、半導体素子面内における絶縁膜の占有率が低減することから、温度変化による絶縁膜全体の変形量が小さくなり、絶縁膜のき裂の発生および成長が抑制されるようになる。
【００９３】
図２７に示した半導体装置では、中央部分１５ｃに開口部１８を設けて半導体素子１面内の表面配線２とランド２ｄを絶縁膜３で覆う例を示した。絶縁膜３が半導体素子面内で占有する体積をさらに減らすため、開口部を表面配線２およびランド２ｄどうしの間に設けるようにしても差し支えない。絶縁膜３を少なくとも表面配線２とランド２ｄの周囲を覆うように設けることによって、絶縁膜の変形量をさらに低減することができる。
【００９４】
〔第１３実施例〕
図２９は本発明の第１３実施例による半導体装置の断面図である。
半導体装置としての基本構成は第７実施例と共通しているので説明を省略する。
本実施例の半導体装置では、絶縁膜３を、接着部材５の弾性係数と同等かそれ以下の弾性係数を有する材料で形成する。絶縁膜３を低弾性化することによって、絶縁膜３にき裂が発生した場合でも、絶縁膜自体の変形が容易となるため、き裂の先端に発生する応力を変形によって緩和することができる。そのため、温度変化の繰り返しによるき裂の成長を抑制する効果を得ることができ、導電性配線の断線を防止することができる。
【００９５】
接着部材５には通常弾性係数が１ＧＰａ程度の材料が使用される。したがって、絶縁膜３には、弾性係数が１ＧＰａ以下の材料を選択して使用する。
【００９６】
上記したように絶縁膜３の低弾性化によって絶縁膜３のき裂発生および成長を抑止できるようになるが、絶縁性テープ１５に導電性配線や絶縁膜３を形成する際の制約などから、絶縁膜３の弾性係数を低くできない場合がある。このような場合は、接着部材５の弾性係数を大きくすることによって絶縁膜３に発生する応力を低減し、絶縁膜３のき裂発生を抑止するのが望ましい。通常使用される絶縁膜３の弾性係数は２．５ＧＰａ程度であり、この絶縁膜３を使用する場合は、接着部材５の弾性係数を１０ＧＰａ以上に設定する。接着部材５に弾性係数の大きな材料を用いることによって絶縁膜３の温度変化時の変形を拘束でき、絶縁膜３のき裂発生を抑止することが可能となる。
【００９７】
【発明の効果】
以上述べたように本発明によれば、温度変化が加わった際の絶縁膜の変形量を小さくすることができ、また絶縁膜に発生する応力を低減することができるので、半導体装置内部の導電性配線の断線発生を防止することが可能となり、信頼性の高い半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１実施例による半導体装置のプリント配線基板上部の部材を取り除いた状態での平面図。
【図２】図１に示した半導体装置の断面図。
【図３】図１に示した第１実施例の他の様態を示すプリント配線基板上部の部材を取り除いた状態での平面図。
【図４】本発明の第２実施例による半導体装置のプリント配線基板上部の部材を取り除いた状態での平面図。
【図５】図４に示した半導体装置の断面図。
【図６】図４に示した第２実施例の他の様態を示すプリント配線基板上部の部材を取り除いた状態での平面図。
【図７】本発明の第３実施例による半導体装置のプリント配線基板上部の部材を取り除いた状態での平面図。
【図８】図７に示した半導体装置の断面図。
【図９】図７に示した第３実施例の他の様態を示すプリント配線基板上部の部材を取り除いた状態での平面図。
【図１０】本発明の第４実施例による半導体装置のプリント配線基板上部の部材を取り除いた状態での平面図。
【図１１】図１０に示した半導体装置の断面図。
【図１２】本発明の第５実施例による半導体装置のプリント配線基板上部の部材を取り除いた状態での平面図。
【図１３】図１２に示した半導体装置の断面図。
【図１４】本発明の第６実施例による半導体装置を示す断面図。
【図１５】本発明の第７実施例による半導体装置を示す絶縁性テープ上部の部材を取り除いた状態での平面図。
【図１６】図１５に示した半導体装置の断面図。
【図１７】図１５に示した第７実施例の他の様態を示すプリント配線基板上部の部材を取り除いた状態での平面図。
【図１８】図１７に示した半導体装置の断面図。
【図１９】本発明の第８実施例による半導体装置の絶縁性テープ上部の部材を取り除いた状態での平面図。
【図２０】図１９に示した半導体装置の断面図。
【図２１】本発明の第９実施例による半導体装置の絶縁性テープ上部の部材を取り除いた状態での平面図。
【図２２】図２１に示した半導体装置の断面図。
【図２３】本発明の第１０実施例による半導体装置の絶縁性テープ上部の部材を取り除いた状態での平面図。
【図２４】図２３に示した半導体装置の断面図。
【図２５】図２３に示した第１０実施例の他の様態を示す絶縁性テープ上部の部材を取り除いた状態での平面図。
【図２６】本発明の第１１実施例による半導体装置を示す断面図。
【図２７】本発明の第１２実施例による半導体装置の断面図。
【図２８】図２７に示した半導体装置の絶縁性テープ上部の部材を取り除いた状態での平面図。
【図２９】本発明の第１３実施例による半導体装置の断面図。
【図３０】従来のＢＧＡ型半導体装置の例を示す断面図
【図３１】図３０に示した従来の半導体装置であり、プリント配線基板上部の部材を取り除いた状態の平面図。
【図３２】絶縁膜のき裂の状態を説明する部分断面拡大図。
【図３３】導電性配線幅と発生応力の関係を有限要素法で解析した結果を示す図。
【図３４】絶縁膜の弾性係数と発生応力の関係を有限要素法で解析した結果を示す図。
【図３５】接着部材の弾性係数と絶縁膜表面の発生応力の関係を有限要素法で解析した結果を示す図。
【符号の説明】
１…半導体素子、１ａ…半導体素子端部、２…表面配線、２ａ…ボンディングパッド、２ｂ…スルーホール、２ｄ…内部配線、２ｄ…ランド、３…絶縁膜、４…プリント配線基板、４ａ…プリント配線基板の半導体素子固着面、５…接着部材、６…金属細線、７…封止樹脂、８…外部端子、９…絶縁膜、１０…絶縁膜のき裂、１１…接着部材のき裂、１２…半導体素子端部を横切る表面配線、１３…幅広部、１４…表面配線群、１５…絶縁性テープ、１５ａ…絶縁性テープの半導体素子固着面、１６…絶縁性テープの開口部、１７…変形拘束部材、１８…絶縁膜の開口部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with a conductive wiring that electrically connects a semiconductor element and an external terminal, and more particularly to a semiconductor device with improved reliability of the conductive wiring.
[0002]
[Prior art]
In order to cope with high-density mounting of semiconductor devices, ball grid array (BGA) type semiconductor devices suitable for increasing the number of pins, reducing the size, and increasing the speed have been put into practical use. The BGA type semiconductor device has a structure in which external terminals are two-dimensionally arranged from solder bumps or the like in the surface of the package of the semiconductor device. In the BGA type semiconductor device, a member called an interposer in which conductive wiring is formed on the surface or on the surface and inside is used for electrical connection between the semiconductor element and the external terminal. Conductive wiring is formed on the surface of the interposer using glass / epoxy as a base material for printed circuit boards and polyimide used in semiconductor devices using tape automated bonding (TAB) technology. Insulated tape etc. are used.
[0003]
An example of a conventional semiconductor device using a printed wiring board as an interposer is disclosed in US Pat. No. 5,216,278 and JP-A-6-506319. Examples of these conventional BGA type semiconductor devices are shown in FIGS. 30 is a cross-sectional view of a conventional BGA type semiconductor device, and FIG. 31 is a plan view of the conventional semiconductor device shown in FIG. 30 with the semiconductor element, sealing resin, and insulating film removed.
[0004]
A conventional BGA type semiconductor device includes a semiconductor element 1, a printed wiring board 4 having a conductive wiring formed on the surface and inside thereof, and an insulating film 3 formed so as to open a part of the conductive wiring. 1, an adhesive member 5 for fixing 1 to the printed wiring board surface, a metal wire 6 for electrically connecting the semiconductor element 1 and the conductive wiring of the printed wiring board, a semiconductor element 1, a metal wire 6, and the printed wiring board 4. It comprises a sealing resin 7 for sealing the semiconductor element fixing surface 4a and an external terminal 8. The conductive wiring is composed of a surface wiring 2, a bonding pad 2a, a through hole 2b, an internal wiring 2c, and a land 2d. The insulating film 3 is called a solder resist or a photoresist, and is formed by a screen printing method, a photo method or the like. Materials such as epoxy, polyimide and polybutadiene are used for the insulating film.
[0005]
The fine metal wire 6 and the conductive wiring of the printed wiring board 4 are connected by a bonding pad 2 a disposed outside the surface of the semiconductor element 1. In the bonding pad 2a portion, an opening 3a is formed in the insulating film 3, so that the fine metal wire 6 and the bonding pad 2a can be joined. The external terminals 8 are provided in a lattice pattern on the external terminal bonding surface 4 b of the printed wiring board, and are arranged both outside and inside the semiconductor element 1. In order to electrically connect the external terminal 8 disposed in the surface of the semiconductor element 1 and the semiconductor element 1, the surface wiring 2 intersects the outline of the semiconductor element 1 from the bonding pad 2 a toward the surface of the semiconductor element 1. The lands 2d are formed up to the land 2d formed on the external terminal joint surface 4b of the printed wiring board to which the external terminals 8 are joined through the through holes 2b connected to the surface wiring or the internal wiring 2c. Yes. In the land 2d, an opening 9a is formed in an insulating film 9 provided on the external terminal bonding surface 4b of the printed wiring board so that the land 2d and the external terminal 8 can be bonded.
[0006]
[Problems to be solved by the invention]
In the conventional semiconductor device, the linear expansion coefficient of the semiconductor element 1 is 2 to 3 × 10.- 6/ ℃, linear expansion coefficient of the printed wiring board is 16 × 10- 6It is about / ° C, and there is a large difference in the linear expansion coefficient between the two. When a temperature change is applied to the semiconductor device having such a configuration, thermal stress due to the difference between the linear expansion coefficients of the two is generated at the interface between the two, and the adhesive member 5 is cracked or peeled off. When a crack or the like occurs in the bonding member 5, the thermal stress generated at the interface between the two is concentrated on the end portion 1 a of the semiconductor element 1 and further increases. When the temperature change is repeatedly applied in such a situation, as shown in FIG. 32 (cross-sectional view showing the state of cracking of the insulating film of the conventional BGA type semiconductor device), the insulating film 3 starts from the end 1a portion of the semiconductor element. Crack 11 is generated.
[0007]
Next, the generation and growth mechanism of the crack 11 in the insulating film 3 will be described. The thermal stress generated by the difference in coefficient of linear expansion between the semiconductor element 1 and the printed wiring board 4 is shared by the entire interface between the two, but when a crack 10 occurs in the adhesive member 5, the crack 10 portion can bear the stress. As a result, stress concentrates on the end portion 1a of the semiconductor element. This stress concentration causes a crack 11 in the insulating film 3. Since the linear expansion coefficient of the insulating film 3 is relatively large and the adhesive member 5 is cracked, the insulating film 3 can be freely deformed by a temperature change. As the temperature change is repeated, the crack 11 of the insulating film 3 gradually progresses while repeating the opening and closing, and eventually grows into a crack crossing the insulating film 3.
[0008]
The inner side (hereinafter also referred to as the inner surface) and the outer side (hereinafter also referred to as the outer surface) of the outer edge portion of the semiconductor element 1 so that the surface wiring 2 crosses the semiconductor element end 1a where the crack 11 of the insulating film 3 is generated. ), The crack 11 also proceeds to the inside of the surface wiring 2, and in any case, there is a high possibility that the surface wiring 2 is disconnected. If the surface wiring is disconnected, the semiconductor device does not function normally, and the reliability of the semiconductor device is significantly reduced.
[0009]
A similar problem also occurs in a semiconductor device using an insulating tape used in the TAB technique in which conductive wiring is formed on the surface as an interposer.
[0010]
The present invention prevents and suppresses disconnection of conductive wiring continuously formed in and out of the surface of the semiconductor element so as to intersect with the outer edge portion (hereinafter also referred to as an outline) of the semiconductor element, An object is to provide a highly reliable semiconductor device.
[0011]
[Means for Solving the Problems]
The above problem can be solved by adopting a means for reducing or constraining a large deformation of the insulating film when a temperature change is applied, which is caused by the occurrence of a crack or the like in the adhesive member.
[0012]
The present invention includes a substrate having a principal surface, conductive wiring formed on the principal surface of the substrate, and an insulating film formed in a desired region between the principal surface of the substrate and the conductive wiring. A semiconductor element disposed on the opposite side of the insulating film from the substrate via an adhesive layer, wherein the conductive wiring is outside the outer edge of the semiconductor element and inside the outer edge of the semiconductor element. The semiconductor device formed so as to connect the two has the following configuration.
[0013]
(A) The conductive wiring is formed so that the width of the position facing the outer edge of the semiconductor element is wider than the width of the position facing the outer edge and / or the inner side of the semiconductor element. .
[0014]
(B) The conductive wiring formed in a region facing the central portion of each side constituting the outer edge portion of the semiconductor in the conductive wiring has a width at a position facing the outer edge portion of the semiconductor element. It is formed so that it may become wider than the width | variety of the position which opposes the outer side and / or inner side of the outer edge part.
[0015]
In the semiconductor device targeted by the present invention, the conductive wiring on the substrate surface is covered with an insulating film except for some openings. The conductive wiring is formed of copper (Cu) or a material obtained by plating the copper surface. Since the material used for the conductive wiring usually has a larger elastic coefficient than the material of the insulating film, the deformation of the insulating film when the temperature changes is restricted by the conductive wiring. Therefore, the amount of deformation of the insulating film can be reduced by increasing the wiring width of the conductive wiring and increasing the proportion of the conductive wiring in the insulating film.
[0016]
FIG. 33 shows a model in which a 1/4 portion of the BGA type semiconductor device is taken out and one conductive wiring is formed in the surface of the semiconductor element. When the semiconductor device is cooled by introducing a crack around the conductive wiring. It is the result of having analyzed the relation between the stress of the conductive wiring surface and the wiring width by the finite element method. The stress reduction effect by increasing the wiring width is clear from FIG. 33. In an actual semiconductor device, it is possible to further reduce the stress by increasing the wiring width of the plurality of conductive wirings.
[0017]
In addition to the stress reduction effect due to the reduction in the amount of deformation of the insulating film, by increasing the wiring width of the conductive wiring at the portion immediately below the end (outer edge) of the semiconductor element where the disconnection of the conductive wiring occurs, the conductive wiring Even if a crack is generated in the conductive wiring, an effect of extending the life until the disconnection (the number of repetitions of temperature change) can be obtained.
[0018]
Furthermore, in a semiconductor device equipped with a rectangular semiconductor element, the central part of the four sides constituting the outline of the semiconductor element is in a plane strain state, and the generated thermal stress increases, so the conductive wiring is disconnected at this part. The probability of doing is increased. Further, if the wiring width is increased more than necessary, the wiring capacity in the semiconductor device increases and noise is generated, which becomes a factor that hinders high-speed operation of the semiconductor element. Therefore, by increasing the wiring width of the conductive wiring formed so as to intersect the outline of the semiconductor element at least in the central portion of the side of the semiconductor element where the probability of occurrence of disconnection increases, the disconnection can be prevented, and the semiconductor device Thus, a semiconductor device can be obtained in consideration of the above characteristics.
[0019]
(C) The conductive wirings are formed in groups, and the conductive wirings located at both ends of the conductive wirings formed in the groups are located at positions facing the outer edge portions of the semiconductor elements. It is formed so that the width is wider than the width of the position facing the outside and / or the inside from the outer edge of the semiconductor element.
[0020]
Also according to the present invention, the proportion of the conductive wiring having a large elastic coefficient occupying the surface of the printed wiring board with respect to the insulating film can be increased, and deformation of the insulating film can be restrained. Further, in the conductive wiring group in which the number of terminals of the semiconductor device is large and the conductive wirings are arranged close to each other in parallel, it may be difficult to increase the wiring width of all the conductive wirings. Also, BGA type semiconductor devices often have semiconductor elements that require high-speed operation. If the conductive wiring width is made larger than necessary, the wiring capacity (inductance) increases, which impedes high-speed operation. There is. For this reason, it is necessary to increase the wiring width to a minimum. In the conductive wiring group, it is possible to pin the deformation of the insulating film at both ends by making the conductive wiring located at least at the end portion wider than the internal wiring, and the amount of deformation of the insulating film can be reduced. .
[0021]
(D) The conductive wiring is formed in a region of the substrate facing a region other than a central portion of each side constituting an outer edge portion of the semiconductor.
[0022]
In a semiconductor device equipped with a rectangular semiconductor element, the central part of the side that forms the outline of the semiconductor element is in a plane strain state, and the generated thermal stress increases, so the probability that the conductive wiring is disconnected at this part is high. Become. Therefore, the possibility of disconnection is reduced by forming a conductive wiring pattern so that no conductive wiring that intersects the outline of the semiconductor element and crosses the end portion is disposed in the central portion. Can do.
[0023]
(E) The conductive wiring is formed so as to obliquely cross the outer edge portion of the semiconductor element.
[0024]
By forming the conductive wiring so as to obliquely cross the outline of the semiconductor element, the proportion of the conductive wiring 2 in the plane of the semiconductor element can be increased, and the deformation restraining effect of the insulating film is increased. . In addition, since the cross-sectional area of the conductive wiring on the outline of the semiconductor element is apparently increased, it is possible to obtain an effect of extending the life from the occurrence of a crack to the disconnection of the wiring.
[0025]
(F) The relationship between the elastic modulus E1 of the insulating film and the elastic modulus E2 of the adhesive layer is such that E1 ≦ E2.
[0026]
The crack of the insulating film is generated and grows when the insulating film itself having a large linear expansion coefficient repeatedly contracts and expands due to a temperature change. The material used for the insulating film is an epoxy resin, a polyimide resin, a polybutadiene resin or the like, and the elastic coefficient of these materials is usually larger than that of the adhesive member. Since the stress generated at the tip of the crack is not relaxed when the elastic modulus of the insulating film is large, the growth of the crack is accelerated as the crack becomes longer. When the elastic modulus of the insulating film is reduced, deformation at the crack tip is facilitated, stress at the crack tip is relaxed, and crack growth can be suppressed.
[0027]
FIG. 34 shows a model in which a 1/4 portion of the BGA type semiconductor device is taken out and one conductive wiring is formed in the surface of the semiconductor element. When the semiconductor device is cooled by introducing a crack around the conductive wiring. It is the result of analyzing the relationship between the stress on the conductive wiring surface at the crack tip and the elastic modulus of the insulating film by the finite element method. From the figure, it is proved that when the elastic modulus of the insulating film is reduced, the stress at the crack tip is also reduced.
[0028]
(G) The elastic modulus of the insulating film is 10 Gpa or more.
[0029]
The crack of the insulating film that causes the disconnection of the conductive wiring is generated when the deformation of the insulating film becomes free due to the occurrence of a crack or separation in the adhesive member. Similarly, if the elastic modulus of the adhesive member is small, deformation of the insulating film cannot be constrained, and cracks are likely to occur in the insulating film. Therefore, if the deformation of the insulating film at the time of temperature change is constrained by increasing the elastic coefficient of the adhesive member, it is possible to suppress the occurrence of cracks in the insulating film.
[0030]
FIG. 35 is a model in which a cross section of a BGA type semiconductor device is taken out, and the result of analyzing the insulating film surface stress at the end of the semiconductor element when the semiconductor device is cooled by the finite element method while changing the elastic coefficient of the adhesive member. It is. In this analysis, the elastic coefficient of the insulating film is 2.5 GPa. From the figure, it is clear that as the elastic modulus of the adhesive member is increased, the stress of the insulating film gradually decreases. However, the rate of decrease in the stress is reduced from about 10 GPa, and it becomes a substantially constant value. Yes. From this result, if the elastic modulus of the adhesive member is set to 10 GPa or more, the stress of the insulating film can be maintained at a low value.
[0031]
Further, according to the trial evaluation conducted by the inventors, a crack was generated in the insulating film after 100 times of temperature change in the semiconductor device in which the elastic modulus of the adhesive member was 1 GPa. However, when the elastic modulus was 17 GPa, the insulating film was not cracked even after 400 times, and the effect could be confirmed.
[0032]
As the elastic coefficient of the adhesive member is increased, the stress generated in the semiconductor element due to the difference in linear expansion coefficient between the semiconductor element and the printed wiring board increases, and the possibility that the semiconductor element will crack increases. Therefore, the range of the elastic modulus used for the adhesive member is 10 GPa as the lower limit, and the upper limit is a value that does not cause cracks in the semiconductor element.
[0033]
Further, the semiconductor device of the present invention includes an insulating tape having one main surface, conductive wiring formed on one main surface of the insulating tape, and one main surface of the insulating tape and the conductive wiring. An insulating film formed in a desired region, and a semiconductor element disposed on the opposite side of the insulating film from the insulating tape via an adhesive layer, the conductive wiring is an outer edge portion of the semiconductor element A semiconductor device formed to connect the outer side and the inner side of the outer edge of the semiconductor element has the following configuration.
[0034]
(H) The conductive wiring is exposed on the insulating tape side of the end portion of the semiconductor element.
[0035]
That is, by removing the insulating film where cracks are likely to occur from the part directly under the edge of the semiconductor element where thermal stress is concentrated, and covering this part with a sealing resin that is tougher than the insulating film, cracks are generated and grown. Can be suppressed.
[0036]
(I) The insulating film is formed in a region requiring insulation from the conductive wiring inside the outer edge portion of the semiconductor element.
[0037]
The insulating film is provided to protect the conductive wiring from coming into contact with other conductor members and the like to cause a short circuit. Therefore, the amount of deformation of the insulating film at the time of temperature change can be reduced by reducing the volume of the insulating film in the semiconductor element surface so as to cover only the periphery of the conductive wiring.
[0038]
(J) A member that restrains deformation of the insulating film is formed in a region facing a region inside the outer edge portion of the semiconductor element of the insulating tape.
[0039]
The member for restraining deformation is preferably formed of a foil-like member, and is preferably formed of the same material as the conductive material. Also, in a semiconductor device equipped with a square semiconductor element, the central portion of the side constituting the outline of the semiconductor element is in a plane strain state, and the generated thermal stress increases, so there is a probability that the conductive wiring is disconnected at this portion. Get higher. Therefore, deformation of the insulating film at the central portion of the side of the semiconductor element may be restricted at a minimum.
[0040]
It is also effective to make the elastic coefficient of the pre-insulating film equal to or less than that of the adhesive member.
[0041]
The crack of the insulating film is generated and grows when the insulating film itself having a large linear expansion coefficient repeatedly contracts and expands due to a temperature change. The material used for the insulating film is an epoxy resin, a polyimide resin, a polybutadiene resin or the like, and the elastic coefficient of these materials is usually larger than that of the adhesive member. Since the stress generated at the tip of the crack is not relaxed when the elastic modulus of the insulating film is large, the growth of the crack is accelerated as the crack becomes longer. When the elastic modulus of the insulating film is reduced, the plastic deformation region at the crack tip is expanded, so that the stress at the crack tip is relaxed and crack growth can be suppressed.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail using examples shown in the drawings.
[First embodiment]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention with a semiconductor element, a sealing resin, and an insulating film removed, and FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. is there.
[0043]
In the figure, conductive wiring is formed on the surface and inside of the printed wiring board 4, and the conductive wiring is composed of a surface wiring 2, a bonding pad 2a, a through hole 2b, an internal wiring 2c, and a land 2d. Yes. Insulating films 3 and 9 having openings 3a and 9a are formed on the surfaces 4a and 4b of the printed wiring board 4, respectively. The rectangular semiconductor element 1 is fixed to the semiconductor element fixing surface 4a of the printed wiring board by an adhesive member 5. The semiconductor element 1 and the conductive wiring are electrically connected by a fine metal wire 6, and the fine metal wire 6 is joined to a bonding pad 2 a provided outside the surface of the semiconductor element 1. In the bonding pad 2a portion, an opening 3a is provided in the insulating film 3 so that the fine metal wire 6 can be bonded. The conductive wiring extends from the bonding pad 2a to the land 2d of the external terminal bonding surface 4b of the printed wiring board through the surface wiring 2 on the surface of the printed wiring board, the through hole 2b in the printed wiring board 4 and the internal wiring 2c. By joining the external terminal 8 to the land 2d, the semiconductor element and the external terminal are electrically connected by the conductive wiring. In the land 2d portion, an opening 9a is provided in the insulating film 9, so that the external terminal 8 can be joined to the land 2d. The semiconductor element 1, the fine metal wire 6 and the semiconductor element fixing surface 4 a of the printed wiring board are covered with a sealing resin 7.
[0044]
Of the surface wiring 2 formed on the semiconductor element fixing surface 4a of the printed wiring board, a wide portion 13 is provided on the surface wiring 12 that crosses the lower portion of the semiconductor element end 1a so as to intersect the outline of the semiconductor element 1. It has been. The wide portion 13 of the surface wiring shown in FIG. 1 is formed by increasing the wiring width between the semiconductor element end 1a and the through hole 2b.
[0045]
For the surface wiring 2, a copper (Cu) foil or a copper foil having a surface plated with gold (Au), nickel (Ni), or the like is used. The printed wiring board 4 is made of a material based on glass / epoxy or the like. A material such as gold (Au), silver (Ag), or aluminum (Al) is used for the thin metal wire 6. For the sealing resin 7, for example, an epoxy resin filled with silica particles is used. The external terminal 8 is made of solder (for example, Pb—Sn eutectic solder) that is widely used when mounting a semiconductor device.
[0046]
According to the semiconductor device of this embodiment, the deformation of the insulating film when the temperature change is applied can be restrained by the surface wiring provided with the wide portion, and the generation and growth of the crack of the insulating film can be suppressed. Can do.
[0047]
In the embodiment shown in FIG. 1, the example in which the wide portion 13 is formed in the surface wiring 2 between the through-hole 2b from the portion immediately below the semiconductor element end portion 1a is shown. The amount of deformation of the insulating film 3 is the minimum at the center of the semiconductor element 1 and the maximum at the end, and the maximum stress is generated immediately below the end 1a. Therefore, the crack of the insulating film 3 occurs at the end 1a of the semiconductor element. To do. For this reason, if the deformation of the insulating film is constrained at the end portion 1a of the semiconductor element, the minimum necessary effect can be obtained. Therefore, the wide portion 13 only needs to be formed at least immediately below the semiconductor element end 1a as shown in FIG. The embodiment as shown in FIG. 3 is particularly effective in the case of a semiconductor device in which the wiring capacity cannot be increased due to the requirement for high-speed operation.
[0048]
[Second Embodiment]
4 is a plan view of the semiconductor device according to the second embodiment of the present invention with the semiconductor element, the sealing resin, and the insulating film removed, and FIG. 5 is a cross-sectional view of the semiconductor device shown in FIG. is there.
[0049]
Since the basic configuration of the semiconductor device is the same as that of the first embodiment, the description thereof is omitted.
In the present embodiment, the surface wiring 12 is formed on the semiconductor element fixing surface 4a of the printed wiring board of the surface wiring 2 and crosses the semiconductor element end 1a so as to intersect with the outline of the semiconductor element 1. The wide portion 13 is provided on the surface wiring 12a disposed in the central portion 1b of the long side of the semiconductor element. The wide portion 13 of the surface wiring 12 shown in FIG. 4 is formed by increasing the wiring width between the through holes 2b from the portion immediately below the semiconductor element end portion 1a.
[0050]
In the semiconductor device in which the rectangular semiconductor element 1 is mounted as in the present embodiment, for example, the central portion 1b of the long side of the semiconductor element is in a plane strain state, and the stress generated immediately below the semiconductor element end 1a of the central portion 1b is generated. It becomes larger than the stress generated in the semiconductor element corner portion 1c. Therefore, since the disconnection of the surface wiring is likely to occur at the end 1a of the central portion 1b on the long side of the semiconductor element, the surface wiring 2 in this portion is widened to restrain the deformation of the insulating film 3, thereby The disconnection of the wiring can be prevented.
[0051]
In this embodiment, an example is shown in which the surface wiring crosses the end portion on the long side of the semiconductor element. However, in the semiconductor device in which the conductive wiring is arranged so as to cross the end portion on the short side of the semiconductor element, the wide portion 13 may be formed also on the surface wiring on the short side.
[0052]
In the embodiment shown in FIG. 4, an example in which the wide portion 13 is formed in the surface wiring 2 between the through-hole 2 b from the portion immediately below the semiconductor element end portion 1 a is shown. The amount of deformation of the insulating film 3 is the minimum at the center of the semiconductor element 1 and the maximum at the end, and the maximum stress is generated immediately below the end 1a. Therefore, the crack in the insulating film 3 occurs at the end 1a of the semiconductor element. To do. For this reason, if the deformation of the insulating film is constrained at the end portion 1a of the semiconductor element, the minimum necessary effect can be obtained. Therefore, the wide portion 13 only needs to be formed at least immediately below the semiconductor element end portion 1a as shown in FIG. The embodiment as shown in FIG. 6 is particularly effective in the case of a semiconductor device in which the wiring capacity cannot be increased due to the requirement for high-speed operation.
[0053]
[Third embodiment]
7 is a plan view of the semiconductor device according to the third embodiment of the present invention with the semiconductor element, the sealing resin, and the insulating film removed, and FIG. 8 is a cross-sectional view of the semiconductor device shown in FIG. is there.
[0054]
Since the basic configuration of the semiconductor device is the same as that of the first embodiment, the description thereof is omitted.
In the present embodiment, among the surface wirings 2 formed on the semiconductor element fixing surface 4a of the printed wiring board, the plurality of surface wirings cross the end 1a so as to intersect the outline of the semiconductor element 1 substantially in parallel. In the surface wiring group 14, the wide portion 13 is provided in the surface wiring located at the end portion 14a of the surface wiring group, and the wiring width is wider than the surface wiring located in the inside 14b of the surface wiring group. The wide portion 13 of the conductive wiring shown in FIG. 7 is formed by increasing the wiring width between the semiconductor element end 1a and the through hole 2b.
[0055]
According to the semiconductor device shown in the present embodiment, the wide portion is formed in the surface wiring located at least at the end of the surface wiring group, so that the deformation of the insulating film when the temperature change is applied is widened at both ends. Pinning can be performed by the surface wiring provided with the portion, and generation and growth of a crack in the insulating film can be suppressed. In addition, the embodiment of FIG. 7 can minimize the increase in wiring capacitance, and is effective particularly in a semiconductor device that requires high-speed operation.
[0056]
In the embodiment shown in FIG. 7, an example in which the wide portion 13 is formed between the through hole 2 b from the portion immediately below the semiconductor element end portion 1 a of the surface wiring 2 located at the end portion 14 a of the surface wiring group 14. Since the deformation amount of the insulating film 3 is maximized at the end portion of the semiconductor element 1, the crack of the insulating film 3 is generated immediately below the semiconductor element end portion 1a. For this reason, if the deformation of the insulating film is constrained at the end portion 1a of the semiconductor element, the minimum necessary effect can be obtained. Therefore, the wide portion 13 only needs to be formed at least directly below the semiconductor element end portion 1a as shown in FIG. The embodiment as shown in FIG. 9 is particularly effective in the case of a semiconductor device in which the wiring capacity cannot be increased due to the requirement for high-speed operation.
[0057]
[Fourth embodiment]
10 is a plan view of the semiconductor device according to the fourth embodiment of the present invention with the semiconductor element, sealing resin, and insulating film removed, and FIG. 11 is a cross-sectional view of the semiconductor device shown in FIG. is there.
[0058]
Since the basic configuration of the semiconductor device is the same as that of the first embodiment, the description thereof is omitted.
In this embodiment, on the semiconductor element fixing surface 4a of the printed wiring board, a surface wiring 2 that crosses the end 1a is provided so as to intersect the outline of the semiconductor element 1 at the central portion 1b on the long side of the semiconductor element. Absent. The surface wiring 2 in this portion extends from the bonding pad 2a toward the outside of the printed wiring board 4, and is connected to the land 2d through the through hole 2b and the internal wiring 2c. Accordingly, only the insulating film 3 and the adhesive member 5 are provided on the semiconductor element fixing surface 4a of the printed wiring board in the portion immediately below the semiconductor element end 1a of the central portion 1b. On the other hand, in the vicinity of the corner 1c of the semiconductor element, the surface wiring 2 is formed so as to cross the semiconductor element end 1a.
[0059]
In the semiconductor device in which the rectangular semiconductor element 1 is mounted as in the present embodiment, for example, the central portion 1b on the long side of the semiconductor element is in a plane strain state, and stress generated in the portion immediately below the semiconductor element end 1a of the central portion 1b is generated. It becomes larger than the stress generated in the semiconductor element corner portion 1c. For this reason, there is a high probability that the disconnection of the conductive wiring occurs at the portion immediately below the end portion 1a of the central portion 1b on the long side of the semiconductor element. Therefore, in the central portion 1b on the long side of the semiconductor element, the surface wiring 2 is routed so as not to cross the semiconductor element end 1a, thereby preventing disconnection of the conductive wiring due to the crack of the insulating film 3. it can.
[0060]
[Fifth embodiment]
12 is a plan view of the semiconductor device according to the fifth embodiment of the present invention with the semiconductor element, the sealing resin, and the insulating film removed, and FIG. 13 is a cross-sectional view of the semiconductor device shown in FIG. .
[0061]
Since the basic configuration of the semiconductor device is the same as that of the first embodiment, the description thereof is omitted.
In the present embodiment, the surface wiring 2 formed on the semiconductor element fixing surface 4a of the printed wiring board, which intersects the outline of the semiconductor element 1 and crosses the semiconductor element end 1a. Among these, the surface wiring 12 disposed in the central portion 1 b on the long side of the semiconductor element is formed so as to cross the semiconductor element end 1 a obliquely with respect to the outline of the semiconductor element 1.
[0062]
By forming the surface wiring 12 so as to obliquely cross the end portion 1a of the semiconductor element, the proportion of the surface wiring 2 in the plane of the semiconductor element 1 can be made larger than when the surface wiring 12 is crossed at a right angle. The deformation restraining effect is increased. Moreover, since the cross-sectional area of the surface wiring on the semiconductor element outline is apparently increased, it is possible to obtain an effect of extending the life from the occurrence of a crack to the wiring.
[0063]
In the semiconductor device in which the rectangular semiconductor element 1 is mounted as in the present embodiment, for example, the central portion 1b on the long side of the semiconductor element is in a plane strain state, and the stress generated in the portion immediately below the semiconductor element end portion 1a in this portion. growing. For this reason, there is a high probability that the disconnection of the conductive wiring occurs in the central portion 1b on the long side of the semiconductor element. Therefore, it is necessary to restrain the deformation of the insulating film 3 at least in the central portion 1b and reduce the deformation amount.
[0064]
[Sixth embodiment]
FIG. 14 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention.
[0065]
Since the basic configuration of the semiconductor device is the same as that of the first embodiment, the description thereof is omitted.
In the semiconductor device of this embodiment, the insulating film 3 is formed of a material having an elastic coefficient equal to or lower than that of the adhesive member 5. By reducing the elasticity of the insulating film 3, even if a crack occurs in the insulating film 3, the insulating film itself can be easily deformed, so that the stress generated at the tip of the crack can be relaxed by the deformation. . Therefore, the effect of suppressing the growth of cracks due to repeated temperature changes can be obtained, and disconnection of the surface wiring can be prevented.
[0066]
A material having an elastic modulus of about 1 GPa is usually used for the adhesive member 5. Therefore, it is desirable to select and use a material having an elastic coefficient of 1 GPa or less for the insulating film 3.
[0067]
As described above, crack generation and growth of the insulating film 3 can be suppressed by lowering the elasticity of the insulating film 3, but due to restrictions in manufacturing the printed wiring board 4, the elastic coefficient of the insulating film 3 cannot be lowered. There is a case. In such a case, it is desirable to reduce the stress generated in the insulating film 3 by increasing the elastic coefficient of the adhesive member 5 and to suppress the generation of cracks in the insulating film 3. The elastic coefficient of the insulating film 3 that is normally used is about 2.5 GPa. When the insulating film 3 is used, the elastic coefficient of the adhesive member 5 is set to 10 GPa or more. By using a material having a large elastic coefficient for the adhesive member 5, it is possible to restrain deformation of the insulating film 3 when the temperature changes, and it is possible to suppress generation of cracks in the insulating film 3.
[0068]
[Seventh embodiment]
15 is a plan view of the semiconductor device according to the seventh embodiment of the present invention with the sealing resin, the adhesive member, and the insulating film removed, and FIG. 16 is a cross-sectional view of the semiconductor device shown in FIG. .
[0069]
In the figure, a conductive wiring and an insulating film 3 are formed on a semiconductor element fixing surface 15a of an insulating tape 15, and the conductive wiring is composed of a surface wiring 2, a bonding pad 2a, and a land 2d. The insulating film 3 is provided with an opening 3a for exposing the bonding pad 2a. The rectangular semiconductor element 1 is fixed to the semiconductor element fixing surface 15 a of the insulating tape 15 by the adhesive member 5. The semiconductor element 1 and the conductive wiring are electrically connected by a metal thin wire 6, and the metal thin wire 6 is joined to a bonding pad 2 a located outside the surface of the semiconductor element 1. In the bonding pad 2a portion, an opening 3a is provided in the insulating film 3 so that the fine metal wire 6 can be bonded. The surface wiring 2 is formed so as to intersect the outline of the semiconductor element 1 and cross the end portion 1a from the bonding pad 2a to the land 2d disposed in the plane of the semiconductor element 1. In the portion where the land 2 d is provided, an opening 16 is formed in the insulating tape 15, and the external terminal 8 is joined to the land 2 d inside the opening 16. The external terminal 8 is provided on the external terminal bonding surface 15b opposite to the semiconductor element fixing surface 15a of the insulating tape 15, and is bonded to a predetermined position on the mounting substrate when the semiconductor device is mounted. The semiconductor element 1, the fine metal wire 6 and the semiconductor element fixing surface 15 a of the insulating tape are covered with a sealing resin 7.
[0070]
Of the surface wiring 2 that crosses the semiconductor element end 1a, the wide portion 13 is formed in the surface wiring 2 that is disposed in the central portion 1b of each side of the semiconductor element 1. The wide portion 13 of the surface wiring 2 shown in FIG. 15 is formed by increasing the wiring width between the land 2d from the end portion 1a of the semiconductor element.
[0071]
For the conductive wiring such as the surface wiring 2, a copper (Cu) foil or a copper foil having a surface plated with gold (Au), nickel (Ni), or the like is used. The insulating tape 15 is made of a material such as polyimide or glass / epoxy. A material such as gold (Au), silver (Ag), or aluminum (Al) is used for the thin metal wire 6. For the adhesive member 5, for example, a material based on an epoxy resin is used. For the sealing resin 7, for example, an epoxy resin filled with silica particles is used. The external terminal 8 is made of solder (for example, Pb—Sn eutectic solder) that is widely used when mounting a semiconductor device.
[0072]
According to the semiconductor device of this embodiment, the deformation of the insulating film when the temperature change is applied can be restrained by the surface wiring provided with the wide portion, and the generation and growth of the crack of the insulating film can be suppressed. Can do.
[0073]
The wide portion 13 only needs to be formed on the surface wiring 2 disposed in the central portion 1b of each side of the semiconductor element 1 as shown in FIG. In the semiconductor device in which the rectangular semiconductor element 1 is mounted as in this embodiment, the central portion 1b of each side of the semiconductor element is in a plane strain state, and the stress generated immediately below the semiconductor element end 1a is increased. Accordingly, since the probability of occurrence of disconnection of the surface wiring 2 at this position increases, it is possible to prevent disconnection of the surface wiring by restraining the displacement of the insulating film 3 at this portion.
[0074]
In the embodiment shown in FIG. 15, an example in which the thin metal wire 6 is used for electrical connection between the semiconductor element 1 and the conductive wiring is shown. The connection between the two may be performed by a method other than a thin metal wire. For example, the connection is performed using a foil-like lead used in the TAB technique or a fine bump using the flip chip technique.
[0075]
In the embodiment shown in FIG. 15, the wide portion 13 is formed on the surface wiring 2 between the semiconductor element end 1a portion and the land 2d. Since the deformation amount of the insulating film 3 is minimum at the center of the semiconductor element 1 and maximum at the end 1a, the crack of the insulating film 3 occurs at the end 1a of the semiconductor element. Therefore, if the deformation of the insulating film 3 is constrained at the semiconductor element end portion 1a, the minimum necessary effect can be obtained. Therefore, as shown in the plan view of FIG. 17, the wide portion 13 only needs to be formed at least directly below the semiconductor element end 1a. 18 is a cross-sectional view of the semiconductor device shown in FIG. The embodiment as shown in FIG. 17 is particularly effective in the case of a semiconductor device in which the wiring capacity cannot be increased due to the requirement for high-speed operation.
[0076]
[Eighth embodiment]
19 is a plan view of the semiconductor device according to the eighth embodiment of the present invention with the semiconductor element, the sealing resin, and the insulating film removed, and FIG. 20 is a cross-sectional view of the semiconductor device shown in FIG. .
[0077]
Since the basic configuration as a semiconductor device is the same as that of the seventh embodiment, the description is omitted.
In the present embodiment, among the surface wirings 2, in the surface wiring group 14 in which the plurality of surface wirings 2 are arranged substantially in parallel, the wide portion 13 is provided on the surface wiring located at the end portion 14 a of the surface wiring group. The wiring width is wider than the surface wiring located in the inside 14b of the surface wiring group. The wide portion 13 of the surface wiring shown in FIG. 19 is formed by increasing the wiring width between the land 2d from the end portion 1a of the semiconductor element.
[0078]
According to the semiconductor device shown in the present embodiment, the wide portion is formed in the surface wiring located at least at the end of the surface wiring group, so that the deformation of the insulating film when the temperature change is applied is widened at both ends. Pinning can be performed by the conductive wiring provided with the portion, and generation and growth of a crack in the insulating film can be suppressed.
[0079]
In the embodiment shown in FIG. 19, the wide portion 13 is formed from the semiconductor element end 1a portion of the surface wiring 2 located at both ends 14a of the surface wiring group 14 to the land 2d. Since the amount of deformation of the insulating film 3 is greatest at the semiconductor element end 1a, the crack of the insulating film 3 occurs at the end 1a. For this reason, if the deformation | transformation of an insulating film is restrained in the semiconductor element edge part 1a part, the minimum required effect will be acquired. Therefore, the wide part 13 should just be formed at least in the part directly under the semiconductor element edge part 1a. Thus, reducing the formation range of the wide portion is effective in the case of a semiconductor device in which the wiring capacity cannot be increased due to the requirement for high-speed operation.
[0080]
[Ninth embodiment]
21 is a plan view of the semiconductor device according to the ninth embodiment of the present invention with the semiconductor element, the sealing resin, and the insulating film removed, and FIG. 22 is a cross-sectional view of the semiconductor device shown in FIG. .
[0081]
Since the basic configuration as a semiconductor device is the same as that of the seventh embodiment, the description is omitted.
In the present embodiment, among the surface wirings 2, the wiring width of the surface wiring 12 extended so as to cross the end portion 1 a of the semiconductor element is wider than the other surface wirings 2. In the surface wiring 12 crossing the semiconductor element end 1a shown in FIG. 21, the width of all wiring between the bonding pad 2a and the land 2d is wide.
[0082]
According to the semiconductor device of this embodiment, the deformation of the insulating film when the temperature change is applied can be restrained by the surface wiring provided with the wide portion, and the generation and growth of the crack of the insulating film can be suppressed. Can do.
[0083]
In the embodiment shown in FIG. 21, the surface wiring 12 traversing the semiconductor element end 1a is made wider than the other surface wiring. Since the deformation amount of the insulating film 3 is minimum at the center of the semiconductor element 1 and maximum at the end 1a, the crack of the insulating film 3 occurs at the end 1a of the semiconductor element. Therefore, if the deformation of the insulating film 3 is constrained at the semiconductor element end portion 1a, the minimum necessary effect can be obtained. Therefore, the portion where the wiring width is widened may be at least a portion immediately below the semiconductor element end 1a.
[0084]
[Tenth embodiment]
FIG. 23 is a plan view of the semiconductor device according to the tenth embodiment of the present invention with the semiconductor element, the sealing resin, and the insulating film removed, and FIG. 24 is a cross-sectional view of the semiconductor device shown in FIG. .
[0085]
Since the basic configuration as a semiconductor device is the same as that of the seventh embodiment, the description is omitted.
In this embodiment, a rectangular deformation restraining member 17 is provided at a central portion 15c in the semiconductor element 1 surface where the land 2d is not formed, which is the semiconductor element fixing surface 15a of the insulating tape. Desirably, the deformation restraining member 17 is made of the same material as that of the surface wiring 2, and a material made of copper (Cu) or the like in the form of a foil is used. By providing a plate-like member made of a material having high rigidity such as copper on the surface of the insulating tape in the semiconductor element surface, it is possible to obtain an effect of restraining deformation of the insulating film due to temperature change.
[0086]
According to the semiconductor device shown in this embodiment, deformation of the insulating film can be constrained by the deformation constraining member, and the deformation amount can be reduced. As a result, the generation and growth of cracks in the insulating film can be suppressed.
[0087]
In the embodiment shown in FIG. 23, the example in which the deformation restraining member 17 is formed in the same square as the shape of the semiconductor element 1 is shown. In the semiconductor device in which the rectangular semiconductor element 1 is mounted as in this embodiment, the central portion of each side of the semiconductor element is in a plane strain state, and the stress generated immediately below the semiconductor element end portion 1a is increased at this portion. Therefore, since the probability of occurrence of disconnection of the surface wiring is increased at this position, disconnection of the surface wiring can be prevented by restraining the displacement of the insulating film 3 at least in this portion. FIG. 25 shows an example in which a cross-shaped deformation restraining member 17 coinciding with the center line passing through two opposite sides of the semiconductor element is formed in order to reduce the deformation amount of the insulating film at the central portion of each side of the semiconductor element. . By making the deformation constraining member 17 into a shape as shown in FIG. 25, it is possible to constrain the deformation of the insulating film at the central portion of each side of the semiconductor element. Further, by reducing the amount of copper foil used, the amount of warping of the insulating tape can be reduced, and the work of fixing the semiconductor element to the insulating tape can be facilitated.
[0088]
[Eleventh embodiment]
FIG. 26 is a sectional view of a semiconductor device according to the eleventh embodiment of the present invention.
[0089]
Since the basic configuration as a semiconductor device is the same as that of the seventh embodiment, the description is omitted.
In this embodiment, since the opening 3b is provided in the insulating film 3 immediately below the semiconductor element end portion 1a, the insulating film 3 does not exist in this portion, and the sealing resin 7 is a semiconductor. It is interposed between the element 1 and the insulating tape 15. By interposing a sealing resin having a higher toughness than the material used for the insulating film 3 directly below the semiconductor element end 1a, the generation of cracks from the semiconductor element end 1a can be suppressed.
[0090]
[Twelfth embodiment]
27 is a cross-sectional view of a semiconductor device according to a twelfth embodiment of the present invention, and FIG. 28 is a plan view of the semiconductor device shown in FIG. 27 with the semiconductor element, sealing resin, and insulating film removed. .
[0091]
Since the basic configuration as a semiconductor device is the same as that of the seventh embodiment, the description is omitted.
In this embodiment, an opening 18 is provided in the insulating film 3 at the central portion 15c in the semiconductor element 1 surface where the land 2d is not formed, which is the semiconductor element fixing surface 15a of the insulating tape. In the central portion 15c, the adhesive member 5 covers the semiconductor element fixing surface 15a of the insulating tape. That is, the insulating film 3 is provided outside the surface of the semiconductor element 1 at a portion other than the bonding pad 2a, and within the surface at a portion where the surface wiring 2 and the land 2d are formed.
[0092]
By not providing the insulating film 3 in the central portion 15c in the semiconductor element surface, the occupation ratio of the insulating film in the semiconductor element surface is reduced, so that the deformation amount of the entire insulating film due to temperature change is reduced, and the insulating film Crack initiation and growth are suppressed.
[0093]
In the semiconductor device shown in FIG. 27, an example is shown in which the opening 18 is provided in the central portion 15 c and the surface wiring 2 and the land 2 d in the surface of the semiconductor element 1 are covered with the insulating film 3. In order to further reduce the volume occupied by the insulating film 3 in the semiconductor element surface, an opening may be provided between the surface wiring 2 and the land 2d. By providing the insulating film 3 so as to cover at least the periphery of the surface wiring 2 and the land 2d, the deformation amount of the insulating film can be further reduced.
[0094]
[Thirteenth embodiment]
FIG. 29 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention.
Since the basic configuration as a semiconductor device is the same as that of the seventh embodiment, the description is omitted.
In the semiconductor device of this embodiment, the insulating film 3 is formed of a material having an elastic coefficient equal to or lower than that of the adhesive member 5. By reducing the elasticity of the insulating film 3, even if a crack occurs in the insulating film 3, the insulating film itself can be easily deformed, so that the stress generated at the tip of the crack can be relaxed by the deformation. . Therefore, the effect of suppressing the growth of cracks due to repeated temperature changes can be obtained, and disconnection of the conductive wiring can be prevented.
[0095]
A material having an elastic modulus of about 1 GPa is usually used for the adhesive member 5. Therefore, a material having an elastic coefficient of 1 GPa or less is selected and used for the insulating film 3.
[0096]
As described above, the generation of cracks and growth of the insulating film 3 can be suppressed by lowering the elasticity of the insulating film 3, but due to restrictions in forming the conductive wiring and the insulating film 3 on the insulating tape 15, In some cases, the elastic modulus of the insulating film 3 cannot be lowered. In such a case, it is desirable to reduce the stress generated in the insulating film 3 by increasing the elastic coefficient of the adhesive member 5 and suppress the generation of cracks in the insulating film 3. The elastic coefficient of the insulating film 3 that is normally used is about 2.5 GPa. When the insulating film 3 is used, the elastic coefficient of the adhesive member 5 is set to 10 GPa or more. By using a material having a large elastic coefficient for the adhesive member 5, it is possible to restrain deformation of the insulating film 3 when the temperature changes, and it is possible to suppress generation of cracks in the insulating film 3.
[0097]
【The invention's effect】
As described above, according to the present invention, the amount of deformation of the insulating film when a temperature change is applied can be reduced, and the stress generated in the insulating film can be reduced. Occurrence of disconnection of the conductive wiring can be prevented, and a highly reliable semiconductor device can be provided.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention with a member on an upper part of a printed wiring board removed.
FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.
3 is a plan view showing a state in which a member on an upper part of a printed wiring board showing another aspect of the first embodiment shown in FIG. 1 is removed; FIG.
FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention with a member on an upper part of a printed wiring board removed.
5 is a cross-sectional view of the semiconductor device shown in FIG. 4;
6 is a plan view showing a state in which a member on an upper part of a printed wiring board showing another aspect of the second embodiment shown in FIG. 4 is removed. FIG.
FIG. 7 is a plan view of a semiconductor device according to a third embodiment of the present invention with a member on an upper part of a printed wiring board removed.
8 is a cross-sectional view of the semiconductor device shown in FIG. 7;
9 is a plan view showing a state in which a member on an upper portion of a printed wiring board showing another aspect of the third embodiment shown in FIG. 7 is removed. FIG.
FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment of the present invention with a member on an upper part of a printed wiring board removed.
11 is a cross-sectional view of the semiconductor device shown in FIG.
FIG. 12 is a plan view of a semiconductor device according to a fifth embodiment of the present invention with a member on an upper part of a printed wiring board removed.
13 is a cross-sectional view of the semiconductor device shown in FIG.
FIG. 14 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
FIG. 15 is a plan view of a semiconductor device according to a seventh embodiment of the present invention with the member on the insulating tape removed;
16 is a cross-sectional view of the semiconductor device shown in FIG.
FIG. 17 is a plan view showing a state in which a member on an upper part of a printed wiring board showing another aspect of the seventh embodiment shown in FIG. 15 is removed;
18 is a cross-sectional view of the semiconductor device shown in FIG.
FIG. 19 is a plan view of the semiconductor device according to the eighth embodiment of the present invention with the member on the insulating tape removed;
20 is a cross-sectional view of the semiconductor device shown in FIG. 19;
FIG. 21 is a plan view of a semiconductor device according to a ninth embodiment of the present invention with a member on an insulating tape removed;
22 is a cross-sectional view of the semiconductor device shown in FIG. 21;
FIG. 23 is a plan view of the semiconductor device according to the tenth embodiment of the present invention with the insulating tape upper member removed;
24 is a cross-sectional view of the semiconductor device shown in FIG. 23;
FIG. 25 is a plan view showing a state in which a member on the upper side of the insulating tape showing another aspect of the tenth embodiment shown in FIG. 23 is removed.
FIG. 26 is a sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.
FIG. 27 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention.
28 is a plan view of the semiconductor device shown in FIG. 27 in a state in which a member above the insulating tape is removed.
FIG. 29 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention.
FIG. 30 is a sectional view showing an example of a conventional BGA type semiconductor device.
31 is a plan view of the conventional semiconductor device shown in FIG. 30 with a member on an upper part of a printed wiring board removed. FIG.
FIG. 32 is an enlarged partial cross-sectional view illustrating a state of a crack in the insulating film.
FIG. 33 is a diagram showing a result of analyzing a relationship between conductive wiring width and generated stress by a finite element method.
FIG. 34 is a diagram showing a result of analyzing a relationship between an elastic coefficient of an insulating film and a generated stress by a finite element method.
FIG. 35 is a diagram showing a result of analyzing a relationship between an elastic coefficient of an adhesive member and a generated stress on the surface of an insulating film by a finite element method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 1a ... Semiconductor element edge part, 2 ... Surface wiring, 2a ... Bonding pad, 2b ... Through hole, 2d ... Internal wiring, 2d ... Land, 3 ... Insulating film, 4 ... Printed wiring board, 4a ... Print Semiconductor element fixing surface of wiring board, 5 ... adhesive member, 6 ... metal thin wire, 7 ... sealing resin, 8 ... external terminal, 9 ... insulating film, 10 ... crack of insulating film, 11 ... crack of adhesive member, DESCRIPTION OF SYMBOLS 12 ... Surface wiring crossing edge part of semiconductor element, 13 ... Wide part, 14 ... Surface wiring group, 15 ... Insulating tape, 15a ... Semiconductor element fixed surface of insulating tape, 16 ... Opening part of insulating tape, 17 ... Deformation restraining member, 18 ... opening of insulating film

Claims (1)

一主面を有する基板と、この基板の一主面に形成された導電性配線と、前記基板の一主面と前記導電性配線との所望の領域に形成された絶縁膜と、この絶縁膜の前記基板とは反対側に接着層を介して配設された半導体素子とを備え、前記導電性配線が前記半導体素子の外縁部より外側と前記半導体素子の外縁部より内側とを結ぶように形成された半導体装置において、
前記導電性配線は群を成して形成されており、この群を成して形成された導電性配線の両端に位置する導電性配線は、前記半導体素子の外縁部と対向する位置の幅が前記半導体素子の外縁部より外側および／または内側と対向する位置の幅よりも広くなるように形成され、
更に、前記群を成して形成された導電性配線の両端に位置する導電性配線は、前記群を成して形成された導電性配線の群内部に位置する導電配線の幅よりも広くなるように形成されていることを特徴とする半導体装置。A substrate having one main surface, conductive wiring formed on one main surface of the substrate, an insulating film formed in a desired region between the one main surface of the substrate and the conductive wiring, and the insulating film A semiconductor element disposed on an opposite side of the substrate via an adhesive layer, and the conductive wiring connects an outer edge portion of the semiconductor element and an inner side of the outer edge portion of the semiconductor element. In the formed semiconductor device,
The conductive lines are formed in groups, electrically conductive wires at both ends of the formed conductive traces form this group, the width of the position facing the outer edge portion of the semiconductor element It is formed to be wider than the width of the position facing the outside and / or the inside from the outer edge of the semiconductor element ,
Furthermore, the conductive wiring located at both ends of the conductive wiring formed in the group is wider than the width of the conductive wiring located inside the group of conductive wiring formed in the group. The semiconductor device is formed as described above .
JP32758097A 1997-11-28 1997-11-28 Semiconductor device Expired - Fee Related JP3658162B2 (en)

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