JP3599031B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3599031B2
JP3599031B2 JP2002034524A JP2002034524A JP3599031B2 JP 3599031 B2 JP3599031 B2 JP 3599031B2 JP 2002034524 A JP2002034524 A JP 2002034524A JP 2002034524 A JP2002034524 A JP 2002034524A JP 3599031 B2 JP3599031 B2 JP 3599031B2
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plate
semiconductor device
die pad
view
chip
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JP2002280408A (en
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忠 込山
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Seiko Epson Corp
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Seiko Epson Corp
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Description

【０００１】
【産業上の利用分野】
本発明は、半導体装置の構造に関するもので、特にパッケージ内部に封入されるＩＣチップが複数ある場合に、ＩＣチップ間の電気的な接続構造を考慮した半導体装置に関するものである。
【０００２】
【従来の技術】
従来この種の半導体装置は、例えばパッケージにＩＣチップを２チップ搭載する場合、図２５に従来の半導体装置の第一の例に関する断面図を示すが、本例によると、ＩＣチップａ・１、ＩＣチップｂ・２は、ダイパッド３上に銀ペースト等の接着剤７によって接合され、金線４によって各々電極ｃ・１０、電極ｄ・１１からダイパッド３の周辺に設けられたリード５に対して電気的に接続され、またＩＣチップａ・１、ＩＣチップｂ・２間も金線４によってＩＣチップａ・１上の電極ａ・８を１ｓｔボンディング側（ワイヤに形成された金ボールを電極に加熱圧着する側）とし、電極ａ・８からＩＣチップｂ・２上の電極ｂ・９へ金線４を引き、電極ｂ・９を２ｎｄボンディング側（金線を加熱圧着するとともにボンディング用の治具によって金線を分離する側）とするようになっていた。なお、ワイヤボンディング後は、封止材６で封止し、必要に応じてリードを整形加工することもある。
【０００３】
また、図２６には、従来の半導体装置の第二の例に関する断面図を示すが、本例によると、ＩＣチップａ・１、ＩＣチップｂ・２は、基板１２上に接着剤７によって接続され、各々の電極から基板１２上の配線パターン１３に対して金線４によって電気的に接続され、さらに基板１２上の配線パターン１３とリード５を金線４を用いて電気的に接続することによって、ＩＣチップａ・１、ＩＣチップｂ・２とリード５は配線パターン１３を介して間接的に電気的な接続をされるようになっていた。なお、図２６中に点線で示すように、ＩＣ上の電極ｄ・１１から直接金線４等で電気的コンタクトをとることもある。
【０００４】
【発明が解決しようとする課題】
前述の半導体装置においては、例えば第一の例の場合は、図２７に従来の半導体装置の第一の例に関する２ｎｄボンディング側での金線切断状態を示す断面図を示すが、ＩＣチップｂ・２の２ｎｄボンディング側である電極ｂ・９においては、金線４をカットするためにワイヤボンディング治具１４によって加えられる荷重によって電極ｂ・９にクラック１５等のダメージが発生する可能性があるとともに、金線４が電極ｂ・９の周辺でＩＣチップｂ・２の上面に点線で示すように下降して接触し、電極の開口部が周辺にあった場合は接触した金線４によってショートすることがあるという課題を有していた。また所望の電極間が離れている場合は、金線が長くなったり、交差したりして金線間や金線とＩＣチップとの間でショートが発生する可能性が生じるという課題もあった。またＩＣチップ間を直接ワイヤボンディングすることは、もし直接ワイヤボンディングされた電極からさらに他の電極との接続や外部との入出力を行いたいときは実施できないという課題もあった。
【０００５】
また第二の例の場合、一般的にはパッケージ内部に用いる基板１２の厚さが約０．４ｍｍ以上になるため、パッケージの厚さ方向の寸法、すなわち図２６における上下方向の寸法に関して、基板の厚さ、ＩＣチップの厚さ、金線の高さの合計が厚くなり（すなわち厚さ方向において、封止材で覆う分の厚さは逆に薄くなり）、例えば厚さ１ｍｍ程度のパッケージを製造する場合は、封止後に金線やＩＣチップ、または基板が封止材から露出する可能性が生じ、品質上の問題となることがあった。また、ＩＣチップを基板上に搭載するため基板サイズが大きくなり、樹脂封止時のパッケージ内部の抵抗が大きくなり、基板自体が封止樹脂によって圧力を受け、パッケージから露出したりする可能性もある。さらに、サイズの大きい基板を使用することは、材料費が高くなりパッケージのコストがアップしてしまうという課題があった。
【０００６】
本発明の目的は、以上のような半導体装置に関し、ＩＣチップ間の電気的接合によって発生する可能性のある、ＩＣチップ上の電極におけるダメージやショートが発生するという問題がなく、また同時にパッケージの薄型化を実現できる半導体装置を供給しようとするもので、特に次のような目的を有する。
【０００７】
１．ＩＣ間の電気的コンタクトをとるのに、中間に中継部を設けてＩＣチップに直接ダメージが加わらないようにする半導体装置の供給。
【０００８】
２．中継部をＩＣチップ間の電気的コンタクトのみならず、外部とのコンタクトもとれるようにする半導体装置の供給。
【０００９】
３．パッケージ内部に中継部を設けたことによりパッケージ内部体積が大きくなり、封止材封入時におけるパッケージ内部の抵抗によって中継部やＩＣチップがパッケージ外部に露出しないようにするもので、凸部を持った中継部を有する半導体装置の供給。
【００１０】
４．パッケージ内部に中継部を設けたことによりパッケージ内部体積が大きくなり、封止材封入時におけるパッケージ内部の抵抗によって中継部やＩＣチップがパッケージ外部に露出しないようにするもので、凸部を持った中継部が中継部を固定するダイパッド裏面に広い面で固定され傾きにくくした半導体装置の供給。
【００１１】
【課題を解決するための手段】
（１）本発明の半導体装置は、電極を有する複数のＩＣチップと、
前記複数のＩＣチップを搭載したダイパッドと、
前記ダイパッドに搭載され、金属プレートと前記金属プレートの上に設けられた絶縁層と前記絶縁層の上に設けられた導電性のパターンとを有するプレートと、
前記複数のＩＣチップの前記電極と前記導電性のパターンとを電気的に接続することにより、前記複数のＩＣチップの相互間を電気的に接続する導電性接続手段と、
を有することを特徴とする。
（２）本発明の半導体装置は、第１の凸部分を有するプレートと、
穴を有するダイパッドであって、前記第１の凸部分が前記穴から突出するように前記プレート上に設けられたダイパッドと、
電極を有するＩＣチップであって、前記ダイパッド上に設けられた複数の前記ＩＣチップと、
前記複数のＩＣチップの前記電極と前記導電性のパターンとを電気的に接続することにより、前記ＩＣチップの相互間を電気的に接続する導電性接続手段と、を有することを特徴とする。
【００１２】
【作用】
予め所望の導電性のパターンを絶縁層の上に形成されたプレートをダイパッド上に搭載し、ＩＣチップ間で接続する必要のある電極を、導電性接合手段を用いて該プレート上の導電性パターンに相互に接続し、特にＩＣチップ側を１ｓｔボンディング側として、導電性パターンを介してＩＣチップ間の電気的コンタクトをとることによって、２ｎｄボンディング側がＩＣチップ上に来ることがないので、ＩＣチップ間を直接ワイヤボンディングする場合に２ｎｄボンディング側となるＩＣチップ上の電極において発生する可能性のあるクラック等のダメージや、金線がＩＣチップ上の開口部に接触することに起因するショートが発生しない。また導電性パターンを形成され、かつダイパッド上に搭載され、ＩＣチップと導電性接合手段によって電気的に接合されたプレートからダイパッド周辺に設けられたリードにも必要に応じて導電性接合手段を中継して電気的に接続することによって、金線が長くなったり交差したりせずにプレート上の導電性パターンを介してＩＣチップ間の電気的コンタクトのみならず、外部とのコンタクトもとれる。さらに該プレート片面または両面に凸部を設け、該プレート上の平坦部分にパターンを形成し、平坦部をダイパッドに搭載するか、ダイパッドに穴を設け、ダイパッド裏面より穴を通して凸部を突出させることによって、凸部が支えとなってダイパッドの浮きを押さえることができ、パッケージの厚さを薄くしてもダイパッド浮きによる金線やＩＣチップ、ダイパッドの封止部分からの露出といった不具合がなくなる。また、いずれの場合もプレートの大きさに関しては、ＩＣチップ上の電極のうち、電気的中継が必要な電極の分だけ配線パターンを形成すれば良いので、基板サイズ（面積）を小さくすることができ、基板上にＩＣチップを搭載する方式に比べ資材費を低く押さえることが出来る。
【００１３】
【実施例】
本発明の実施例を以下に説明する。
【００１４】
図１は、本発明の半導体装置に関する第一の実施例のパッケージ内部の平面図である。図１によれば、本発明の半導体装置は、ダイパッド３上にＩＣチップａ・１、ＩＣチップｂ・２が搭載され、さらにダイパッド３上に導電性の配線パターン１３が形成されたプレート１７が搭載される。ＩＣチップａ・１上の電極ａ・８、及びＩＣチップｂ・２上の電極ｂ・９は各々１ｓｔボンディング側とし、プレート１７上の配線パターン１３を２ｎｄボンディング側として金線４によってワイヤボンディングされている。そのほかリードに直接ワイヤボンディングする電極のうちＩＣチップａ・１のプレート１７と反対側の電極ｃ・１０、ＩＣチップｂ・２のプレート１７と反対側の電極ｄ・１１、ＩＣチップａ・１の側面側の電極ｅ・１８、ＩＣチップｂ・２の側面側の電極ｄ・２４に関しては、金線４を用いて直接電極からリード５へワイヤボンディングされている。ワイヤボンディングの順序はどの電極から始めても良い。すなわち、本発明のポイントは常に１ｓｔボンディング側がＩＣチップの電極になることであって、ワイヤボンディングの順序は問題にならない。次にさらに詳しく説明するために、図２に本発明の半導体装置に関する第一の実施例のパッケージ内部の断面図を示すが、図２によれば本発明の第一の実施例の場合に用いられるプレート１７は接着剤７によってダイパッド３に接合されているが、接着剤７は必要に応じて導電性でも非道電性でも構わない。図２中で、導電性の配線パターン１３は、プレート１７上の絶縁層１６の上に形成されている。接着剤７の材質は、ポリイミドやアルミ箔、ポリエチレンの両面テープのようなテープ材でも銀ペーストやエポキシ樹脂のような液状の接着剤でも良いがプレート１７の高さの安定性を考えると厚さの安定しているテープ材の方がよい。なおプレートの厚さは、金線４がパッケージから飛び出さない程度であれば良いのであって、特に限定する必要はないがダイパッドへの張り付け前の取扱易さを考えると、樹脂基板で０．２ｍｍ以上、金属板で０．１ｍｍ程度以上はあった方がよい。もちろん、基板の厚さとＩＣチップ（ａ・１またはｂ・２）の厚さと金線の厚さを足した合計がパッケージの厚さ以内にしなければならないのは言うまでもない。またプレート１７の材質も導電性か非導電性かは必要に応じて決定する。材質としては、ポリイミド樹脂基板、ガラスエポキシ基板、ＢＴレジン等の樹脂基板やセラミック基板、アルミや銅等の金属の板に酸化膜形成やポリイミドフィルム貼付け等の絶縁処理をしその上に金や銅の薄膜導電パターンを形成したものでもよい。コスト面からすれば樹脂基板が有利であるがプレートの反りや耐湿性等の信頼性を考慮すれば金属のプレートの方がよい。図３には本発明の半導体装置の第一に関するプレートの形成方法を示した斜視図を示す。図３（ａ）はプレート１７の斜視図で、基になる板であるが、材質については前述のとおりである。次に、図３（ｂ）はプレートの上に絶縁層を形成した時の斜視図であるが、絶縁層は酸化膜やエポキシ樹脂、ポリエステルシート等プレートと電極を絶縁していれば特に材質は特定しなくてもよい。またプレートが絶縁性の材質の場合は、絶縁層１６を形成しなくてもよい。（すなわち、プレート上に直接配線パターン１３を形成してもよい。）次に図３（ｃ）は配線パターンの層を形成した時の斜視図で、配線パターンは、初めは絶縁層１６上一帯に形成される。次に図３（ｄ）は表面に感光性のレジスト２７を塗布したときの斜視図で、絶縁層１６上に形成された配線パターン１３上に感光性のレジスト２７が塗布される。さらに図３（ｅ）はレジストに必要なパターン２８を焼き付けた場合の斜視図である。レジスト２７上にはＩＣチップ間を中継するためのパターン２８が、必要なパターンの形状に、必要な形状をトレースしたマスク（例えば鉄や銅、アルミ等の金属やガラスにアルミや銅、金等のパターンを塗布したもの）によって紫外光を必要な部分にだけ限って当てることによって焼き付けられる。図３（ｆ）は、不必要なレジストが除去された時の斜視図で、不必要なレジスト（すなわち焼き付けられなかった部分）を取り除く。除去方法は、酸系の溶液、例えば硫酸や過酸化水素水を用いて剥離させる。図３（ｇ）は個別に配線パターン１３を形成したときの斜視図で、図３（ｆ）で残されたレジストの形状にエッチングして必要なパターン以外を除去したものである。エッチングの方法は、ウェット、電解、ドライ、無電解何れの方法でもよい。最後に、図３（ｈ）にプレートの配線パターンの出来上りの斜視図を示したが、配線パターン１３の上のレジストは、紫外光による表面の変質層をプラズマや或は研磨等の機械的方法でもよいが除去した後に、硫酸や過酸化水素水等の酸系の溶液で除去し、配線パターン１３のみを、絶縁層１６の上に形成する。何れにしても、基板の上に絶縁層を設けて（基板自身が非道電性であれば絶縁層は形成する必要はない）、その上に導電性の配線パターンさえ形成されていればよい。
【００１５】
図４は、本発明の半導体装置に関する第二の実施例に関するパッケージ内部の平面図を示すが、本実施例はプレート１７に対するＩＣチップ電極が複数共用できる場合に関するもので、プレート１７上の共通の配線パターン２５は各電極のペア（例えば図１における電極ａ・８、電極ｂ・９各々の組合せ）個別に設けず、共通の配線パターン２５とし、これに各電極ａ・８、電極ｂ・９から配線する。プレート周辺の詳細については、図５に本発明の半導体装置の第二の実施例に関するプレート周辺の斜視図を示すので参照されたい。
【００１６】
また、図６には本発明の半導体装置の第三の実施例に関するパッケージ内部の平面図を示すが、本実施例は本発明の請求項１に関する半導体装置の第２の実施例のごとく共通の配線パターンを設ける代わりにプレート１７の材質を銅や鉄等の金属のままとし、前述のごとく絶縁処理や配線パターンを設けず導電性のままとして各電極ａ・８、ｂ・９からプレート１７に直接接続したもので、わかりやすくするために図７に本発明の半導体装置の第三の実施例に関するプレート付近の斜視図を示す。本実施例の場合には、請求項１による第２の実施例のようにパターンの形成が要らない。
【００１７】
また図８には、本発明の半導体装置の第四の実施例に関するパッケージ内部の平面図を示すが、本実施例はプレート１７に対しＩＣチップａ・１、ｂ・２の電極が一部共通で一部独立した場合で、独立した電極は銅や鉄などの金属のプレート１７の一部に前述のごとく絶縁層１６を設け、その上に導電性の共通の配線パターン２５を形成し、この共通の配線パターン２５にＩＣチップａ・１、ＩＣチップｂ・２を１ｓｔボンディング側とし、プレート１７上の共通の配線パターン２５を２ｎｄボンディング側としてワイヤボンディングし、共通電極部分はプレート１７の地を２ｎｄボンディング側として直接ボンディングしたものである。わかりやすくするために、図９に本発明の半導体装置の第四の実施例に関するプレート付近の斜視図を示すので図８と併せて参照されたい。
【００１８】
次に図１０に、本発明の半導体装置に関する第五の実施例のパッケージ内部の平面図を示す。図１０によれば本発明の第五の実施例の場合、第一〜第四の実施例の構造に加え、さらに金線４によってプレート１７の配線パターン１３とリード５との間で電気的コンタクトがとられている。図１１は本発明の半導体装置に関する第五の実施例のプレート付近の斜視図である。配線パターン１３は図１０のように凸型に変形させても、図１のように長方形でも、△でも◇でもワイヤボンディングできればどの様な形でも良い。本実施例の場合は、ＩＣチップ間で電気的接続が可能なことに加え、さらにＩＣチップ間で接続された電極と外部との信号のやり取りが可能になる。またＩＣチップａ・１の近辺にあるリードに対してもプレート１７上の配線パターン１３を介してＩＣチップｂ・２から導通を得ることができ、ＩＣチップ上の電極とリードが離れていても電気的に接続できる点での実施例とは相違性を有する。
【００１９】
次に図１２に、本発明の半導体装置に関する第六の実施例のパッケージ内部の平面図を示す。図１２によれば、本発明の第一〜第四の実施例の構造に加え、プレート１７に金線４より高い凸部ａ・２０を設けている。さらに詳しく説明するために図１３に、本発明の半導体装置に関する第六の実施例のパッケージ内部の断面図を示す。図１３によれば、金線４より高い凸部ａ・２０はパッケージの外周部に達していて、基板がそれ以上浮かないようにストッパになっている。但し図１３の凸部ａ・２０の点線の部分に示すように、パッケージの外周にまで達していなくてもよい。これは、基板が浮いたときのストッパになれば良いので、通常はパッケージの内部に隠れる程度の寸法で金線の高さより高ければよい。図１４には、本発明の半導体装置に関する第六の実施例の凸部の形成方法を示す斜視図を示す。先ず図１４（ａ）は、凸部とその取付前の状態を示す斜視図であるが、図１４（ａ）によれば凸部ａ・２０は、予め旋盤による研削加工、或は金型による射出成形等によって形成しておく。形は図１４（ａ）のごとく円筒型でも角柱でも、何でもよいがプレート１７との接合面は特に平坦にしておく。プレート１７と凸部の接合は接着剤７によっておこなう。接着剤７の材質は前述のとおり。次に図１４（ｂ）は凸部とその取付後の状態を示す斜視図であるが、凸部ａ・（２０）は接着剤７によってプレート１７に接合されている。本実施例の場合、樹脂封止の際にダイパッド３が図１３の上方向に浮いても凸部ａ・２０がストッパになって金線４が封止材の外に露出しないという点で第一〜第五の実施例と相違性を有する。
【００２０】
また図１５に、本発明の半導体装置に関する第七の実施例のパッケージ内部の裏面側の平面図を示す。図１５によれば、本発明の第一〜第四の実施例の構造に加え、プレート１７にパッケージの下方向に向けた凸部ｂ・２１を設け、さらにダイパッド３に穴２２を開けておき、この穴２２にプレート１７の凸部ｂ・２１を通している。さらに詳しく説明するために図１６に、本発明の半導体装置に関する第七の実施例のパッケージ内部の断面図を示す。図１６によれば、プレート１７に設けられたパッケージの下方向に向けた凸部ｂ・２１は、穴２２を通ってパッケージの下側に貫通している。ＩＣチップａ・１、ＩＣチップｂ・２とプレート１７との電気的コンタクトは、プレート１７上の凸部と反対側に設けられた配線パターン１３と各ＩＣチップ上の電極ａ・８、電極ｂ・９とを金線４で結ぶことでとられている。凸部ｂ・２１とプレート１７の接合は接着剤７で行う。本実施例の場合は、樹脂封止の際にダイパッド３が図の下方向に下げられるようなことがあっても、凸部ｂ・２１がストッパになってダイパッド３が封止材６の外に露出しないという点で前述の各実施例と相違性を有する。
【００２１】
次に図１７に、本発明の半導体装置に関する第八の実施例のパッケージ内部の平面図を示す。ここで、図１７（ａ）はＩＣチップの搭載された表面の平面図、図１７（ｂ）は裏面の平面図を示す。図１７（ａ）によれば、本発明の第一の実施例の構造に加え、プレート１７に本発明の半導体装置に関する第六の実施例のように凸部ａ・２０を設け、また図１１（ｂ）によればプレート１７の下面には本発明の半導体装置に関する第七の実施例のようにパッケージの下方向に向けた凸部ｂ・２１を設けてダイパッド３の穴２２を通って凸部ｂ・２１が突出している。
【００２２】
さらに詳しく説明するために図１８に、本発明の半導体装置に関する第八の実施例のパッケージ内部の断面図を示す。図１８によれば、プレート１７上面には凸部ａ・２０が、また下面にはパッケージの下方向に向けた凸部ｂ・２１がそれぞれ設けられ、凸部ｂ・２１はダイパッド３の穴２２を通ってパッケージの下側に貫通している。ＩＣチップａ・１、ＩＣチップｂ・２とプレート１７との電気的コンタクトは、プレート１７に設けられた配線パターン１３と各ＩＣチップ上の電極ａ・８、電極ｂ・９とを金線４で結ぶことでとられている。本実施例の場合は、樹脂封止の際にダイパッド３が図の上方向または下方向のどちらの方向に動かされても、凸部ａ・２０及び凸部ｂ・２１がストッパになって金線４やダイパッド３が封止材６の外に露出しないという点で前述の各実施例と相違性を有する。なお、凸部ａ・２０、凸部ｂ・２１の形成方法は、図１４で説明した方法に準ずるものとする。
【００２３】
次に図１９に、本発明の半導体装置に関する第九の実施例のパッケージ内部の平面図を示す。図１９によれば、本発明の第一の実施例の構造に加え、プレート１７に金線４との電気的接続用配線パターン１３を形成した凸部ｃ・２３を設け、ダイパッド３の穴２４を通してダイパッド３の上側すなわちＩＣチップの搭載側で突出させている。さらに詳しく説明するために、図２０に、本発明の半導体装置に関する第九の実施例のパッケージ内部の断面図を示す。図２０によれば、プレート１７に設けられた金線４との電気的接続用配線パターン１３を形成した凸部ｃ・２３は、ダイパッド３の穴２４を通してダイパッド３の上側すなわちＩＣチップ側へ突出している。プレート１７は接着剤７でダイパッド３へ接合されている。図２１に本発明の半導体装置に関する第九の実施例の凸部ｃ・２３の形成方法を示す斜視図を示す。図２１（ａ）は基になるプレート１７の斜視図である。次に図２１（ｂ）はプレート１７上に酸化膜やエポキシ樹脂等の絶縁層１６を形成し、さらにその上に導電性の配線パターン１３を形成した時の斜視図（絶縁層の材質及び配線パターンの形成方法については図３の説明を参照願いたい。）、図２１（ｃ）はさらに配線パターン１３上に感光性のレジスト２７を塗布したときの斜視図。図２１（ｄ）は、配線パターン１３の上に必要な形状をレジスト上に焼き付けたときの斜視図で、最終的に残したいパターンの部分（つまり配線パターン１３の部分・図の斜線部分）を露光させる。図中では斜線の部分が露光して硬膜化したレジスト２８である。露光の方法については図３の方法に従う。図２１（ｅ）は、凸部を形成したときの斜視図である。ダイパッドに接合する部分をカットしたもので図の点線の部分である。カットする深さは、導電性のパターンを形成されたプレートが最終的な製品から飛び出さない程度であればよいが、概ね、カットした部分の残りの厚さが０．２ｍｍ以上あれば強度上問題はない。点線部分の加工はフライスでも旋盤でも、研磨でもカットさえできれば何を用いてもよいが、フライスまたは旋盤程度の加工でよい。図２１（ｆ）は凸部２１の出来上り状態を示す斜視図で、配線パターン部以外の未硬化のレジスト２９（図２１（ｅ）参照）を除去し、さらにエッチングして本図では中央部の不要なパターン（点線で示す）を除去し、両端の硬膜化したレジスト２８を落したものである。硬膜化したレジストの除去については図３（ｈ）の説明を参照のこと。図２２は本発明の半導体装置に関する第九に実施例のプレートの実装方法を示す斜視図を示す。図２２によれば、プレート１７は、図ではダイパッド３の下方より凸部を上にして接着剤７を介してダイパッド３に接着される。接着剤７は先にプレート１７またはダイパッド３の接合面に塗布しても良いし、テープならばその都度貼ってもよい。接着剤７の材質は前述のとおり。本実施例の場合、ダイパッド３とプレート１７との接合面を広く取れるので、ダイパッド３とプレート１７の接合強度が高くなる上に、プレート１７のダイパッド３より下側の部分の面積が必要に応じて広く取れる（場合によってはダイパッド３より広くできる）ので、樹脂封止時にダイパッド３が図２０における下側に押し下げられても、プレート１７が広い面でストッパとして作用するため、より確実にダイパッド３が封止材６の外に露出することを防ぐという点で前述の各実施例と相違性を有する。
【００２４】
次に図２３に、本発明の半導体装置に関する第十の実施例のパッケージ内部の平面図を示す。図２３によれば、本発明の第一の実施例の構造に加え、プレート１７に設けた金線４との電気的接続用配線パターン１３を形成した凸部ｃ・２３の上方にさらに凸部ｄ・１９を設け（凸部ｄ・１９の形成方法は凸部ａ・２０の形成方法と同様にする。図１４の説明を参照のこと。）、ダイパッド３に穴２４を開けておき、上向きの凸部ｃ・２３、凸部ｄ・１９を穴２２から突出させる。さらに詳しく説明するために、図２４に、本発明の半導体装置に関する第十の実施例のパッケージ内部の断面図を示す。図２４によれば、プレート１７に設けた凸部ｃ・２３とその上方に設けられた凸部ｄ・１９は、ダイパッド３の穴２４を貫通してダイパッド３の上面に突出している。金線４はＩＣチップａ・１、ｂ・２の各々の電極から凸部ｃ・２０に設けられた配線パターン１３に配線パターン側を２ｎｄボンディング側としてワイヤボンディングされる。本実施例の場合、ダイパッド３とプレート１７との接合面を広く取れる上に樹脂封止時にダイパッド３が図の上側または下側のどちらにに押されても、プレート１７のダイパッド３より下側の部分や凸部ｄ１９がストッパとなるので、ダイパッド３や金線４が封止材６の外に露出しないという点で前述の各実施例と相違性を有する。
【００２５】
【発明の効果】
以上述べたように、本発明によれば、予め所望の導電性のパターンを形成されたプレートをダイパッド上に搭載し、プレート上の導電性配線パターンに、該ＩＣチップの電極のうちＩＣチップ間で接続する必要のあるものを１ｓｔボンディング側として導電性接合手段を用いて接続し、導電性配線パターンを介してＩＣチップ間の電気的コンタクトをとることによって、２ｎｄボンディング側がＩＣチップ上に来ることがないので、ＩＣチップ間を直接ワイヤボンディングする場合に発生する可能性がある２ｎｄボンディング側ＩＣチップ上の電極におけるクラック等のダメージの発生や金線がＩＣチップ上の開口部に接触することに起因するショートが発生しない。また導電性配線パターンを形成されダイパッド上に搭載され、ＩＣチップと導電性接合手段によって電気的に接合されたプレートからダイパッド周辺に設けられたリードにも必要に応じて導電性接合手段を介して電気的に接合することによって、ＩＣチップ間の電気的接続をとりつつ、それらのＩＣチップ間接続電極と外部との信号のやり取りが可能になる。さらに該プレート片面または両面に凸部を設けることによって、凸部がストッパとなってダイパッドの浮きを押さえることができ、パッケージの厚さをを薄くしてもダイパッド浮きによる金線やＩＣチップ、ダイパッドの封止部分からの露出といった不具合がなくなるという効果を有する。また、ダイパッドに穴を設け、ダイパッドに穴を設け、プレートをダイパッドに接着すると共に、プレートに設けた凸部をダイパッドの穴から突出させることによって、より広い面でダイパッドにプレートを固定することが出来、プレートが取れにくく、かつ高さが安定する。
【図面の簡単な説明】
【図１】本発明の半導体装置に関する第一の実施例のパッケージ内部の平面図。
【図２】本発明の半導体装置に関する第一の実施例のパッケージ内部の断面図。
【図３】本発明のプレートの形成方法を示した斜視図。
【図４】本発明の半導体装置の第二の実施例に関する平面図。
【図５】本発明の半導体装置の第二の実施例に関するプレート周辺の斜視図。
【図６】本発明の半導体装置に関する第三の実施例に関するパッケージ内部の平面図。
【図７】本発明の半導体装置に関する第三の実施例に関するプレート付近の斜視図。
【図８】本発明の半導体装置に関する第四の実施例に関するパッケージ内部の平面図。
【図９】本発明の半導体装置に関する第四の実施例に関するプレート付近の斜視図。
【図１０】本発明の半導体装置に関する第五の実施例のパッケージ内部の平面図。
【図１１】本発明の半導体装置に関する第五の実施例のプレート付近の斜視図。
【図１２】本発明の半導体装置に関する第六の実施例のパッケージ内部の平面図。
【図１３】本発明の半導体装置に関する第六の実施例のパッケージ内部の断面図。
【図１４】本発明の半導体装置に関する第六の実施例の凸部の形成方法を示す斜視図。
【図１５】本発明の半導体装置に関する第七の実施例のパッケージ内部の裏面側の平面図。
【図１６】本発明の半導体装置に関する第七の実施例のパッケージ内部の断面図。
【図１７】本発明の半導体装置に関する第八の実施例のパッケージ内部の平面図。
【図１８】本発明の半導体装置に関する第八の実施例のパッケージ内部の断面図。
【図１９】本発明の半導体装置に関する第九の実施例のパッケージ内部の平面図。
【図２０】本発明の半導体装置に関する第九の実施例のパッケージ内部の断面図。
【図２１】本発明の半導体装置に関する第九の実施例の凸部ｃの形成方法を示す斜視図。
【図２２】本発明の半導体装置に関する第九の実施例のプレートの実装方法を示す斜視図。
【図２３】本発明の半導体装置に関する第十の実施例のパッケージ内部の平面図。
【図２４】本発明の半導体装置に関する第十の実施例のパッケージ内部の断面図。
【図２５】従来の半導体装置の第一の例に関する断面図。
【図２６】従来の半導体装置の第二の例に関する断面図。
【図２７】従来の半導体装置の第一の例に関する２ｎｄボンディング側での金線切断状態を示す断面図。
【符号の説明】
１．ＩＣチップａ
２．ＩＣチップｂ
３．ダイパッド
４．金線
５．リード
６．封止材
７．接着剤
８．電極ａ
９．電極ｂ
１０．電極ｃ
１１．電極ｄ
１２．基板
１３．配線パターン
１４．ワイヤボンディング治具
１５．クラック
１６．絶縁層
１７．プレート
１８．電極ｅ
１９．凸部ｄ
２０．凸部ａ
２１．凸部ｂ
２２．穴
２３．凸部ｃ
２４．穴
２５．共通のパターン
２６．ＩＣチップａの近くにあるリード
２７．レジスト
２８．硬膜化したレジスト
２９．未硬化のレジスト[0001]
[Industrial applications]
The present invention relates to a structure of a semiconductor device, and more particularly to a semiconductor device that takes into account an electrical connection structure between IC chips when there are a plurality of IC chips sealed in a package.
[0002]
[Prior art]
Conventionally, this type of semiconductor device has, for example, a cross-sectional view of a first example of a conventional semiconductor device when two IC chips are mounted on a package. FIG. The IC chip b · 2 is bonded to the die pad 3 with an adhesive 7 such as a silver paste, and the gold wire 4 is used to connect the electrodes c · 10 and d · 11 to the leads 5 provided around the die pad 3. The electrode a.8 on the IC chip a.1 is electrically connected between the IC chip a.1 and the IC chip b.2 by the gold wire 4 on the first bonding side (the gold ball formed on the wire is used as the electrode). The gold wire 4 is drawn from the electrode a · 8 to the electrode b · 9 on the IC chip b · 2, and the electrode b · 9 is placed on the 2nd bonding side (the gold wire is heated / pressed and bonded). Depending on the tool It was supposed to be the side) to separate the gold wire Te. After the wire bonding, the leads may be sealed with the sealing material 6 and the leads may be shaped if necessary.
[0003]
FIG. 26 is a cross-sectional view of a second example of the conventional semiconductor device. According to this example, the IC chips a and b are connected to the substrate 12 by the adhesive 7. Then, each electrode is electrically connected to the wiring pattern 13 on the substrate 12 by the gold wire 4, and further, the wiring pattern 13 on the substrate 12 is electrically connected to the lead 5 by using the gold wire 4. As a result, the IC chip a.1, the IC chip b.2 and the lead 5 are electrically connected indirectly via the wiring pattern 13. In addition, as shown by a dotted line in FIG. 26, the electrical contact may be made directly from the electrode d.11 on the IC with the gold wire 4 or the like.
[0004]
[Problems to be solved by the invention]
In the above-described semiconductor device, for example, in the case of the first example, FIG. 27 is a cross-sectional view showing a gold wire cut state on the 2nd bonding side according to the first example of the conventional semiconductor device. In the electrode b · 9 on the 2nd bonding side of No. 2, the load applied by the wire bonding jig 14 for cutting the gold wire 4 may cause damage to the electrode b · 9 such as a crack 15 and the like. , The gold wire 4 descends and comes into contact with the upper surface of the IC chip b · 2 around the electrode b · 9 as shown by the dotted line. If the opening of the electrode is in the periphery, the gold wire 4 is short-circuited. There was a problem that there was. In addition, when the desired electrodes are separated from each other, there is also a problem that the gold wires become longer or cross and a short circuit may occur between the gold wires or between the gold wires and the IC chip. . In addition, there is another problem that direct wire bonding between IC chips cannot be performed when it is desired to perform connection with another electrode or input / output with the outside from the directly wire bonded electrode.
[0005]
In the case of the second example, since the thickness of the substrate 12 used inside the package is generally about 0.4 mm or more, the dimension in the thickness direction of the package, that is, the vertical dimension in FIG. The total thickness of the IC chip, the thickness of the IC chip, and the height of the gold wire is increased (that is, the thickness covered by the encapsulating material is reduced in the thickness direction). In the case of manufacturing, there is a possibility that a gold wire, an IC chip, or a substrate may be exposed from the sealing material after sealing, which may cause a quality problem. Also, since the IC chip is mounted on the substrate, the size of the substrate increases, the resistance inside the package at the time of resin sealing increases, and the substrate itself may be exposed to pressure by the sealing resin and be exposed from the package. is there. Furthermore, there is a problem that using a large-sized substrate increases material cost and package cost.
[0006]
An object of the present invention is to provide a semiconductor device as described above, which has no problem of causing damage or short-circuit in electrodes on the IC chip, which may be caused by electrical bonding between the IC chips, and at the same time, has An object of the present invention is to provide a semiconductor device which can be made thinner, and particularly has the following object.
[0007]
1. Supply of a semiconductor device for preventing electrical damage between IC chips by providing an intermediate portion for making electrical contact between ICs.
[0008]
2. Supply of a semiconductor device that enables a relay unit to make not only electrical contact between IC chips but also external contact.
[0009]
3. The provision of the relay section inside the package increases the internal volume of the package, and prevents the relay section and the IC chip from being exposed to the outside of the package due to the resistance inside the package when the sealing material is sealed. Supply of a semiconductor device having a relay unit.
[0010]
4. The provision of the relay section inside the package increases the internal volume of the package, and prevents the relay section and the IC chip from being exposed to the outside of the package due to the resistance inside the package when the sealing material is sealed. Supply of a semiconductor device in which a relay portion is fixed to a wide surface on a rear surface of a die pad for fixing the relay portion and is hardly inclined.
[0011]
[Means for Solving the Problems]
(1) A semiconductor device according to the present invention includes a plurality of IC chips having electrodes,
A die pad on which the plurality of IC chips are mounted;
Plate mounted on the die pad, having a metal plate and an insulating layer provided on the metal plate and a conductive pattern provided on the insulating layer,
A conductive connection means for electrically connecting the electrodes of the plurality of IC chips and the conductive pattern, thereby electrically connecting the plurality of IC chips to each other;
It is characterized by having.
(2) A semiconductor device according to the present invention includes a plate having a first convex portion;
A die pad having a hole, the die pad being provided on the plate so that the first convex portion protrudes from the hole,
An IC chip having electrodes, wherein the plurality of IC chips are provided on the die pad;
And electrically connecting the electrodes of the plurality of IC chips and the conductive pattern, thereby electrically connecting the IC chips to each other.
[0012]
[Action]
A plate in which a desired conductive pattern is formed on an insulating layer in advance is mounted on a die pad, and electrodes that need to be connected between IC chips are connected to the conductive pattern on the plate using conductive bonding means. In particular, by making the IC chip side the first bonding side and making electrical contact between the IC chips via the conductive pattern, the second bonding side does not come on the IC chip, so that the IC chip side Does not cause damage such as cracks that may occur in electrodes on the IC chip on the 2nd bonding side when direct wire bonding is performed, and short-circuiting caused by the gold wire contacting the opening on the IC chip does not occur. . In addition, a conductive pattern is formed and mounted on the die pad, and the conductive bonding means is relayed as necessary to a lead provided around the die pad from a plate electrically bonded to the IC chip by the conductive bonding means. As a result, the gold wires do not become long or intersect, so that not only the electrical contacts between the IC chips but also the external contacts can be obtained via the conductive patterns on the plate. Further, providing a convex portion on one or both surfaces of the plate, forming a pattern on a flat portion on the plate, mounting the flat portion on a die pad, or providing a hole in the die pad, and projecting the convex portion through the hole from the back surface of the die pad. Accordingly, the protrusion serves as a support and can suppress the floating of the die pad, and even if the thickness of the package is reduced, a problem such as exposure of the gold wire, the IC chip, and the die pad from the sealing portion due to the floating of the die pad is eliminated. In any case, regarding the size of the plate, the wiring pattern may be formed only for the electrodes on the IC chip that need to be electrically relayed, so that the substrate size (area) can be reduced. Thus, material costs can be reduced compared to the method of mounting an IC chip on a substrate.
[0013]
【Example】
Embodiments of the present invention will be described below.
[0014]
FIG. 1 is a plan view showing the inside of a package according to a first embodiment of the semiconductor device of the present invention. According to FIG. 1, in the semiconductor device of the present invention, a plate 17 on which an IC chip a · 1 and an IC chip b · 2 are mounted on a die pad 3 and a conductive wiring pattern 13 is formed on the die pad 3 is provided. Be mounted. The electrodes a.8 on the IC chip a.1 and the electrodes b.9 on the IC chip b.2 are respectively set to the first bonding side, and the wiring pattern 13 on the plate 17 is set to the second bonding side and wire-bonded by the gold wire 4. ing. In addition, of the electrodes directly wire-bonded to the leads, the electrodes c and 10 on the opposite side to the plate 17 of the IC chip a.1, the electrodes d and 11 on the opposite side to the plate 17 of the IC chip b. The electrode e.18 on the side surface and the electrode d.24 on the side surface of the IC chip b.2 are directly wire-bonded from the electrode to the lead 5 using the gold wire 4. The order of wire bonding may be started from any electrode. That is, the point of the present invention is that the first bonding side is always the electrode of the IC chip, and the order of wire bonding does not matter. Next, in order to explain in more detail, FIG. 2 shows a cross-sectional view of the inside of the package of the semiconductor device of the first embodiment of the present invention. The plate 17 to be bonded is bonded to the die pad 3 by an adhesive 7, but the adhesive 7 may be conductive or non-conductive as required. In FIG. 2, a conductive wiring pattern 13 is formed on an insulating layer 16 on a plate 17. The material of the adhesive 7 may be a tape material such as a double-sided tape of polyimide, aluminum foil or polyethylene, or a liquid adhesive such as a silver paste or an epoxy resin. A stable tape material is better. The thickness of the plate is not particularly limited as long as the gold wire 4 does not protrude from the package, and is not particularly limited. It is better that the distance is 2 mm or more and about 0.1 mm or more for a metal plate. Of course, the sum of the thickness of the substrate, the thickness of the IC chip (a.1 or b.2), and the thickness of the gold wire must be within the thickness of the package. Whether the material of the plate 17 is conductive or non-conductive is determined as necessary. As a material, a resin substrate such as a polyimide resin substrate, a glass epoxy substrate, a BT resin or the like, a ceramic substrate, or a metal plate such as aluminum or copper is subjected to an insulation treatment such as formation of an oxide film or a polyimide film, and then gold or copper is formed thereon. A thin film conductive pattern may be formed. From the viewpoint of cost, a resin substrate is advantageous, but a metal plate is preferred in consideration of reliability such as warpage and moisture resistance of the plate. FIG. 3 is a perspective view showing a method for forming a plate relating to the first of the semiconductor device of the present invention. FIG. 3A is a perspective view of the plate 17, which is a base plate. The material is as described above. Next, FIG. 3 (b) is a perspective view when an insulating layer is formed on the plate. The insulating layer is made of an oxide film, an epoxy resin, a polyester sheet, or the like. It is not necessary to specify. When the plate is made of an insulating material, the insulating layer 16 need not be formed. (That is, the wiring pattern 13 may be formed directly on the plate.) Next, FIG. 3C is a perspective view when a wiring pattern layer is formed, and the wiring pattern is initially formed all over the insulating layer 16. Formed. Next, FIG. 3D is a perspective view when a photosensitive resist 27 is applied to the surface, and the photosensitive resist 27 is applied to the wiring pattern 13 formed on the insulating layer 16. FIG. 3E is a perspective view in a case where a necessary pattern 28 is printed on the resist. On the resist 27, a pattern 28 for relaying between IC chips is formed in a required pattern shape and a mask obtained by tracing the required shape (for example, metal such as iron, copper, aluminum, glass, aluminum, copper, gold, etc. Is applied by applying ultraviolet light only to necessary parts. FIG. 3F is a perspective view when the unnecessary resist has been removed, and the unnecessary resist (that is, the portion that has not been burned) is removed. The removal is performed by using an acid-based solution such as sulfuric acid or hydrogen peroxide. FIG. 3 (g) is a perspective view when the wiring patterns 13 are individually formed, and is obtained by etching the resist remaining in FIG. The etching method may be any of wet, electrolytic, dry, and electroless methods. Finally, FIG. 3 (h) shows a perspective view of the completion of the wiring pattern of the plate. The resist on the wiring pattern 13 is formed by applying a mechanical method such as plasma or polishing to the altered layer on the surface due to ultraviolet light. After removal, the substrate is removed with an acid-based solution such as sulfuric acid or hydrogen peroxide solution, and only the wiring pattern 13 is formed on the insulating layer 16. In any case, it is sufficient that an insulating layer is provided on the substrate (if the substrate itself is non-conductive, it is not necessary to form the insulating layer), and only a conductive wiring pattern is formed thereon.
[0015]
FIG. 4 is a plan view showing the inside of a package according to a second embodiment of the semiconductor device of the present invention. This embodiment relates to a case where a plurality of IC chip electrodes for the plate 17 can be shared. The wiring pattern 25 is not provided individually for each pair of electrodes (for example, a combination of each of the electrodes a and 8 and the electrodes b and 9 in FIG. 1). Wiring from. FIG. 5 is a perspective view of the periphery of the plate according to the second embodiment of the semiconductor device of the present invention for details of the periphery of the plate.
[0016]
FIG. 6 is a plan view showing the inside of a package according to a third embodiment of the semiconductor device of the present invention. This embodiment is common to the second embodiment of the semiconductor device according to claim 1 of the present invention. Instead of providing the wiring pattern, the material of the plate 17 is made of a metal such as copper or iron, and as described above, the plate 17 is transferred from each of the electrodes a, 8, b, and 9 to the plate 17 while maintaining the insulation without providing the wiring pattern. FIG. 7 is a perspective view showing the vicinity of a plate according to a third embodiment of the semiconductor device of the present invention, which is directly connected and is easy to understand. In the case of this embodiment, it is not necessary to form a pattern as in the second embodiment of the present invention.
[0017]
FIG. 8 is a plan view showing the inside of the package according to the fourth embodiment of the semiconductor device of the present invention. In this embodiment, the electrodes of the IC chips a1, b2 are partially common to the plate 17. In this case, the independent electrode is provided with an insulating layer 16 on a part of a metal plate 17 such as copper or iron as described above, and a conductive common wiring pattern 25 is formed thereon. The common wiring pattern 25 is wire-bonded to the IC chip a · 1 and the IC chip b · 2 as the first bonding side, and the common wiring pattern 25 on the plate 17 is used as the second bonding side. Direct bonding is performed as the second bonding side. For the sake of simplicity, FIG. 9 shows a perspective view of the vicinity of the plate relating to the fourth embodiment of the semiconductor device of the present invention.
[0018]
Next, FIG. 10 is a plan view showing the inside of a package according to a fifth embodiment of the semiconductor device of the present invention. According to FIG. 10, in the case of the fifth embodiment of the present invention, in addition to the structure of the first to fourth embodiments, an electric contact is made between the wiring pattern 13 of the plate 17 and the lead 5 by the gold wire 4. Has been taken. FIG. 11 is a perspective view of the vicinity of a plate according to a fifth embodiment of the semiconductor device of the present invention. The wiring pattern 13 may be deformed into a convex shape as shown in FIG. 10, may be rectangular as shown in FIG. 1, or may have any shape as long as wire bonding can be performed. In the case of this embodiment, in addition to being capable of electrical connection between the IC chips, it is possible to exchange signals between the electrodes connected between the IC chips and the outside. In addition, conduction can be obtained from the IC chip b · 2 to the lead near the IC chip a · 1 via the wiring pattern 13 on the plate 17 even if the electrode on the IC chip is separated from the lead. It differs from the embodiment in that it can be electrically connected.
[0019]
Next, FIG. 12 is a plan view showing the inside of a package according to a sixth embodiment of the semiconductor device of the present invention. According to FIG. 12, in addition to the structure of the first to fourth embodiments of the present invention, the plate 17 is provided with a projection a · 20 higher than the gold wire 4. FIG. 13 is a cross-sectional view showing the inside of a package according to a sixth embodiment of the semiconductor device of the present invention for further explanation. According to FIG. 13, the convex portion a · 20 higher than the gold wire 4 reaches the outer peripheral portion of the package and serves as a stopper so that the substrate does not float any more. However, as shown by the dotted line portion of the convex portion a · 20 in FIG. 13, it does not have to reach the outer periphery of the package. Since it is sufficient that this serves as a stopper when the substrate floats, it is usually sufficient that the dimension is small enough to be hidden inside the package and higher than the height of the gold wire. FIG. 14 is a perspective view illustrating a method of forming a convex portion according to a sixth embodiment of the semiconductor device of the present invention. First, FIG. 14A is a perspective view showing a convex portion and a state before the convex portion is attached. According to FIG. 14A, the convex portions a and 20 are previously ground by a lathe or a die. It is formed by injection molding or the like. The shape may be cylindrical or prismatic as shown in FIG. 14 (a), but the joining surface with the plate 17 is particularly flat. The bonding between the plate 17 and the convex portion is performed by the adhesive 7. The material of the adhesive 7 is as described above. Next, FIG. 14B is a perspective view showing the convex portion and a state after the convex portion is attached. The convex portion a (20) is joined to the plate 17 by the adhesive 7. In the case of the present embodiment, even if the die pad 3 floats upward in FIG. 13 during resin sealing, the protrusions a and 20 serve as stoppers, and the gold wire 4 is not exposed outside the sealing material. There is a difference from the first to fifth embodiments.
[0020]
FIG. 15 is a plan view showing the inside of the package according to the seventh embodiment of the semiconductor device of the present invention on the back surface side. According to FIG. 15, in addition to the structure of the first to fourth embodiments of the present invention, a plate 17 is provided with a convex portion b.21 directed downward from the package, and a hole 22 is formed in the die pad 3. The projections b and 21 of the plate 17 pass through the holes 22. FIG. 16 is a cross-sectional view showing the inside of a package according to a seventh embodiment of the semiconductor device of the present invention for further detailed description. According to FIG. 16, the downwardly protruding portions b and 21 provided on the plate 17 pass through the holes 22 to the lower side of the package. The electrical contact between the IC chip a · 1, the IC chip b · 2 and the plate 17 is made up of the wiring pattern 13 provided on the side opposite to the convex portion on the plate 17 and the electrodes a · 8 and electrode b on each IC chip.・ It is obtained by connecting 9 with gold wire 4. The bonding between the protruding portions b and 21 and the plate 17 is performed with the adhesive 7. In the case of the present embodiment, even when the die pad 3 may be lowered in the downward direction in the drawing at the time of resin sealing, the protrusions b and 21 serve as stoppers and the die pad 3 This embodiment is different from the above embodiments in that it is not exposed to light.
[0021]
FIG. 17 is a plan view showing the inside of a package according to an eighth embodiment of the semiconductor device of the present invention. Here, FIG. 17A is a plan view of a front surface on which an IC chip is mounted, and FIG. 17B is a plan view of a back surface. According to FIG. 17 (a), in addition to the structure of the first embodiment of the present invention, the plate 17 is provided with convex portions a and 20 as in the sixth embodiment relating to the semiconductor device of the present invention. According to (b), as in the seventh embodiment relating to the semiconductor device of the present invention, a convex portion b · 21 directed downward of the package is provided on the lower surface of the plate 17 so as to project through the hole 22 of the die pad 3. The part b · 21 protrudes.
[0022]
FIG. 18 is a cross-sectional view showing the inside of a package according to an eighth embodiment of the semiconductor device of the present invention for explaining in more detail. According to FIG. 18, the convex portions a and 20 are provided on the upper surface of the plate 17, and the convex portions b and 21 are provided on the lower surface of the plate 17 in the downward direction. Through to the underside of the package. The electrical contact between the IC chip a · 1, the IC chip b · 2 and the plate 17 is made by connecting the wiring pattern 13 provided on the plate 17 and the electrodes a · 8 and the electrode b · 9 on each IC chip to the gold wire 4. It is taken by tying in. In the case of this embodiment, regardless of whether the die pad 3 is moved in the upward or downward direction in the drawing at the time of resin sealing, the convex portions a and 20 and the convex portions b and This embodiment differs from the above embodiments in that the wires 4 and the die pad 3 are not exposed outside the sealing material 6. The method for forming the convex portions a and 20 and the convex portions b and 21 is based on the method described with reference to FIG.
[0023]
Next, FIG. 19 is a plan view showing the inside of a package according to a ninth embodiment of the semiconductor device of the present invention. According to FIG. 19, in addition to the structure of the first embodiment of the present invention, the plate 17 is provided with a projection c · 23 on which the wiring pattern 13 for electrical connection to the gold wire 4 is formed. Through the upper side of the die pad 3, that is, the mounting side of the IC chip. For further details, FIG. 20 is a sectional view showing the inside of a package according to a ninth embodiment of the semiconductor device of the present invention. According to FIG. 20, the protrusion c · 23 formed with the wiring pattern 13 for electrical connection with the gold wire 4 provided on the plate 17 projects through the hole 24 of the die pad 3 to the upper side of the die pad 3, that is, to the IC chip side. ing. The plate 17 is bonded to the die pad 3 with the adhesive 7. FIG. 21 is a perspective view showing a method for forming the projections c23 of the ninth embodiment relating to the semiconductor device of the present invention. FIG. 21A is a perspective view of the base plate 17. Next, FIG. 21 (b) is a perspective view when an insulating layer 16 such as an oxide film or an epoxy resin is formed on a plate 17 and a conductive wiring pattern 13 is further formed thereon (material and wiring of the insulating layer). Please refer to the description of FIG. 3 for the method of forming the pattern.), And FIG. 21C is a perspective view when a photosensitive resist 27 is further applied on the wiring pattern 13. FIG. 21D is a perspective view when a required shape is printed on the resist on the wiring pattern 13, and a part of the pattern that is finally to be left (that is, a part of the wiring pattern 13 and a hatched part in the drawing) is shown. Expose. In the figure, the hatched portions indicate the resist 28 that has been hardened by exposure. The method of exposure follows the method of FIG. FIG. 21E is a perspective view when a convex portion is formed. The portion to be joined to the die pad is cut and is indicated by the dotted line in the figure. The cutting depth may be such that the plate on which the conductive pattern is formed does not protrude from the final product. However, in general, if the remaining thickness of the cut portion is 0.2 mm or more, the strength is increased. No problem. The processing of the dotted line portion may be performed by milling, lathe, polishing or cutting as long as it can be cut. FIG. 21F is a perspective view showing a completed state of the convex portion 21. The uncured resist 29 (see FIG. 21E) other than the wiring pattern portion is removed and further etched to form a central portion in this drawing. An unnecessary pattern (indicated by a dotted line) is removed, and the hardened resist 28 at both ends is dropped. For the removal of the hardened resist, see the description of FIG. FIG. 22 is a perspective view showing a ninth embodiment of a method of mounting a plate relating to the semiconductor device of the present invention. According to FIG. 22, the plate 17 is adhered to the die pad 3 via the adhesive 7 with the convex portion upward from below the die pad 3 in the figure. The adhesive 7 may be applied first to the joint surface of the plate 17 or the die pad 3, or may be applied each time a tape is used. The material of the adhesive 7 is as described above. In the case of the present embodiment, since the bonding surface between the die pad 3 and the plate 17 can be widened, the bonding strength between the die pad 3 and the plate 17 is increased, and the area of the portion of the plate 17 below the die pad 3 is necessary. 20 (in some cases, it can be wider than the die pad 3), so that even if the die pad 3 is pushed down in FIG. 20 during resin sealing, the plate 17 acts as a stopper on a wide surface, so the die pad 3 Is different from the above-described embodiments in that it is prevented from being exposed outside the sealing material 6.
[0024]
Next, FIG. 23 is a plan view showing the inside of a package according to a tenth embodiment of the semiconductor device of the present invention. According to FIG. 23, in addition to the structure of the first embodiment of the present invention, a protrusion is further formed above the protrusion c · 23 on which the wiring pattern 13 for electrical connection with the gold wire 4 provided on the plate 17 is formed. d · 19 are provided (the method of forming the convex portions d · 19 is the same as the method of forming the convex portions a · 20; see the description of FIG. 14). Are projected from the hole 22. For further details, FIG. 24 is a sectional view showing the inside of a package according to a tenth embodiment of the semiconductor device of the present invention. According to FIG. 24, the protrusions c and 23 provided on the plate 17 and the protrusions d and 19 provided above the plate 17 pass through the holes 24 of the die pad 3 and protrude from the upper surface of the die pad 3. The gold wire 4 is wire-bonded from the respective electrodes of the IC chips a.1 and b.2 to the wiring pattern 13 provided on the protrusion c.20 with the wiring pattern side being the second bonding side. In the case of the present embodiment, the bonding surface between the die pad 3 and the plate 17 can be widened, and even if the die pad 3 is pressed to the upper side or the lower side in FIG. And the protrusion d19 serve as a stopper, so that the die pad 3 and the gold wire 4 are not exposed to the outside of the sealing material 6, which is different from the above embodiments.
[0025]
【The invention's effect】
As described above, according to the present invention, a plate on which a desired conductive pattern is formed in advance is mounted on a die pad, and a conductive wiring pattern on the plate is provided between the IC chips among the electrodes of the IC chip. By using the conductive bonding means as the first bonding side and connecting the IC chips via the conductive wiring pattern, the second bonding side comes on the IC chip. Because there is no damage, there is a possibility that damage such as cracks on electrodes on the 2nd bonding side IC chip, which may occur when direct wire bonding is performed between IC chips, and that a gold wire comes into contact with an opening on the IC chip. No resulting short circuit occurs. Also, a conductive wiring pattern is formed and mounted on the die pad, and a lead provided around the die pad from a plate electrically connected to the IC chip by the conductive bonding means via the conductive bonding means as necessary. By electrically connecting, it is possible to exchange signals between the IC chip connection electrodes and the outside while making electrical connection between the IC chips. Further, by providing a convex portion on one or both surfaces of the plate, the convex portion serves as a stopper to suppress the floating of the die pad. Even if the thickness of the package is reduced, gold wires, IC chips, and die pads due to the floating of the die pad are provided. This has the effect of eliminating problems such as exposure from the sealing portion. Also, it is possible to fix the plate to the die pad on a wider surface by providing a hole in the die pad, providing a hole in the die pad, bonding the plate to the die pad, and projecting a protrusion provided on the plate from the hole of the die pad. It is difficult to remove the plate and the height is stable.
[Brief description of the drawings]
FIG. 1 is a plan view of the inside of a package according to a first embodiment of the semiconductor device of the present invention.
FIG. 2 is a sectional view of the inside of a package according to a first embodiment of the semiconductor device of the present invention.
FIG. 3 is a perspective view illustrating a method of forming a plate according to the present invention.
FIG. 4 is a plan view relating to a second embodiment of the semiconductor device of the present invention.
FIG. 5 is a perspective view around a plate according to a second embodiment of the semiconductor device of the present invention.
FIG. 6 is a plan view showing the inside of a package according to a third embodiment of the semiconductor device of the present invention;
FIG. 7 is a perspective view of the vicinity of a plate according to a third embodiment of the semiconductor device of the present invention.
FIG. 8 is a plan view showing the inside of a package according to a fourth embodiment of the semiconductor device of the present invention;
FIG. 9 is a perspective view of the vicinity of a plate according to a fourth embodiment of the semiconductor device of the present invention.
FIG. 10 is a plan view showing the inside of a package according to a fifth embodiment of the semiconductor device of the present invention;
FIG. 11 is a perspective view showing the vicinity of a plate according to a fifth embodiment of the semiconductor device of the present invention.
FIG. 12 is a plan view showing the inside of a package according to a sixth embodiment of the semiconductor device of the present invention;
FIG. 13 is a sectional view showing the inside of a package according to a sixth embodiment of the semiconductor device of the present invention;
FIG. 14 is a perspective view illustrating a method of forming a convex portion according to a sixth embodiment of the semiconductor device of the present invention.
FIG. 15 is a plan view of a back surface inside a package according to a seventh embodiment of the semiconductor device of the present invention.
FIG. 16 is a sectional view showing the inside of a package according to a seventh embodiment of the semiconductor device of the present invention;
FIG. 17 is a plan view showing the inside of a package according to an eighth embodiment of the semiconductor device of the present invention;
FIG. 18 is a sectional view showing the inside of a package according to an eighth embodiment of the semiconductor device of the present invention;
FIG. 19 is a plan view showing the inside of a package according to a ninth embodiment of the semiconductor device of the present invention;
FIG. 20 is a sectional view of the inside of a package according to a ninth embodiment of the semiconductor device of the present invention;
FIG. 21 is a perspective view showing a method of forming a projection c according to a ninth embodiment of the semiconductor device of the present invention.
FIG. 22 is a perspective view illustrating a method of mounting a plate according to a ninth embodiment of the semiconductor device of the present invention.
FIG. 23 is a plan view showing the inside of a package according to a tenth embodiment of the semiconductor device of the present invention;
FIG. 24 is a sectional view showing the inside of a package according to a tenth embodiment of the semiconductor device of the present invention;
FIG. 25 is a sectional view of a first example of a conventional semiconductor device.
FIG. 26 is a sectional view of a second example of a conventional semiconductor device.
FIG. 27 is a cross-sectional view showing a gold wire cut state on the second bonding side according to a first example of a conventional semiconductor device.
[Explanation of symbols]
1. IC chip a
2. IC chip b
3. Die pad
4. Gold wire
5. Lead
6. Sealing material
7. adhesive
8. Electrode a
9. Electrode b
10. Electrode c
11. Electrode d
12. substrate
13. Wiring pattern
14． Wire bonding jig
15. crack
16. Insulating layer
17． plate
18. Electrode e
19. Convex part d
20. Convex part a
21. Convex part b
22. hole
23. Convex part c
24. hole
25. Common patterns
26. Lead near IC chip a
27. Resist
28. Hardened resist
29. Uncured resist

Claims (6)

電極を有する複数のＩＣチップと、
前記複数のＩＣチップを搭載したダイパッドと、
前記ダイパッドに搭載され、金属プレートと前記金属プレートの上に設けられた絶縁層と前記絶縁層の上に設けられた導電性のパターンとを有するプレートと、
前記複数のＩＣチップの前記電極と前記導電性のパターンとを電気的に接続することにより、前記複数のＩＣチップの相互間を電気的に接続する導電性接続手段と、
を有することを特徴とする半導体装置。A plurality of IC chips having electrodes;
A die pad on which the plurality of IC chips are mounted;
Plate mounted on the die pad, having a metal plate and an insulating layer provided on the metal plate and a conductive pattern provided on the insulating layer,
A conductive connection means for electrically connecting the electrodes of the plurality of IC chips and the conductive pattern, thereby electrically connecting the plurality of IC chips to each other;
A semiconductor device comprising: 請求項１記載の半導体装置において、
前記プレートの上面のみ、下面のみまたは上・下両面には、前記導電性パターンと前記導電性接続手段とのコンタクト部分以外に凸部分が設けられていることを特徴とする半導体装置。The semiconductor device according to claim 1,
A semiconductor device, wherein a convex portion is provided on only the upper surface, only the lower surface, or both upper and lower surfaces of the plate, in addition to the contact portion between the conductive pattern and the conductive connecting means. 請求項１記載の半導体装置において、
前記ダイパッドは、穴を有しており、
前記プレートの下面のみ、または、上・下両面には、前記導電性パターンと前記導電性接続手段とのコンタクト部分以外に凸部分が設けられ、
前記凸部分のうち前記プレートの下面に設けられたものは、前記穴から突出していることを特徴とする半導体装置。The semiconductor device according to claim 1,
The die pad has a hole,
Only the lower surface of the plate, or the upper and lower surfaces, provided with a convex portion other than a contact portion between the conductive pattern and the conductive connection means,
The semiconductor device according to claim 1, wherein one of the convex portions provided on the lower surface of the plate protrudes from the hole. 請求項２または３に記載の半導体装置において、
前記凸部分は、前記導電性接続手段が前記モールド部分から露出しない高さに設けられたものであることを特徴とする半導体装置。The semiconductor device according to claim 2, wherein
The semiconductor device according to claim 1, wherein the convex portion is provided at a height at which the conductive connection means is not exposed from the mold portion. 請求項１から４のいずれかに記載の半導体装置において、
前記凸部分の少なくとも一部は、前記モールド部分から露出していることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein
A semiconductor device, wherein at least a part of the convex portion is exposed from the mold portion. 第１の凸部分を有するプレートと、
穴を有するダイパッドであって、前記第１の凸部分が前記穴から突出するように前記プレート上に設けられたダイパッドと、
電極を有するＩＣチップであって、前記ダイパッド上に設けられた複数の前記ＩＣチップと、
前記複数のＩＣチップの前記電極と前記導電性のパターンとを電気的に接続することにより、前記ＩＣチップの相互間を電気的に接続する導電性接続手段と、を有することを特徴とする半導体装置。A plate having a first convex portion;
A die pad having a hole, the die pad being provided on the plate so that the first convex portion protrudes from the hole,
An IC chip having electrodes, wherein the plurality of IC chips are provided on the die pad;
A conductive connection means for electrically connecting the electrodes of the plurality of IC chips and the conductive pattern, thereby electrically connecting the IC chips to each other. apparatus.
JP2002034524A 2002-02-12 2002-02-12 Semiconductor device Expired - Lifetime JP3599031B2 (en)

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JP6228412B2 (en) * 2013-09-18 2017-11-08 エスアイアイ・セミコンダクタ株式会社 Semiconductor device
WO2020170650A1 (en) * 2019-02-22 2020-08-27 パナソニックＩｐマネジメント株式会社 Semiconductor module, power semiconductor module, and power electronic equipment using either of same

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