JP3531485B2 - Power converter - Google Patents
Power converterInfo
- Publication number
- JP3531485B2 JP3531485B2 JP22402398A JP22402398A JP3531485B2 JP 3531485 B2 JP3531485 B2 JP 3531485B2 JP 22402398 A JP22402398 A JP 22402398A JP 22402398 A JP22402398 A JP 22402398A JP 3531485 B2 JP3531485 B2 JP 3531485B2
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- Prior art keywords
- current
- phase
- output
- converter
- command value
- Prior art date
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Description
【０００１】[0001]
【発明の属する技術分野】本発明は複数の変換器を並列
接続する電力変換装置に係わり、特に複数の変換器間を
流れる循環電流を抑制するのに好適な電力変換装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter in which a plurality of converters are connected in parallel, and more particularly to a power converter suitable for suppressing a circulating current flowing between a plurality of converters.
【０００２】[0002]
【従来の技術】従来のインバータ制御装置としては、特
開昭63−287371号公報に記載のように、リアクトルを介
して負荷に並列接続された２台のインバータの出力電流
の差分にゲインを乗じ、ＰＷＭ制御用の搬送波の１周期
毎に発生する同期信号毎に、ＰＷＭ電圧指令値である変
調波を加算して、２台のインバータ間に流れる循環電流
を抑制するものが開示されている。2. Description of the Related Art As a conventional inverter control device, as described in JP-A-63-287371, a gain is multiplied by a difference between output currents of two inverters connected in parallel to a load via a reactor. , A modulation wave that is a PWM voltage command value is added to each synchronization signal generated in each cycle of a carrier wave for PWM control to suppress a circulating current flowing between two inverters.
【０００３】[0003]
【発明が解決しようとする課題】上述したように、従来
技術ではインバータの出力電流の差分から循環電流補正
量を計算しているので、インバータが３台以上の場合に
はこの制御装置を適用できず、変換器間を流れる循環電
流を抑制することができないという問題があった。As described above, in the prior art, the circulating current correction amount is calculated from the difference between the output currents of the inverters. Therefore, this control device can be applied when the number of inverters is three or more. Therefore, there is a problem that the circulating current flowing between the converters cannot be suppressed.
【０００４】また、循環電流の検出値は瞬時値であり、
検出値にフィルタを入れると位相が遅れてしまうので、
フィルタを制御に入れることができないという問題があ
った。The detected value of the circulating current is an instantaneous value,
If a filter is added to the detected value, the phase will be delayed, so
There was a problem that the filter could not be put into control.
【０００５】さらに、循環電流の検出は瞬時値の交流量
であるため、パルスのずれ分によるパルス周波数成分の
電流リップルを検出して循環電流を補正すると、変換器
を安定に制御できないという問題があった。Further, since the circulating current is detected as an AC value of an instantaneous value, if the circulating current is corrected by detecting the current ripple of the pulse frequency component due to the pulse shift, there is a problem that the converter cannot be controlled stably. there were.
【０００６】また、循環電流のパルス周波数成分の電流
リップルに定常的に生じる直流成分により、変換器間の
バランスが悪くなり、変換器の出力電流容量を最大値ま
で利用できないという問題があった。Further, there is a problem that the output current capacity of the converter cannot be utilized up to the maximum value due to the imbalance between the converters due to the DC component that is constantly generated in the current ripple of the pulse frequency component of the circulating current.
【０００７】本発明の目的は、変換器の並列数が３以上
の場合にも循環電流を抑制することができる電力変換装
置を提供することにある。An object of the present invention is to provide a power converter which can suppress circulating current even when the number of converters in parallel is three or more.
【０００８】また、本発明の他の目的は、変換器を安定
して制御することのできる電力変換装置を提供すること
にある。Another object of the present invention is to provide a power converter capable of stably controlling the converter.
【０００９】さらに、本発明の他の目的は、電流容量の
最大限まで変換器間の電流を利用することができる電力
変換装置を提供することにある。Further, another object of the present invention is to provide a power conversion device which can utilize the current between the converters to the maximum of the current capacity.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するため
に本発明の電力変換装置は、外部からの出力指令値に応
じて３相電流を出力する変換器を複数台並列接続し、該
各変換器の合成電流を出力する電力変換装置において、
前記各変換器の各相出力電流を検出する変換器出力検出
手段と、前記合成電流を検出する合成電流検出手段と、
該合成電流検出手段で検出された合成電流より、各変換
器の各相毎の平均電流を求める平均電流算出手段と、該
平均電流算出手段により求められた各相毎の平均電流
と、前記変換器出力検出手段により検出された各相出力
電流との偏差を求め、前記外部からの出力指令値を前記
偏差により補正し、循環電流を抑制する出力指令値補正
手段を備えたことを特徴とするものである。In order to achieve the above object, the power converter of the present invention has a plurality of converters connected in parallel, each of which outputs a three-phase current according to an output command value from the outside. In the power converter that outputs the combined current of the converter,
Converter output detection means for detecting each phase output current of each converter, combined current detection means for detecting the combined current,
An average current calculating means for obtaining an average current for each phase of each converter from the combined current detected by the combined current detecting means; an average current for each phase obtained by the average current calculating means; Is provided with output command value correction means for determining a deviation from each phase output current detected by the device output detection means, correcting the output command value from the outside by the deviation, and suppressing the circulating current. It is a thing.
【００１１】[0011]
【発明の実施の形態】以下、本発明の一実施例につい
て、図１及び図２を用いて説明する。図１は、本発明の
一実施例である電力変換装置である。なお、以下の説明
において変換器、ＰＷＭ制御装置はそれぞれ３台ある
が、同様の構成であるためそれぞれ１台の制御系につい
て説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a power conversion device according to an embodiment of the present invention. In the following description, there are three converters and three PWM control devices, but since they have the same configuration, only one control system will be described.
【００１２】図１に示すように、変換器７−１，７−２
及び７−３は出力電流容量を大きくするために３並列接
続構成となっている。変換器７−１の出力端子のそれぞ
れＵ相，Ｖ相，Ｗ相には、電流検出器８−１ｕ，８−１
ｖ，８−１ｗを介してリアクトル９−１ｕ，９−１ｖ及
び９−１ｗが接続されている。ここで、変換器７−１，
７−２，７−３のＵ相出力電流Ｉ１ｕ，Ｉ２ｕ，Ｉ３ｕ
は、リアクトル９−１ｕ，９−２ｕ，９−３ｕを介して
合成され、発電電動機１３の２次巻線のＵ相に変換器合
成電流Ｉｕを供給する。また、電流検出器１２ｕにより
検出される変換器出力電流ＩＦＡｕは、ＰＷＭ制御器６
−１，６−２，６−３及び、３相２相変換器１５ａに入
力される。３相２相変換器１５ａでは、数１に示す行列
式により、３相の入力値を直交する２軸のデータであ
る、ｄ軸電流検出値Ｉｄｆとｑ軸電流検出値Ｉｑｆに変
換している。なお、前述した２軸のデータであるｄ軸電
流検出値Ｉｄｆとｑ軸電流検出値Ｉｑｆとは、それぞれ
有効電力成分，無効電力成分を示している。As shown in FIG. 1, converters 7-1 and 7-2 are provided.
And 7-3 have a three-parallel connection configuration in order to increase the output current capacity. The current detectors 8-1u and 8-1 are connected to the U-phase, V-phase and W-phase of the output terminals of the converter 7-1, respectively.
Reactors 9-1u, 9-1v and 9-1w are connected via v, 8-1w. Here, the converter 7-1,
7-2, 7-3 U-phase output currents I1u, I2u, I3u
Are combined via the reactors 9-1u, 9-2u, 9-3u and supply the converter combined current Iu to the U phase of the secondary winding of the generator motor 13. Further, the converter output current IFAu detected by the current detector 12u is the PWM controller 6
It is input to the -1, 6-2, 6-3 and the three-phase / two-phase converter 15a. In the three-phase / two-phase converter 15a, the three-phase input values are converted into the d-axis current detection value Idf and the q-axis current detection value Iqf, which are biaxial data orthogonal to each other, by the determinant shown in Formula 1. . The d-axis current detection value Idf and the q-axis current detection value Iqf, which are the two-axis data described above, indicate the active power component and the reactive power component, respectively.
【００１３】[0013]
【数１】 [Equation 1]
【００１４】ここで、数１に示すωは、発電電動機１３
の２次側の励磁周波数であり、周波数検出器１８により
検出される。また、数１により得られるｄ軸電流検出値
Ｉdfおよびｑ軸電流検出値Ｉｑｆは直流成分となる。な
お、以上の説明では変換器７−１，７−２，７−３の出
力端子のＵ相について説明しているが、Ｖ相，Ｗ相も同
様の構成となっている。Here, ω shown in Equation 1 is the generator motor 13
This is the excitation frequency on the secondary side of, and is detected by the frequency detector 18. Further, the d-axis current detection value Idf and the q-axis current detection value Iqf obtained by the equation 1 become the DC component. Although the U phase of the output terminals of the converters 7-1, 7-2 and 7-3 has been described in the above description, the V phase and the W phase have the same configuration.
【００１５】また、ｄ軸電流検出値Ｉｄｆ及びｑ軸電流
検出値Ｉｑｆは、ｄ軸電流指令値Ｉｄ* 及びｑ軸電流指
令値Ｉｑ* と共に電流調整器３に入力される。電流調整
器３では、ｄ軸電流指令値Ｉｄ* 及びｑ軸電流指令値Ｉ
ｑ* と、ｄ軸電流検出値Ｉｄｆ及び、ｑ軸電流検出値Ｉ
ｑｆとの偏差を演算増幅し、その出力値である発電機ｄ
軸電圧指令Ｖｄ* 及び、発電機ｑ軸電圧指令Ｖｑ* を２
相３相変換器４ａへ入力している。The d-axis current detection value Idf and the q-axis current detection value Iqf are input to the current regulator 3 together with the d-axis current command value Id * and the q-axis current command value Iq *. In the current regulator 3, the d-axis current command value Id * and the q-axis current command value I
q *, d-axis current detection value Idf, and q-axis current detection value I
The deviation from qf is calculated and amplified, and the output value of the generator d
Axis voltage command Vd * and generator q-axis voltage command Vq * are set to 2
It is input to the phase-to-phase converter 4a.
【００１６】[0016]
【数２】 [Equation 2]
【００１７】ここで、数２に示すωは、発電電動機１３
の２次側の励磁周波数である。２相３相変換器４ａで
は、数２に示す行列式により、三相の変換器出力電圧指
令値Ｖｕ* ，Ｖｖ* ，Ｖｗ* に変換され、ＰＷＭ制御器
６−１，６−２，６−３にそれぞれ入力される。Here, ω shown in Equation 2 is the generator motor 13
Is the excitation frequency on the secondary side of. In the two-phase / three-phase converter 4a, the three-phase converter output voltage command values Vu *, Vv *, and Vw * are converted by the determinant shown in Equation 2, and the PWM controllers 6-1, 6-2, 6 are used. -3 are input respectively.
【００１８】図２は、図１に示すＰＷＭ制御器の制御ブ
ロック図である。なお、図２ではＰＷＭ制御器６−１の
みを示しているが、ＰＷＭ制御器６−２，６−３も同様
の構成となっている。FIG. 2 is a control block diagram of the PWM controller shown in FIG. Although only the PWM controller 6-1 is shown in FIG. 2, the PWM controllers 6-2 and 6-3 have the same configuration.
【００１９】図２に示すように、変換器出力電圧指令値
Ｖｕ* ，Ｖｖ* ，Ｖｗ* は、加減算器１９ａｕ，１９ａ
ｖ，１９ａｗに入力される。加減算器１９ａｕ，１９ａ
ｖ，１９ａｗからの出力は、ＰＷＭパルス発生器２２
ｕ，２２ｖ，２２ｗに入力され、出力パルスＰｕ，Ｐ
ｖ，ＰｗをＰＷＭ制御器６−１と接続された変換器７−
１のＵ相，Ｖ相，Ｗ相の素子のゲートに入力している。
そして、変換器７−１は、ＰＷＭパルスに基づいて素子
をオン／オフさせて相電流を出力する。As shown in FIG. 2, converter output voltage command values Vu *, Vv *, Vw * are added / subtracted by adders / subtractors 19au, 19a.
v, 19aw. Adder / subtractor 19au, 19a
The output from v, 19aw is the PWM pulse generator 22.
u, 22v, 22w, and output pulses Pu, P
A converter 7-in which v and Pw are connected to the PWM controller 6-1
It is input to the gates of the U-phase, V-phase, and W-phase elements of No. 1.
Then, the converter 7-1 turns on / off the element based on the PWM pulse, and outputs the phase current.
【００２０】また、除算器２０ｕ，２０ｖ，２０ｗで
は、変換器７−１，７−２，７−３の合成電流ＩＦＡ
ｕ，ＩＦＡｖ，ＩＦＡｗを変換器の並列台数で除算し、
平均出力電流信号ＩＦｕ，ＩＦｖ，ＩＦｗを作成してい
る。平均出力電流信号ＩＦｕ，ＩＦｖ，ＩＦｗは、加減
算器１９ｂｕ，１９ｂｖ，１９ｂｗに入力される。ここ
で、電流検出器８−１ｕ，８−１ｖ，８−１ｗにより検
出された変換器出力電流検出値ＩＦ１ｕ，ＩＦ１ｖ，Ｉ
Ｆ１ｗも加減算器１９ｂｕ，１９ｂｖ，１９ｂｗにそれ
ぞれ入力され、平均出力電流信号ＩＦｕ，ＩＦｖ，ＩＦ
ｗとの偏差を変換器７−１のＵ相，Ｖ相，Ｗ相について
それぞれ演算を行っている。この偏差が、変換器７−
１，７−２，７−３間を流れる循環電流であり、循環電
流は合成電流には現れないので、合成電流から作成した
平均出力電流と、変換器７−１，７−２，７−３の出力
電流との差分で循環電流を検出することができる。循環
電流は、乗算器２１ｕ，２１ｖ，２１ｗでゲインを乗じ
て、これらの出力を加減算器１９ａｕ，１９ａｖ，１９
ａｗに入力している。In the dividers 20u, 20v, 20w, the combined current IFA of the converters 7-1, 7-2, 7-3 is used.
u, IFAv, IFAw divided by the number of parallel converters,
The average output current signals IFu, IFv, IFw are created. The average output current signals IFu, IFv, IFw are input to the adder / subtractors 19bu, 19bv, 19bw. Here, the converter output current detection values IF1u, IF1v, I detected by the current detectors 8-1u, 8-1v, 8-1w.
F1w is also input to the adder / subtractors 19bu, 19bv, 19bw, respectively, and the average output current signals IFu, IFv, IF
The deviation from w is calculated for each of the U phase, V phase, and W phase of the converter 7-1. This deviation is the converter 7-
This is a circulating current flowing between 1, 7-2 and 7-3, and since the circulating current does not appear in the combined current, the average output current created from the combined current and the converters 7-1, 7-2, 7- The circulating current can be detected by the difference from the output current of No. 3. The circulating currents are multiplied by the gains in the multipliers 21u, 21v, 21w, and these outputs are added / subtracted by the adders / subtractors 19au, 19av, 19w.
I am typing in aw.
【００２１】以上述べたように本実施によれば、合成電
流検出値ＩＦＡｕ，ＩＦＡｖ，ＩＦＡｗの平均出力電流
Ｉｆｕ，Ｉｆｖ，Ｉｆｗと、変換器７−１の変換器出力
電流検出値ＩＦ１ｕ，ＩＦ１ｖ，ＩＦ１ｗの偏差とから
循環電流を求めて、これにゲインを乗じて、循環電流を
減じるように変換器出力電圧指令値Ｖｕ*，Ｖｖ*，Ｖｗ
* を補正している。この結果、変換器７−１，７−２，
７−３間を流れる循環電流を抑制することができる。ま
た、変換器７−１，７−２，７−３の合成電流を検出
し、平均出力電流基準信号を作成しているので、変換器
７−１が２並列多重以上の場合でも循環電流を抑制する
ことができる。As described above, according to the present embodiment, the average output currents Ifu, Ifv, Ifw of the combined current detection values IFAu, IFAv, IFAw and the converter output current detection values IF1u, IF1v, of the converter 7-1 are obtained. The circulating current is obtained from the deviation of IF1w, multiplied by a gain, and the converter output voltage command values Vu *, Vv *, Vw are calculated so as to reduce the circulating current.
* Is corrected. As a result, the converters 7-1, 7-2,
The circulating current flowing between 7 and 3 can be suppressed. Further, since the combined current of the converters 7-1, 7-2, 7-3 is detected and the average output current reference signal is created, the circulating current is calculated even when the converter 7-1 is two parallel multiplex or more. Can be suppressed.
【００２２】なお、本実施例では３相２相変換器１５ａ
を用いて３相２相変換を行っているが、３相２相零相変
換式を用いてもよい。また、２相３相変換で２相３相変
換器４ａを用いるかわりに、２相３相零相変換式であっ
てもよい。In this embodiment, the three-phase / two-phase converter 15a is used.
Although the three-phase / two-phase conversion is performed by using, the three-phase / two-phase zero-phase conversion formula may be used. Further, instead of using the 2-phase / 3-phase converter 4a for 2-phase / 3-phase conversion, a 2-phase / 3-phase zero-phase conversion formula may be used.
【００２３】次に、本発明の他の実施例について図３，
図４を用いて説明する。図３は、本発明の他の実施例で
あるＰＷＭ制御器の制御ブロック図、図４は、図３に示
す内部発振器の制御ブロック図である。Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 3 is a control block diagram of a PWM controller according to another embodiment of the present invention, and FIG. 4 is a control block diagram of the internal oscillator shown in FIG.
【００２４】本実施例では、図３に示すように、合成電
流検出値ＩＦＡｕ，ＩＦＡｖ，ＩＦＡｗを除算器２０
ｕ，２０ｖ，２０ｗにより変換器の並列台数で除算し、
内部発振器入力信号３１ｕ，３１ｖ，３１ｗを内部発振
器２４ｕ，２４ｖ，２４ｗに入力している。また、内部
発振器２４ｕ，２４ｖ，２４ｗでは、内部発振器出力信
号３２ｕ，３２ｖ，３２ｗを加減算器１９ｂｕ，１９ｂ
ｖ，１９ｂｗに入力している。ここで、加減算器１９ｂ
ｕ，１９ｂｖ，１９ｂｗでは内部発振器出力信号３２
ｕ，３２ｖ，３２ｗと変換器出力電流ＩＦ１ｕ，ＩＦ１
ｖ，ＩＦ１ｗとの偏差、すなわち変換器７−１，７−
２，７−３間の循環電流を求めている。乗算器２１ｕ，
２１ｖ，２１ｗでは、加減算器１９ｂｕ，１９ｂｖ，１
９ｂｗで求めた偏差にゲインを乗じ、その値を加減算器
１９ａｕ，１９ａｖ，１９ａｗに入力している。In this embodiment, as shown in FIG. 3, the divider 20 divides the combined current detection values IFAu, IFAv, IFAw.
Divide by the parallel number of converters by u, 20v, 20w,
The internal oscillator input signals 31u, 31v, 31w are input to the internal oscillators 24u, 24v, 24w. Further, in the internal oscillators 24u, 24v, 24w, the internal oscillator output signals 32u, 32v, 32w are added / subtracted by the adders / subtractors 19bu, 19b.
v, 19bw. Here, the adder / subtractor 19b
In u, 19bv, 19bw, the internal oscillator output signal 32
u, 32v, 32w and converter output currents IF1u, IF1
deviation from v, IF1w, that is, converters 7-1, 7-
The circulating current between 2 and 7-3 is obtained. Multiplier 21u,
21v and 21w, adder / subtractors 19bu, 19bv, 1
The deviation obtained in 9 bw is multiplied by a gain, and the value is input to adder / subtractors 19 au, 19 av, 19 aw.
【００２５】次に、内部発振器２４ｕの動作について図
４を用いて説明する。なお、以下の説明ではＵ相につい
て述べるが、３相とも構成は同じである。図４に示すよ
うに、内部発振器入力信号３１ｕおよび内部発振器２４
ｕの内部発振器出力信号32ｕは位相差検出手段２８ｕに
入力され、内部発振器２４ｕの内部発振器入力信号３１
ｕと内部発振器出力信号３２ｕの位相差Δθを計算す
る。演算された位相差Δθは、加減算器１９ｃｕに入力
される。また内部発振器２４ｕの基準角周波数２５の積
分値、すなわち位相は、積分器２６ｕで演算され、加減
算器１９ｃｕで位相差Δθと加算され、発振器２７ｕに
入力される。発振器２７ｕは、入力された位相信号に基
づいて大きさ“１”の正弦波を乗算器３３ｕに入力す
る。また、内部発振器２４ｕの内部発振器入力信号３１
ｕは、振幅検出手段２９ｕにより振幅を演算され、フィ
ルタ３０ｕを通して乗算器３３ｕに入力する。従って内
部発振器２４ｕの内部発振器出力信号３２ｕは、平均出
力電流である内部発振器入力信号３１ｕの振幅のみフィ
ルタ効果を持たせ、位相遅れなく追従したものとなる。Next, the operation of the internal oscillator 24u will be described with reference to FIG. Note that the U phase will be described in the following description, but the configuration is the same for all three phases. As shown in FIG. 4, the internal oscillator input signal 31u and the internal oscillator 24
The internal oscillator output signal 32u of u is input to the phase difference detecting means 28u, and the internal oscillator input signal 31 of the internal oscillator 24u is input.
The phase difference Δθ between u and the internal oscillator output signal 32u is calculated. The calculated phase difference Δθ is input to the adder / subtractor 19cu. The integrated value of the reference angular frequency 25 of the internal oscillator 24u, that is, the phase is calculated by the integrator 26u, added with the phase difference Δθ by the adder / subtractor 19cu, and input to the oscillator 27u. The oscillator 27u inputs a sine wave of size "1" to the multiplier 33u based on the input phase signal. In addition, the internal oscillator input signal 31 of the internal oscillator 24u
The amplitude of u is calculated by the amplitude detecting means 29u and input to the multiplier 33u through the filter 30u. Therefore, the internal oscillator output signal 32u of the internal oscillator 24u has a filtering effect only on the amplitude of the internal oscillator input signal 31u, which is the average output current, and follows up without phase delay.
【００２６】以上述べたように、本実施例によれば、変
換器７−１，７−２，７−３の平均電流の振幅のみにフ
ィルタ効果を持たせた内部発振器出力信号３２ｕを用い
て循環電流を抑制するため、検出電流に含まれるパルス
周波数成分のリップルに対して影響を受けずに循環電流
を抑制できる。As described above, according to this embodiment, the internal oscillator output signal 32u in which only the amplitude of the average current of the converters 7-1, 7-2, 7-3 is given the filter effect is used. Since the circulating current is suppressed, the circulating current can be suppressed without being affected by the ripple of the pulse frequency component included in the detected current.
【００２７】図５は、本発明の他の実施例であるＰＷＭ
制御器の制御ブロック図である。FIG. 5 shows a PWM according to another embodiment of the present invention.
It is a control block diagram of a controller.
【００２８】本実施例では、変換器７−１，７−２，７
−３からの合成電流検出値ＩＦＡｕ，ＩＦＡｖ，ＩＦＡ
ｗの３相を除算器２０ｂに入力し、変換器出力電流検出
値ＩＦ１ｕ，ＩＦ１ｖ，ＩＦ１ｗとの偏差、すなわち循
環電流を加減算器１９ｂｕ，１９ｂｖ，１９ｂｗで演算
している。そして、これらの循環電流を３相２相変換器
１５ｂに入力して、２軸のデータを演算し、乗算器１４
ａによりゲインを乗じて位相調整器３４に入力し、これ
らの出力を２相３相変換器４ｂに入力して、３相の交流
信号に変換している。２相３相変換器４ｂからの交流信
号は、変換器出力電圧指令値Ｖｕ* ，Ｖｖ* ，Ｖｗ* と
共に加減算器１９ａｕ，１９ａｖ，１９ａｗに入力さ
れ、循環電流を減じるように電圧指令値を補正し、ＰＷ
Ｍパルス発生器２２ｕ，２２ｖ，２２ｗによりゲートパ
ルスＰｕ，Ｐｖ，Ｐｗを出力している。In this embodiment, the converters 7-1, 7-2, 7 are used.
Detected current values IFAu, IFAv, IFA from -3
The three phases of w are input to the divider 20b, and deviations from the converter output current detection values IF1u, IF1v, IF1w, that is, circulating currents are calculated by the adders / subtractors 19bu, 19bv, 19bw. Then, these circulating currents are input to the three-phase / two-phase converter 15b, the data of the two axes are calculated, and the multiplier 14
The gain is multiplied by a and input to the phase adjuster 34, and these outputs are input to the two-phase / three-phase converter 4b and converted into a three-phase AC signal. The AC signal from the two-phase / three-phase converter 4b is input to the adder / subtractors 19au, 19av, 19aw together with the converter output voltage command values Vu *, Vv *, Vw *, and the voltage command value is corrected so as to reduce the circulating current. And then PW
Gate pulses Pu, Pv, Pw are output by the M pulse generators 22u, 22v, 22w.
【００２９】この場合、合成電流を３相２相変換器１５
ｂにより３相２相変換した後に、除算器２０ｂにより変
換器台数で除算した値を用いて補正することも可能であ
る。以上のように本実施例によれば、循環電流を３相２
相変換器１５ｂにより３相２相変換を行っているので、
循環電流から必要とする電圧補正量をベクトル量として
瞬時に演算でき、循環電流を効率よく抑制することがで
きる。In this case, the combined current is converted into a three-phase / two-phase converter 15
It is also possible to perform correction by using a value obtained by dividing the number of converters by the divider 20b after the three-phase / two-phase conversion by b. As described above, according to this embodiment, the circulating current is divided into three phases and two phases.
Since three-phase / two-phase conversion is performed by the phase converter 15b,
The voltage correction amount required from the circulating current can be instantaneously calculated as a vector amount, and the circulating current can be efficiently suppressed.
【００３０】図６は、本発明の他の実施例であるＰＷＭ
制御器の制御ブロック図である。本実施例では、図５に
示すＰＷＭ制御器において、位相調整器３４と２相３相
変換器４ｂとの間にフィルタ３５を設けた構造となって
いる。FIG. 6 shows a PWM according to another embodiment of the present invention.
It is a control block diagram of a controller. In the present embodiment, the PWM controller shown in FIG. 5 has a structure in which a filter 35 is provided between the phase adjuster 34 and the 2-phase / 3-phase converter 4b.
【００３１】以上のように本実施例によれば、３相２相
変換を行って回転座標上の直流量に変換しているので、
循環電流の検出値に位相遅れを生じさせずにフィルタを
付加できるので、変換器を安定に制御するとともに循環
電流を抑制できる。As described above, according to this embodiment, the three-phase / two-phase conversion is performed to convert the direct current amount on the rotating coordinate.
Since a filter can be added without causing a phase delay in the detected value of the circulating current, the converter can be stably controlled and the circulating current can be suppressed.
【００３２】図７は、本発明の他の実施例であるＰＷＭ
制御器の制御ブロック図である。本実施例では、図６に
示すＰＷＭ制御器において、加減算器１９ｂｕ，１９ｂ
ｖ，１９ｂｗからの出力信号をゲイン演算器１７ｕ，１
７ｖ，１７ｗに入力し、ゲイン演算器１７ｕ，１７ｖ，
１７ｗの出力信号と、２相３相変換器４ｂの出力信号を
乗算器１４ｕ，１４ｖ，１４ｗに入力する構造としてお
り、各相の循環電流の大きさに応じて電圧を補正するよ
うにしている。FIG. 7 shows a PWM according to another embodiment of the present invention.
It is a control block diagram of a controller. In this embodiment, in the PWM controller shown in FIG. 6, adder / subtractors 19bu and 19b are added.
The output signals from v and 19 bw are gain calculators 17 u and 1
7v, 17w, and gain calculators 17u, 17v,
The output signal of 17w and the output signal of the 2-phase / 3-phase converter 4b are input to the multipliers 14u, 14v, 14w, and the voltage is corrected according to the magnitude of the circulating current of each phase. .
【００３３】以上のように本実施例によれば、自相の循
環電流の大きさに応じて電圧補正量を決めるので、自相
の循環電流が大きいときはそれに比例して補正量を大き
くでき、小さいときは補正量を小さくできるので、他の
相の循環電流の影響による補正量の変化を小さくするこ
とができる。As described above, according to this embodiment, the voltage correction amount is determined according to the magnitude of the circulating current of the self phase, so that when the circulating current of the self phase is large, the correction amount can be increased in proportion thereto. When it is small, the correction amount can be made small, so that the change in the correction amount due to the influence of the circulating current of the other phase can be made small.
【００３４】また、本実施例では３相２相変換を用いた
電圧指令値補正値の演算を行うこともできる。Further, in this embodiment, the voltage command value correction value can be calculated by using the three-phase / two-phase conversion.
【００３５】図８は、本発明の他の実施例である電力変
換装置を示す構成図である。なお、図８では３相とも同
様な構成であるので、Ｕ相についてのみ示している。FIG. 8 is a configuration diagram showing a power conversion device according to another embodiment of the present invention. Note that FIG. 8 shows the same configuration for all three phases, so only the U phase is shown.
【００３６】本実施例は、変換器７−１ｕ，７−２ｕを
２並列に接続した構成となっている。２並列に接続され
た変換器７−１ｕ，７−２ｕからのＵ相出力電流は、そ
れぞれリアクトル９−１ｕ，９−２ｕを介して合成され
る。また、変換器７−１ｕ，７−２ｕとリアクトル９−
１ｕ，９−２ｕ間にそれぞれ接続された電流検出器８−
１ｕ，８−２ｕより検出される循環電流を、加減算器１
９ｄｕに入力して検出電流の差分を求めている。そし
て、検出電流の差分を３相２相変換器１５ｃに入力し、
位相調整器３４で循環電流を電圧成分ベクトルに換算
し、２相３相変換器４ｃで３相のデータに戻して、乗算
器１４ｂでゲインを乗じている。乗算器１４ｂからの信
号は、変換器出力電圧指令値Ｖｕ* と共に加減算器１９
ａｕ１，１９ａｕ２に入力され、循環電流を減じるよう
に変換器出力電圧指令値Ｖｕ* を補正している。In this embodiment, the converters 7-1u and 7-2u are connected in parallel in two. U-phase output currents from the converters 7-1u and 7-2u connected in parallel in two are combined via reactors 9-1u and 9-2u, respectively. In addition, the converters 7-1u and 7-2u and the reactor 9-
Current detector 8-connected between 1u and 9-2u
The circulating currents detected by 1u and 8-2u are added / subtracted by the adder / subtractor 1
It is input to 9du to find the difference between the detected currents. Then, the difference between the detected currents is input to the 3-phase / 2-phase converter 15c,
The phase adjuster 34 converts the circulating current into a voltage component vector, the 2-phase / 3-phase converter 4c restores the 3-phase data, and the multiplier 14b multiplies the gain. The signal from the multiplier 14b is added to the adder / subtractor 19 together with the converter output voltage command value Vu *.
The converter output voltage command value Vu * is corrected so as to reduce the circulating current by being input to au1 and 19au2.
【００３７】以上述べたように本実施によれば、２並列
接続の場合では簡単な構成で循環電流を検出でき、前述
した実施例と同様に循環電流を抑制することができる。As described above, according to this embodiment, the circulating current can be detected with a simple structure in the case of the two parallel connections, and the circulating current can be suppressed as in the above-described embodiments.
【００３８】図９は、本発明の他の実施例である電力変
換装置を示す構成図である。本実施例では、変換器７−
１，７−２，７−３にそれぞれ対応した電流調整器３−
１，３−２，３−３及び、２相３相変換器４ａ，３相２
相変換器１５ａを設けており、電流調整器３−１，３−
２，３−３の入力信号には、検診変換器１台分のｄ軸電
流指令値Ｉｄ* およびｑ軸電流指令値Ｉｑ* が入力され
る。ここで、電流調整器３−１のフィードバック信号Ｉ
Ｆ１ｄ，ＩＦ１ｑには、変換器７−１の出力電流検出値
ＩＦ１ｕ，ＩＦ１ｖ，ＩＦ１ｗを３相２相変換器１５ａ
１で変換した値を用いている。なお、以上の説明では変
換器７−１の制御系について述べているが、変換器７−
２，７−３も変換器７−１と同様の電流制御系を設けて
いる。FIG. 9 is a configuration diagram showing a power conversion device according to another embodiment of the present invention. In this embodiment, the converter 7-
Current regulators 3 corresponding to 1, 7-2 and 7-3, respectively
1, 3-2, 3-3, 2 phase 3 phase converter 4a, 3 phase 2
The phase converter 15a is provided, and the current regulators 3-1 and 3- are provided.
The d-axis current command value Id * and the q-axis current command value Iq * for one examination converter are input to the input signals 2 and 3-3. Here, the feedback signal I of the current regulator 3-1
The output current detection values IF1u, IF1v, and IF1w of the converter 7-1 are supplied to the F1d and IF1q as the three-phase to two-phase converter 15a.
The value converted in 1 is used. In the above description, the control system of the converter 7-1 has been described.
2, 7-3 are also provided with the same current control system as the converter 7-1.
【００３９】以上述べたように本実施例によれば、変換
器７−１，７−２，７−３のそれぞれに対応させた台数
分の電流調整器３−１，３−２，３−３を設けたことに
より、各変換器の出力電流と指令値の偏差を減少させる
ように動作するので、変換器を流れる電流が等しくな
り、その結果として循環電流を抑制することができる。
図１０は、本発明の他の実施例であるＰＭＷ制御器の制
御ブロック図である。本実施例では、図６の構成に加え
て、加減算器１９ｂｕ，１９ｂｖ，１９ｂｗからの出力
信号より、循環電流の直流成分を直流成分演算器１６
ｕ,１６ｖ,１６ｗにて演算し、乗算器３３ａｕ，３３ａ
ｖ，３３ａｗによりゲインを乗じて加減算器１９ｅｕ，
１９ｅｖ，１９ｅｗに入力して電圧指令値を補正する構
成となっている。As described above, according to this embodiment, the number of current regulators 3-1, 3-2, 3-corresponding to the converters 7-1, 7-2, 7-3, respectively. By providing 3, the converter operates so as to reduce the deviation between the output current of each converter and the command value, so that the currents flowing through the converters become equal and, as a result, the circulating current can be suppressed.
FIG. 10 is a control block diagram of a PMW controller according to another embodiment of the present invention. In the present embodiment, in addition to the configuration of FIG. 6, the DC component of the circulating current is calculated from the output signals from the adder / subtractors 19bu, 19bv, 19bw.
u, 16v, 16w, and multipliers 33au, 33a
The gain is multiplied by v, 33aw and the adder / subtractor 19eu,
19ev and 19ew are input to correct the voltage command value.
【００４０】以上述べたように、本実施例によれば、直
流成分を検出しているため、回路のインダクタンス値や
抵抗値、スイッチング素子特性のばらつきに起因する循
環電流を抑制することができる。As described above, according to the present embodiment, since the DC component is detected, it is possible to suppress the circulating current due to the variations in the inductance value and resistance value of the circuit and the switching element characteristics.
【００４１】[0041]
【発明の効果】合成電流から求めた平均出力電流と各変
換器の出力電流の偏差から循環電流を求めて、ゲインを
乗じて循環電流を減じるように電圧指令値を補正するの
で、変換器間を流れる循環電流を抑制することができ
る。また、合成電流の平均電流の振幅のみにフィルタ効
果を入れるため、該平均電流を位相と振幅成分に分割
し、内部発振器の信号の位相を該平均電流の位相に一致
させ、また、該内部発振器の振幅成分にはフィルタ効果
を入れた振幅値を用いて循環電流を抑制するため、検出
電流に含まれるパルス周波数成分のリップルに対して影
響を受けずに循環電流を抑制できる。The circulating current is obtained from the deviation between the average output current obtained from the combined current and the output current of each converter, and the voltage command value is corrected so as to reduce the circulating current by multiplying it by the gain. It is possible to suppress the circulating current that flows through. Further, in order to put a filtering effect only on the amplitude of the average current of the combined current, the average current is divided into a phase and an amplitude component, and the phase of the signal of the internal oscillator is made to match the phase of the average current. Since the circulating current is suppressed by using the amplitude value including the filter effect for the amplitude component of 1, the circulating current can be suppressed without being affected by the ripple of the pulse frequency component included in the detected current.
【００４２】また、自相の循環電流の大きさに応じて電
圧補正量を決めるので、自相の循環電流が大きいときは
それに比例して補正量を大きくでき、小さいときは補正
量を小さくできるので、他の相の循環電流の影響による
補正量の変化を小さくすることができる。Since the voltage correction amount is determined according to the magnitude of the self-phase circulating current, the correction amount can be increased proportionally when the self-phase circulating current is large, and can be reduced when the self-phase circulating current is small. Therefore, it is possible to reduce the change in the correction amount due to the influence of the circulating current of the other phase.
【００４３】また、直流成分を検出しているため、回路
のインダクタンス値や抵抗値，スイッチング素子特性の
ばらつきに起因する循環電流を抑制することができる。Further, since the DC component is detected, it is possible to suppress the circulating current due to the variations in the inductance value and resistance value of the circuit and the switching element characteristics.
【図１】本発明の一実施である電力変換装置を示す構成
図である。FIG. 1 is a configuration diagram showing a power conversion device according to an embodiment of the present invention.
【図２】図１に示すＰＷＭ制御装置の制御ブロック図で
ある。FIG. 2 is a control block diagram of the PWM control device shown in FIG.
【図３】本発明の他の実施例であるＰＷＭ制御装置の制
御ブロック図である。FIG. 3 is a control block diagram of a PWM control device according to another embodiment of the present invention.
【図４】図３に示す内部発振器の制御ブロック図であ
る。FIG. 4 is a control block diagram of the internal oscillator shown in FIG.
【図５】本発明の他の実施例であるＰＷＭ制御装置の制
御ブロック図である。FIG. 5 is a control block diagram of a PWM control device according to another embodiment of the present invention.
【図６】本発明の他の実施例であるＰＷＭ制御装置の制
御ブロック図である。FIG. 6 is a control block diagram of a PWM control device according to another embodiment of the present invention.
【図７】本発明の他の実施例であるＰＷＭ制御装置の制
御ブロック図である。FIG. 7 is a control block diagram of a PWM control device according to another embodiment of the present invention.
【図８】本発明の他の実施例である電力変換装置を示す
構成図である。FIG. 8 is a configuration diagram showing a power conversion device according to another embodiment of the present invention.
【図９】本発明の他の実施例である電力変換装置を示す
構成図である。FIG. 9 is a configuration diagram showing a power conversion device according to another embodiment of the present invention.
【図１０】本発明の他の実施例であるＰＷＭ制御装置の
制御ブロック図である。FIG. 10 is a control block diagram of a PWM control device according to another embodiment of the present invention.
Ｉｄ* …ｄ軸電流指令値、Ｉｑ* …ｑ軸電流指令値、
３，３−１，３−２，３−３，３ｕ…電流調整器、４
ａ，４ｂ，４ａｕ…２相３相変換器、Ｖｕ*，Ｖｖ*，Ｖ
ｗ* …変換器出力電圧指令値、６−１，６−２，６−３
…ＰＷＭ制御器、７−１，７−２，７−３，７−１ｕ，
７−２ｕ…変換器、８−１ｕ，８−１ｖ，８−１ｗ，８
−２ｕ，８−２ｖ，８−２ｗ，８−３ｕ，８−３ｖ,８
−３ｗ,１２ｕ，１２ｖ，１２ｗ…電流検出器、Ｖｄ*
…発電機ｄ軸電圧指令、Ｖｑ* …発電機ｑ軸電圧指令、
９−１ｕ，９−１ｖ，９−１ｗ，９−２ｕ，９−２ｖ，
９−２ｗ，９−３ｕ，９−３ｖ，９−３ｗ…リアクト
ル、Ｉ１ｕ，Ｉ１ｖ,Ｉ１ｗ,Ｉ２ｕ，Ｉ２ｖ，Ｉ２ｗ，
Ｉ３ｕ，Ｉ３ｖ，Ｉ３ｗ…変換器出力電流、Ｉｕ，Ｉ
ｖ，Ｉｗ…変換器合成電流、１３…発電電動機、１４
ａ，１４ｂ，１４ｕ，１４ｖ，１４ｗ…乗算器、１５
ａ，１５ｂ，１５ｃ…３相２相変換器、Ｉｄｆ…ｄ軸電
流検出値、Ｉｑｆ…ｑ軸電流検出値、１６ｕ,１６ｖ,１
６ｗ…直流成分演算器、１７ｕ，１７ｖ，１７ｗ…ゲイ
ン演算器、１８…周波数検出器、ω…励磁周波数、ＩＦ
１ｕ，ＩＦ１ｖ，ＩＦ１ｗ，ＩＦ２ｕ，ＩＦ２ｖ，ＩＦ
２Ｗ，ＩＦ３ｕ，ＩＦ３ｖ，ＩＦ３ｗ…変換器出力電流
検出値、ＩＦＡｕ，ＩＦＡｖ，ＩＦＡｗ…合成電流検出
値、Δθ…位相差、１９ａｕ，１９ａｖ，１９ａｗ，１
９ｂｕ，１９ｂｖ，１９ｂｗ，１９ｃｕ，１９ｄｕ，１
９ｅｕ，１９ｅｖ，１９ｅｗ，１９ａｕ１，１９ａｕ２
…加減算器、２０ｕ，２０ｖ，２０ｗ，２０ｂ…除算
器、２１ｕ，２１ｖ，２１ｗ…ゲイン乗算器、２２ｕ，
２２ｖ，２２ｗ…ＰＷＭパルス発生器、Ｐｕ，Ｐｖ，Ｐ
ｗ…ゲートパルス、ＩＦｕ，ＩＦｖ，Ｉｆｗ…平均出力
電流、２４ｕ，２４ｖ，２４ｗ…内部発振器、２５…基
準角周波数、２６ｕ…積分器、２７ｕ…発振器、２８ｕ
…位相差検出手段、２９ｕ…振幅検出手段、３０ｕ…フ
ィルタ、３１ｕ…内部発振器入力信号、３２ｕ…内部発
振器出力信号、３３ｕ，３３ａｕ，３３ａｖ，３３ａｗ
…乗算器、３４…位相調整器、３５…フィルタ、ＩＦ１
ｄ，ＩＦ１ｑ，ＩＦ２ｄ，ＩＦ２ｑ,ＩＦ３ｄ,Ｉｆ３ｑ
…変換器出力電流検出値２軸成分。Id * ... d-axis current command value, Iq * ... q-axis current command value,
3, 3-1, 3-2, 3-3, 3u ... Current regulator, 4
a, 4b, 4au ... 2-phase / 3-phase converter, Vu *, Vv *, V
w * ... Converter output voltage command value, 6-1, 6-2, 6-3
... PWM controller, 7-1, 7-2, 7-3, 7-1u,
7-2u ... Converter, 8-1u, 8-1v, 8-1w, 8
-2u, 8-2v, 8-2w, 8-3u, 8-3v, 8
-3w, 12u, 12v, 12w ... Current detector, Vd *
… Generator d-axis voltage command, Vq *… Generator q-axis voltage command,
9-1u, 9-1v, 9-1w, 9-2u, 9-2v,
9-2w, 9-3u, 9-3v, 9-3w ... Reactor, I1u, I1v, I1w, I2u, I2v, I2w,
I3u, I3v, I3w ... Converter output current, Iu, I
v, Iw ... Converter combined current, 13 ... Generator motor, 14
a, 14b, 14u, 14v, 14w ... Multiplier, 15
a, 15b, 15c ... 3-phase / two-phase converter, Idf ... d-axis current detection value, Iqf ... q-axis current detection value, 16u, 16v, 1
6w ... DC component calculator, 17u, 17v, 17w ... Gain calculator, 18 ... Frequency detector, ω ... Excitation frequency, IF
1u, IF1v, IF1w, IF2u, IF2v, IF
2W, IF3u, IF3v, IF3w ... Converter output current detection value, IFAu, IFAv, IFAw ... Combined current detection value, Δθ ... Phase difference, 19au, 19av, 19aw, 1
9 bu, 19 bv, 19 bw, 19 cu, 19 du, 1
9eu, 19ev, 19ew, 19au1, 19au2
... adder / subtractor, 20u, 20v, 20w, 20b ... divider, 21u, 21v, 21w ... gain multiplier, 22u,
22v, 22w ... PWM pulse generator, Pu, Pv, P
w ... Gate pulse, IFu, IFv, Ifw ... Average output current, 24u, 24v, 24w ... Internal oscillator, 25 ... Reference angular frequency, 26u ... Integrator, 27u ... Oscillator, 28u
... phase difference detection means, 29u ... amplitude detection means, 30u ... filter, 31u ... internal oscillator input signal, 32u ... internal oscillator output signal, 33u, 33au, 33av, 33aw
... multiplier, 34 ... phase adjuster, 35 ... filter, IF1
d, IF1q, IF2d, IF2q, IF3d, If3q
... Converter output current detection value 2-axis component.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 久保田 譲 茨城県日立市大みか町七丁目２番１号 株式会社 日立製作所 電力・電機開発 本部内 (72)発明者 本部 光幸 茨城県日立市大みか町七丁目２番１号 株式会社 日立製作所 電力・電機開発 本部内 (72)発明者 樋口 幹祐 茨城県日立市幸町三丁目１番１号 株式 会社 日立製作所 日立工場内 (56)参考文献 特開 平５−15069（ＪＰ，Ａ) 特開 昭63−287371（ＪＰ，Ａ) 特開 平６−153519（ＪＰ，Ａ) 特開 平10−178742（ＪＰ，Ａ) 特開 平６−78550（ＪＰ，Ａ) 特開 平５−15070（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 7/48 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Yuzuru Kubota 7-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Electric Power & Electric Development Division (72) Mitsuyuki Inventor, head office 7 Mika-cho, Oita, Ibaraki 2-2-1 Hitachi, Ltd., Electric Power & Electric Machinery Development Division (72) Inventor, Mikisuke Higuchi 3-1-1, Saiwaicho, Hitachi, Ibaraki Hitachi Ltd., Hitachi, Ltd. (56) References 5-15069 (JP, A) JP 63-287371 (JP, A) JP 6-153519 (JP, A) JP 10-178742 (JP, A) JP 6-78550 (JP, A) JP-A-515070 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H02M 7/48
Claims (5)
出力する変換器を複数台並列接続し、該各変換器の合成
電流を出力する電力変換装置において、該電力変換装置が、 前記複数台の変換器を制御する複数台の制御器と、 前記各変換器の各相出力電流を検出する変換器出力検出
手段と、 前記合成電流を検出する合成電流検出手段とを具備し、前記制御器が、前記 合成電流検出手段で検出された合成
電流より、各変換器の各相毎の平均電流を求める平均電
流算出手段と、 該平均電流算出手段により求められた各相毎の平均電流
を入力する発振器と、前記変換器出力検出手段により検
出された各相出力電流と該発振器の出力とから偏差を求
め、 前記外部からの出力指令値を前記偏差により補正し、循
環電流を抑制する出力指令値補正手段とを備えたことを
特徴とする電力変換装置。1. A power converter in which a plurality of converters for outputting a three-phase current are connected in parallel according to an output command value from the outside and a combined current of the converters is output, the power converter comprising: comprising a plurality of controllers for controlling said plurality of converters, said a converter output detecting means for detecting a phase output current of each converter, and a composite current detecting means for detecting said composite current, An average current calculation means for obtaining an average current for each phase of each converter from the combined current detected by the combined current detection means; and an average for each phase obtained by the average current calculation means. Electric current
A deviation from the output of each oscillator and the output of each phase detected by the converter output detection means, the output command value from the outside is corrected by the deviation, and the circulating current is suppressed. power conversion device is characterized in that an output command value correcting means.
出力する変換器を複数台並列接続し、該各変換器の合成
電流を出力する電力変換装置において、該電力変換装置が、 前記複数台の変換器を制御する複数台の制御器と、 前記各変換器の各相出力電流を検出する変換器出力検出
手段と、 前記合成電流を検出する合成電流検出手段とを具備し、前記制御器が、前記 合成電流検出手段で検出された合成
電流より、各変換器の各相毎の平均電流を求める平均電
流算出手段と、前記平均電流の位相を調整する位相調整手段と、 前記平均電流のリップルを除去するフィルタ手段と、 該フィルタ手段によりリップルを除去された平均電流と
前記変換器出力検出手段による各相出力電流の偏差を求
め、 前記外部からの出力指令値を前記偏差により補正し、循
環電流を抑制する出力指令値補正手段とを備えたことを
特徴とする電力変換装置。2. A power converter for connecting a plurality of converters for outputting a three-phase current in parallel according to an output command value from the outside and outputting a combined current of the converters, wherein the power converter comprises: comprising a plurality of controllers for controlling said plurality of converters, said a converter output detecting means for detecting a phase output current of each converter, and a composite current detecting means for detecting said composite current, An average current calculation means for obtaining an average current for each phase of each converter from the combined current detected by the combined current detection means; a phase adjustment means for adjusting the phase of the average current; Filter means for removing the ripple of the average current, a deviation between the average current from which the ripple is removed by the filter means and the output current of each phase by the converter output detecting means is obtained, and the output command value from the outside is calculated by the deviation. Correct The power conversion apparatus characterized by comprising an inhibiting output command value correcting means circulating current.
の電力変換装置において、 前記制御器が、 前記 偏差を有効電力成分と無効電力成分とに変換し、 前記外部からの出力指令値を前記偏差により補正して循
環電流を抑制する出力指令値補正手段を備えたことを特
徴とする電力変換装置。3. The method according to claim 1 or 2.
Of the power converter, wherein the controller converts the said deviation and active power component and a reactive power component, suppresses the output command value correcting means correcting the circulating current by the difference output command value from the external An electric power conversion device comprising:
前記フィルタ手段は平均電流の位相を調整する位相調整
手段を備えたことを特徴とする電力変換装置。4. The power conversion device according to claim 2,
Said filter means you characterized power converter further comprising a phase adjusting means for adjusting the phase of the average current.
出力する変換器を複数台並列接続し、該各変換器の合成
電流を出力する電力変換装置において、該電力変換装置が、 前記複数台の変換器を制御する複数台の制御器と、 前記各変換器の各相出力電流を検出する変換器出力検出
手段と、 前記合成電流を検出する合成電流検出手段とを具備し、前記制御器が、前記 合成電流検出手段で検出された合成
電流より、各変換器の各相毎の平均電流を求める平均電
流算出手段と、前記平均電流の位相を調整する位相調整手段と、 前記 平均電流算出手段により求められた各相毎の平均電
流と前記変換器出力検出手段により求められる各相出力
の偏差の直流成分を検出する直流成分検出手段と、 前記外部からの出力指令値を前記偏差により補正し、循
環電流を抑制する出力指令値補正手段とを備えたことを
特徴とする電力変換装置。5. A power converter that connects a plurality of converters that output a three-phase current in parallel according to an output command value from the outside and that outputs a combined current of the converters, wherein the power converter comprises: comprising a plurality of controllers for controlling said plurality of converters, said a converter output detecting means for detecting a phase output current of each converter, and a composite current detecting means for detecting said composite current, wherein the controller is from the detected combined current in the combined current detecting means, average current calculation means for calculating an average current of each phase of each transducer, a phase adjusting means for adjusting the phase of the average current, the A DC component detecting means for detecting a DC component of a deviation of each phase output obtained by the converter output detecting means and an average current for each phase obtained by an average current calculating means, and an output command value from the outside Circulation corrected by deviation Power conversion apparatus characterized by comprising an inhibiting output command value correcting means current.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22402398A JP3531485B2 (en) | 1998-08-07 | 1998-08-07 | Power converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22402398A JP3531485B2 (en) | 1998-08-07 | 1998-08-07 | Power converter |
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| Publication Number | Publication Date |
|---|---|
| JP2000060137A JP2000060137A (en) | 2000-02-25 |
| JP3531485B2 true JP3531485B2 (en) | 2004-05-31 |
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|---|---|---|---|
| JP22402398A Expired - Lifetime JP3531485B2 (en) | 1998-08-07 | 1998-08-07 | Power converter |
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| CN100352126C (en) * | 2004-04-01 | 2007-11-28 | 台达电子工业股份有限公司 | Emergency power surply system using shared battery and input current balance method |
| JP5211952B2 (en) * | 2008-09-08 | 2013-06-12 | 富士電機株式会社 | Parallel redundancy system for power converter |
| KR101735071B1 (en) | 2015-04-10 | 2017-05-12 | 삼성중공업 주식회사 | Limited current apparatus for 3phase load |
| JP2018133987A (en) * | 2017-02-17 | 2018-08-23 | ニチコン株式会社 | Power converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287371A (en) * | 1987-05-15 | 1988-11-24 | Mitsubishi Electric Corp | Interphase reactor multiplex system pwm inverter |
| JP2887013B2 (en) * | 1991-04-25 | 1999-04-26 | 三菱電機株式会社 | Parallel operation control device for three-phase AC output converter |
| JP2708648B2 (en) * | 1991-04-22 | 1998-02-04 | 三菱電機株式会社 | Parallel operation control device |
| JP3041661B2 (en) * | 1992-08-24 | 2000-05-15 | 株式会社日立製作所 | Inverter parallel operation control method and device, and uninterruptible power supply |
| JP3028268B2 (en) * | 1992-11-12 | 2000-04-04 | 株式会社日立製作所 | Power converter |
| JPH10178742A (en) * | 1996-12-18 | 1998-06-30 | Fuji Electric Co Ltd | Circuit for controlling transfer of effective power of serial inverter |
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