JP3529902B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3529902B2
JP3529902B2 JP16905795A JP16905795A JP3529902B2 JP 3529902 B2 JP3529902 B2 JP 3529902B2 JP 16905795 A JP16905795 A JP 16905795A JP 16905795 A JP16905795 A JP 16905795A JP 3529902 B2 JP3529902 B2 JP 3529902B2
Authority
JP
Japan
Prior art keywords
polishing
semiconductor device
layer
present
mno
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16905795A
Other languages
Japanese (ja)
Other versions
JPH0922888A (en
Inventor
貞浩 岸井
明良 大石
隣太郎 鈴木
健三 塙
成生 植田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Mitsui Mining and Smelting Co Ltd
Original Assignee
Fujitsu Ltd
Mitsui Mining and Smelting Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Mitsui Mining and Smelting Co Ltd filed Critical Fujitsu Ltd
Priority to JP16905795A priority Critical patent/JP3529902B2/en
Priority to TW085108035A priority patent/TW317003B/en
Priority to KR1019960027065A priority patent/KR100251057B1/en
Publication of JPH0922888A publication Critical patent/JPH0922888A/en
Priority to US08/884,165 priority patent/US6159858A/en
Application granted granted Critical
Publication of JP3529902B2 publication Critical patent/JP3529902B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1409—Abrasive particles per se
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1454—Abrasive powders, suspensions and pastes for polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は一般に半導体装置の
製造に関し、特に研磨工程を含む半導体装置の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor device manufacturing, and more particularly to a method of manufacturing a semiconductor device including a polishing step.

【０００２】[0002]

【従来の技術】半導体装置、特に半導体集積回路では、
基板上に形成した絶縁層上に配線パターンを埋め込んだ
配線構造を多層積層した多層配線構造が一般に使われ
る。このような多層配線構造では第１の、下層配線構造
上に他の配線構造が形成されるため、各々の配線構造は
平坦な表面を有することが要求される。2. Description of the Related Art In semiconductor devices, especially semiconductor integrated circuits,
A multi-layer wiring structure in which a wiring structure in which a wiring pattern is embedded on an insulating layer formed on a substrate is multi-layered is generally used. In such a multilayer wiring structure, since another wiring structure is formed on the first lower wiring structure, each wiring structure is required to have a flat surface.

【０００３】そこで、従来より、多層配線構造を形成す
る場合には、絶縁層上にコンタクトホールあるいは配線
溝を形成し、かかる絶縁層上に、前記コンタクトホール
あるいは配線溝を埋めるように金属層を堆積し、次いで
かかる金属層を、前記絶縁層表面が露出するまで研磨に
より除去し、平坦な配線構造を形成することが行われて
いる。かかる配線構造は上主面が平坦であるため、その
上に次の配線構造を容易に形成することができる。Therefore, conventionally, when forming a multilayer wiring structure, a contact hole or a wiring groove is formed on an insulating layer, and a metal layer is formed on the insulating layer so as to fill the contact hole or the wiring groove. It has been practiced to deposit and then remove the metal layer by polishing until the surface of the insulating layer is exposed to form a flat wiring structure. Since this wiring structure has a flat upper main surface, the next wiring structure can be easily formed thereon.

【０００４】以下、かかる研磨工程を含む従来の半導体
装置の製造方法を、ＭＯＳトランジスタの製造工程を例
に、図４〜８を参照しながら説明する。図４（Ａ）を参
照するに、ＭＯＳトランジスタは例えばｐ型にドープさ
れたＳｉ基板１上に、前記基板１上に形成されたフィー
ルド酸化膜１ａが画成する活性領域１Ａに対応して形成
される。より具体的には、ＭＯＳトランジスタは前記活
性領域１Ａ表面に形成されたｎ+ 型拡散領域１ｂと、前
記活性領域１Ａ表面上に、前記拡散領域１ｂからＭＯＳ
トランジスタのチャネル領域１ｄにより隔てられて形成
された別の拡散領域１ｃと、前記チャネル領域１ｄ上
に、ゲート酸化膜（図示せず）を挟んで形成されたゲー
ト電極２とより構成され、前記ゲート電極２の側壁には
側壁絶縁膜２ａ，２ｂが形成される。また、前記拡散領
域１ｂおよび１ｃはそれぞれＭＯＳトランジスタのソー
ス領域およびドレイン領域として作用する。A conventional method of manufacturing a semiconductor device including such a polishing step will be described below with reference to FIGS. Referring to FIG. 4A, a MOS transistor is formed on, for example, a p-type doped Si substrate 1 corresponding to an active region 1A defined by a field oxide film 1a formed on the substrate 1. To be done. More specifically, the MOS transistor includes an n + -type diffusion region 1b formed on the surface of the active region 1A and a MOS region formed on the surface of the active region 1A from the diffusion region 1b.
The transistor includes a diffusion region 1c formed by being separated by a channel region 1d of a transistor, and a gate electrode 2 formed on the channel region 1d with a gate oxide film (not shown) interposed therebetween. Sidewall insulating films 2a and 2b are formed on the sidewalls of the electrode 2. The diffusion regions 1b and 1c act as the source region and the drain region of the MOS transistor, respectively.

【０００５】図４（Ａ）の工程では、かかるＭＯＳトラ
ンジスタを埋め込むように、ＳｉＯ 2 よりなる層間絶縁
膜３が、例えばＣＶＤ法等により、典型的には５０ｎｍ
程度の厚さに堆積される。その結果、前記ゲート電極お
よび拡散領域１ｂ，１ｃは前記絶縁膜３により覆われ
る。ただし、図４（Ａ）に示すように、絶縁膜３の表面
は前記ゲート電極２に対応した凹凸を有する。In the process of FIG. 4A, the MOS transistor
To embed the transistor 2Interlayer insulation consisting of
The film 3 is typically 50 nm formed by, for example, the CVD method.
It is deposited to a thickness of the order. As a result, the gate electrode and
And the diffusion regions 1b and 1c are covered with the insulating film 3.
It However, as shown in FIG. 4A, the surface of the insulating film 3
Has unevenness corresponding to the gate electrode 2.

【０００６】次に、図４（Ｂ）の工程で前記絶縁膜３の
表面が一様に研磨され、その結果絶縁膜３の表面が平坦
化される。さらに図５（Ｃ）の工程で、前記絶縁膜３が
レジスト（図示せず）を使ったフォトリソグラフィによ
りパターニングされ、その結果、前記絶縁膜３中に、前
記拡散領域１ｂに対応して、前記領域１ｂの表面を露出
するコンタクトホール３ａが形成される。さらに、図５
（Ｄ）の工程において、図５（Ｃ）の構造上にＷ，Ａ
ｌ，Ｃｕ等の金属あるいは合金よりなる導体層４を一様
な厚さに、例えばＣＶＤ法により堆積する。その結果、
前記導体層４は前記コンタクトホール３ａを埋め、前記
コンタクトホールにおいて拡散領域１ｂと電気的に接触
する。先にも説明したように、図５（Ｄ）の構造では前
記導体層４は前記コンタクトホール３ａを埋めるため、
導体層４表面上には前記コンタクトホール３ａに対応し
て凹部４ａが現れる。換言すると、前記導体層４の表面
には凹凸が生じる。Next, in the step of FIG. 4B, the surface of the insulating film 3 is uniformly polished, and as a result, the surface of the insulating film 3 is flattened. Further, in the step of FIG. 5C, the insulating film 3 is patterned by photolithography using a resist (not shown), and as a result, the insulating film 3 is formed in the insulating film 3 corresponding to the diffusion region 1b. Contact hole 3a exposing the surface of region 1b is formed. Furthermore, FIG.
In the process of (D), W and A are formed on the structure of FIG.
The conductor layer 4 made of a metal or alloy such as l or Cu is deposited to a uniform thickness by, for example, the CVD method. as a result,
The conductor layer 4 fills the contact hole 3a and makes electrical contact with the diffusion region 1b in the contact hole. As described above, in the structure of FIG. 5D, the conductor layer 4 fills the contact hole 3a,
A recess 4a appears on the surface of the conductor layer 4 corresponding to the contact hole 3a. In other words, the surface of the conductor layer 4 has irregularities.

【０００７】そこで、次に図６（Ｅ）の工程において前
記導体層４が一様に研磨され、図６（Ｅ）に示すように
絶縁膜３の表面が平坦な構造が得られる。かかる導体層
４の研磨は導体層４を構成する金属に対して選択的に作
用し、絶縁層３の上主面が露出した段階で停止する。そ
の結果前記コンタクトホール３ａを埋めるように、前記
拡散領域１ｂに接触する導体プラグ４ｂが形成される。
研磨による平坦化の結果、前記導体プラグ４ｂの上主面
は前記絶縁膜３の上主面と一致する。Then, in the next step of FIG. 6E, the conductor layer 4 is uniformly polished to obtain a structure in which the surface of the insulating film 3 is flat as shown in FIG. 6E. The polishing of the conductor layer 4 selectively acts on the metal forming the conductor layer 4, and stops when the upper main surface of the insulating layer 3 is exposed. As a result, a conductor plug 4b contacting the diffusion region 1b is formed so as to fill the contact hole 3a.
As a result of the flattening by polishing, the upper main surface of the conductor plug 4b coincides with the upper main surface of the insulating film 3.

【０００８】次に、図６（Ｆ）の工程において、前記平
坦化された図６（Ｅ）の構造上にＳｉＯ2 等よりなる別
の絶縁膜５が堆積され、図７（Ｇ）の工程でフォトリソ
グラフィ法によりパターニングされ、前記導体プラグ４
ｂを露出する溝５ａが形成される。さらに図７（Ｈ）の
工程において、Ｗ，Ａｌ，Ｃｕ等の金属あるいは合金よ
りなる別の導体層６が、前記図７（Ｇ）の構造上に堆積
され、その結果前記溝５ａに対応して導体層６には凹部
６ａが、図７（Ｈ）に示すように形成される。Next, in the step of FIG. 6 (F), another insulating film 5 made of SiO 2 or the like is deposited on the flattened structure of FIG. 6 (E), and then the step of FIG. 7 (G). Is patterned by photolithography with the conductive plug 4
A groove 5a exposing b is formed. Further, in the step of FIG. 7 (H), another conductor layer 6 made of a metal or alloy such as W, Al, Cu is deposited on the structure of FIG. 7 (G), so that it corresponds to the groove 5a. A recess 6a is formed in the conductor layer 6 as shown in FIG. 7 (H).

【０００９】さらに、図８（Ｉ）の工程において前記導
体層６を研磨し、図８（Ｉ）に示す平坦化された構造が
得られる。図８（Ｉ）の構造では、前記絶縁膜５中の溝
を前記導体層６の一部をなす導体パターン６ｂが埋め
る。さらにかかる構造上に、図８（Ｉ）の工程でさらに
別の絶縁層７を堆積する。かかる構造では、絶縁層７上
に必要に応じて様々な配線パターンを形成することがで
きる。Further, the conductor layer 6 is polished in the step of FIG. 8 (I) to obtain the flattened structure shown in FIG. 8 (I). In the structure of FIG. 8I, the groove in the insulating film 5 is filled with the conductor pattern 6b forming a part of the conductor layer 6. Further, another insulating layer 7 is deposited on the structure in the step of FIG. In such a structure, various wiring patterns can be formed on the insulating layer 7 as needed.

【００１０】[0010]

【発明が解決しようとする課題】上記の半導体装置の製
造工程において、図６（Ｅ）あるいは図８（Ｉ）の導体
層４あるいは６の研磨工程は、α−Ａｌ2 Ｏ3 よりなる
砥粒とＨ2 Ｏ2 等よりなる酸化剤との混合物よりなる研
磨剤を使い、ウレタン樹脂等の研磨布上において実行さ
れる。例えば、かかる研磨剤として、Rodel-Nitta 社よ
り商品名 MSW1000として供給されている研磨剤が一般的
に使用されている。かかる研磨工程では、酸化剤が前記
導体層を酸化させ、形成された酸化物が砥粒により研削
・除去される。In the above-described semiconductor device manufacturing process, the polishing step for the conductor layer 4 or 6 in FIG. 6 (E) or FIG. 8 (I) is performed by using abrasive grains made of α-Al 2 O 3. And an oxidizer such as H 2 O 2 and the like, and a polishing cloth made of urethane resin or the like. For example, as such an abrasive, the abrasive supplied by Rodel-Nitta under the trade name MSW1000 is generally used. In such a polishing step, the oxidizing agent oxidizes the conductor layer, and the formed oxide is ground and removed by the abrasive grains.

【００１１】例えば、Ｗよりなる導体層を前記α−Ａｌ
2 Ｏ3 砥粒により研磨する場合、Ｈ 2 Ｏ2 によりＷの酸
化物Ｗx Ｏy が形成され、かかる酸化物が前記砥粒によ
り削られる。ところが、かかる酸化剤を含んだ研磨剤を
Ｗ等の導体層の研磨に使用すると、酸化剤が前記導体層
凹部、例えば凹部４ａを埋める導体層４中に、前記導体
層４の堆積時に形成される継ぎ目部ないしシーム４ｃに
沿って侵入してしまい、その結果、かかる酸化剤の存在
下で実行される研磨工程により、前記シーム４ｃが、図
９（Ａ）に示す状態から図９（Ｂ）に示す状態へと、酸
化剤のエッチング作用により拡大してしまう問題が発生
する。その結果、導体プラグ４ｂの中央部には前記拡大
したシーム４ｃに対応して大きくまた深い凹部が形成さ
れてしまい、コンタクトホール３ａにおける拡散領域１
ｂと導体パターン６ｂとの接触が不確実になってしまう
問題点が生じる。かかる導体プラグに研磨時に形成され
る凹部は、特にコンタクトホール３ａの大きさが０．５
μｍあるいはそれ以下の高い集積密度を有する半導体装
置および集積回路において、特に深刻な信頼性の低下を
もたらす。前記シーム４ｃは、大きなアスペクト比を有
するコンタクトホールを導体層の堆積により埋める際
に、コンタクトホールの側壁面からコンタクトホール中
央部に向かって成長する導体層が、前記コンタクトホー
ル中央部で衝合することにより形成され、多量の欠陥を
含んでいると考えられる。このため、前記シーム４ｃ
は、Ｈ2 Ｏ2 等の酸化剤により、容易にエッチングを受
ける。For example, a conductor layer made of W is used as the α-Al.
2O3When polishing with abrasive grains, H 2O2By the acid of W
Compound WxOyAre formed, and such oxides are formed by the abrasive grains.
It is scraped. However, an abrasive containing such an oxidizing agent
When used for polishing a conductor layer such as W, the oxidant is
In the conductor layer 4 filling the recess, for example, the recess 4a, the conductor
The seam or seam 4c formed during the deposition of layer 4
The presence of such oxidants as a result
By the polishing step performed below, the seam 4c is
The state shown in FIG. 9 (A) changes to the state shown in FIG. 9 (B).
There is a problem that it expands due to the etching action of the agent
To do. As a result, the enlarged portion is formed in the central portion of the conductor plug 4b.
Large and deep recesses are formed corresponding to the seams 4c
The diffusion region 1 in the contact hole 3a.
The contact between b and the conductor pattern 6b becomes uncertain.
Problems arise. Formed on such a conductor plug during polishing
In particular, the size of the contact hole 3a is 0.5.
A semiconductor device having a high integration density of μm or less
Devices and integrated circuits suffer particularly serious reliability degradation.
Bring The seam 4c has a large aspect ratio.
When filling the contact hole by depositing the conductor layer
In the contact hole from the side wall surface of the contact hole
The conductor layer that grows toward the center is the contact hole.
Formed by abutting in the center of the
It is considered to include. Therefore, the seam 4c
Is H2O2Easily receives etching with an oxidizing agent such as
Kick

【００１２】そこで、本発明は、上記の課題を解決した
新規で有用な研磨剤、砥粒、研磨方法、および半導体装
置の製造方法を提供することを概括的目的とする。本発
明のより具体的な目的は、酸化剤を含まない研磨剤、あ
るいは酸化剤と併用する必要のない砥粒、あるいはこれ
らを使った研磨方法、あるいはこれらを使った半導体装
置の製造方法を提供することにある。Therefore, it is a general object of the present invention to provide a new and useful polishing agent, abrasive grains, polishing method, and semiconductor device manufacturing method that solve the above problems. A more specific object of the present invention is to provide an abrasive containing no oxidizing agent, or an abrasive grain that does not need to be used in combination with an oxidizing agent, a polishing method using these, or a method for manufacturing a semiconductor device using these. To do.

【００１３】[0013]

【課題を解決するための手段】そこで本発明は上記の課
題を、請求項１に記載したように、基板上に絶縁層を形
成する工程と；前記絶縁層に凹部を形成する工程と；前
記凹部を埋めるように、前記絶縁層上に導体層を堆積す
る工程と；前記導体層を、前記絶縁層が露出するまで研
磨する研磨工程とを含む半導体装置の製造方法におい
て、前記研磨工程を、ＭｎＯ２を砥粒として含む研磨剤
を使って実行することを特徴とする半導体装置の製造方
法により、または請求項２に記載したように、さらに、
前記基板を酸で洗浄する洗浄工程を含み、前記洗浄工程
は前記研磨工程の後で実行されることを特徴とする請求
項１記載の半導体装置の製造方法により、または請求項
３に記載したように、前記洗浄工程は、前記酸と酸化剤
との混合液により実行されることを特徴とする請求項２
記載の半導体装置の製造方法により解決する。The The present invention is the above object, according to an aspect of, as described in 請 Motomeko 1, step a to form an insulating layer on a substrate; forming a recess in said insulating layer; In the method for manufacturing a semiconductor device, the method further includes: a step of depositing a conductor layer on the insulating layer so as to fill the recess; and a step of polishing the conductor layer until the insulating layer is exposed. , MnO 2 as an abrasive grain is used for the method of manufacturing a semiconductor device, or as described in claim 2 , further comprising:
It includes a cleaning step of cleaning the substrate with an acid, such that the cleaning process has been described by the method of manufacturing a semiconductor device according to claim 1, characterized in that it is performed after the polishing step, or to claim 3 3. The cleaning process according to claim 2 , wherein the cleaning process is performed with a mixed solution of the acid and the oxidizing agent.
This is solved by the method of manufacturing a semiconductor device described above.

【００１４】請求項１の発明によれば、導体層の研磨工
程おいてＭｎＯ２を砥粒として使うことにより、ＭｎＯ
２中の酸素が導体層を構成する金属を酸化させる。その
結果、このようにして生成した反応生成物が、反応の結
果還元されたＭｎ２Ｏ３あるいは未反応のＭｎＯ２によ
り研削されるものと考えられる。例えば、導体層がＷで
構成されている場合、研磨時に以下の反応 ＭｎＯ２＋Ｗ→Ｍｎ２Ｏ３＋ＷｘＯｙ が砥粒と導体層との間に生じ、生成したＷｘＯｙが研磨
布および未反応のＭｎＯ2により研削・除去されるもの
と考えられる。本発明では、酸化作用を行うＭｎＯ２が
固体であり、Ｈ２Ｏ２等の液体状の酸化剤は研磨時に使
用されないため、酸化剤がシームに侵入することがな
い。このため、図９（Ｂ）に示したシームのような、絶
縁体中に埋め込まれた微細な導体パターン中の欠陥部が
研磨の際にエッチングされてしまう問題が生じることが
なく、信頼性の高いコンタクトを形成することができ
る。According to the first aspect of the present invention, by using MnO 2 as abrasive grains in the step of polishing the conductor layer, MnO 2 can be obtained.
Oxygen in 2 oxidizes the metal forming the conductor layer. As a result, it is considered that the reaction product thus produced is ground by Mn 2 O 3 reduced as a result of the reaction or unreacted MnO 2 . For example, when the conductor layer is composed of W, the following reaction MnO 2 + W → Mn 2 O 3 + W x O y occurs between the abrasive grains and the conductor layer during polishing, and the generated W x O y is polished. It is considered to be ground and removed by the cloth and unreacted MnO 2 . In the present invention, MnO 2 that performs an oxidizing action is solid, and a liquid oxidizing agent such as H 2 O 2 is not used during polishing, so the oxidizing agent does not enter the seam. Therefore, there is no problem that a defective portion in a fine conductor pattern embedded in an insulator is etched during polishing, such as a seam shown in FIG. High contacts can be formed.

【００１５】また本発明の特徴によれば、Ｍｎ砥粒の粒
径を１０μｍ以下に設定することにより、絶縁体中に埋
め込まれた微細な導体パターン中に形成される凹部の大
きさを最小化することができる。請求項１記載の本発明
の特徴によれば、本発明は半導体装置の配線パターンに
使われる導体の研磨に効果的であり、半導体装置の製造
に有用である。According to another feature of the present invention, the size of the recess formed in the fine conductor pattern embedded in the insulator is minimized by setting the grain size of the Mn abrasive grains to 10 μm or less. can do. According to the features of the present invention described in claim 1 , the present invention is effective for polishing a conductor used for a wiring pattern of a semiconductor device, and is useful for manufacturing a semiconductor device.

【００１６】請求項２記載の本発明の特徴によれば、研
磨工程の後、基板を酸、例えばＨＣｌ、Ｈ２ＳＯ４ 、Ｈ
ＮＯ３あるいはＨＦで洗浄することにより、ＭｎＯ
２が、例えば反応ＭｎＯ２＋２ＨＣｌ＋Ｈ２Ｏ２→Ｍｎ
Ｃｌ２＋２Ｈ２Ｏ＋Ｏ２、あるいはＭｎＯ２＋２ＨＮＯ
３＋Ｈ２Ｏ２→Ｍｎ（ＮＯ３）２＋Ｈ２Ｏ＋Ｏ２、ある
いはＭｎＯ２＋Ｈ２ＳＯ４＋Ｈ２Ｏ２→ＭｎＳＯ４＋２
Ｈ２Ｏ＋Ｏ２、あるいはＭｎＯ２＋２ＨＦ＋Ｈ２Ｏ２→
ＭｎＦ２＋２Ｈ２Ｏ＋Ｏ２により酸に溶解し、その結果
基板のＭｎによる汚染および残留パーティクル量を最小
化することができる。ただし、上記反応において、反応
生成物ＭｎＣｌ２，Ｍｎ（ＮＯ３）２，ＭｎＳＯ４，Ｍ
ｎＦ２はすべて水溶性化合物である。また、上記の洗浄
工程では液体状の酸化剤であるＨ２Ｏ２が使われるが、
研磨工程と異なり、洗浄工程におけるＨ２Ｏ２の濃度は
２％以下（研磨工程の１／２５）であり、また洗浄工程
は短時間で終了するため、また砥粒による研削がなされ
ないため、かかる酸化剤による導電性プラグのシームの
侵食は実質的に生じない。According to a feature of the present invention as set forth in claim 2 , after the polishing step, the substrate is treated with an acid such as HCl, H 2 SO 4 , H 2.
By cleaning with NO 3 or HF, MnO
2 is, for example, the reaction MnO 2 + 2HCl + H 2 O 2 → Mn
Cl 2 + 2H 2 O + O 2 or MnO 2 + 2HNO
3 + H 2 O 2 → Mn (NO 3 ) 2 + H 2 O + O 2 or MnO 2 + H 2 SO 4 + H 2 O 2 → MnSO 4 +2
H 2 O + O 2 or MnO 2 + 2HF + H 2 O 2 →
MnF 2 + 2H 2 O + O 2 dissolves in an acid, and as a result, contamination of the substrate by Mn and the amount of residual particles can be minimized. However, in the above reaction, the reaction products MnCl 2 , Mn (NO 3 ) 2 , MnSO 4 , M
All nF 2 are water-soluble compounds. In addition, in the above cleaning process, H 2 O 2 which is a liquid oxidant is used.
Unlike the polishing step, the concentration of H 2 O 2 in the cleaning step is 2% or less (1/25 of that in the polishing step), and the cleaning step is completed in a short time, and since grinding with abrasive grains is not performed, Substantially no erosion of the seam of the conductive plug by such an oxidant occurs.

【００１７】請求項３記載の本発明の特徴によれば、洗
浄工程で、基板洗浄を酸と酸化剤の混合液により実行す
ることにより、洗浄効率を向上させることができる。こ
のため、本発明により、高い歩留りで半導体装置を製造
することができる。研磨工程と異なり、洗浄工程で酸化
剤を使用してもコンタクトホールを埋める導体プラグが
侵食されることはほとんどない。このため、かかる洗浄
工程の結果得られた半導体装置の信頼性が低下すること
はない。According to the third aspect of the present invention, the cleaning efficiency can be improved by cleaning the substrate with the mixed solution of the acid and the oxidizing agent in the cleaning step. Therefore, according to the present invention, semiconductor devices can be manufactured with high yield. Unlike the polishing process, even if an oxidizer is used in the cleaning process, the conductor plug filling the contact hole is hardly eroded. Therefore, the reliability of the semiconductor device obtained as a result of the cleaning process does not deteriorate.

【００１８】[0018]

【発明の実施の形態】以下、本発明を、半導体装置の製
造に適用した場合につき、実施例にもとづいて説明す
る。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the case where the present invention is applied to the manufacture of a semiconductor device will be described based on Examples.

【００１９】[0019]

【実施例】図１は本発明の一実施例を説明する図であ
る。図１を参照するに、図示の構造は本発明の研磨剤の
効果を検証するために作成した試験片を示し、Ｓｉ基板
１１上に約５０ｎｍの厚さでＣＶＤ法により堆積された
ＳｉＯ2 層１２を含む。層１２には複数のコンタクトホ
ール１２ａおよび１２ｂが様々な内径Ｄ1 ，Ｄ2 で形成
されており、かかるコンタクトホール１２ａ，１２ｂを
埋めるようにＷ層１３が約５０ｎｍの厚さで堆積され
る。Ｗ層１３は例えばＣＶＤ法により堆積され、その表
面に、前記コンタクトホール１２ａ，１２ｂに対応して
凹部１３ａが形成される。さらに、コンタクトホール１
２ａあるいは１２ｂを埋めるＷプラグ中には、Ｗ層１３
の堆積に伴い、シーム１３ｂが形成される。先にも説明
したように、かかるシーム１３ｂは、Ｗ層１３がコンタ
クトホール１２ａ，１２ｂの側壁から内方に成長する際
に、Ｗ層１３の表面が収斂・衝合することにより形成さ
れ、多数の欠陥を含んでいる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an embodiment of the present invention. Referring to FIG. 1, the structure shown is a test piece prepared for verifying the effect of the polishing agent of the present invention. A SiO 2 layer deposited on a Si substrate 11 to a thickness of about 50 nm by a CVD method. Including 12. A plurality of contact holes 12a and 12b are formed in the layer 12 with various inner diameters D 1 and D 2 , and a W layer 13 is deposited to a thickness of about 50 nm so as to fill the contact holes 12a and 12b. The W layer 13 is deposited by, for example, a CVD method, and a recess 13a is formed on the surface thereof so as to correspond to the contact holes 12a and 12b. Furthermore, contact hole 1
In the W plug filling 2a or 12b, the W layer 13
The seam 13b is formed in accordance with the accumulation of. As described above, the seam 13b is formed by the surface of the W layer 13 converging and abutting when the W layer 13 grows inward from the side walls of the contact holes 12a and 12b. Including defects.

【００２０】以下、かかる試験片について、本発明者が
行った実験結果を説明する。本実験では、前記試験片上
のＷ層１３表面を、様々な粒径のＭｎＯ2 とＨ2 Ｏの混
合物よりなる研磨剤により研磨した。ただし、研磨剤中
のＭｎＯ2 の割合は約２０重量％程度に設定し、研磨
は、Rodel-Nitta 社から商品名SUBA400 として供給され
るウレタン樹脂研磨布を使って行った。また、研磨の際
の圧力は２００〜７００g/cm2 の範囲に設定した。The results of experiments conducted by the inventor of the test piece will be described below. In this experiment, the surface of the W layer 13 on the test piece was polished with an abrasive made of a mixture of MnO 2 and H 2 O having various particle sizes. However, the proportion of MnO 2 in the polishing agent was set to about 20% by weight, and polishing was performed using a urethane resin polishing cloth supplied under the trade name SUBA400 from Rodel-Nitta. The pressure during polishing was set in the range of 200 to 700 g / cm 2 .

【００２１】さらに、比較のため、従来の研磨剤を使っ
て、同一の条件で図１の試験片のＷ層１３を研磨した。
使用した従来の研磨剤はRodel-Nitta 社の商品番号 MSW
1000であり、α−Ａｌ2 Ｏ3 よりなる砥粒とフタル酸カ
リウムとを含む。ただし、この従来例の場合には、前記
研磨剤をＨ2 Ｏ2 と混合して使用した。Further, for comparison, the conventional polishing agent was used to polish the W layer 13 of the test piece of FIG. 1 under the same conditions.
The conventional abrasive used is Rodel-Nitta product number MSW.
1000, including abrasive grains made of α-Al2 O3 and potassium phthalate. However, in the case of this conventional example, the abrasive was mixed with H 2 O 2 and used.

【００２２】また、本実験では、研磨剤の効果の評価
は、図１の試験片においてＳｉＯ2 層１２上のＷ層１３
が完全に除去された後さらに２分間オーバーエッチング
を行い、その後で図９（Ｂ）に示すような、コンタクト
ホール３ａあるいは１２ｂを埋める導体プラグ中に形成
された凹部の深さを、試験片の断面をＳＥＭで観察する
ことにより求めることにより行った。In this experiment, the effect of the abrasive was evaluated by the W layer 13 on the SiO2 layer 12 in the test piece of FIG.
Is completely removed, overetching is further performed for 2 minutes, and then the depth of the recess formed in the conductor plug filling the contact hole 3a or 12b as shown in FIG. It was performed by observing the cross section by SEM.

【００２３】図２は、圧力を３５０g/cm2 に設定し、パ
ターンの無いＳｉＯ2 （図中○で示す）およびＣＶＤ法
で堆積したＷ層（図中●で示す）の各々の研磨速度を示
す。図２よりわかるように、粒子系が２μｍ以上になる
と、ＳｉＯ2 の研磨速度が上昇し、Ｗの研磨速度が低下
しはじめる。Ｗの研磨速度が大きいと、研磨のスループ
ットが向上する。また、ＳｉＯ2 の研磨速度は小さい方
が、ストッパ効果が高いことを意味する。従ってＳｉＯ
2 の研磨速度は小さく、Ｗの研磨速度は大きいほうが良
い。図２より、粒径は１０μｍ以下が好ましいことがわ
かる。FIG. 2 shows the polishing rates of the SiO2 (shown by circles in the figure) without a pattern and the W layer (shown by ● in the figure) deposited by the CVD method with the pressure set at 350 g / cm 2 . . As can be seen from FIG. 2, when the particle size is 2 μm or more, the polishing rate of SiO 2 increases and the polishing rate of W begins to decrease. When the polishing rate of W is high, the polishing throughput is improved. Further, the smaller the polishing rate of SiO 2, the higher the stopper effect. Therefore SiO
It is better that the polishing rate of 2 is low and the polishing rate of W is high. It can be seen from FIG. 2 that the particle size is preferably 10 μm or less.

【００２４】プラグの埋め込みを想定すると、粒子径が
大きい方が、プラグへ研磨剤が入り込まないためよいと
予想できる。しかし、図２に示す通り、実験にほり、粒
子径が１０μｍ以下の方がよいことがわかった。上記の
ことから、本発明による研磨剤は、図４〜図８に説明し
た半導体装置の製造において、例えば図６（Ｅ）の工程
あるいは図８（Ｉ）の工程で導体層４あるいは６を絶縁
膜上から選択的に研磨・除去するのに有効であることが
わかる。先に説明したように、本発明によるＭｎＯ2 砥
粒を含んだ研磨剤は、粒径が１０μｍよりも小さい場
合、Ｗに対して選択的に作用するため、図６（Ｅ）の工
程において、導体層４をＷ層とした場合、層４下のＳｉ
Ｏ2 層３が露出した時点で研磨は自動的に停止する。Assuming plug embedding, it can be expected that the larger the particle size, the better because the abrasive will not enter the plug. However, as shown in FIG. 2, it was found by experiment that it was better that the particle size was 10 μm or less. From the above, the abrasive according to the present invention insulates the conductor layer 4 or 6 in the step of FIG. 6E or the step of FIG. 8I in the manufacture of the semiconductor device described in FIGS. It can be seen that it is effective in selectively polishing and removing from the film. As described above, the abrasive containing MnO 2 abrasive grains according to the present invention selectively acts on W when the grain size is smaller than 10 μm, so that in the step of FIG. When the conductor layer 4 is a W layer, Si under the layer 4
Polishing is automatically stopped when the O 2 layer 3 is exposed.

【００２５】一方、本発明の研磨剤を半導体装置の製造
に使う場合、研磨剤による金属汚染を回避するため、研
磨工程の後でＭｎ砥粒を含む研磨剤を、洗浄により、基
板から実質的に完全に除去する必要がある。以下、Ｍｎ
Ｏ2 砥粒を使った研磨工程の後で実行されるかかる洗浄
工程を説明する。On the other hand, when the polishing agent of the present invention is used for manufacturing a semiconductor device, in order to avoid metal contamination by the polishing agent, the polishing agent containing Mn abrasive grains is substantially washed from the substrate after the polishing step by washing. Need to be completely removed. Below, Mn
The cleaning process performed after the polishing process using O 2 abrasive grains will be described.

【００２６】本発明では残留しているＭｎＯ2 砥粒を、
様々な酸溶液中で洗浄することにより溶解し、除去す
る。本発明の発明者は、かかる洗浄処理について、以下
の様々な酸溶液を使って実験したところ、良好な結果を
得た。以下、本発明者が行った洗浄処理の実験について
説明する。In the present invention, the residual MnO 2 abrasive grains are
Dissolve and remove by washing in various acid solutions. The inventor of the present invention has conducted favorable experiments on the cleaning treatment using various acid solutions described below. Hereinafter, the experiment of the cleaning process performed by the present inventor will be described.

【００２７】本実験では、前記研磨処理を行った試験片
を、 （Ａ） ＨＣｌ＋Ｈ2 Ｏ2 ＋Ｈ2 Ｏ （１：１：４８体
積比）； （Ｂ） ＨＮＯ3 ＋Ｈ2 Ｏ2 ＋Ｈ2 Ｏ （１：１：４８
体積比）； （Ｃ） Ｈ2 ＳＯ4 ＋Ｈ2 Ｏ2 ＋Ｈ2 Ｏ （１：１：４
８）；および （Ｄ） ＨＦ＋Ｈ2 Ｏ2 ＋Ｈ2 Ｏ（１：１：４８） 中でそれぞれ３０秒間処理し、引き続きスクラバ処理を
行った。このようにして得た試料をそれぞれ試料Ａ，試
料Ｂ，試料Ｃ，試料Ｄとする。かかる試料Ａ〜Ｄでは、
以下の反応 ＭｎＯ2 ＋２ＨＣｌ＋Ｈ2 Ｏ2 →ＭｎＣｌ2 ＋２Ｈ2 Ｏ＋Ｏ2 ＭｎＯ2 ＋２ＨＮＯ3 ＋Ｈ2 Ｏ2 →Ｍｎ（ＮＯ3 ）2 ＋Ｈ2 Ｏ＋Ｏ2 ＭｎＯ2 ＋Ｈ2 ＳＯ4 ＋Ｈ2 Ｏ2 →ＭｎＳＯ4 ＋２Ｈ2 Ｏ＋Ｏ2 ＭｎＯ2 ＋２ＨＦ＋Ｈ2 Ｏ2 →ＭｎＦ2 ＋２Ｈ2 Ｏ＋Ｏ2 がそれぞれ生じ、水溶性の反応生成物ＭｎＣｌ2 ，Ｍｎ
（ＮＯ3 ）2 ，ＭｎＳＯ 4 ，ＭｎＦ2 が形成されると予
想される。In this experiment, the test piece subjected to the polishing treatment was used.
To (A) HCl + H2O2+ H2O (1: 1: 48 bodies
Product ratio); (B) HNO3+ H2O2+ H2O (1: 1: 48
Volume ratio); (C) H2SOFour+ H2O2+ H2O (1: 1: 4
8); and (D) HF + H2O2+ H2O (1: 1: 48) Each for 30 seconds, then scrubber treatment
went. The samples thus obtained are referred to as sample A and test, respectively.
Material B, Sample C, and Sample D. In such samples A to D,
The following reaction   MnO2+ 2HCl + H2O2→ MnCl2+ 2H2O + O2   MnO2+ 2HNO3+ H2O2→ Mn (NO3)2+ H2O + O2   MnO2+ H2SOFour+ H2O2→ MnSOFour+ 2H2O + O2   MnO2+ 2HF + H2O2→ MnF2+ 2H2O + O2 And a water-soluble reaction product MnCl2, Mn
(NO3)2, MnSO Four, MnF2Is formed
I am thought.

【００２８】また、比較のため、前記試験片のうち、前
記ＭｎＯ2 砥粒を含む研磨剤で研磨処理したものを酸処
理せずに直接スクラバ処理した試料、および前記α−Ａ
ｌ2Ｏ3 研磨剤（Rodel-Nitta MSW1000)で研磨したもの
を直接スクラバ処理した試料を作成し、これらの試料を
それぞれ試料Ｅおよび試料Ｆとした。For comparison, among the test pieces, a sample which was polished with an abrasive containing MnO2 abrasive grains was directly scrubbed without acid treatment, and the α-A.
Samples obtained by directly scrubbing those polished with an l 2 O 3 abrasive (Rodel-Nitta MSW1000) were designated as sample E and sample F, respectively.

【００２９】このようにして得た試料Ａ〜Ｆについて、
いずれも０．５％の濃度のＨＦに２０秒間浸漬した後、
金属汚染および残留粒子を評価した。その結果を以下の
表に示す。With respect to the samples A to F thus obtained,
After soaking in HF with a concentration of 0.5% for 20 seconds,
Metal contamination and residual particles were evaluated. The results are shown in the table below.

【００３０】[0030]

【表１】 [Table 1]

【００３１】このように、本発明の洗浄工程を適用した
試料Ａ〜Ｄでは、いずれもＭｎによる汚染は無視できる
程度であり、また残留粒子数も従来のもの（試料Ｆ）よ
りも少ないことがわかる。また、前記試料Ａ〜Ｄでは、
酸洗浄を省略したもの（試料Ｅ）に対してもＭｎによる
金属汚染が減少していることがわかる。この結果は、洗
浄により前記化学式で示した反応が生じ、残留ＭｎＯ2
が溶解されることを示している。As described above, in each of the samples A to D to which the cleaning process of the present invention is applied, the contamination by Mn is negligible, and the number of residual particles is smaller than that of the conventional sample (sample F). Recognize. Further, in the samples A to D,
It can be seen that the metal contamination due to Mn is reduced even in the case where the acid cleaning is omitted (Sample E). This result indicates that the reaction represented by the above chemical formula occurs due to the washing and residual MnO 2
Are dissolved.

【００３２】以上の研磨工程において、ＭｎＯ2 を砥粒
とする本発明の研磨剤が有効な被研磨物は、前記Ｗ層に
限定されるものではなく、ＡｌやＣｕ等の金属あるいは
合金も含まれる。図３は、本発明による研磨工程を含ん
だ半導体装置の製造工程を示すフローチャートである。In the above polishing step, the object to be polished, in which the polishing agent of the present invention containing MnO 2 as abrasive grains is effective, is not limited to the W layer, but includes metals or alloys such as Al and Cu. Be done. FIG. 3 is a flowchart showing a manufacturing process of a semiconductor device including a polishing process according to the present invention.

【００３３】図３を参照するに、工程Ｓ１において基板
あるいはウェハ上にデバイス構造が形成され、工程Ｓ２
において、かかるデバイス構造を覆うように絶縁膜が堆
積される。この絶縁膜は、例えば図４（Ｂ）に示すよう
にＣＶＤ法で堆積したＳｉＯ 2 膜でもよいが、例えばＢ
ＳＧやＢＰＳＧ等の他の組成の絶縁膜、あるいはＳＯＧ
等、他の方法で堆積したＳｉＯ2 膜でもよい。Referring to FIG. 3, in step S1, the substrate
Alternatively, a device structure is formed on the wafer, and step S2
In this case, an insulating film is deposited to cover such device structure.
Is piled up. This insulating film is, for example, as shown in FIG.
Deposited on the surface by CVD method 2It may be a membrane, but for example B
Insulating film of other composition such as SG or BPSG, or SOG
SiO deposited by other methods such as2It may be a membrane.

【００３４】さらに工程Ｓ３で、先に工程Ｓ２で堆積し
た絶縁膜をパターニングし、絶縁膜中に、図５（Ｃ）の
コンタクトホール３ａに相当するコンタクトホールある
いは溝等の凹パターンを形成する。さらに、工程Ｓ４
で、かかる絶縁膜上に、前記凹パターンを埋めるように
導体層４に対応する導体層を堆積する。ここで導体層は
Ｗ以外に、半導体集積回路で一般的に使われているＡ
ｌ，Ｃｕ等の金属あるいは合金であってもよい。In step S3, the insulating film previously deposited in step S2 is patterned to form a concave pattern such as a contact hole or a groove corresponding to the contact hole 3a in FIG. 5C in the insulating film. Further, step S4
Then, a conductor layer corresponding to the conductor layer 4 is deposited on the insulating film so as to fill the concave pattern. Here, the conductor layer is A, which is generally used in semiconductor integrated circuits, in addition to W.
It may be a metal or alloy such as l or Cu.

【００３５】次に、工程Ｓ５において、前記導体層を、
本発明によるＭｎＯ2 を砥粒として含む研磨剤により、
通常の研磨布上で研磨する。この研磨工程では、ＭｎＯ
2 砥粒はＨ2 Ｏ等の溶媒中に懸濁して使用されるが、本
発明では前記溶媒に酸化剤を添加することはしない。そ
の結果、研磨の際に前記凹パターンを埋めている導体層
中に形成されているシームが酸化剤に侵食されることが
なく、また砥粒により研磨されてしまうことがない。Next, in step S5, the conductor layer is
With the abrasive containing MnO 2 according to the present invention as abrasive grains,
Polish on a normal polishing cloth. In this polishing process, MnO
The 2 abrasive grains are used by suspending them in a solvent such as H 2 O, but in the present invention, an oxidizing agent is not added to the solvent. As a result, at the time of polishing, the seam formed in the conductor layer filling the concave pattern is not eroded by the oxidizing agent and is not polished by the abrasive grains.

【００３６】次に、工程Ｓ６において、前記工程Ｓ５で
研磨した基板を酸中で処理し、残留しているＭｎＯ2 を
酸に溶解させて除去する。この工程では、先に説明した
ＨＣｌ，Ｈ2 ＳＯ4 ，ＨＮＯ3 ，ＨＦ等の酸に酸化剤を
混合し、残留しているＭｎＯ 2 を溶解・除去する。その
結果、砥粒として使ったＭｎＯ2 による基板の金属汚染
が除去され、さらに残留粒子数が減少する。Next, in step S6, in step S5
Treat the polished substrate in acid to remove residual MnO2
Dissolve in acid and remove. In this process,
HCl, H2SOFour, HNO3, HF and other acids with oxidants
MnO remaining after mixing 2Is dissolved and removed. That
As a result, MnO used as abrasive grains2Substrate metal contamination by
Are removed, and the number of residual particles is further reduced.

【００３７】さらに、工程Ｓ６の後、このようにして得
られた構造上にさらに別の構造を次の工程で形成しても
よい。工程Ｓ６で得られた構造は、清浄で平坦な上主面
を有するため、その上に容易に次の構造を形成すること
ができる。また、本発明による、ＭｎＯ2 よりなる砥
粒，かかる砥粒を含む研磨剤、およびかかる研磨剤を使
った研磨方法は、半導体装置の製造に限定されるもので
はなく、一般の研磨工程にも有用である。Further, after step S6, another structure may be formed in the next step on the structure thus obtained. Since the structure obtained in step S6 has a clean and flat upper main surface, the next structure can be easily formed thereon. Further, the abrasive grains made of MnO 2 , the polishing agent containing the abrasive grains, and the polishing method using the polishing agent according to the present invention are not limited to the manufacture of semiconductor devices, and can be applied to general polishing steps. It is useful.

【００３８】以上、本発明を好ましい実施例にもとづい
て説明したが、本発明はかかる実施例に限定されるもの
ではなく、その要旨内において様々な変形・変更が可能
である。Although the present invention has been described above based on the preferred embodiments, the present invention is not limited to such embodiments, and various modifications and changes can be made within the scope thereof.

【００３９】[0039]

【発明の効果】請求項１の発明によれば、従来の研磨剤
で砥粒と併用される液体の酸化剤が本発明では使われな
いため、かかる酸化剤が研磨工程で導体プラグのシーム
等、コンタクトを形成する導体パターン中の欠陥部に侵
入することがない。このため、信頼性の高いコンタクト
を形成することができる。According to the first aspect of the present invention, since a liquid oxidizer that is used together with abrasive grains in the conventional abrasive is not used in the present invention, such an oxidizer is used in the polishing step such as the seam of the conductor plug. , Does not penetrate into the defective portion in the conductor pattern forming the contact. Therefore, a highly reliable contact can be formed.

【００４０】また本発明の特徴によれば、Ｍｎ砥粒の粒
径を１０μｍ以下に設定することにより、絶縁層中に埋
め込まれた微細な導体パターン中に研磨の際に形成され
る凹部の大きさを最小化することができる。請求項１記
載の本発明の特徴によれば、本発明は半導体装置の配線
パターンに使われる導体の研磨に効果的であり、半導体
装置の製造に有用である。Further, according to a feature of the present invention, by setting the grain size of the Mn abrasive grains to 10 μm or less, the size of the recesses formed during polishing in the fine conductor pattern embedded in the insulating layer. Can be minimized. According to the features of the present invention described in claim 1 , the present invention is effective for polishing a conductor used for a wiring pattern of a semiconductor device, and is useful for manufacturing a semiconductor device.

【００４１】請求項２記載の本発明の特徴によれば、研
磨工程の後、基板を酸、例えばＨＣｌ、Ｈ２ＳＯ４ 、Ｈ
ＮＯ３あるいはＨＦで洗浄することにより、結果基板の
Ｍｎによる汚染および残留パーティクル量を最小化する
ことができる。請求項３記載の本発明の特徴によれば、
洗浄工程で、基板洗浄を酸と酸化剤の混合液により実行
することにより、洗浄効率を向上させることができ、そ
の結果高い歩留りで半導体装置を製造することができ
る。研磨工程と異なり、洗浄工程で酸化剤を使用しても
コンタクトホールを埋める導体プラグが侵食されること
はほとんどない。このため、かかる洗浄工程の結果得ら
れた半導体装置の信頼性が低下することはない。According to a feature of the present invention as defined in claim 2 , after the polishing step, the substrate is treated with an acid such as HCl, H 2 SO 4 , H 2.
By cleaning with NO 3 or HF, the contamination of Mn on the resultant substrate and the amount of residual particles can be minimized. According to the features of the invention as set forth in claim 3 ,
By cleaning the substrate in the cleaning step with a mixed solution of an acid and an oxidizing agent, cleaning efficiency can be improved, and as a result, semiconductor devices can be manufactured with a high yield. Unlike the polishing process, even if an oxidizer is used in the cleaning process, the conductor plug filling the contact hole is hardly eroded. Therefore, the reliability of the semiconductor device obtained as a result of the cleaning process does not deteriorate.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明で使った試験片の構成を示す図である。FIG. 1 is a diagram showing a configuration of a test piece used in the present invention.

【図２】本発明の効果を示す図である。FIG. 2 is a diagram showing an effect of the present invention.

【図３】本発明の研磨工程を使った半導体装置の製造方
法を示す図である。FIG. 3 is a diagram showing a method for manufacturing a semiconductor device using the polishing process of the present invention.

【図４】（Ａ），（Ｂ）は従来の半導体装置の製造工程
を示す図（その一）である。4A and 4B are views (No. 1) showing a manufacturing process of a conventional semiconductor device.

【図５】（Ｃ），（Ｄ）は従来の半導体装置の製造工程
を示す図（その二）である。5 (C) and 5 (D) are views showing a conventional manufacturing process of a semiconductor device (No. 2).

【図６】（Ｅ），（Ｆ）は従来の半導体装置の製造工程
を示す図（その三）である。6 (E) and 6 (F) are views (No. 3) showing a conventional manufacturing process of a semiconductor device.

【図７】（Ｇ），（Ｈ）は従来の半導体装置の製造工程
を示す図（その四）である。7 (G) and 7 (H) are views showing a conventional semiconductor device manufacturing process (No. 4).

【図８】（Ｉ），（Ｊ）は従来の半導体装置の製造工程
を示す図（その五）である。8 (I) and 8 (J) are views showing a conventional semiconductor device manufacturing process (No. 5).

【図９】（Ａ），（Ｂ）は、従来の研磨工程で発生して
いた問題点を示す図である。9 (A) and 9 (B) are views showing a problem that has occurred in a conventional polishing process.

【符号の説明】[Explanation of symbols]

１，１１ 基板 １ａ フィールド酸化膜 １ｂ，１ｃ 拡散領域 １ｄ チャネル領域 ２ ゲート電極 ２ａ，２ｂ ゲート側壁絶縁膜 ３，５，７，１２ 絶縁膜 ３ａ コンタクトホール ４，６ 導体層 ４ａ 凹部 ４ｂ 導体プラグ ４ｃ シーム ５ａ 溝 ６ａ 凹部 ６ｂ 導体パターン １２ａ コンタクトホール １３ａ 導体パターン凹部 １３ｂ シーム 1,11 substrate 1a Field oxide film 1b, 1c diffusion area 1d channel region 2 Gate electrode 2a, 2b Gate sidewall insulating film 3,5,7,12 Insulation film 3a Contact hole 4,6 Conductor layer 4a recess 4b conductor plug 4c seam 5a groove 6a recess 6b Conductor pattern 12a contact hole 13a Conductor pattern recess 13b seam

フロントページの続き (72)発明者 鈴木 隣太郎 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 塙 健三 埼玉県上尾市原市1380−１ (72)発明者 植田 成生 埼玉県北足立郡吹上町富士見４−12−25 (56)参考文献 特開 平５−156238（ＪＰ，Ａ) 特開 平７−86216（ＪＰ，Ａ) 特開 昭48−34396（ＪＰ，Ａ) 特開 昭64−87930（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/304 B24D 3/00 Front page continued (72) Inventor Neitaro Suzuki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Kenzo Hanawa 1380-1, Ageo-shi Hara, Saitama Prefecture (72) Inventor Seisei Ueda Saitama 4-12-25 Fujimi, Fukiage-machi, Kitadachi-gun, Japan (56) References JP-A-5-156238 (JP, A) JP-A-7-86216 (JP, A) JP-A-48-34396 (JP, A) JP-A-64-87930 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/304 B24D 3/00

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 基板上に絶縁層を形成する工程と、 前記絶縁層に凹部を形成する工程と、 前記凹部を埋めるように、前記絶縁層上に導体層を堆積
する工程と、 前記導体層を、前記絶縁層が露出するまで研磨する研磨
工程とを含む半導体装置の製造方法において、 前記研磨工程を、ＭｎＯ２を砥粒として含む研磨剤を使
って実行することを特徴とする半導体装置の製造方法。And 1. A process for forming an insulating layer on a substrate, forming a recess in the insulating layer, so as to fill the recess, depositing a conductive layer on the insulating layer, the conductor layer And a polishing step of polishing the insulating layer until it is exposed, wherein the polishing step is performed using an abrasive containing MnO 2 as abrasive grains. Production method. 【請求項２】 さらに、前記基板を酸で洗浄する洗浄工
程を含み、前記洗浄工程は前記研磨工程の後で実行され
ることを特徴とする請求項１記載の半導体装置の製造方
法。Wherein further comprising a cleaning step of cleaning the substrate with an acid, wherein the washing step is a method of manufacturing a semiconductor device according to claim 1, characterized in that it is performed after the polishing step. 【請求項３】 前記洗浄工程は、前記酸と酸化剤との混
合液により実行されることを特徴とする請求項２記載の
半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2 , wherein the cleaning step is performed with a mixed liquid of the acid and the oxidizing agent.
JP16905795A 1995-07-04 1995-07-04 Method for manufacturing semiconductor device Expired - Fee Related JP3529902B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP16905795A JP3529902B2 (en) 1995-07-04 1995-07-04 Method for manufacturing semiconductor device
TW085108035A TW317003B (en) 1995-07-04 1996-07-03 Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry
KR1019960027065A KR100251057B1 (en) 1995-07-04 1996-07-04 Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry
US08/884,165 US6159858A (en) 1995-07-04 1997-06-27 Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16905795A JP3529902B2 (en) 1995-07-04 1995-07-04 Method for manufacturing semiconductor device

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Publication Number Publication Date
JPH0922888A JPH0922888A (en) 1997-01-21
JP3529902B2 true JP3529902B2 (en) 2004-05-24

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KR (1) KR100251057B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615691B1 (en) 1998-12-18 2006-08-25 도소 가부시키가이샤 A member for polishing, surface plate for polishing and polishing method using the same
KR100637887B1 (en) 1998-12-28 2006-10-23 도소 가부시키가이샤 Molded body for polishing, surface plate for polishing and polishing method using the same
US6379223B1 (en) * 1999-11-29 2002-04-30 Applied Materials, Inc. Method and apparatus for electrochemical-mechanical planarization
KR100444307B1 (en) * 2001-12-28 2004-08-16 주식회사 하이닉스반도체 Method for manufacturing of metal line contact plug of semiconductor device
JP2003338469A (en) 2002-05-21 2003-11-28 Fujitsu Ltd Abrasive, polishing method, and cleaning method
US10323162B2 (en) 2009-12-11 2019-06-18 Mitsui Minig & Smelting Co., Ltd. Abrasive material
JP4940289B2 (en) 2009-12-11 2012-05-30 三井金属鉱業株式会社 Abrasive
JP2011218494A (en) 2010-04-09 2011-11-04 Mitsui Mining & Smelting Co Ltd Polishing slurry, and polishing method therefor
JP5935531B2 (en) 2012-06-14 2016-06-15 富士通株式会社 Abrasive and method for producing abrasive

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KR970008387A (en) 1997-02-24
KR100251057B1 (en) 2000-04-15

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