JP3507732B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3507732B2
JP3507732B2 JP27825599A JP27825599A JP3507732B2 JP 3507732 B2 JP3507732 B2 JP 3507732B2 JP 27825599 A JP27825599 A JP 27825599A JP 27825599 A JP27825599 A JP 27825599A JP 3507732 B2 JP3507732 B2 JP 3507732B2
Authority
JP
Japan
Prior art keywords
semiconductor
layer
region
type
semiconductor region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP27825599A
Other languages
Japanese (ja)
Other versions
JP2001102577A (en
Inventor
孝 四戸
雄介 川口
彰博 八幡
和敏 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP27825599A priority Critical patent/JP3507732B2/en
Publication of JP2001102577A publication Critical patent/JP2001102577A/en
Application granted granted Critical
Publication of JP3507732B2 publication Critical patent/JP3507732B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置、特に
電力用のスーパージャンクション素子に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a super junction element for electric power.

【０００２】[0002]

【従来の技術】図７は、従来の縦型スーパージャンクシ
ョンＭＯＳＦＥＴの素子構造を示した断面図である。2. Description of the Related Art FIG. 7 is a sectional view showing a device structure of a conventional vertical super junction MOSFET.

【０００３】この素子の基本構造は、ｎ+ 型半導体基板
に形成されたｎ+ 型ドレイン層１、その上にエピタキシ
ャル成長されたｎ- 型ベース層（図示せず）、ｐ型ベー
ス層３、ｎ+ 型ソース層４、ｐ+ 型層５、ドレイン電極
６、ソース電極７、ゲート電極８、ゲート絶縁膜９、ｎ
- 型ベース層内でｎ型低濃度層１０及びｐ型低濃度層１
１が交互に繰り返し配置された補助領域によって構成さ
れている。The basic structure of this device is that an n + type drain layer 1 formed on an n + type semiconductor substrate, an n − type base layer (not shown) epitaxially grown thereon, a p type base layer 3, n. + Type source layer 4, p + type layer 5, drain electrode 6, source electrode 7, gate electrode 8, gate insulating film 9, n
- n-type by type base layer low-concentration layer 10 and the p-type low concentration layer 1
1 is composed of auxiliary regions arranged alternately and repeatedly.

【０００４】なお、図では、ｎ型低濃度層１０の左半分
及びｐ型低濃度層１１の右半分に対応した領域からなる
単位領域のみ示しているが、実際には隣接する単位領域
どおしが単位領域間の境界面で面対称になるようにして
複数配置されている。In the figure, only the unit regions consisting of the left half of the n-type low-concentration layer 10 and the right half of the p-type low-concentration layer 11 are shown. A plurality of ridges are arranged so as to be plane-symmetric at the boundary surface between the unit regions.

【０００５】ｎ型低濃度層１０とｐ型低濃度層１１とが
交互に繰り返し配置された補助領域の効果については、
例えば「Ｔ．Ｆｕｊｉｈｉｒａ，Ｊｐｎ．Ｊ．Ａｐｐ
ｌ．Ｐｈｙｓ．Ｖｏｌ．３６（１９９７）ｐｐ．６２５
４−６２６２」に開示されている。これによれば、補助
領域のｎ型低濃度層１０とｐ型低濃度層１１の繰り返し
方向のキャリア積分量が、概略５×１０12ｃｍ-2以下で
ほぼ同一になるように設計すれば、これらの低濃度層間
に逆方向電圧が印加された場合に、これらの低濃度層は
完全に空乏化するというものである。Regarding the effect of the auxiliary region in which the n-type low concentration layer 10 and the p-type low concentration layer 11 are alternately and repeatedly arranged,
For example, "T. Fujihira, Jpn. J. App.
l. Phys. Vol. 36 (1997) pp. 625
4-6262 ". According to this, if the n-type low-concentration layer 10 and the p-type low-concentration layer 11 in the auxiliary region are designed such that the carrier integration amount in the repeating direction is approximately 5 × 10 12 cm −2 or less, they are substantially the same, When a reverse voltage is applied between these low concentration layers, these low concentration layers are completely depleted.

【０００６】この原理によれば、例えばｎ型低濃度層１
０の濃度をｎ- 型ベース層の濃度の１００倍に設定して
も、ｎ型低濃度層１０の幅を狭くしてキャリア積分量が
５×１０12ｃｍ-2以下になるように調整すれば、補助領
域ではブレークダウンが起こらないことになる。したが
って、このような補助領域をｎ+ 型ドレイン層１とｐ型
ベース層３とに挟まれた領域に形成すれば、この部分の
抵抗を著しく低減することが可能となる。According to this principle, for example, the n-type low concentration layer 1
Even if the concentration of 0 is set to 100 times the concentration of the n − -type base layer, the width of the n-type low-concentration layer 10 should be narrowed so that the integrated carrier amount becomes 5 × 10 12 cm −2 or less. Thus, no breakdown will occur in the auxiliary area. Therefore, if such an auxiliary region is formed in a region sandwiched between the n + type drain layer 1 and the p type base layer 3, the resistance of this portion can be significantly reduced.

【０００７】また、この補助領域はその厚さ方向の長さ
に比例して耐圧が増加するという性質を持っているの
で、オン抵抗は耐圧に直線的に比例する。一方、補助領
域のない場合には、ｎ- 型ベース層の濃度を減らしなが
ら厚さを増加させないと耐圧が増加しないので、オン抵
抗は耐圧の２乗に比例して著しく増加する。したがっ
て、高耐圧が要求される素子になるほど、補助領域を設
けたことによるオン抵抗の低減効果が大きくなる。Further, since the withstand voltage of this auxiliary region increases in proportion to its length in the thickness direction, the on-resistance is linearly proportional to the withstand voltage. On the other hand, when the auxiliary region is not provided, the breakdown voltage does not increase unless the thickness of the n − type base layer is increased while the concentration of the n − type base layer is reduced. Therefore, the on-resistance significantly increases in proportion to the square of the breakdown voltage. Therefore, the more the element is required to have a higher breakdown voltage, the greater the effect of reducing the on-resistance due to the provision of the auxiliary region.

【０００８】また、補助領域のｐ型低濃度層１１はｐ型
ベース層３と接続されてソース電極７とほぼ等電位に設
定されており、補助領域のｎ型低濃度層１０はｎ+ 型ド
レイン層１と接続されてドレイン電極６とほぼ等電位に
設定されている。したがって、縦型ＭＯＳＦＥＴがター
ンオフし始めると、補助領域内部のキャリアは速やかに
素子外部へ吐き出されて空乏層が広がり、高速にターン
オフすることが可能となる。Further, the p-type low-concentration layer 11 in the auxiliary region is connected to the p-type base layer 3 and set to substantially the same potential as the source electrode 7, and the n-type low-concentration layer 10 in the auxiliary region is n + -type. It is connected to the drain layer 1 and is set to have substantially the same potential as the drain electrode 6. Therefore, when the vertical MOSFET starts to turn off, the carriers inside the auxiliary region are quickly discharged to the outside of the element, the depletion layer spreads, and it becomes possible to turn off at high speed.

【０００９】また、このような素子の製造方法は、
「Ｇ．Ｄｅｂｏｙ ｅｔ ａｌ．，ＩＥＤＭ９８（１９
９８）ｐｐ．６８３−６８５」に開示されている。Further, the manufacturing method of such an element is as follows.
"G. Deboy et al., IEDM 98 (19
98) pp. 683-685 ".

【００１０】これによれば、ｎ+ 型半導体基板上に例え
ば厚さ１０μｍのエピタキシャル層を形成して、補助領
域のｎ型低濃度層１０及びｐ型低濃度層１１が形成され
る領域に、イオン注入によって選択的に不純物を導入す
る。さらに、エピタキシャル層を形成して同様の工程を
行ない、これを素子の耐圧・厚さに応じて数回繰り返
す。According to this, for example, an epitaxial layer having a thickness of 10 μm is formed on the n + type semiconductor substrate, and in the region where the n type low concentration layer 10 and the p type low concentration layer 11 of the auxiliary region are formed, Impurities are selectively introduced by ion implantation. Further, an epitaxial layer is formed and the same steps are performed, and this is repeated several times depending on the breakdown voltage and thickness of the device.

【００１１】次に、ｐ型ベース層３などのイオン注入を
行った後、熱拡散により、それぞれのエピタキシャル層
内部に形成されたイオン注入層から不純物を拡散させ
て、互いの層のｎ型低濃度層１０及びｐ型低濃度層１１
が接続されるようにする。その後、ｎ+ 型ソース層４、
ｐ+ 型層５、ゲート絶縁膜９、ゲート電極８、ソース電
極７、ドレイン電極６などを形成し、素子を完成させ
る。Next, after ion-implanting the p-type base layer 3 etc., impurities are diffused from the ion-implanted layers formed inside the respective epitaxial layers by thermal diffusion, so that the n-type lower layers of the respective layers are reduced. Concentration layer 10 and p-type low concentration layer 11
To be connected. After that, the n + type source layer 4,
The p + type layer 5, the gate insulating film 9, the gate electrode 8, the source electrode 7, the drain electrode 6 and the like are formed to complete the device.

【００１２】上述したような製造方法を用いることによ
り、比較的簡単に補助領域を形成することができる。By using the manufacturing method as described above, the auxiliary region can be formed relatively easily.

【００１３】しかしながら、上述した従来の素子構造で
は、「Ｐ．Ｍ．Ｓｈｅｎｏｙ ｅｔａｌ．，ＩＳＰＳＤ
９９（１９９９）ｐｐ．９９−１０２」に開示されてい
るように、補助領域のｎ型低濃度層１０とｐ型低濃度層
１１のキャリア積分量がずれると、ターンオフ時間や内
蔵逆導通ダイオードの逆回復時間が大きく変動するとと
もに、耐圧が著しく低下するという問題が生じる。However, in the above-mentioned conventional device structure, "PM Shenoy et al., ISPSD" is used.
99 (1999) pp. 99-102 ", if the carrier integration amounts of the n-type low-concentration layer 10 and the p-type low-concentration layer 11 in the auxiliary region deviate from each other, the turn-off time and the reverse recovery time of the built-in reverse conducting diode fluctuate significantly. At the same time, there arises a problem that the breakdown voltage is significantly lowered.

【００１４】また、エピタキシャル成長は高温で行なう
ので、最初に行なったエピタキシャル成長層中に導入さ
れている不純物がしだいに拡散するため、補助領域下部
のキャリア積分量がずれやすいという問題が生じる。Further, since the epitaxial growth is carried out at a high temperature, the impurities introduced into the epitaxial growth layer initially formed diffuse gradually, so that there is a problem that the carrier integrated amount in the lower portion of the auxiliary region tends to shift.

【００１５】また、従来の素子構造では、補助領域のｐ
型低濃度層１１がｎ+ 型ドレイン層１に接しているの
で、この部分の空乏層はｐ型低濃度層１１内部にしか広
がらない。一方、補助領域のｎ型低濃度層１０は比較的
濃度の低いｐ型ベース層３に接しているので、この部分
の空乏層はｎ型低濃度層１０内部だけでなく、ｐ型ベー
ス層３内部にも広がる。その結果、ｐ型低濃度層１１と
ｎ+ 型ドレイン層１が接している部分の電界強度が高く
なり、この部分で素子全体の耐圧が制限されるという問
題が生じる。Further, in the conventional device structure, p of the auxiliary region is
Since the low-concentration type layer 11 is in contact with the n + -type drain layer 1, the depletion layer in this portion spreads only inside the low-concentration layer 11 of the p-type. On the other hand, since the n-type low-concentration layer 10 in the auxiliary region is in contact with the p-type base layer 3 having a relatively low concentration, the depletion layer in this portion is not only inside the n-type low-concentration layer 10 but also in the p-type base layer 3. Also spreads inside. As a result, the electric field strength increases at the portion where the p-type low-concentration layer 11 and the n + -type drain layer 1 are in contact with each other, and the breakdown voltage of the entire device is limited at this portion.

【００１６】２次元数値計算の結果によれば、補助領域
の長さＬが３５０μｍ、補助領域のｎ型低濃度層１０及
びｐ型低濃度層１１の幅Ｗｎ及びＷｐがともに３．５μ
ｍ、ｎ型低濃度層１０及びｐ型低濃度層１１の濃度Ｃｎ
及びＣｐがともに３×１０15ｃｍ-3の場合に、素子の耐
圧は４９５０Ｖであった。局部的な電界集中のない理想
的な素子の耐圧は、半導体の絶縁破壊電界強度と補助領
域の長さとの積で表される７０００Ｖになるはずなの
で、この素子構造では７０％の耐圧しか得られないこと
になる。According to the result of the two-dimensional numerical calculation, the length L of the auxiliary region is 350 μm, and the widths Wn and Wp of the n-type low concentration layer 10 and the p-type low concentration layer 11 of the auxiliary region are both 3.5 μm.
Concentration Cn of m, n-type low concentration layer 10 and p-type low concentration layer 11
When both Cp and Cp were 3 × 10 15 cm −3 , the breakdown voltage of the device was 4950V. The ideal breakdown voltage of an element without local electric field concentration should be 7,000 V, which is represented by the product of the dielectric breakdown field strength of the semiconductor and the length of the auxiliary region. Therefore, with this element structure, a breakdown voltage of only 70% can be obtained. There will be no.

【００１７】[0017]

【発明が解決しようとする課題】このように、スーパー
ジャンクション素子は、オン抵抗の低減や高速ターンオ
フといった優れた性能を有している。しかしながら、従
来のスーパージャンクション素子は、補助領域のｎ型低
濃度層とｐ型低濃度層のキャリア積分量がずれると、タ
ーンオフ時間や内蔵逆導通ダイオードの逆回復時間が大
きく変動するとともに、耐圧が著しく低下するという問
題があった。また、ｐ型低濃度層とｎ+ 型ドレイン層が
接している部分の電界強度が高くなり、この部分で素子
全体の耐圧が制限されるという問題もあった。As described above, the super junction element has excellent performances such as reduction of on-resistance and high speed turn-off. However, in the conventional super junction element, if the carrier integration amount of the n-type low concentration layer and the p-type low concentration layer of the auxiliary region is deviated, the turn-off time and the reverse recovery time of the built-in reverse conducting diode are largely changed and the breakdown voltage is high. There was a problem of a significant decrease. Further, there is a problem that the electric field strength increases in a portion where the p-type low concentration layer and the n + -type drain layer are in contact with each other, and the withstand voltage of the entire device is limited in this portion.

【００１８】本発明は上記従来の課題に対してなされた
ものであり、従来の素子に比べて耐圧及びターンオフ特
性を向上させることが可能な半導体装置を提供すること
を目的としている。The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device capable of improving withstand voltage and turn-off characteristics as compared with a conventional element.

【００１９】[0019]

【課題を解決するための手段】本発明に係る半導体装置
は、以下の構成を有している。なお、本発明の理解を容
易にするため、後述する実施形態において説明する図面
の参照番号を付して本発明の構成を示す。A semiconductor device according to the present invention has the following configuration. In addition, in order to facilitate understanding of the present invention, the configuration of the present invention is shown with reference numerals of the drawings described in the embodiments described later.

【００２０】本発明は、第１導電型の不純物が含有され
た第１の半導体領域（１）と、前記第１の半導体領域
（１）と離間して形成され第２導電型の不純物が含有さ
れた第２の半導体領域（３）と、前記第１の半導体領域
（１）と前記第２の半導体領域（３）との間に設けら
れ、第１導電型の不純物が含有された第１の半導体層
（１０）と第２導電型の不純物が含有された第２の半導
体層（１１）とが前記第１の半導体領域（１）と第２の
半導体領域（３）とが対向する方向と交差する方向に交
互に繰り返し配置された第３の半導体領域（１０、１
１）と、を有する半導体装置であって、交互に繰り返し
配置された前記第１の半導体層（１０）及び第２の半導
体層（１１）の繰り返し方向のキャリア積分量が、第２
の半導体層（１１）の方が第１の半導体層（１０）より
も大きくなるように構成され、前記第１の半導体領域
（１）と前記第３の半導体領域（１０、１１）の少なく
とも第２の半導体層（１１）との間に前記第１の半導体
領域（１）よりも第１導電型の不純物濃度の低い第４の
半導体領域（１３）が形成されていることを特徴とす
る。According to the present invention, a first semiconductor region (1) containing a first conductivity type impurity and a second conductivity type impurity formed apart from the first semiconductor region (1) are contained. A second semiconductor region (3) formed between the first semiconductor region (1) and the second semiconductor region (3), and a first conductivity type impurity is contained therein. Of the semiconductor layer (10) and the second semiconductor layer (11) containing an impurity of the second conductivity type face the first semiconductor region (1) and the second semiconductor region (3). Third semiconductor regions (10, 1) alternately arranged in a direction intersecting with
1) and, wherein the carrier integration amount in the repeating direction of the first semiconductor layer (10) and the second semiconductor layer (11) alternately and repeatedly arranged is the second
Of the first semiconductor region (1) and the third semiconductor region (10, 11) are configured to be larger than the first semiconductor layer (10). A fourth semiconductor region (13) having an impurity concentration of the first conductivity type lower than that of the first semiconductor region (1) is formed between the second semiconductor layer (11) and the second semiconductor layer (11).

【００２１】本発明では、第３の半導体領域（補助領
域）の第２の半導体層の繰り返し方向のキャリア積分量
（Ｑ２）が第１の半導体層の繰り返し方向のキャリア積
分量（Ｑ１）よりも大きくなるようにしている（Ｑ２＞
Ｑ１）ので、ターンオフの際に第１の半導体層が空乏化
した後にも第２の半導体層の中央部には非空乏化領域が
残存している。そのため、電流がこの非空乏化領域を通
って排出されることになり、高速にターンオフすること
が可能となる（特に、ｎ型に比べてｐ型のキャリアの移
動度が小さいことから、第１の半導体層がｎ型で第２の
半導体層がｐ型である場合に、効果が大きい）。製造プ
ロセス等に起因するキャリア積分量の変動が多少あって
としても、Ｑ２とＱ１との大小関係が逆転しない程度に
Ｑ２及びＱ１の値を設定しておけば、ターンオフ時間の
揃った素子を容易に製造することが可能となる。In the present invention, the carrier integration amount (Q2) in the repeating direction of the second semiconductor layer of the third semiconductor region (auxiliary region) is larger than the carrier integration amount (Q1) in the repeating direction of the first semiconductor layer. I try to make it bigger (Q2>
Since Q1), the non-depleted region remains in the central portion of the second semiconductor layer even after the first semiconductor layer is depleted during turn-off. Therefore, the current is discharged through this non-depleted region, and it is possible to turn off at a high speed (particularly, since the mobility of p-type carriers is smaller than that of n-type, The effect is great when the semiconductor layer is n-type and the second semiconductor layer is p-type). Even if there is some variation in the carrier integration amount due to the manufacturing process, etc., if the values of Q2 and Q1 are set so that the magnitude relationship between Q2 and Q1 does not reverse, an element with a uniform turn-off time can be easily manufactured. Can be manufactured.

【００２２】また、第２の半導体層の中央部に非空乏化
領域が残存することから、第２の半導体領域の電位が非
空乏化領域を介して第１の半導体領域の近傍まで達する
ことになるが、第１の半導体領域と第３の半導体領域と
の間に第１の半導体領域よりも不純物濃度の低い第４の
半導体領域が形成されているので、空乏層が不純物濃度
の低い第４の半導体領域の内部に広がって電界を緩和
し、高耐圧化をはかることが可能となる。Further, since the non-depleted region remains in the central portion of the second semiconductor layer, the potential of the second semiconductor region reaches the vicinity of the first semiconductor region through the non-depleted region. However, since the fourth semiconductor region whose impurity concentration is lower than that of the first semiconductor region is formed between the first semiconductor region and the third semiconductor region, the depletion layer is the fourth semiconductor region whose impurity concentration is low. It is possible to increase the breakdown voltage by spreading inside the semiconductor region and relaxing the electric field.

【００２３】前記発明において、前記第３の半導体領域
（１０、１１）の第２の半導体層（１１）は、前記第１
の半導体領域（１）側の方が前記第２の半導体領域
（３）側よりも不純物濃度が低くなるように構成された
複数の半導体層からなることが好ましい。In the above invention, the second semiconductor layer (11) of the third semiconductor region (10, 11) is the first semiconductor layer (11).
It is preferable that the semiconductor region (1) side is composed of a plurality of semiconductor layers configured to have an impurity concentration lower than that of the second semiconductor region (3) side.

【００２４】このような構成により、第３の半導体領域
（補助領域）の第２の半導体層における第１の半導体領
域に近い側の領域が容易に空乏化するため、第２の半導
体領域の電位の影響をより一層抑制することが可能とな
り、高耐圧化をより一層高めることが可能となる。ま
た、第２の半導体領域に近い側の領域では、第２の半導
体層は比較的低抵抗となるので、排出電流が制限されて
ターンオフの高速性が損なわれることはない。With this structure, the region of the second semiconductor layer of the third semiconductor region (auxiliary region) on the side closer to the first semiconductor region is easily depleted, so that the potential of the second semiconductor region is reduced. It is possible to further suppress the influence of, and it is possible to further enhance the high breakdown voltage. Further, in the region close to the second semiconductor region, the second semiconductor layer has a relatively low resistance, so that the discharge current is limited and the high-speed turn-off is not impaired.

【００２５】また、前記発明において、前記第４の半導
体領域（１３）は、前記第１の半導体領域（１）と前記
第３の半導体領域（１０、１１）との間に形成されたバ
ッファ領域であってもよい。Further, in the above invention, the fourth semiconductor region (13) is a buffer region formed between the first semiconductor region (1) and the third semiconductor region (10, 11). May be

【００２６】このような構成により、第３の半導体領域
（補助領域）の第２の半導体層が比較的高濃度となるこ
とによって内蔵逆導通ダイオードの逆回復電流が大きく
なっても、バッファ領域にキャリアを蓄積することでソ
フトリカバリ特性が得られ、電圧振動を効果的に防止す
ることが可能となる。With such a structure, even if the reverse recovery current of the built-in reverse conducting diode becomes large due to the relatively high concentration of the second semiconductor layer in the third semiconductor region (auxiliary region), the buffer region will be stored in the buffer region. By accumulating carriers, soft recovery characteristics can be obtained, and voltage oscillation can be effectively prevented.

【００２７】[0027]

【発明の実施の形態】以下、本発明の実施形態を図面を
参照して説明する。DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【００２８】なお、以下の実施形態では、第１導電型を
ｎ型とし、第２導電型をｐ型とした場合を示している
が、第１導電型をｐ型とし、第２導電型をｎ型とするこ
とも可能である。In the following embodiments, the first conductivity type is n type and the second conductivity type is p type. However, the first conductivity type is p type and the second conductivity type is It can also be an n-type.

【００２９】（第１の実施形態）図１は、本発明の第１
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
Vertical super junction MOSF according to the embodiment
It is sectional drawing which showed the element structure of ET.

【００３０】なお、基本的な素子構造や基本的な製造方
法については、すでに図７を用いて説明した従来の縦型
スーパージャンクションＭＯＳＦＥＴとほぼ同様であ
り、図７に示した構成要素に対応する構成要素について
は同一の参照番号を付し、ここではこれらの詳細な説明
は省略する（図２〜図５に示した第２〜第５の実施形態
についても同様）。The basic element structure and the basic manufacturing method are almost the same as those of the conventional vertical type super junction MOSFET already described with reference to FIG. 7, and correspond to the constituent elements shown in FIG. The same reference numerals are given to the constituent elements, and detailed description thereof will be omitted here (the same applies to the second to fifth embodiments shown in FIGS. 2 to 5).

【００３１】本実施形態の縦型スーパージャンクション
ＭＯＳＦＥＴでは、補助領域（第３の半導体領域）のｐ
型低濃度層（第２の半導体層）１１のキャリア積分量Ｑ
ｐは、ｎ型低濃度層（第１の半導体層）１０のキャリア
積分量Ｑｎよりも大きくなる（Ｑｐ＞Ｑｎ）ように設定
されている。また、これらのキャリア積分量は、Ｑｐ及
びＱｎともに、５×１０12ｃｍ-2以下となるように設定
されている。また、ｐ型低濃度層１１とｎ+ 型ドレイン
層（第１の半導体領域）１との間には、ｎ- 型層（第４
の半導体領域）１３が形成されている。In the vertical superjunction MOSFET of this embodiment, p in the auxiliary region (third semiconductor region) is used.
Carrier integrated amount Q of the low concentration layer (second semiconductor layer) 11
p is set to be larger than the integrated carrier amount Qn of the n-type low concentration layer (first semiconductor layer) 10 (Qp> Qn). Further, the integrated amounts of these carriers are set to be 5 × 10 12 cm −2 or less for both Qp and Qn. Further, between the p-type low concentration layer 11 and the n + type drain layer (first semiconductor region) 1, an n − type layer (fourth type) is formed.
Semiconductor region) 13 is formed.

【００３２】本実施形態によれば、ターンオフが開始し
てｎ型低濃度層１０が完全に空乏化しても、ｐ型低濃度
層１１の中央部付近（図では左端付近の領域に対応）に
非空乏化領域が残り、ｎ型に比べて移動度の小さいｐ型
のキャリア（ホール）による電流が、この非空乏化領域
を通って排出されるので、高速ターンオフを実現するこ
とができる。According to the present embodiment, even if the turn-off is started and the n-type low-concentration layer 10 is completely depleted, the p-type low-concentration layer 11 is near the center (corresponding to the region near the left end in the figure). The non-depleted region remains, and the current due to the p-type carriers (holes) having a smaller mobility than the n-type is discharged through the non-depleted region, so that high-speed turn-off can be realized.

【００３３】ターンオフ時間は、ＱｐとＱｎとの大小関
係が逆転してＱｎ＞Ｑｐとなると急に遅くなるが、予め
マージンを見込んでＱｐ＞Ｑｎとなるように設定してあ
れば、多少のプロセス変動があってもＱｐ＞Ｑｎの関係
が保持されるので、ターンオフ時間が大きくばらつくよ
うなことはない。例えば、プロセス変動によってＱｐと
Ｑｎとの差が５％程度ばらつく場合があり得るが、Ｑｐ
がＱｎよりも７〜８％程度多くなるように設定しておけ
ば、プロセス変動があっても確実にＱｐ＞Ｑｎの関係を
維持することができる。The turn-off time is abruptly delayed when the magnitude relation between Qp and Qn is reversed and Qn> Qp, but if the margin is set in advance so that Qp> Qn, some process Even if there is a change, the relationship of Qp> Qn is maintained, so the turn-off time does not vary greatly. For example, the difference between Qp and Qn may vary by about 5% due to process variation.
Is set to be about 7 to 8% larger than Qn, it is possible to reliably maintain the relationship of Qp> Qn even if there is a process variation.

【００３４】また、ｐ型低濃度層１１の中央部付近に非
空乏化領域が残ることから、ｐ型低濃度層１１の中央部
の下部領域の電位が非空乏化領域を介してｐ型ベース層
３の電位と同電位となり、ｎ+ 型ドレイン層１との境界
部付近で電界強度が高くなるという問題が考えられる。
本実施形態では、ｎ- 型層１３によって空乏層を広げる
ことができるため、電界が緩和されて高耐圧を維持する
ことができ、このような問題を防止することができる。Further, since the non-depleted region remains near the central portion of the p-type low concentration layer 11, the potential of the lower region of the central portion of the p-type low concentration layer 11 is p-type base via the non-depleted region. The potential is the same as that of the layer 3, and there is a problem that the electric field strength increases near the boundary with the n + type drain layer 1.
In the present embodiment, since the depletion layer can be widened by the n − type layer 13, the electric field can be relaxed and the high breakdown voltage can be maintained, and such a problem can be prevented.

【００３５】なお、ｎ型低濃度層１０とｐ型低濃度層１
１との接合終端領域については、補助領域の端部に半分
のキャリア積分量を持つｐ型低濃度層１１を配置し、通
常のｎ- 型ベース層に対するガードリングやＲＥＳＵＲ
Ｆなどの接合終端構造を適用することが望ましい。The n-type low concentration layer 10 and the p-type low concentration layer 1
For the junction termination region with 1, the p-type low-concentration layer 11 having a half carrier integration amount is arranged at the end of the auxiliary region, and a guard ring for the normal n − -type base layer or a RESUUR is provided.
It is desirable to apply a junction termination structure such as F.

【００３６】（第２の実施形態）図２は、本発明の第２
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
Vertical super junction MOSF according to the embodiment
It is sectional drawing which showed the element structure of ET.

【００３７】本実施形態では、第１の実施形態の素子構
造に加えてさらに、補助領域のｐ型低濃度層１１の下部
領域にｐ- 型層１４を形成している。In the present embodiment, in addition to the device structure of the first embodiment, a p − type layer 14 is formed in the lower region of the p type low concentration layer 11 in the auxiliary region.

【００３８】本実施形態によれば、ｐ- 型層１４がそれ
よりも高不純物濃度のｐ型低濃度層１１より早く空乏化
されるので、ｐ型ベース層３と同電位の領域が入り込ま
ない。その結果、電界が緩和されてより高耐圧を維持す
ることが可能となる。According to this embodiment, the p − -type layer 14 is depleted earlier than the p-type low-concentration layer 11 having a higher impurity concentration, so that the region having the same potential as the p-type base layer 3 does not enter. . As a result, the electric field is alleviated, and a higher breakdown voltage can be maintained.

【００３９】なお、図に示した例では、ｐ型低濃度層は
二つの濃度領域としているが、下層側に行くにしたがっ
て不純物濃度が低くなるような３以上の濃度領域を設け
るようにしてもよい。In the example shown in the figure, the p-type low concentration layer has two concentration regions, but three or more concentration regions may be provided so that the impurity concentration becomes lower toward the lower layer side. Good.

【００４０】また、図に示した例では、ｎ型低濃度層１
０は均一濃度となるように形成されているが、ｐ型低濃
度層１１の濃度変化に合わせて、下層側に行くにしたが
って低濃度になるようにしてもよい。In the example shown in the figure, the n-type low concentration layer 1
Although 0 is formed to have a uniform concentration, the concentration may be decreased toward the lower layer side according to the concentration change of the p-type low concentration layer 11.

【００４１】このような構成によれば、数回のエピタキ
シャル成長によって素子を形成する際に、高温に晒され
る時間が長く熱拡散によるＱの変動量の大きな補助領域
下部が低濃度に、高温に晒される時間が短くＱの変動量
の小さな補助領域上部が高濃度に形成されるので、オン
抵抗を低く保ったまま高耐圧化をはかることが可能とな
る。According to this structure, when the element is formed by epitaxial growth several times, the lower part of the auxiliary region, which is exposed to a high temperature for a long time and has a large fluctuation amount of Q due to thermal diffusion, is exposed to a low concentration and a high temperature. Since the upper part of the auxiliary region having a short period of time and a small Q variation amount is formed at a high concentration, it is possible to increase the breakdown voltage while keeping the on-resistance low.

【００４２】（第３の実施形態）図３は、本発明の第３
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
Vertical super junction MOSF according to the embodiment
It is sectional drawing which showed the element structure of ET.

【００４３】本実施形態では、ｎ+ 型ドレイン層１と補
助領域との間に、ｎ+ 型ドレイン層よりも低濃度のｎ型
バッファ層１５が形成されている。In this embodiment, the n-type buffer layer 15 having a lower concentration than that of the n + -type drain layer is formed between the n + -type drain layer 1 and the auxiliary region.

【００４４】本実施形態によれば、ｐ型ベース層３及び
ｐ型低濃度層１１をアノード層とし、ｎ+ 型ドレイン層
１及びｎ型低濃度層１０をカソード層とする内蔵逆導通
ダイオードの逆回復特性を、ソフトリカバリにすること
ができる。また、ｐ型低濃度層１１だけでなくｎ型バッ
ファ層１５内部にも空乏層が広がるので、電界が緩和さ
れ、素子耐圧を向上させることが可能となる。According to this embodiment, a built-in reverse conducting diode having the p-type base layer 3 and the p-type low concentration layer 11 as the anode layers and the n + -type drain layer 1 and the n-type low concentration layer 10 as the cathode layers is provided. The reverse recovery characteristic can be soft recovery. In addition, since the depletion layer spreads not only in the p-type low concentration layer 11 but also in the n-type buffer layer 15, the electric field is alleviated, and the breakdown voltage of the device can be improved.

【００４５】本発明に係るスーパージャンクションＭＯ
ＳＦＥＴでは、Ｑｐ＞Ｑｎとしたために逆回復電流が大
きくなり、ダイオードの電圧が回復する際に、電流減少
率に比例する電圧の跳ね上がりが発生して、電圧振動を
引き起こすという問題を生じやすい。このような場合で
も、ｎ型バッファ層１５を形成することによってキャリ
アが蓄積され、逆回復時のテール領域での電流減少率が
減少して電圧の跳ね上がりが低減されるという効果があ
る。Superjunction MO according to the present invention
In the SFET, since Qp> Qn, the reverse recovery current becomes large, and when the voltage of the diode recovers, a voltage jump proportional to the current decrease rate occurs, which easily causes a problem of voltage oscillation. Even in such a case, the formation of the n-type buffer layer 15 has the effect of accumulating carriers, reducing the current reduction rate in the tail region during reverse recovery, and reducing the voltage jump.

【００４６】なお、キャリア蓄積の観点からは、ｎ型バ
ッファ層１５の厚さをキャリアの拡散長以上に設定する
ことが望ましい。例えば、ｎ型バッファ層１５の厚さ
は、耐圧４５００Ｖの素子では７５μｍ程度となるよう
にする。From the viewpoint of carrier accumulation, it is desirable to set the thickness of the n-type buffer layer 15 to be equal to or more than the diffusion length of carriers. For example, the thickness of the n-type buffer layer 15 is set to about 75 μm for a device having a withstand voltage of 4500V.

【００４７】（第４の実施形態）図４は、本発明の第４
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
Vertical super junction MOSF according to the embodiment
It is sectional drawing which showed the element structure of ET.

【００４８】本実施形態では、第３の実施形態の素子構
造に加えてさらに、ｐ- 型層１４が形成されている。す
なわち、本実施形態は、第２の実施形態と第３の実施形
態を併せたような構造を有しており、したがって、第２
の実施形態及び第３の実施形態で得られるそれぞれの効
果を得ることができる。In this embodiment, a p -- type layer 14 is further formed in addition to the element structure of the third embodiment. That is, the present embodiment has a structure in which the second embodiment and the third embodiment are combined, and accordingly, the second embodiment
The respective effects obtained in the embodiment and the third embodiment can be obtained.

【００４９】（第５の実施形態）図５は、本発明の第５
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Fifth Embodiment) FIG. 5 shows the fifth embodiment of the present invention.
Vertical super junction MOSF according to the embodiment
It is sectional drawing which showed the element structure of ET.

【００５０】本実施形態では、第２の実施形態の素子構
造に加えてさらに、ｎ型バッファ層１５が形成されてお
り、本実施形態によっても、第２の実施形態及び第３の
実施形態で得られる効果と同様の効果を得ることができ
る。In the present embodiment, an n-type buffer layer 15 is further formed in addition to the element structure of the second embodiment. Also in this embodiment, the n-type buffer layer 15 is also formed in the second and third embodiments. The same effect as that obtained can be obtained.

【００５１】（第６の実施形態）図６は、本発明の第６
の実施形態に係る横型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した斜視図である。(Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
Lateral super junction MOSF according to the embodiment
It is the perspective view which showed the element structure of ET.

【００５２】なお、基本的な原理については図１等に示
した縦型スーパージャンクションＭＯＳＦＥＴと同様で
あり、図１等に示した構成要素に対応する構成要素につ
いては同一の参照番号を付している。The basic principle is the same as that of the vertical super junction MOSFET shown in FIG. 1 and the like, and the same reference numerals are attached to the components corresponding to the components shown in FIG. There is.

【００５３】第１〜第５の実施形態で説明した縦型スー
パージャンクションＭＯＳＦＥＴでは、ドレイン電極６
を半導体基板の一方の主面側に、ソース電極７を半導体
基板の他方の主面側にそれぞれ形成した構造であった
が、本実施形態の横型スーパージャンクションＭＯＳＦ
ＥＴでは、ドレイン電極６及びソース電極７は半導体基
板の同一主面側に形成されている。In the vertical type super junction MOSFET described in the first to fifth embodiments, the drain electrode 6
Was formed on one main surface side of the semiconductor substrate, and the source electrode 7 was formed on the other main surface side of the semiconductor substrate.
In ET, the drain electrode 6 and the source electrode 7 are formed on the same main surface side of the semiconductor substrate.

【００５４】このような横型スーパージャンクションＭ
ＯＳＦＥＴにおいても、縦型スーパージャンクションＭ
ＯＳＦＥＴと同様、補助領域におけるｐ型低濃度層１１
のキャリア積分量Ｑｐとｎ型低濃度層１０のキャリア積
分量Ｑｎとの関係をＱｐ＞Ｑｎとなるように設定すると
ともに、ｐ型低濃度層１１とｎ+ 型ドレイン層１との間
にｎ- 型層１３を設けることにより、縦型スーパージャ
ンクションＭＯＳＦＥＴと同様の効果を得ることが可能
となる。Such a horizontal super junction M
Also in OSFET, vertical super junction M
Similar to the OSFET, the p-type low concentration layer 11 in the auxiliary region
N of the relation between carrier integrated amount Qn of the carrier integral quantity Qp and the n-type low-concentration layer 10 and sets such that Qp> Qn, between the p-type low concentration layer 11 and the n + -type drain layer 1 - by providing the mold layer 13, it is possible to obtain the same effect as the vertical superjunction MOSFET.

【００５５】なお、図６に示した横型スーパージャンク
ションＭＯＳＦＥＴは、図１に示した第１の実施形態の
縦型スーパージャンクションＭＯＳＦＥＴに対応する構
造となっているが、その他の実施形態において説明した
縦型スーパージャンクションＭＯＳＦＥＴに対応する構
造を横型スーパージャンクションＭＯＳＦＥＴに適用す
ることも可能である。The horizontal superjunction MOSFET shown in FIG. 6 has a structure corresponding to the vertical superjunction MOSFET of the first embodiment shown in FIG. 1, but the vertical superjunction MOSFET has the vertical structure described in the other embodiments. It is also possible to apply the structure corresponding to the type super junction MOSFET to the lateral type super junction MOSFET.

【００５６】以上、本発明の実施形態を説明したが、本
発明は上記実施形態に限定されるものではない。例え
ば、上記実施形態では、基本となる素子構造をＭＯＳＦ
ＥＴとしたが、ＳＩＴなど他の素子構造に対して適用す
ることも可能である。その他、本発明はその趣旨を逸脱
しない範囲内において種々変形して実施することが可能
である。Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above embodiment, the basic element structure is a MOSF.
Although ET is used, it can also be applied to other element structures such as SIT. In addition, the present invention can be variously modified and implemented within a range not departing from the gist thereof.

【００５７】[0057]

【発明の効果】本発明によれば、補助領域の一方の半導
体層のキャリア積分量Ｑ１と他方の半導体層のキャリア
積分量Ｑ２との関係がＱ２＞Ｑ１となるようにしたの
で、ターンオフの際に他方の半導体層に非空乏化領域が
残存し、この非空乏化領域を通って電流が排出されるこ
とになり、ターンオフを高速化することが可能となる。
また、ドレイン側の高不純物濃度領域と補助領域との間
に低不純物濃度領域を設けることにより、空乏層が低不
純物濃度領域に広がって電界を緩和するため、高耐圧化
をはかることが可能となる。According to the present invention, the relation between the carrier integration amount Q1 of one semiconductor layer in the auxiliary region and the carrier integration amount Q2 of the other semiconductor layer is Q2> Q1. In addition, the non-depleted region remains in the other semiconductor layer, and the current is discharged through this non-depleted region, so that the turn-off can be speeded up.
Further, by providing a low impurity concentration region between the high impurity concentration region on the drain side and the auxiliary region, the depletion layer spreads to the low impurity concentration region and relaxes the electric field, so that it is possible to increase the breakdown voltage. Become.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 1 is a cross-sectional view showing a device structure of a vertical super junction MOSFET according to a first embodiment of the present invention.

【図２】本発明の第２の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 2 is a sectional view showing an element structure of a vertical super junction MOSFET according to a second embodiment of the present invention.

【図３】本発明の第３の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 3 is a sectional view showing an element structure of a vertical superjunction MOSFET according to a third embodiment of the present invention.

【図４】本発明の第４の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 4 is a cross-sectional view showing an element structure of a vertical super junction MOSFET according to a fourth embodiment of the present invention.

【図５】本発明の第５の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 5 is a sectional view showing an element structure of a vertical super junction MOSFET according to a fifth embodiment of the present invention.

【図６】本発明の第６の実施形態に係る横型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した斜視図。FIG. 6 is a perspective view showing an element structure of a lateral super junction MOSFET according to a sixth embodiment of the present invention.

【図７】従来技術に係る縦型スーパージャンクションＭ
ＯＳＦＥＴの素子構造を示した断面図。FIG. 7 is a vertical super junction M according to the related art.
Sectional drawing which showed the element structure of OSFET.

【符号の説明】[Explanation of symbols]

１…ｎ+ 型ドレイン層（第１の半導体領域） ３…ｐ型ベース層（第２の半導体領域） ４…ｎ+ 型ソース層 ５…ｐ+ 型層 ６…ドレイン電極 ７…ソース電極 ８…ゲート電極 ９…ゲート絶縁膜 １０…ｎ型低濃度層（第１の半導体層） １１…ｐ型低濃度層（第２の半導体層） １３…ｎ- 型層（第４の半導体領域） １４…ｐ- 型層 １５…ｎ型バッファ層（第４の半導体領域）1 ... N + type drain layer (first semiconductor region) 3 ... P type base layer (second semiconductor region) 4 ... N + type source layer 5 ... P + type layer 6 ... Drain electrode 7 ... Source electrode 8 ... Gate electrode 9 ... Gate insulating film 10 ... N-type low concentration layer (first semiconductor layer) 11 ... P-type low concentration layer (second semiconductor layer) 13 ... N - type layer (fourth semiconductor region) 14 ... p − type layer 15 ... n type buffer layer (fourth semiconductor region)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 和敏 神奈川県川崎市幸区小向東芝町１番地 株式会社東芝研究開発センター内 (56)参考文献 特開 平７−7154（ＪＰ，Ａ) 特開 平10−223896（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/336 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazutoshi Nakamura 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research and Development Center Co., Ltd. (56) Reference JP-A-7-7154 (JP, A) JP-A-10-223896 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】第１導電型の不純物が含有された第１の半
導体領域と、 前記第１の半導体領域と離間して形成され第２導電型の
不純物が含有された第２の半導体領域と、 前記第１の半導体領域と前記第２の半導体領域との間に
設けられ、第１導電型の不純物が含有された第１の半導
体層と第２導電型の不純物が含有された第２の半導体層
とが前記第１の半導体領域と第２の半導体領域とが対向
する方向と交差する方向に交互に繰り返し配置された第
３の半導体領域と、 を有する半導体装置であって、 交互に繰り返し配置された前記第１の半導体層及び第２
の半導体層の繰り返し方向のキャリア積分量が、第２の
半導体層の方が第１の半導体層よりも大きくなるように
構成され、 前記第１の半導体領域と前記第２の半導体層との間に前
記第１の半導体領域よりも第１導電型の不純物濃度の低
い第４の半導体領域が選択的に形成され、前記第１の半
導体領域と前記第１の半導体層とが接していることを特
徴とする半導体装置。1. A first semiconductor region containing an impurity of a first conductivity type, and a second semiconductor region formed apart from the first semiconductor region and containing an impurity of a second conductivity type. A first semiconductor layer provided between the first semiconductor region and the second semiconductor region and containing a first conductivity type impurity; and a second semiconductor layer containing a second conductivity type impurity. A semiconductor device having a third semiconductor region in which a semiconductor layer is alternately and repeatedly arranged in a direction intersecting a direction in which the first semiconductor region and the second semiconductor region are opposed to each other, and the semiconductor device is alternately repeated. The arranged first semiconductor layer and second
Of the semiconductor layer of the second semiconductor layer is larger than that of the first semiconductor layer, and the carrier integration amount in the repeating direction of the second semiconductor layer is between the first semiconductor region and the second semiconductor layer. A fourth semiconductor region having an impurity concentration of the first conductivity type lower than that of the first semiconductor region is selectively formed in the first semiconductor region;
A semiconductor device , wherein a conductor region is in contact with the first semiconductor layer . 【請求項２】第１導電型の不純物が含有された第１の半
導体領域と、 前記第１の半導体領域と離間して形成され第２導電型の
不純物が含有された第２の半導体領域と、 前記第１の半導体領域と前記第２の半導体領域との間に
設けられ、第１導電型の不純物が含有された第１の半導
体層と第２導電型の不純物が含有された第２の半導体層
とが前記第１の半導体領域と第２の半導体領域とが対向
する方向と交差する方向に交互に繰り返し配置された第
３の半導体領域と、 を有する半導体装置であって、 交互に繰り返し配置された前記第１の半導体層及び第２
の半導体層の繰り返し方向のキャリア積分量が、第２の
半導体層の方が第１の半導体層よりも大きくなるように
構成され、 前記第１の半導体領域と前記第３の半導体領域の少なく
とも第２の半導体層との間に前記第１の半導体領域より
も第１導電型の不純物濃度の低い第４の半導体領域が形
成され、 前記第３の半導体領域の第２の半導体層は、前記第１の
半導体領域側の方が前記第２の半導体領域側よりも不純
物濃度が低くなるように構成された複数の半導体層から
なることを特徴とする半導体装置。2. A first half containing impurities of the first conductivity type.
A conductive region and a second conductive type that are formed apart from the first semiconductor region.
Between a second semiconductor region containing an impurity and the first semiconductor region and the second semiconductor region
A first semiconductor which is provided and contains impurities of a first conductivity type
Body layer and second semiconductor layer containing impurities of the second conductivity type
And the first semiconductor region and the second semiconductor region face each other.
Which are alternately arranged repeatedly in the direction intersecting
A semiconductor device having three semiconductor regions, the first semiconductor layer and the second semiconductor layer being alternately and repeatedly arranged.
The carrier integration amount in the repeating direction of the semiconductor layer of
So that the semiconductor layer is larger than the first semiconductor layer
It consists less of said first semiconductor region and the third semiconductor region
Between the first semiconductor region and the second semiconductor layer
Also has a fourth semiconductor region of the first conductivity type having a low impurity concentration.
A plurality of semiconductor layers of the second semiconductor layer of the third semiconductor region, the impurity concentration of which is lower on the first semiconductor region side than on the second semiconductor region side. A semiconductor device comprising:
JP27825599A 1999-09-30 1999-09-30 Semiconductor device Expired - Lifetime JP3507732B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27825599A JP3507732B2 (en) 1999-09-30 1999-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27825599A JP3507732B2 (en) 1999-09-30 1999-09-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2001102577A JP2001102577A (en) 2001-04-13
JP3507732B2 true JP3507732B2 (en) 2004-03-15

Family

ID=17594796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27825599A Expired - Lifetime JP3507732B2 (en) 1999-09-30 1999-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3507732B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231903A (en) * 2018-01-24 2018-06-29 重庆大学 A kind of soft superjunction power MOSFET for restoring body diode of band

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4924781B2 (en) * 1999-10-13 2012-04-25 株式会社豊田中央研究所 Vertical semiconductor device
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6713813B2 (en) 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
JP2002246595A (en) * 2001-02-19 2002-08-30 Shindengen Electric Mfg Co Ltd Transistor
US6878989B2 (en) 2001-05-25 2005-04-12 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
EP1267415A3 (en) * 2001-06-11 2009-04-15 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
JPWO2003065459A1 (en) 2002-01-28 2005-05-26 三菱電機株式会社 Semiconductor device
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
JP3634848B2 (en) 2003-01-07 2005-03-30 株式会社東芝 Power semiconductor device
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP2005175416A (en) * 2003-11-19 2005-06-30 Fuji Electric Device Technology Co Ltd Semiconductor device for use in space
KR100994719B1 (en) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 Superjunction semiconductor device
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
JP2006186145A (en) 2004-12-28 2006-07-13 Toshiba Corp Semiconductor device and manufacturing method thereof
WO2006108011A2 (en) 2005-04-06 2006-10-12 Fairchild Semiconductor Corporation Trenched-gate field effect transistors and methods of forming the same
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
JP5315058B2 (en) * 2006-12-07 2013-10-16 新電元工業株式会社 Semiconductor device and manufacturing method thereof
WO2009039441A1 (en) 2007-09-21 2009-03-26 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
CN102138206B (en) * 2008-09-01 2014-03-12 罗姆股份有限公司 Semiconductor device and manufacturing method thereof
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
JP6221436B2 (en) 2013-07-10 2017-11-01 富士電機株式会社 Superjunction MOSFET, manufacturing method thereof, and composite semiconductor device in which diodes are connected in parallel
CN105122458B (en) 2013-09-18 2018-02-02 富士电机株式会社 Semiconductor device and its manufacture method
CN104779296B (en) * 2015-04-24 2018-10-12 无锡同方微电子有限公司 A kind of asymmetric super node MOSFET structure and preparation method thereof
JP7257423B2 (en) * 2019-01-21 2023-04-13 日産自動車株式会社 Semiconductor device and its manufacturing method
CN113851542B (en) * 2021-09-24 2024-04-12 电子科技大学重庆微电子产业技术研究院 Super junction MOSFET with soft reverse recovery characteristic
CN116741812A (en) * 2023-08-11 2023-09-12 深圳天狼芯半导体有限公司 N-BAL-based super junction Schottky diode for improving current density and preparation method thereof
CN116722033A (en) * 2023-08-11 2023-09-08 深圳天狼芯半导体有限公司 Super junction schottky diode with improved P column and preparation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231903A (en) * 2018-01-24 2018-06-29 重庆大学 A kind of soft superjunction power MOSFET for restoring body diode of band
CN108231903B (en) * 2018-01-24 2020-06-02 重庆大学 Super junction power MOSFET with soft recovery body diode

Also Published As

Publication number Publication date
JP2001102577A (en) 2001-04-13

Similar Documents

Publication Publication Date Title
JP3507732B2 (en) Semiconductor device
US7531871B2 (en) Power semiconductor switching element
JP3799888B2 (en) Superjunction semiconductor device and method for manufacturing the same
US9825127B2 (en) Super junction semiconductor device with field extension zones
JP2000040822A (en) Superjunction semiconductor element and its manufacture
US20030235942A1 (en) Semiconductor device
JP2004511910A (en) Trench double diffused metal oxide semiconductor transistor incorporating trench Schottky rectifier
JP2003101022A (en) Power semiconductor device
JP2002314099A (en) Schottky diode and its manufacturing method
JP2008258443A (en) Semiconductor device for power and method for manufacturing the same
JPH08306937A (en) High-breakdown strength semiconductor device
JPH0457110B2 (en)
JPH10178174A (en) Semiconductor device and power converting device using the same
KR100194668B1 (en) Power insulated gate bipolar transistor
US7470960B1 (en) High-voltage power semiconductor device with body regions of alternating conductivity and decreasing thickness
JP2000269518A (en) Powering semiconductor device and method for forming semiconductor layer
JP2000509916A (en) Semiconductor device controllable by electric field effect
JP2001127285A (en) Vertical field-effect transistor
JPH0878668A (en) Semiconductor device for power
JP4770009B2 (en) Superjunction Schottky diode
JP2009105219A (en) Semiconductor device
JPH0620141B2 (en) Conduction modulation type MOSFET
JPH0992826A (en) Semiconductor device and its simulation method
KR100505562B1 (en) Insulated Gate Bipolar Transistor with Multi-Layer Buffer Structure and Manufacturing Method Thereof
EP0107773B1 (en) Thyristor with turn-off capability

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20031216

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20031219

R151 Written notification of patent or utility model registration

Ref document number: 3507732

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071226

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081226

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091226

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091226

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101226

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111226

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121226

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121226

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131226

Year of fee payment: 10

EXPY Cancellation because of completion of term