JP3505562B2 - Power supply circuit - Google Patents
Power supply circuitInfo
- Publication number
- JP3505562B2 JP3505562B2 JP15249298A JP15249298A JP3505562B2 JP 3505562 B2 JP3505562 B2 JP 3505562B2 JP 15249298 A JP15249298 A JP 15249298A JP 15249298 A JP15249298 A JP 15249298A JP 3505562 B2 JP3505562 B2 JP 3505562B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- power supply
- well region
- conductivity type
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、液晶表示装置な
どを駆動する電源回路（以下、駆動電源回路と称す）を
具備する半導体集積装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device having a power supply circuit (hereinafter referred to as a drive power supply circuit) for driving a liquid crystal display device or the like.
【０００２】[0002]
【従来の技術】図５は液晶パネルの走査線図と駆動回路
ブロック図である。液晶パネル６０はＣＯＭ走査線５３
（走査ライン）を形成したガラス基板と、ＳＥＧ走査線
５４（データライン）を形成したガラス基板を対向さ
せ、その基板間に液晶を充填した構造となっている。Ｃ
ＯＭ走査線５３とＳＥＧ走査線５４に電位を与え、これ
らの電位が与えられた走査線が交差する点で液晶が動作
する。2. Description of the Related Art FIG. 5 is a scanning line diagram and a drive circuit block diagram of a liquid crystal panel. The liquid crystal panel 60 has a COM scanning line 53.
The glass substrate on which the (scanning line) is formed and the glass substrate on which the SEG scanning line 54 (data line) is formed face each other, and liquid crystal is filled between the substrates. C
A potential is applied to the OM scan line 53 and the SEG scan line 54, and the liquid crystal operates at the intersection of the scan lines to which these potentials are applied.
【０００３】また、ＣＯＭ走査線５３の電位とＳＥＧ走
査線５４の電位の差、つまり、ＣＯＭ走査線５３とＳＥ
Ｇ走査線５４間の電圧の大きさと、この電圧の極性で液
晶の動作は変わってくる。これらの走査線に電位を与え
る回路がＣＯＭ駆動回路５１とＳＥＧ駆動回路５２であ
る。この液晶パネル６０と、液晶パネル６０のＣＯＭ走
査線５３およびＳＥＧ走査線５４を駆動するＣＯＭ駆動
回路５１およびＳＥＧ駆動回路５２と、これらの駆動回
路に電源を供給する駆動電源回路７０と、図示しない制
御信号を出力するロジック回路で液晶表示装置は構成さ
れている。Further, the difference between the potential of the COM scanning line 53 and the potential of the SEG scanning line 54, that is, the COM scanning line 53 and the SE.
The operation of the liquid crystal depends on the magnitude of the voltage between the G scan lines 54 and the polarity of this voltage. The circuits that give potentials to these scanning lines are the COM drive circuit 51 and the SEG drive circuit 52. The liquid crystal panel 60, the COM drive circuit 51 and the SEG drive circuit 52 that drive the COM scan line 53 and the SEG scan line 54 of the liquid crystal panel 60, the drive power supply circuit 70 that supplies power to these drive circuits, and not shown. A liquid crystal display device is configured by a logic circuit that outputs a control signal.
【０００４】この液晶パネル６０は、例えば、ＳＥＧ走
査線５４は１２８本、ＣＯＭ走査線５３は６４本で１２
８×６４のマトリックスで表示される。また、ＣＯＭ走
査線５３とＳＥＧ走査線５４の交点近傍は微小な浮遊コ
ンデンサＡが形成される。図６は液晶表示装置を駆動す
る従来の駆動電源回路図である。ここでは、図５の駆動
電源回路７０の詳細な回路図を示す。図示しないロジッ
ク回路の電源電圧ＶDDを４倍チャージポンプ回路９６で
４倍の電位レベルに昇圧（電位的にはマイナス方向）す
る。ここで４倍チャージポンプ回路９６とは、電源電圧
ＶDDを基準にしてマイナス側に４倍の電圧とする。つま
りＶDD−４×ＶDD＝−３×ＶDDの電圧とする回路のこと
をいう。This liquid crystal panel 60 has, for example, 128 SEG scanning lines 54 and 64 COM scanning lines 53.
It is displayed in an 8x64 matrix. In addition, a minute floating capacitor A is formed near the intersection of the COM scan line 53 and the SEG scan line 54. FIG. 6 is a conventional drive power supply circuit diagram for driving a liquid crystal display device. Here, a detailed circuit diagram of the drive power supply circuit 70 of FIG. 5 is shown. The power supply voltage VDD of a logic circuit (not shown) is boosted (potentially in the negative direction) by a quadruple charge pump circuit 96 to a quadruple potential level. Here, the quadruple charge pump circuit 96 is a quadruple voltage on the minus side with respect to the power supply voltage VDD. In other words, it means a circuit for setting a voltage of VDD-4 * VDD = -3 * VDD.
【０００５】Ｖ0 とＶEE間を可変抵抗Ｒ16も含めて抵抗
Ｒ11〜Ｒ15で抵抗分割し、各分割個所からそれぞれオペ
アンプ回路１０１（ここでは差動増幅器８１とｐＭＯＳ
ＦＥＴ８６および電流源回路９１で構成されるオペアン
プ回路のみを代表として示した。他の４個のオペアンプ
回路を上から１０２、１０３、１０４、１０５と符号を
付すこととする）を介してＶ0 ＝ＶDD、Ｖ01、Ｖ02 Ｖ
03、Ｖ04、Ｖ05の６種類の電位レベルを発生させる。こ
の回路ではオペアンプ回路１００を５個必要とする。Between V0 and VEE, including the variable resistor R16, is resistance-divided by resistors R11 to R15, and the operational amplifier circuit 101 (here, the differential amplifier 81 and pMOS, respectively) is divided from each division.
Only the operational amplifier circuit including the FET 86 and the current source circuit 91 is shown as a representative. The other four operational amplifier circuits will be labeled 102, 103, 104, and 105 from the top) and V0 = VDD, V01, V02 V
Six potential levels of 03, V04 and V05 are generated. This circuit requires five operational amplifier circuits 100.
【０００６】例えば、ＶDD＝３Ｖとし、４倍チャージポ
ンプ回路９６でＶEE＝−９Ｖとし、３Ｖ−（−９Ｖ）＝
１２Ｖを５等分分割した場合（６４分割の場合は一般
に、非等分分割であるが、ここでは単純化して５等分分
割とした）、つまり、可変抵抗を０Ωとした場合、ＶEE
O ＝ＶEEとなり、分割点の電位はＶ11＝３Ｖ−２．４Ｖ
＝０．６Ｖ、Ｖ12＝３Ｖ−（２．４Ｖ×２）＝−１．８
Ｖ、Ｖ13＝３Ｖ−（２．４Ｖ×３）＝−４．２Ｖ、Ｖ14
＝３Ｖ−（２．４Ｖ×４）＝−６．６Ｖ、Ｖ15＝ＶEE0
＝３Ｖ−（２．４Ｖ×５）＝−９Ｖとなる。可変抵抗を
調整することで、例えば、ＶEE0 が−９Ｖから−３Ｖ程
度に可変できる。For example, VDD = 3V, VEE = -9V in the quadruple charge pump circuit 96, 3V-(-9V) =
When 12V is divided into 5 equal parts (in the case of 64 divisions, it is generally non-equal division, but here it is simplified into 5 equal divisions), that is, when the variable resistance is 0Ω, VEE
O = VEE, and the potential at the dividing point is V11 = 3V-2.4V
= 0.6V, V12 = 3V- (2.4V × 2) =-1.8
V, V13 = 3V- (2.4V × 3) =-4.2V, V14
= 3V- (2.4V × 4) =-6.6V, V15 = VEE0
= 3V− (2.4V × 5) = − 9V. By adjusting the variable resistance, for example, VEE0 can be changed from -9V to -3V.
【０００７】この駆動電源回路７０は通常、可変抵抗で
調整したＶEE0 を用いて、このＶ0−ＶEE0 を５分割
し、Ｖ0 〜Ｖ05の６種類の電位レベルを発生させる電源
であり、これらの電位を図５のＣＯＭ駆動回路５１やＳ
ＥＧ駆動回路５２へ供給する。図６の回路のＶ01とＶ03
を出力するオペアンプ回路１０１、１０３では、ｐＭＯ
ＳＦＥＴがＶDD側に接続され電流源回路９１、９３がＶ
EE0 側に接続されている。またＶ02、Ｖ04、Ｖ05を出力
するオペアンプ回路１０２、１０４、１０５では、ｎＭ
ＯＳＦＥＴがＶEE0 側に接続され、電流源回路９２、９
４、９５がＶDD側に接続されている。This drive power supply circuit 70 is a power supply which normally uses VEE0 adjusted by a variable resistor to divide this V0-VEE0 into five to generate six potential levels V0 to V05. COM drive circuit 51 and S of FIG.
It is supplied to the EG drive circuit 52. V01 and V03 of the circuit of FIG.
In the operational amplifier circuits 101 and 103 that output
SFET is connected to VDD side and current source circuits 91 and 93 are V
It is connected to the EE0 side. Further, in the operational amplifier circuits 102, 104 and 105 which output V02, V04 and V05, nM
The OSFET is connected to the VEE0 side and the current source circuits 92 and 9 are connected.
4, 95 are connected to the VDD side.
【０００８】この駆動電源回路７０から出力されるＶ0
、Ｖ01、Ｖ02、Ｖ03、Ｖ04、Ｖ05の電位を図５のＣＯ
Ｍ駆動回路５１とＳＥＧ駆動回路５２の液晶駆動回路に
入力し、液晶パネル側へＣＯＭ出力およびＳＥＭ出力を
出力する。図７は図５のＣＯＭ駆動回路およびＳＥＧ駆
動回路の出力波形である。図６に示した駆動電源回路の
各電位レベルをＣＯＭ駆動回路５１およびＳＥＧ駆動回
路５２で時間的に変化させて、液晶パネル６０を駆動す
る。実線の波形はＣＯＭ出力１１１で、点線の波形はＳ
ＥＧ出力１１２である。このＣＯＭ出力１１１の電位が
ＣＯＭ走査線５３の電位となり、ＳＥＧ出力１１２の電
位がＳＥＧ走査線５４の電位となる。V0 output from the drive power supply circuit 70
, V01, V02, V03, V04, V05 are set to the CO of FIG.
It is input to the liquid crystal drive circuits of the M drive circuit 51 and the SEG drive circuit 52, and COM output and SEM output are output to the liquid crystal panel side. FIG. 7 shows output waveforms of the COM drive circuit and the SEG drive circuit of FIG. The liquid crystal panel 60 is driven by temporally changing each potential level of the drive power supply circuit shown in FIG. 6 by the COM drive circuit 51 and the SEG drive circuit 52. The solid line waveform is the COM output 111, and the dotted line waveform is S
The EG output 112. The potential of the COM output 111 becomes the potential of the COM scanning line 53, and the potential of the SEG output 112 becomes the potential of the SEG scanning line 54.
【０００９】ＣＯＭ出力１１１はＶ01を基準電位にＶ01
からＶ05へ、またＶ05からＶ01へ電位が変動し、さらに
Ｖ01からＶ04に基準電位を変えて、Ｖ04からＶ0 へ、Ｖ
0 からＶ04へ電位が変動する。また、ＳＥＧ出力１１２
はＶ02を基準電位に、Ｖ02からＶ0 へ、Ｖ0 からＶ02へ
電位が変動し、Ｖ02からＶ03に基準電位を変えて、Ｖ03
からＶ05へ、Ｖ05からＶ03へ電位が変動する。The COM output 111 has V01 as a reference potential and V01.
From V05 to V01, and from V05 to V01, the reference potential is further changed from V01 to V04, and from V04 to V0, V
The potential changes from 0 to V04. In addition, the SEG output 112
Changes from V02 to V0, from V0 to V02, and changes the reference potential from V02 to V03.
To V05 and V05 to V03.
【００１０】前記のように、ＣＯＭ出力１１１のＶ01、
Ｖ04はＳＥＧ出力１１２の電位が変動している場合に、
電位が固定されているので、非選択電位と呼ばれてい
る。またＳＥＧ出力１１２ではＶ02、Ｖ03が非選択電位
と呼ばれている。前記したように、ＣＯＭ出力１１１と
ＳＥＧ出力１１２の電位差が液晶パネル６０に印加され
て、画像が形成される。As described above, V01 of the COM output 111,
V04 is when the potential of SEG output 112 is fluctuating,
Since the potential is fixed, it is called non-selection potential. In the SEG output 112, V02 and V03 are called non-selection potentials. As described above, the potential difference between the COM output 111 and the SEG output 112 is applied to the liquid crystal panel 60 to form an image.
【００１１】[0011]
【発明が解決しようとする課題】この液晶パネル６０
は、前記したように、ＣＯＭ走査線５３とＳＥＧ走査線
５４の交差点近傍が液晶を介して対向しているので、微
小な浮遊コンデンサＡが多数配置された構造となる。図
６のＶ01、Ｖ03を出力するオペアンプ回路１０１、１０
３では、インピーダンスの高い電流源回路９１、９３が
ＶEE0 側に接続され、Ｖ02、Ｖ04、Ｖ05を出力するオペ
アンプ回路１０２、１０４、１０５では、インピーダン
スの高い電流源回路９２、９４、９５がＶDD側に接続さ
れている。そのために、図７のように、ＳＥＧ出力１１
２の電位が変化した瞬間に、液晶パネル６０の浮遊コン
デンサＡを介してＣＯＭ出力１１１に電位変動のノイズ
１０３、１０４（ヒゲ電圧ノイズ）が重畳する（図
８）。This liquid crystal panel 60
As described above, since the vicinity of the intersection of the COM scanning line 53 and the SEG scanning line 54 faces each other via the liquid crystal, a large number of minute floating capacitors A are arranged. Operational amplifier circuits 101 and 10 for outputting V01 and V03 in FIG.
In 3, the high impedance current source circuits 91, 93 are connected to the VEE0 side, and in the operational amplifier circuits 102, 104, 105 that output V02, V04, V05, the high impedance current source circuits 92, 94, 95 are on the VDD side. It is connected to the. Therefore, as shown in FIG. 7, the SEG output 11
At the moment when the potential of 2 changes, noise 103 and 104 (whisker voltage noise) of potential fluctuation are superimposed on the COM output 111 via the floating capacitor A of the liquid crystal panel 60 (FIG. 8).
【００１２】この重畳するノイズには、動作時のオペア
ンプ回路のインピーダンスの違いにより、大きなノイズ
１０３と小さなノイズ１０４の２種類ある。これらのノ
イズ１０３、１０４が液晶パネルの画質を悪化させる、
クロストークの原因となる。一方、これを防止するため
に、電流源回路９１〜９５のインピーダンスを下げる
と、今度は駆動電源回路７０の消費電流が増大する。There are two types of superposed noise, a large noise 103 and a small noise 104, depending on the difference in impedance of the operational amplifier circuit during operation. These noises 103 and 104 deteriorate the image quality of the liquid crystal panel,
It causes crosstalk. On the other hand, if the impedance of the current source circuits 91 to 95 is lowered in order to prevent this, the current consumption of the drive power supply circuit 70 increases this time.
【００１３】この発明の目的は、前記の課題を解決し
て、消費電流が小く、クロストークが発生しない駆動電
源回路を提供することにある。An object of the present invention is to solve the above problems and provide a driving power supply circuit which consumes less current and does not cause crosstalk.
【００１４】[0014]
【課題を解決するための手段】前記の目的を達成するた
めに、複数種類の電位レベルを発生させる電源回路にお
いて、グランド電位レベルと、単位電位レベルと、該単
位電位レベルを反転した反転単位電位レベルと、前記単
位電位レベルをチャージポンプ回路で高電位に変換した
高電位レベルと、該高電位レベルを反転した反転高電位
レベルの５種類の電位レベルを発生する構成とする。To achieve the above object, in a power supply circuit for generating a plurality of types of potential levels, a ground potential level, a unit potential level, and an inverted unit potential obtained by inverting the unit potential level. Five types of potential levels are generated: a level, a high potential level obtained by converting the unit potential level to a high potential by a charge pump circuit, and an inverted high potential level obtained by inverting the high potential level.
【００１５】前記電源回路は液晶表示装置を駆動するも
のであって、前記グランド電位を前記液晶表示装置の走
査ラインの非選択電位に用いるとよい。前記の電源回路
を半導体装置に集積するとよい。この半導体装置の形成
方法は、第１導電形の半導体基板の表面層に第２導電形
の第１ウエル領域を選択的に形成し、該第１ウエル領域
と離して、第２導電形の第２ウエル領域、第３ウエル領
域および第４ウエル領域をそれぞれ選択的に形成し、前
記第１ウエル領域の表面層に第１導電形の第５ウエル領
域を選択的に形成し、該第５ウエル領域の表面層に第２
導電形の第１ソース領域と第２導電形の第１ドレイン領
域を選択的にそれぞれ形成し、該第１ソース領域と該第
１ドレイン領域に挟まれた前記第５ウエル領域上に第１
ゲート絶縁膜を介して第１ゲート電極を形成して、第１
ｐチャネルＭＯＳＦＥＴを形成し、前記第２ウエル領域
の表面層に第１導電形の第２ソース領域と第２ドレイン
領域を選択的にそれぞれ形成し、該第２ソース領域と該
第２ドレイン領域に挟まれる第２ウエル領域上に第２ゲ
ート絶縁膜を介して第２ゲート電極を形成して、第２ｎ
チャネルＭＯＳＦＥＴを形成し、前記第３ウエル領域の
表面層に第１導電形の第３ソース領域と第３ドレイン領
域を選択的にそれぞれ形成し、該第３ソース領域と該第
３ドレイン領域に挟まれる第３ウエル領域上に第３ゲー
ト絶縁膜を介して第３ゲート電極を形成して、第３ｎチ
ャネルＭＯＳＦＥＴを形成し、前記第４ウエル領域の表
面層に第１導電形の第４ソース領域と第４ドレイン領域
を選択的にそれぞれ形成し、該第４ソース領域と該第４
ドレイン領域に挟まれる第４ウエル領域上に第４ゲート
絶縁膜を介して第４ゲート電極を形成して、第４ｎチャ
ネルＭＯＳＦＥＴを形成し、前記半導体基板の表面層に
第２導電形の第５ソース領域と第５ドレイン領域を選択
的にそれぞれ形成し、該第５ソース領域と該第５ドレイ
ン領域に挟まれる前記半導体基板上に第５ゲート絶縁膜
を介して第５ゲート電極を形成して、第５ｐチャネルＭ
ＯＳＦＥＴを形成し、前記半導体基板の表面層に第２導
電形の第６ソース領域と第６ドレイン領域を選択的にそ
れぞれ形成し、該第６ソース領域と該第６ドレイン領域
に挟まれる前記半導体基板上に第６ゲート絶縁膜を介し
て第６ゲート電極を形成して、第６ｐチャネルＭＯＳＦ
ＥＴを形成する。前記の第１ｐ、第５および第６のｐチ
ャネルＭＯＳＦＥＴと第２ないし第４ｎチャネルＭＯＳ
ＦＥＴを用いて電源回路を構成し、前記第１ｐチャネル
ＭＯＳＦＥＴのゲート電極の電位を浮遊（フローティン
グ）電位とするとよい。The power supply circuit drives a liquid crystal display device, and the ground potential is preferably used as a non-selection potential of a scanning line of the liquid crystal display device. The power supply circuit may be integrated in a semiconductor device. According to this method of forming a semiconductor device, a first well region of a second conductivity type is selectively formed on a surface layer of a semiconductor substrate of a first conductivity type, and the first well region of the second conductivity type is separated from the first well region of the second conductivity type. The second well region, the third well region and the fourth well region are selectively formed, and the fifth well region of the first conductivity type is selectively formed in the surface layer of the first well region. Second on the surface layer of the area
A first source region of conductivity type and a first drain region of second conductivity type are selectively formed, respectively, and a first region is formed on the fifth well region sandwiched between the first source region and the first drain region.
Forming a first gate electrode through the gate insulating film,
A p-channel MOSFET is formed, and a second source region and a second drain region of the first conductivity type are selectively formed in the surface layer of the second well region, and the second source region and the second drain region are formed. A second gate electrode is formed on the sandwiched second well region via a second gate insulating film, and a second n
A channel MOSFET is formed, a third source region and a third drain region of the first conductivity type are selectively formed in the surface layer of the third well region, and sandwiched between the third source region and the third drain region. A third gate electrode is formed on the third well region via a third gate insulating film to form a third n-channel MOSFET, and a fourth source region of the first conductivity type is formed on the surface layer of the fourth well region. And a fourth drain region are selectively formed, and the fourth source region and the fourth drain region are formed.
A fourth gate electrode is formed on the fourth well region sandwiched between the drain regions via a fourth gate insulating film to form a fourth n-channel MOSFET, and a fifth conductivity type fifth electrode is formed on the surface layer of the semiconductor substrate. A source region and a fifth drain region are selectively formed, and a fifth gate electrode is formed on the semiconductor substrate sandwiched by the fifth source region and the fifth drain region via a fifth gate insulating film. , 5th p channel M
An OSFET is formed, a sixth source region and a sixth drain region of the second conductivity type are selectively formed on a surface layer of the semiconductor substrate, and the semiconductor is sandwiched between the sixth source region and the sixth drain region. A sixth gate electrode is formed on the substrate via a sixth gate insulating film to form a sixth p-channel MOSF.
Form ET. The above-mentioned first p, fifth and sixth p-channel MOSFETs and second to fourth n-channel MOSs
It is preferable that a power supply circuit is configured by using the FET and the potential of the gate electrode of the first p-channel MOSFET is set to a floating potential.
【００１６】[0016]
【発明の実施の形態】図１はこの発明の第１実施例の液
晶パネルを駆動する半導体集積装置に形成された駆動電
源回路で、同図（ａ）はＶ1 、−Ｖ1 を発生する回路
で、同図（ｂ）はＶ0 、−Ｖ0 を発生する回路である。
同図（ａ）において、オペアンプ回路１を用いて構成さ
れた非反転増幅器１０の基準電圧ＶS に対して、可変抵
抗Ｒ1 を変えることで、Ｖ0 より低い任意のＶ1 を形成
し、反転チャージポンプ回路２で−Ｖ1 を発生させる。
例えば、基準電圧ＶS ＝１．２Ｖとし、（Ｒ1 ＋Ｒ2 ）
／Ｒ１＝２とすると、Ｖ1 ＝ＶS ×（Ｒ1 ＋Ｒ2 ）／Ｒ
1 ＝２．４Ｖ、−Ｖ1 ＝−２．４Ｖとなる。FIG. 1 shows a driving power supply circuit formed in a semiconductor integrated device for driving a liquid crystal panel according to a first embodiment of the present invention. FIG. 1 (a) shows a circuit for generating V1 and -V1. (B) of the figure shows a circuit for generating V0 and -V0.
In FIG. 1A, by changing the variable resistor R1 with respect to the reference voltage VS of the non-inverting amplifier 10 configured by using the operational amplifier circuit 1, an arbitrary V1 lower than V0 is formed and the inverting charge pump circuit is formed. At -2, -V1 is generated.
For example, when the reference voltage VS is 1.2 V, (R1 + R2)
/ R1 = 2, V1 = VS * (R1 + R2) / R
1 = 2.4V and -V1 = -2.4V.
【００１７】従って、同図（ａ）の回路でＶGND 、Ｖ1
、−Ｖ1 という３種類の電位レベルを発生させること
ができる。同図（ｂ）において、ロジック電源の電圧Ｖ
DDを、例えば、４倍チャージポンプ回路３の入力に入
れ、ＶDDの４倍の電圧をＶ0 として出力する。またこの
Ｖ0を反転チャージポンプ回路４に入力し、−Ｖ0 を出
力する。例えば、ＶDD＝３Ｖとすると、Ｖ0 ＝ＶDD×４
＝１２Ｖ、−Ｖ0 ＝−１２Ｖとなる。Therefore, in the circuit shown in FIG.
, -V1 can generate three types of potential levels. In the same figure (b), the voltage V of the logic power supply
For example, DD is input to the input of the 4 × charge pump circuit 3 and a voltage 4 × VDD is output as V 0. Further, this V0 is input to the inverting charge pump circuit 4 and -V0 is output. For example, if VDD = 3V, V0 = VDD × 4
= 12V, -V0 = -12V.
【００１８】従って、同図（ｂ）の回路でＶGND 、Ｖ1
、−Ｖ1 という３種類の電位レベルを発生させること
ができる。つまり、同図（ａ）と同図（ｂ）を組み合わ
せて駆動電源回路とすれば、インピーダンスの低いグラ
ンド電位ＶGND を中心として、プラス側にＶ1 、Ｖ0 マ
イナス側に−Ｖ1 、−Ｖ0 の５種類の電位レベルを発生
させることができる。Therefore, in the circuit shown in FIG. 2B, VGND and V1
, -V1 can generate three types of potential levels. That is, if a driving power supply circuit is formed by combining FIG. 11A and FIG. 11B, five types of V1 on the plus side, -V1 and -V0 on the minus side are centered around the ground potential VGND having a low impedance. Potential levels can be generated.
【００１９】図２は、この発明の第２実施例で、図１の
駆動電源回路の電位を用いて液晶パネルを駆動する出力
波形である。図１の駆動電源回路で、Ｖ1 、−Ｖ1 、Ｖ
0 、−Ｖ0 とグランド電位ＶGND の５種類の電位レベル
を発生させ、これらの電位レベルを組み合わせて、図５
のＣＯＭ駆動回路５１およびＳＥＧ駆動回路５２のＣＯ
Ｍ出力６とＳＥＧ出力７を発生させる。このインピーダ
ンスの低いグランド電位ＶGND を、図７の波形のＶ01、
Ｖ04に相当する非選択電位として用いる。FIG. 2 shows an output waveform for driving the liquid crystal panel by using the potential of the driving power supply circuit of FIG. 1 in the second embodiment of the present invention. In the drive power supply circuit of FIG. 1, V1, -V1, V
5 types of potential levels of 0, -V0 and the ground potential VGND are generated, and these potential levels are combined to obtain the result shown in FIG.
Of the COM drive circuit 51 and the SEG drive circuit 52 of
The M output 6 and the SEG output 7 are generated. The ground potential VGND with low impedance is V01,
It is used as a non-selection potential corresponding to V04.
【００２０】同図の実線はＣＯＭ出力６の波形で点線が
ＳＥＧ出力７の波形である。これらのＣＯＭ出力６の電
位とＳＥＧ出力７の電位の差の電圧が、液晶に印加され
る電圧であり、この電圧波形は、図７のＣＯＭ出力１１
１とＳＥＧ出力１１２間の電圧波形と同じである。図６
の駆動電源回路では、５個のオペアンプ回路１０１から
１０５が用いられているが、図１の駆動電源回路は１個
のオペアンプ回路１で構成される。そのため、消費電流
を小さくすることができる。The solid line in the figure is the waveform of the COM output 6, and the dotted line is the waveform of the SEG output 7. The voltage of the difference between the potential of the COM output 6 and the potential of the SEG output 7 is the voltage applied to the liquid crystal, and this voltage waveform has the COM output 11 of FIG.
1 and the SEG output 112 have the same voltage waveform. Figure 6
In the drive power supply circuit of No. 5, five operational amplifier circuits 101 to 105 are used, but the drive power supply circuit of FIG. 1 is composed of one operational amplifier circuit 1. Therefore, current consumption can be reduced.
【００２１】また、グランド電位ＶGND を非選択電位に
選定することで、回路インピーダンスが大幅に低減さ
れ、前記のヒゲ電圧であるノイズがＣＯＭ出力６に重畳
されることがなく、従って、クロストークも画面に現れ
ず、画質が向上する。図３はロジック回路とレベルシフ
ト回路および液晶駆動回路のブロック図である。この図
は、本発明の駆動電源回路４０の５種類の電位が、液晶
駆動回路５０を介して液晶パネル６０に与えられる様子
を示したブロック図である。Further, by selecting the ground potential VGND as the non-selection potential, the circuit impedance is significantly reduced, and the above-mentioned mustache voltage noise is not superimposed on the COM output 6, and therefore crosstalk also occurs. It does not appear on the screen and the image quality improves. FIG. 3 is a block diagram of a logic circuit, a level shift circuit, and a liquid crystal drive circuit. This figure is a block diagram showing a state in which five kinds of potentials of the drive power supply circuit 40 of the present invention are applied to the liquid crystal panel 60 via the liquid crystal drive circuit 50.
【００２２】ロジック回路４１とレベルシフト回路４２
とは液晶駆動回路５０（ＣＯＭ駆動回路とＳＥＧ駆動回
路をいう）を制御する信号回路である。レベルシフト回
路４２は低電位のロジック回路４１からの信号を高電位
レベルの信号にレベルシフトする回路である。また点線
で示した本発明の駆動電源回路４０からＶGND 、Ｖ1、
−Ｖ1 、Ｖ0 、−Ｖ0 の電位を液晶駆動回路５０へ与え
る。液晶駆動回路５０のＣＯＭ駆動回路とＳＥＧ駆動回
路からＣＯＭ出力、ＳＥＧ出力が点線で示した液晶パネ
ル６０に出力される。Logic circuit 41 and level shift circuit 42
Is a signal circuit for controlling the liquid crystal drive circuit 50 (referring to the COM drive circuit and the SEG drive circuit). The level shift circuit 42 is a circuit that shifts the signal from the low potential logic circuit 41 to a high potential level signal. Further, from the drive power supply circuit 40 of the present invention shown by the dotted line, VGND, V1,
The potentials -V1, V0, -V0 are applied to the liquid crystal drive circuit 50. The COM output and the SEG output from the COM drive circuit and the SEG drive circuit of the liquid crystal drive circuit 50 are output to the liquid crystal panel 60 shown by the dotted line.
【００２３】この発明の駆動電源回路４０を用いること
で、安定な（インピーダンスが低い）グランド電位ＶGN
D をＣＯＭ出力の非選択電位とすることができて、ノイ
ズの重畳が抑制されて、クロストークの発生を防止でき
る。また、この発明の駆動電源回路４０では、オペアン
プ回路はＶ1 の電位を発生させるのに用いだけで、−Ｖ
1 、Ｖ0 、−Ｖ0 の電位はチャージポンプを用いて行う
ため、従来、オペアンプ回路が５個必要であったものが
１個で済み、また消費電流の大幅な低減が図れる。By using the driving power supply circuit 40 of the present invention, a stable (low impedance) ground potential VGN is obtained.
D can be set to the non-selection potential of the COM output, the superposition of noise can be suppressed, and the occurrence of crosstalk can be prevented. Further, in the drive power supply circuit 40 of the present invention, the operational amplifier circuit is used only for generating the potential of V1, and -V
Since the potentials of 1, V0, and -V0 are controlled by using the charge pump, only one operational amplifier circuit, which conventionally required five operational amplifier circuits, is required, and the current consumption can be significantly reduced.
【００２４】図４は図３のブロック図の回路を形成する
ＣＭＯＳ半導体装置の要部断面図である。ｎ基板２１の
表面層にｐウエル２６を形成し、このｐウエル２６と離
して３個のｐウエル２２を形成する。ｐウエル２６の表
面層にｎウエル２７を形成し、このｎウエル２７の表面
層にｐソース２８とｐドレイン２９を形成する。これら
のｐソース２８とｐドレイン２９に挟まれたｎウエル２
７上にゲート絶縁膜を介してゲート３０を形成し、ＰＭ
ＯＳ３を形成する。FIG. 4 is a cross-sectional view of essential parts of a CMOS semiconductor device forming the circuit of the block diagram of FIG. A p well 26 is formed in the surface layer of the n substrate 21, and three p wells 22 are formed apart from the p well 26. An n well 27 is formed on the surface layer of the p well 26, and a p source 28 and a p drain 29 are formed on the surface layer of the n well 27. The n well 2 sandwiched between these p source 28 and p drain 29
7. A gate 30 is formed on the gate electrode 7 through a gate insulating film, and PM
Form OS3.
【００２５】またｐウエル２２の表面層にｎソース２３
とｎドレイン２４を形成し、ｎソース２３とｎドレイン
２４に挟まれたｐウエル２２の表面にゲート絶縁膜を介
してゲート２５を形成する。このようにしてＮＭＯＳ
１、ＮＭＯＳ２、ＮＭＯＳ３が形成される。またｎ基板
２１の表面層にｐソース３２とｐドレイン３１を形成
し、これらのｐソース３２とｐドレイン３１に挟まれた
ｎ基板２１上にゲート絶縁膜を介してゲート３３を形成
しＰＭＯＳ１、ＰＭＯＳ２を形成する。これらのＮＭＯ
Ｓ１、２、３とＰＭＯＳ１、２、３とでＣＭＯＳ半導体
装置が形成される。The n source 23 is formed on the surface layer of the p well 22.
And an n drain 24 are formed, and a gate 25 is formed on the surface of the p well 22 sandwiched between the n source 23 and the n drain 24 via a gate insulating film. In this way NMOS
1, NMOS2, NMOS3 are formed. Further, a p-source 32 and a p-drain 31 are formed on the surface layer of the n-substrate 21, and a gate 33 is formed on the n-substrate 21 sandwiched between the p-source 32 and the p-drain 31 via a gate insulating film to form the PMOS 1, The PMOS 2 is formed. These NMOs
A CMOS semiconductor device is formed by S1, 2, and 3 and PMOSs 1, 2, and 3.
【００２６】このＰＭＯＳ３はフローティングとなって
おり、ｐソース２８をロジック回路の電源電圧ＶDDに接
続する。またＰＭＯＳ３のｐドレイン２９とＮＭＯＳ３
のｎドレイン２４を接続し、ｎソース２３をグランド電
位ＶGND とする。またＮＭＯＳ１のｎソース２３に−Ｖ
0 を印加し、ＮＭＯＳ２のソース２３に−Ｖ1 を印加
し、ＰＭＯＳ２のｐソース３２にＶ1 を印加し、ＰＭＯ
Ｓ１のソース２３にＶ0を印加する。This PMOS 3 is floating and connects the p-source 28 to the power supply voltage VDD of the logic circuit. In addition, p-drain 29 of PMOS3 and NMOS3
N drain 24 is connected, and the n source 23 is set to the ground potential VGND. In addition, -V is applied to the n source 23 of NMOS1.
0 is applied, -V1 is applied to the source 23 of the NMOS2, V1 is applied to the p-source 32 of the PMOS2, and PMO is applied.
V0 is applied to the source 23 of S1.
【００２７】図示しない各種回路および点線で示すよう
に接続し、ＮＭＯＳ２、ＰＭＯＳ３、ＮＭＯＳ３および
ＰＭＯＳ２のゲートに制御信号を入れることで、Ｖ1 、
−Ｖ１、ＶGND の電位で構成される電圧波形（図２の点
線波形）が出力１から出力される。同様に一点鎖線のよ
うに接続して、出力２からＶ0 、−Ｖ0 、ＶGND の電位
で構成される電圧波形（図２の実線波形）を出力１から
出力することができる。Various circuits (not shown) are connected to each other as shown by a dotted line, and control signals are input to the gates of NMOS2, PMOS3, NMOS3 and PMOS2 to obtain V1,
A voltage waveform (dotted line waveform in FIG. 2) composed of the potentials of −V1 and VGND is output from the output 1. Similarly, the voltage waveform (solid line waveform in FIG. 2) composed of the potentials of V0, -V0, and VGND can be output from the output 2 from the output 1 by connecting as shown by the one-dot chain line.
【００２８】このように、フローティングＰＭＯＳを形
成することで、図２の出力波形を出力できる液晶駆動回
路を、本発明の駆動電源回路を形成した半導体集積装置
に集積できる。尚、前記した実施例ではｎ基板を用いた
場合を説明したが、ｐ基板を用いてプラスの４倍昇圧回
路としても同様の効果が期待できる。この場合はフロー
ティングＭＯＳはＰＭＯＳではなくＮＭＯＳとする。By thus forming the floating PMOS, the liquid crystal drive circuit capable of outputting the output waveform shown in FIG. 2 can be integrated in the semiconductor integrated device in which the drive power supply circuit of the present invention is formed. In addition, although the case where the n substrate is used has been described in the above-mentioned embodiment, the same effect can be expected even if the p substrate is used and the plus 4 times booster circuit is used. In this case, the floating MOS is NMOS instead of PMOS.
【００２９】[0029]
【発明の効果】この発明により、オペアンプ回路を４個
削減できて、消費電流を大幅に低減できる。また、安定
なグランド電位をＣＯＭ出力の非選択電位に活用できる
ために、クロストークの発生を防止できる。According to the present invention, the number of operational amplifier circuits can be reduced by 4, and the current consumption can be greatly reduced. Further, since the stable ground potential can be used as the non-selection potential of the COM output, the occurrence of crosstalk can be prevented.
【図１】この発明の第１実施例の液晶表示装置を駆動す
る半導体集積装置に形成された駆動電源回路で、同図
（ａ）はＶ1 、−Ｖ1 を発生する回路図で、同図（ｂ）
はＶ0 、−Ｖ0 を発生する回路図FIG. 1 is a drive power supply circuit formed in a semiconductor integrated device for driving a liquid crystal display device according to a first embodiment of the present invention. FIG. 1A is a circuit diagram for generating V1 and -V1. b)
Is a circuit diagram that generates V0 and -V0
【図２】この発明の第２実施例で、図１の駆動電源回路
の電位を用いて液晶パネルを駆動する出力波形図FIG. 2 is an output waveform diagram for driving a liquid crystal panel by using the potential of the driving power supply circuit of FIG. 1 in the second embodiment of the present invention.
【図３】ロジック回路とレベルシフト回路および液晶駆
動回路のブロック図FIG. 3 is a block diagram of a logic circuit, a level shift circuit, and a liquid crystal drive circuit.
【図４】図３のブロック図の回路を形成するＣＭＯＳ半
導体装置の要部断面図4 is a cross-sectional view of main parts of a CMOS semiconductor device forming the circuit of the block diagram of FIG.
【図５】液晶パネルの走査線図と駆動回路ブロック図FIG. 5 is a scanning line diagram of a liquid crystal panel and a drive circuit block diagram.
【図６】液晶表示装置を駆動する従来の駆動電源回路図FIG. 6 is a conventional drive power supply circuit diagram for driving a liquid crystal display device.
【図７】図５のＣＯＭ駆動回路およびＳＥＧ駆動回路の
出力波形図FIG. 7 is an output waveform diagram of the COM drive circuit and the SEG drive circuit of FIG.
【図８】ノイズが重畳されたＣＯＭ出力波形図FIG. 8 is a COM output waveform diagram on which noise is superimposed.
１ オペアンプ回路 ２ 反転チャージポンプ回路 ３ ４倍チャージポンプ回路 ４ 反転チャージポンプ回路 ６ ＣＯＭ出力 ７ ＳＥＧ出力 ２１ ｎ基板 ２２、２６ ｐウエル ２３ ｎソース ２４ ｎドレイン ２５、３０、３３ ゲート ２７ ｎウエル ２８、３２ ｐソース ２９、３１ ｐドレイン ４０ 駆動電源回路（本発明） ４１ ロジック回路 ４２ レベルシフト ５０ 液晶駆動回路 ５１ ＣＯＭ駆動回路 ５２ ＳＥＧ駆動回路 ５３ ＣＯＭ走査線 ５４ ＳＥＧ走査線 ６０ 液晶パネル ７０ 駆動電源回路（従来） ＶDD ロジック回路電源電圧 ＶGND グランド電位 ＶS 基準電圧 Ｒ1 可変抵抗 Ｒ2 抵抗 Ｖ0 、Ｖ1 、Ｖ01、Ｖ02、Ｖ03、Ｖ04、Ｖ05 電位 ＮＭＯＳ１〜３ ｎチャネルＭＯＳＦＥＴ ＰＭＯＳ１〜３ ｐチャネルＭＯＳＦＥＴ 1 Opamp circuit 2 Inversion charge pump circuit 34x charge pump circuit 4 Inversion charge pump circuit 6 COM output 7 SEG output 21 n substrate 22, 26 p well 23 n source 24 n drain 25, 30, 33 gates 27 n-well 28, 32 p source 29, 31 p drain 40 drive power supply circuit (present invention) 41 Logic circuit 42 level shift 50 LCD drive circuit 51 COM drive circuit 52 SEG drive circuit 53 COM scan line 54 SEG scan line 60 LCD panel 70 Drive power supply circuit (conventional) VDD logic circuit power supply voltage VGND Ground potential VS reference voltage R1 variable resistor R2 resistance V0, V1, V01, V02, V03, V04, V05 potential NMOS 1-3 n-channel MOSFET PMOS 1-3 p-channel MOSFET
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 27/04 (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 3/07 G02F 1/133 G09G 3/20 G09G 3/36 H01L 21/822 H01L 27/04 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 identification code FI H01L 27/04 (58) Fields investigated (Int.Cl. 7 , DB name) H02M 3/07 G02F 1/133 G09G 3/20 G09G 3/36 H01L 21/822 H01L 27/04
Claims (3)
電位レベルを発生させる電源回路において、グランド電
位レベルと、単位電位レベルと、該単位電位レベルを反
転した反転単位電位レベルと、前記単位電位レベルをチ
ャージポンプ回路で高電位に変換した高電位レベルと、
該高電位レベルを反転した反転高電位レベルの５種類の
電位レベルを発生し、前記グランド電位を前記液晶表示
装置の走査ラインの非選択電位に用いることを特徴とす
る電源回路。1. A power supply circuit for generating a plurality of types of potential levels for driving a liquid crystal display device, wherein a ground potential level, a unit potential level, an inverted unit potential level obtained by inverting the unit potential level, and the unit. A high potential level obtained by converting the potential level to a high potential by a charge pump circuit,
The ground potential is generated in the liquid crystal display by generating five kinds of potential levels, which are inverted high potential levels obtained by inverting the high potential level.
A power supply circuit characterized by being used for a non-selection potential of a scanning line of a device .
集積したことを特徴とする電源回路。2. A power supply circuit comprising the power supply circuit according to claim 1 integrated in a semiconductor device.
電形の第１ウエル領域を選択的に形成し、該第１ウエル
領域と離して、第２導電形の第２ウエル領域、第３ウエ
ル領域および第４ウエル領域をそれぞれ選択的に形成
し、前記第１ウエル領域の表面層に第１導電形の第５ウ
エル領域を選択的に形成し、該第５ウエル領域の表面層
に第２導電形の第１ソース領域と第２導電形の第１ドレ
イン領域を選択的にそれぞれ形成し、該第１ソース領域
と該第１ドレイン領域に挟まれた前記第５ウエル領域上
に第１ゲート絶縁膜を介して第１ゲート電極を形成し
て、第１ｐチャネルＭＯＳＦＥＴを形成し、 前記第２ウエル領域の表面層に第１導電形の第２ソース
領域と第２ドレイン領域を選択的にそれぞれ形成し、該
第２ソース領域と該第２ドレイン領域に挟まれる第２ウ
エル領域上に第２ゲート絶縁膜を介して第２ゲート電極
を形成して、第２ｎチャネルＭＯＳＦＥＴを形成し、 前記第３ウエル領域の表面層に第１導電形の第３ソース
領域と第３ドレイン領域を選択的にそれぞれ形成し、該
第３ソース領域と該第３ドレイン領域に挟まれる第３ウ
エル領域上に第３ゲート絶縁膜を介して第３ゲート電極
を形成して、第３ｎチャネルＭＯＳＦＥＴを形成し、 前記第４ウエル領域の表面層に第１導電形の第４ソース
領域と第４ドレイン領域を選択的にそれぞれ形成し、該
第４ソース領域と該第４ドレイン領域に挟まれる第４ウ
エル領域上に第４ゲート絶縁膜を介して第４ゲート電極
を形成して、第４ｎチャネルＭＯＳＦＥＴを形成し、 前記半導体基板の表面層に第２導電形の第５ソース領域
と第５ドレイン領域を選択的にそれぞれ形成し、該第５
ソース領域と該第５ドレイン領域に挟まれる前記半導体
基板上に第５ゲート絶縁膜を介して第５ゲート電極を形
成して、第５ｐチャネルＭＯＳＦＥＴを形成し、 前記半導体基板の表面層に第２導電形の第６ソース領域
と第６ドレイン領域を選択的にそれぞれ形成し、該第６
ソース領域と該第６ドレイン領域に挟まれる前記半導体
基板上に第６ゲート絶縁膜を介して第６ゲート電極を形
成して、第６ｐチャネルＭＯＳＦＥＴを形成し、 前記第１ｐ、第５および第６のｐチャネルＭＯＳＦＥＴ
と第２ないし第４ｎチャネルＭＯＳＦＥＴを用いて電源
回路を構成し、前記第１ｐチャネルＭＯＳＦＥＴの前記
第５ウエル領域を浮遊（フローティング）構造とするこ
とを特徴とする請求項２に記載の電源回路。3. A second well region of the second conductivity type is selectively formed in a surface layer of a semiconductor substrate of the first conductivity type, and is separated from the first well region. , A third well region and a fourth well region are selectively formed, and a fifth well region of the first conductivity type is selectively formed in a surface layer of the first well region, and a surface of the fifth well region is formed. A first source region of a second conductivity type and a first drain region of a second conductivity type are selectively formed in the layer, and on the fifth well region sandwiched between the first source region and the first drain region. A first p-channel MOSFET by forming a first gate electrode via a first gate insulating film, and forming a second source region and a second drain region of the first conductivity type on the surface layer of the second well region. Selectively formed respectively, the second source region and the second drain A second gate electrode is formed on a second well region sandwiched by the regions via a second gate insulating film to form a second n-channel MOSFET, and a surface layer of the third well region has a first conductivity type first The third source region and the third drain region are selectively formed, and the third gate electrode is formed on the third well region sandwiched by the third source region and the third drain region via the third gate insulating film. Then, a third n-channel MOSFET is formed, and a fourth source region and a fourth drain region of the first conductivity type are selectively formed in the surface layer of the fourth well region, and the fourth source region and the fourth drain region are formed. A fourth gate electrode is formed on a fourth well region sandwiched between the four drain regions via a fourth gate insulating film to form a fourth n-channel MOSFET, and a second conductivity type first gate electrode is formed on the surface layer of the semiconductor substrate. 5 source area A fifth drain region selectively formed respectively, fifth
A fifth gate electrode is formed on the semiconductor substrate sandwiched by the source region and the fifth drain region via a fifth gate insulating film to form a fifth p-channel MOSFET, and a second layer is formed on the surface layer of the semiconductor substrate. Selectively forming a sixth source region and a sixth drain region of conductivity type, and
A sixth gate electrode is formed on the semiconductor substrate sandwiched between the source region and the sixth drain region via a sixth gate insulating film to form a sixth p-channel MOSFET, and the first p, fifth and sixth p-channel MOSFETs are formed. P-channel MOSFET
When constitute a power supply circuit with a second through 4n channel MOSFET, the said first 1p channel MOSFET
The power supply circuit according to claim 2, wherein the fifth well region has a floating structure .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15249298A JP3505562B2 (en) | 1998-06-02 | 1998-06-02 | Power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15249298A JP3505562B2 (en) | 1998-06-02 | 1998-06-02 | Power supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11346473A JPH11346473A (en) | 1999-12-14 |
| JP3505562B2 true JP3505562B2 (en) | 2004-03-08 |
Family
ID=15541659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15249298A Expired - Fee Related JP3505562B2 (en) | 1998-06-02 | 1998-06-02 | Power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3505562B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4001856B2 (en) * | 2003-10-30 | 2007-10-31 | ローム株式会社 | LIGHT EMITTING ELEMENT DRIVE DEVICE, DISPLAY MODULE HAVING LIGHT EMITTING ELEMENT DRIVE DEVICE, AND ELECTRONIC DEVICE HAVING DISPLAY MODULE |
-
1998
- 1998-06-02 JP JP15249298A patent/JP3505562B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11346473A (en) | 1999-12-14 |
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