JP3474914B2 - Automatic balancing device - Google Patents
Automatic balancing deviceInfo
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- JP3474914B2 JP3474914B2 JP04979894A JP4979894A JP3474914B2 JP 3474914 B2 JP3474914 B2 JP 3474914B2 JP 04979894 A JP04979894 A JP 04979894A JP 4979894 A JP4979894 A JP 4979894A JP 3474914 B2 JP3474914 B2 JP 3474914B2
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Description
【発明の詳細な説明】
【0001】
【産業上の利用分野】本発明は、インピーダンスメータ
で用いられる自動平衡装置に関し、特に誤差が少なく高
精度且つ高速なインピーダンス測定を可能とする自動平
衡装置に関する。
【0002】
【従来の技術】被測定試料のインピーダンスを測定する
インピーダンスメータでは、試料に信号源を接続し、試
料に印加される電圧Vと、試料に流れる電流Iに基づい
て試料のインピーダンスZをZ=V/Iとして求めてい
る。この電流Iは、図5に示すように、信号源12が供
給された試料11と接地間に、既知の抵抗値Rrをもつ
基準素子(抵抗)13を直列に接続し、試料11と基準
素子13の接続点の電圧Viを測定して、I=Vi/R
rとして求めることができる。このとき、試料11と基
準抵抗13の接続点Pに、接地との間に浮遊容量Cpや
絶縁抵抗Rp等から成るアドミタンスYpをもつ浮遊ア
ドミタンス14があると、試料11に流れた電流の一部
が浮遊アドミタンスYpに分流して電流検出誤差が発生
し、高精度なインピーダンスの測定が困難になる。
【0003】かかる問題を解決するには、図6に示すよ
うな、試料11と基準抵抗13の接続点の電位を略接地
電位と等しくするような信号源15を付加した構成をも
つ、云わゆるハーフブリッジ型の自動平衡装置が実用化
されている。
【0004】上記ハーフブリッジ型の自動平衡装置は、
信号源15を安価な演算増幅器を用いて構成している
が、高い周波数領域では演算増幅器の利得が周波数に反
比例して低下し、浮遊容量を主成分とする浮遊アドミタ
ンスは周波数に比例して増大するため、接地への分流電
流に起因する電流の検出誤差は周波数の2乗に比例して
大きくなるという問題がある。
【0005】そこで、本願発明者は、かかる問題点を軽
減した、図7に示すような、自動平衡装置を提案してい
る(特開平4−204267号)。
【0006】この自動平衡装置は、試料21と、この試
料21に流れる電流を電圧に変換する基準素子23とを
直列に接続し、試料21の基準素子23と接続されない
端子側を信号源22で駆動し、試料21と基準素子23
との接続点Pの信号を基準電位に平衡させる自動平衡装
置であり、試料21と基準素子23との接続点の信号を
増幅する演算増幅器24と、演算増幅器24の出力信号
を記憶して、その後、補償信号として発生する補償信号
発生装置25と、補償信号発生装置25から発生される
補償信号と、演算増幅器24からの出力信号とを加算し
て、基準素子23の試料21と接続されていない端子側
から試料21と基準素子23との接続点に帰還する加算
器27とを設けて構成されている。
【0007】
【発明が解決しようとする課題】以上説明したように、
特開平4−204267号において提案した自動平衡装
置では、演算増幅器の出力と同じ信号を発生する補償信
号発生装置を用いて、試料21と基準素子(基準抵抗)
23との接続点の電位を基準電位に保って平衡度を改善
している。
【0008】しかしながら、近年、使用される周波数領
域は益々高周波数領域に拡大しており、また更に、高精
度且つ高速な測定を可能とするインピーダンス測定装置
が望まれている等の事情から、上記のような自動平衡装
置では十分な精度で且つ高速なインピーダンス測定が困
難である。
【0009】例えば、周波数が高くなると、増幅器の利
得が低下し、1回の補償操作で得られる平衡度の改善率
が低下してしまう。また、補償器の入出力間の利得や位
相にずれがあると、1回の補償操作で得られる平衡度の
改善率が低下する。更に、補償操作1回当りの平衡度の
改善率が低下すると、補償操作を多数回繰り返さないと
十分な平衡状態に達せず、高速なインピーダンス測定が
できない。
【0010】上述のような自動平衡装置では、補償信号
発生装置25として演算増幅器(増幅回路)24の出力
波形を略そのままの形で記憶し出力する回路を用いた場
合、このような補償信号発生装置は完全にハードウェア
で構成でき、補償操作は十分高速に繰り返し実行できる
ので、補償操作を多数回繰り返しても、十分な平衡度に
達するのにそれほど時間はかからない。しかし、このよ
うなハードウェア構成は複雑で大型になるため、集積回
路化できない少量生産機種では高価になる欠点があっ
た。
【0011】これに対して、演算増幅器(増幅回路)か
らの出力信号をベクトル電圧計で測定し、位相と振幅を
任意に設定できる発振器を制御して補償信号を発生する
ような補償信号発生装置を用いれば、利得や位相の調整
を含めて、ソフトウェアで処理できる部分が多いため、
ハードウェア構成は簡単となり、安価に作成できる。ま
た、装置の製造時に、補償回路の入力から出力までの伝
達関数を”1”に調整して、1回の補償操作で得られる
平衡度の改善率を向上することも比較的容易である。
【0012】しかしながら、この手法では、増幅手段の
利得が極端に低下する高い周波数になると、1回の補償
操作で得られる平衡度の改善率が低下し、補償操作を多
数回繰り返さないと十分な平衡度に達しない。こうなる
と、前記ベクトル電圧の測定などに時間を要するこの手
法では、十分な平衡度に達するまでに時間がかかる欠点
があった。
【0013】そこで、本発明は、いかなる条件であって
も、補償操作の少ない繰り返しで、十分な平衡度に到達
する自動平衡装置を提供することを目的とする。すなわ
ち、本発明の目的は、高精度且つ高速なインピーダンス
測定を可能とする自動平衡装置を提供することにある。
【0014】
【課題を解決するための手段】前述の課題を解決するた
めに本発明の自動平衡装置は、試料の第1の端子に直列
に接続される所定のインピーダンスをもつ基準素子と、
前記基準素子と接続されない前記試料の第2の端子に電
源を供給する信号源を有し、前記試料と前記基準素子の
接続点の電位を所定の基準電位に平衡させる自動平衡装
置において、前記試料の第1の端子からの信号を増幅す
る増幅手段と、該増幅手段の出力側に接続され、補償信
号を生成して出力する補償手段と、該補償手段からの補
償信号と前記増幅手段からの出力信号を加算し、得られ
た加算信号を、前記基準素子の前記試料と接続されてい
ない端子に供給する加算手段とを備え、前記補償手段
は、前記補償手段の出力から入力に至る外部回路の伝達
関数を求め、得られた伝達関数と前記補償手段の出力信
号と前記増幅手段の出力信号とに基づいて、前記増幅手
段の出力信号をゼロにするのに必要な新たな補償信号を
生成して出力するように構成される。
【0015】
【作用】本発明では、第2の端子に信号源から電源が供
給されている試料の第1の端子に、基準素子が直列に接
続され、上記第1の端子からの信号を増幅する増幅手段
に補償信号を生成する補償手段が接続され、上記補償信
号と増幅手段の出力信号の加算信号が上記基準素子を介
して上記増幅手段にフィードバック入力される構成を有
し、上記補償手段は、補償手段の出力から入力に至る外
部回路の伝達関数を求め、得られた伝達関数と前記補償
手段の出力信号と前記増幅手段の出力信号とに基づい
て、増幅手段の出力信号をゼロにするのに必要な新たな
補償信号を生成することにより、上記試料と基準素子の
接続点の電位を所定の基準電位に平衡させている。
【0016】
【実施例】次に、本発明の実施例について図面を参照し
ながら説明する。図1は本発明による自動平衡装置の一
実施例を示す構成ブロック図である。本実施例において
は、試料1の一端側が信号源2に接続され、他端側が基
準素子(抵抗)3に接続され、また試料1と基準素子3
の接続点が演算増幅器5の反転入力端子に接続され、非
反転入力端子が基準電位(接地電位)に接続されてい
る。演算増幅器5の出力は加算器4と補償回路6に供給
され、加算器4には、演算増幅器5の出力信号と補償回
路6の出力信号とが供給され、加算信号が基準素子3を
経て演算増幅器5の反転入力端子に帰還入力されてい
る。ここで、信号源2は、出力Eを発生する信号発生回
路と、出力インピーダンスZsとして表現され、基準素
子3のインピーダンスをZr、演算増幅器5の利得をA
とする。
【0017】補償回路6は、演算増幅器5からの出力信
号に基づいて、該演算増幅器5の出力信号をゼロにする
のに必要な補償信号を生成して加算器4に出力する。補
償回路6での補償信号の生成は次のように行なわれる。
【0018】先ず、補償回路6から任意の初期設定され
た信号V1を出力する。このときの補償回路6への入力
信号、すなわち演算増幅器5の出力信号X1を測定す
る。尚、図1では、Vn及びXnと一般化して示してい
る。
【0019】次に、補償回路6の出力を、信号V1とは
異なる信号V2に設定し、このときの補償回路6への入
力(演算増幅器5の出力)X2を測定する。
【0020】補償回路6の出力から入力に至る伝達関数
Gを、入力変化に対する出力変化の割合として、次の
(1)式を求める。
G=(X2−X1)/(V2−V1) (1)
【0021】続いて、伝達関数G、演算増幅器5の現在
の出力信号X2、補償回路の現在の出力信号V2から、
演算増幅器5の出力信号をゼロにするような出力信号V
3を(2)式により求める。
V3=V2−(X2/G) (2)
【0022】ここで、X2よりX1の方が小さい場合に
は、次のような(3)式を用いることもできる。
V3=V1−(X1/G) (3)
【0023】以上のように補償信号を生成して、帰還す
ることにより、簡単に平衡状態が達成される.一方、実
際の装置では、補償回路6の入力信号を測定するときの
分解能や、補償回路の出力設定分解能が十分でなかった
り、回路の一部に非線形特性を有する部分があると、上
記一回の操作、処理では十分な平衡度に達しない場合が
ある。このような場合には、増幅回路(演算増幅器)の
出力信号が十分ゼロに近くなるまで、演算増幅器の出力
を測定し、(2)式または(3)式に基づいて補償信号
を生成する操作、処理を繰り返せば良い。
【0024】上述操作、処理により十分な平衡度に達す
るので、以後は適当な時間間隔で、上記増幅回路の出力
測定及び(2)式、または(3)式に基づく補償信号の
生成処理を繰り返すことにより、必要な平衡度を維持で
きる。
【0025】また、試料の交換等により平衡度が著しく
悪化したときは、もしそれによって伝達関数Gも大きく
変化している可能性があるならば、新たに、前述の補償
回路6からの初期設定信号V1の設定、補償回路6への
入力の測定、補償回路6からのV2(≠V1)の生成出
力、(1)式に基づく伝達関数Gの算出及び、(2)式
または(3)式に基づく補償信号の生成処理を行なう。
【0026】本実施例による処理を、図2の各部信号の
ベクトル図を参照して説明する。補償回路6から出力さ
れる初期設定補償ベクトル信号V1に対して、測定で得
られる入力ベクトル信号X1、補償ベクトル信号V2に
対して得られる入力ベクトル信号X2が図示のような関
係にあると、伝達関数Gは、(1)式に基づいて、ベク
トル信号X1及びX2の差ベクトルと、ベクトル信号V
1及びV2の差ベクトルの比で求まる。補償回路6への
入力、つまり演算増幅器5の出力ベクトル信号X3がゼ
ロになるような補償ベクトル信号V3は、(2)式に基
づいて、ベクトル信号V2からX2/Gを減算して得ら
れるベクトル信号V3として得られることになる。
【0027】以上の実施例において、信号V1は前回の
補償信号そのもの、あるいはゼロとするのが簡単である
が、回路や試料の特性が変化しない範囲ならば任意の値
でよい。もし信号源2の電圧Eをゼロにできれば、V1
=0のときX1=0になるので、信号V1に対する測定
は行わなくて済むが、装置の製造時ではなく、インピー
ダンス測定時に伝達関数を求める場合は、試料にかかる
信号が大きく変化して、そのインピーダンスを変化させ
る恐れがあるので望ましくない。
【0028】ここで、信号V2は、信号V1と等しくな
ければ原理的には任意の値でよいが、|V2−V1|お
よび|X2−X1|があまりにも小さいと、その測定精
度が十分でなくなるので、これらの精度、したがって伝
達関数の精度が十分確保できるだけ信号V1の値から離
れた値に信号V2を設定する。|X2−X1|の下限値
XL、|V2−V1|の下限値VL、Gの概略値G0は
設計時に決まるので、次の式を満たすように信号V1と
V2の値を決める。
|V2−V1|≧VL (4)
|V2−V1|≧XL/|G0| (5)
ただし、|V2−V1|を大きくし過ぎると、演算増幅
器が飽和したり、伝達関数Gの非線形性が強くなって、
十分な平衡度が得られないことがある。また、増幅回路
の利得が十分でないとき|V2−V1|を大きくする
と、試料にかかる電圧が大きな割合で変動することがあ
り、ヒステリシスのある試料の測定では測定値の再現性
を悪化させる。したがって、特にインピーダンスの測定
中に伝達関数Gを求めるときは、|V2−V1|を必要
最小限の大きさにすることが望ましい。補償回路の出力
を信号V1の値の周辺のいくつかの値に設定して増幅回
路の出力を測定し、V1から各方向へ向かっての伝達関
数を求めれば、伝達関数の非線形性を確認することもで
きる。
【0029】ところで、図1の構成におけるP点からQ
点までの伝達関数Gqpは次式(6)で与えられる。変
化分のみ考えればよいので、信号源の出力電圧Eは考慮
する必要はない。実際にEは任意の値でよい。
Gqp=−A・Zx/{(1+A)Zx+Zr} (6)
ここで、
Zx:試料のインピーダンスZdut+信号源の出力イン
ピーダンスZs
Zr:基準素子のインピーダンス
A :増幅器としての演算増幅器の利得
|Zx|≧|Zr|、且つ|A|>>1であれば、Gq
pは約−1で一定となる。このように、条件が良いとき
は、製造時に一度、前述操作により伝達関数Gを求めて
おけばよく、インピーダンス測定時には、(2)式や
(3)式に基づく補償信号の生成操作のみを行えばよ
い。周波数が高くなって|A|>>1の条件が満足され
なくなると、Zxの値やAの変動によって伝達関数が大
きく変化するため、インピーダンス測定ごとに伝達関数
Gを求めて平衡操作を行なった方が有利である
【0030】図3には、上述実施例における補償回路6
の具体的な構成ブロック図が示されている。演算増幅器
5からの出力信号は、帯域通過フィルタ611で所望の
帯域の信号が抽出され、利得調整器612でレベルが調
整された後、A/Dコンバータ613で、クロック発生
器621からのクロックに基づいてデジタルデータに変
換される。A/Dコンバータ613からのデジタルデー
タは、アドレス発生器620から発生されるアドレス信
号によって書き込み及び読み出しが制御され、メモリと
しての、例えば、書き込みと読み出しを独立に実行でき
るデュアルポートメモリ614に書き込まれる。デュア
ルポートメモリ614には、例えば、波形情報が複数周
期分書き込まれる。
【0032】デュアルポートメモリ614から読み出さ
れたデジタルデータは、デジタル信号処理回路(DS
P)615に送出され、前述操作処理(演算増幅器5の
出力信号の検出、伝達関数Gの導出等)により必要な振
幅と位相をもつ正弦波のデジタル補償信号V3に対応す
る信号を生成してデュアルポートメモリ616に格納す
る。すなわち、デジタル信号処理回路615は、補償回
路6の出力信号と、演算増幅器5の出力信号とから、演
算増幅器5の出力をゼロにするのに必要な補償回路6の
出力信号の新たな値を算出して、出力信号として出力す
る。デジタル信号処理回路615における処理は、フー
リエ積分等の公知の方法での処理であり、演算増幅器5
の出力信号をベクトルとして求めることができる。
【0033】デュアルポートメモリ616から読み出さ
れたデータは、D/Aコンバータ617でアナログ信号
に変換され、帯域通過フィルタ618で所定帯域成分の
みが抽出されて利得調整器619でレベル調整され、前
述補償信号V3として加算器4に供給される。補償信号
V3は、加算器4で演算増幅器5からの出力信号と加算
され、基準素子3の一端を駆動する。
【0034】ここで、デジタル信号処理回路615の処
理が十分高速であれば、デュアルポートメモリ614は
省略できる。
【0035】前記手順により求められる伝達関数は、こ
の実施例ではDSPの出力から入力までの伝達関数に相
当し、途中の経路に存在する帯域通過フィルタや利得調
整器など全ての構成要素の特性を含む。この伝達関数
は、前記補償回路6の出力から入力までの伝達関数とは
異なるが、演算増幅器5の出力信号がゼロのとき、DS
Pの入力信号がゼロになるのであるから、この実施例に
おいても、前記手順で平衡度の改善率を向上できるのは
明らかである。また、帯域通過フィルタや利得調整器の
特性が予め分かっていなくても、また変化しても、全体
の伝達関数に含めて測定されるので、平衡度の改善率が
悪化することはない。
【0036】図3に示す構成において、帯域通過フィル
タ611,618は、測定信号周波数付近の信号のみを
通し、不要雑音を低減するために用いられているが、必
ずしも必要ではない。
【0037】利得調整器612は、A/Dコンバータ6
13の分解能を補う目的で用いられており、A/Dコン
バータ613の入力信号がその変換範囲を越えず、且
つ、なるべく変換範囲いっぱいに変化するように、増幅
回路の出力信号に応じてその利得を調整するが、必ずし
も必要ではない。
【0038】利得調整器619は、D/Aコンバータ6
17の分解能や出力信号の範囲の不足を補う目的で用い
られており、D/Aコンバータ617をなるべく変換範
囲いっぱいのデータで駆動するように、補償回路6の出
力に応じてその利得を調整するが、必ずしも必要ではな
い。
【0039】クロック発生器621は、A/D変換速度
およびD/A変換速度を決めるクロック信号を発生す
る。そのクロック信号は、A/Dコンバータ613,D
/Aコンバータ617及びアドレス発生器620に供給
される。アドレス発生器620は、メモリとしてのデュ
アルポートメモリ614,616のアドレスを発生す
る。測定周波数が1MHzの場合、クロック周波数を、
例えば16MHzにする。
【0040】アドレス発生器620は、このクロックに
同期して順次16種類のアドレスを発生し、デュアルポ
ートメモリ614,616に与える。これら2つのメモ
リで同じアドレスを用いれば、補償回路6の入力検出と
出力設定における信号の位相関係を常に一定に保つこと
ができる。複数周期分のアドレスを発生させて、デュア
ルポートメモリ614に取り込むサンプル数を多くすれ
ば、平均化により等価雑音レベルを下げ、演算増幅器5
の出力信号の検出感度を上げることもできる。
【0041】純粋2進アドレスを用いると、アドレスの
最上位ビットの変化周波数が測定信号の周波数に一致し
て測定に妨害を与えることがあるので、アドレスを疑似
ランダム信号にしてもよい。また、クロック周波数を測
定周波数の整数倍である16MHzからずらして、例え
ば15.5MHzや15.2MHzにして、それぞれ2
周期、5周期分の信号を記憶手段に格納するなどして
も、測定信号に対する妨害を低減できる。このようにす
ると、サンプリング位相の種類が増加するので、フーリ
エ積分などで信号の基本波成分を求めるときに、増幅手
段の出力信号の高調波成分をより高い次数まで消去でき
るとともに、雑音やA/D変換回路の量子化誤差の影響
を平均化作用によって低減できる効果もある。クロック
周波数を測定周波数の15.5倍にして、アドレスを疑
似ランダム信号にしたときの、アドレスとデータの例を
図4に示す。
【0042】前掲特開平4−204267号には、A/
D変換回路やD/A変換回路の分解能の不足を補う方
法、演算増幅器の出力雑音を軽減する方法、A/D変換
回路の変換速度の不足を補う方法、安定化インピーダン
スを用いて演算増幅器の利得を上げる方法等が図1〜図
11を参照して記載されているが、これらの補助的な手
法と、本発明を組み合わせて使用できるのは明白であ
る。
【0043】以上の実施例においては、増幅手段の利得
が低くなる高い周波数においても補償操作の少ない繰り
返しで十分な平衡度を得ることができるので、インピー
ダンスを短時間で測定することができる。また、補償回
路の入力や出力にフィルタ等が設けられていて、それら
の伝達関数が変化しても、補償操作当たりの平衡度の改
善率が悪化しない。
【0044】
【発明の効果】以上説明したように、本発明の自動平衡
装置によれば、最小限の補償操作で十分な平衡度が得ら
れ、インピーダンス測定を高精度且つ高速に行なうこと
ができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic balancing device used in an impedance meter, and more particularly to an automatic balancing device which has a small error and enables high-accuracy and high-speed impedance measurement. . 2. Description of the Related Art In an impedance meter for measuring the impedance of a sample to be measured, a signal source is connected to the sample, and the impedance Z of the sample is measured based on a voltage V applied to the sample and a current I flowing through the sample. It is determined as Z = V / I. As shown in FIG. 5, this current I is obtained by connecting a reference element (resistance) 13 having a known resistance value Rr in series between the sample 11 supplied with the signal source 12 and the ground, The voltage Vi at the connection point No. 13 is measured, and I = Vi / R
r can be obtained. At this time, if there is a floating admittance 14 having an admittance Yp including a stray capacitance Cp and an insulation resistance Rp between the ground and the connection point P between the sample 11 and the reference resistor 13, a part of the current flowing through the sample 11 Is diverted to the floating admittance Yp, and a current detection error occurs, making it difficult to measure impedance with high accuracy. In order to solve such a problem, a configuration is adopted in which a signal source 15 is added as shown in FIG. 6 so that the potential at the connection point between the sample 11 and the reference resistor 13 is substantially equal to the ground potential. A half-bridge type automatic balancer has been put to practical use. [0004] The above half-bridge type automatic balancer comprises:
Although the signal source 15 is configured using an inexpensive operational amplifier, in a high frequency region, the gain of the operational amplifier decreases in inverse proportion to the frequency, and the floating admittance mainly composed of the floating capacitance increases in proportion to the frequency. Therefore, there is a problem in that a current detection error caused by a shunt current to the ground increases in proportion to the square of the frequency. Therefore, the inventor of the present application has proposed an automatic balancing device as shown in FIG. 7 in which such a problem is reduced (Japanese Patent Laid-Open No. 4-204267). In this automatic balancing apparatus, a sample 21 and a reference element 23 for converting a current flowing through the sample 21 into a voltage are connected in series, and a terminal of the sample 21 not connected to the reference element 23 is connected to a signal source 22. Driving, the sample 21 and the reference element 23
An automatic amplifier for amplifying a signal at a connection point between the sample 21 and the reference element 23, and an output signal of the operation amplifier 24, After that, a compensation signal generator 25 generated as a compensation signal, a compensation signal generated from the compensation signal generator 25, and an output signal from the operational amplifier 24 are added and connected to the sample 21 of the reference element 23. An adder 27 is provided which feeds back from a non-terminal side to a connection point between the sample 21 and the reference element 23. [0007] As described above,
In the automatic balancing device proposed in Japanese Patent Application Laid-Open No. 4-204267, a sample 21 and a reference element (reference resistance) are used by using a compensation signal generator that generates the same signal as the output of the operational amplifier.
The equilibrium degree is improved by keeping the potential at the connection point with the reference 23 at the reference potential. However, in recent years, the frequency range used has been expanding to a higher and higher frequency range, and an impedance measuring apparatus capable of high-precision and high-speed measurement has been desired. It is difficult to measure impedance with sufficient accuracy and at high speed with an automatic balancing device such as the one described above. For example, as the frequency increases, the gain of the amplifier decreases, and the rate of improvement in the degree of balance obtained by one compensation operation decreases. Further, if there is a shift in the gain or phase between the input and output of the compensator, the rate of improvement in the degree of balance obtained by one compensation operation is reduced. Further, when the rate of improvement of the degree of balance per one compensation operation is reduced, a sufficient balance state cannot be reached unless the compensation operation is repeated many times, and high-speed impedance measurement cannot be performed. In the above-described automatic balancing apparatus, when a circuit for storing and outputting the output waveform of the operational amplifier (amplifier circuit) 24 in almost the same form as the compensation signal generator 25 is used, such a compensation signal generator is used. The device can be completely configured in hardware and the compensation operation can be performed repeatedly fast enough so that a large number of repetitions of the compensation operation do not take much time to reach a sufficient degree of equilibrium. However, since such a hardware configuration is complicated and large, there is a disadvantage in that a small production model that cannot be integrated is expensive. On the other hand, a compensation signal generator for measuring an output signal from an operational amplifier (amplifier circuit) with a vector voltmeter and controlling an oscillator capable of arbitrarily setting a phase and an amplitude to generate a compensation signal. If you use, there are many parts that can be processed by software, including adjustment of gain and phase,
The hardware configuration is simple and can be created at low cost. Also, it is relatively easy to adjust the transfer function from the input to the output of the compensation circuit to "1" at the time of manufacturing the device to improve the balance improvement rate obtained by one compensation operation. However, in this method, at a high frequency at which the gain of the amplifying means extremely decreases, the rate of improvement of the degree of balance obtained by one compensation operation decreases, and it is not sufficient unless the compensation operation is repeated many times. Does not reach equilibrium. In this case, this method, which requires time for the measurement of the vector voltage, has a disadvantage that it takes time to reach a sufficient degree of equilibrium. SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic balancing device that can achieve a sufficient balance with a small number of repetitions of the compensation operation under any conditions. That is, an object of the present invention is to provide an automatic balancing device that enables high-accuracy and high-speed impedance measurement. In order to solve the above-mentioned problems, an automatic balancing apparatus according to the present invention comprises: a reference element having a predetermined impedance connected in series to a first terminal of a sample;
An automatic balancing device that has a signal source that supplies power to a second terminal of the sample that is not connected to the reference element and that balances a potential at a connection point between the sample and the reference element to a predetermined reference potential; Amplifying means for amplifying a signal from the first terminal, a compensating means connected to the output side of the amplifying means for generating and outputting a compensation signal, a compensating signal from the compensating means and a signal from the amplifying means. An adding circuit that adds an output signal and supplies the obtained added signal to a terminal of the reference element that is not connected to the sample, wherein the compensating means includes an external circuit from an output to an input of the compensating means. Communication
A function is obtained, and the obtained transfer function and the output signal of the compensation means are obtained.
And generating and outputting a new compensation signal required to make the output signal of the amplifying means zero based on the signal and the output signal of the amplifying means. According to the present invention, a reference element is connected in series to a first terminal of a sample whose power is supplied from a signal source to a second terminal, and a signal from the first terminal is amplified. A compensating means for generating a compensation signal is connected to the amplifying means, and a sum signal of the compensation signal and the output signal of the amplifying means is fed back to the amplifying means via the reference element, Is the output from the output of the compensation means to the input.
The transfer function of the partial circuit is obtained, and the obtained transfer function and the compensation
Based on the output signal of the means and the output signal of the amplifying means.
Te, by generating a new compensation signal required for the output signal of the amplifying means to zero, thereby balancing the potential of the connection point of the sample and the reference element to a predetermined reference potential. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the automatic balancing apparatus according to the present invention. In this embodiment, one end of the sample 1 is connected to the signal source 2, the other end is connected to the reference element (resistance) 3, and the sample 1 and the reference element 3 are connected.
Is connected to the inverting input terminal of the operational amplifier 5, and the non-inverting input terminal is connected to the reference potential (ground potential). The output of the operational amplifier 5 is supplied to an adder 4 and a compensating circuit 6. The output signal of the operational amplifier 5 and the output signal of the compensating circuit 6 are supplied to the adder 4, and the added signal is calculated via the reference element 3. The signal is fed back to the inverting input terminal of the amplifier 5. Here, the signal source 2 is represented by a signal generating circuit for generating an output E and an output impedance Zs. The impedance of the reference element 3 is Zr, and the gain of the operational amplifier 5 is A.
And The compensating circuit 6 generates a compensating signal necessary to make the output signal of the operational amplifier 5 zero based on the output signal from the operational amplifier 5 and outputs the signal to the adder 4. The generation of the compensation signal in the compensation circuit 6 is performed as follows. First, an arbitrary initially set signal V1 is output from the compensation circuit 6. At this time, the input signal to the compensation circuit 6, that is, the output signal X1 of the operational amplifier 5 is measured. In FIG. 1, Vn and Xn are generalized. Next, the output of the compensation circuit 6 is set to a signal V2 different from the signal V1, and the input (output of the operational amplifier 5) X2 to the compensation circuit 6 at this time is measured. The transfer function G from the output to the input of the compensating circuit 6 is defined as the following equation (1) as the ratio of the output change to the input change. G = (X2-X1) / (V2-V1) (1) Subsequently, from the transfer function G, the current output signal X2 of the operational amplifier 5, and the current output signal V2 of the compensation circuit,
An output signal V that makes the output signal of the operational amplifier 5 zero.
3 is obtained by equation (2). V3 = V2- (X2 / G) (2) Here, when X1 is smaller than X2, the following equation (3) can be used. V3 = V1- (X1 / G) (3) As described above, by generating and feeding back a compensation signal, a balanced state is easily achieved. On the other hand, in an actual device, if the resolution when measuring the input signal of the compensating circuit 6 or the output setting resolution of the compensating circuit is not sufficient, or if a part of the circuit has a non-linear characteristic, the above-described one-time operation is performed. In some cases, the degree of equilibrium may not be reached in the operation and processing described above. In such a case, the operation of measuring the output of the operational amplifier until the output signal of the amplifier circuit (operational amplifier) is sufficiently close to zero and generating a compensation signal based on the equation (2) or (3) is performed. The process may be repeated. Since a sufficient degree of balance is reached by the above operation and processing, thereafter, at an appropriate time interval, the output measurement of the amplifier circuit and the processing of generating a compensation signal based on the equation (2) or (3) are repeated. Thereby, the required degree of equilibrium can be maintained. If the degree of equilibrium is significantly deteriorated due to the exchange of a sample or the like, if there is a possibility that the transfer function G is also largely changed by this, a new initial setting from the compensation circuit 6 described above is newly performed. Setting of signal V1, measurement of input to compensation circuit 6, generation output of V2 (生成 V1) from compensation circuit 6, calculation of transfer function G based on equation (1), and equation (2) or (3) Is performed on the basis of the compensation signal. The processing according to the present embodiment will be described with reference to the vector diagram of each signal in FIG. If the input vector signal X1 obtained by the measurement and the input vector signal X2 obtained from the compensation vector signal V2 have the relationship shown in the drawing with respect to the initial setting compensation vector signal V1 output from the compensation circuit 6, the signal is transmitted. The function G is based on the equation (1), and the difference vector between the vector signals X1 and X2 and the vector signal V
It is determined by the ratio of the difference vector between 1 and V2. The input to the compensation circuit 6, that is, the compensation vector signal V3 such that the output vector signal X3 of the operational amplifier 5 becomes zero is a vector obtained by subtracting X2 / G from the vector signal V2 based on the equation (2). It will be obtained as signal V3. In the above embodiment, it is easy to set the signal V1 to the previous compensation signal itself or to zero, but any value may be used as long as the characteristics of the circuit and the sample do not change. If the voltage E of the signal source 2 can be made zero, V1
When X = 0, X1 = 0, so that the measurement for the signal V1 does not need to be performed. However, when the transfer function is obtained not at the time of manufacturing the device but at the time of measuring the impedance, the signal applied to the sample greatly changes. It is not desirable because impedance may be changed. Here, the signal V2 may be an arbitrary value in principle if it is not equal to the signal V1, but if | V2-V1 | and | X2-X1 | are too small, the measurement accuracy is sufficient. Therefore, the signal V2 is set to a value as far as possible from the value of the signal V1 as far as these accuracy, and hence the accuracy of the transfer function, can be sufficiently ensured. Since the lower limit value XL of | X2-X1 | and the lower limit value VL of | V2-V1 | and the approximate value G0 of G are determined at the time of design, the values of the signals V1 and V2 are determined so as to satisfy the following equation. | V2-V1 | ≧ VL (4) | V2-V1 | ≧ XL / | G0 | (5) However, if | V2-V1 | is too large, the operational amplifier may be saturated or the transfer function G may be non-linear. Has become stronger,
Sufficient equilibrium may not be obtained. Also, if | V2−V1 | is increased when the gain of the amplifier circuit is not sufficient, the voltage applied to the sample may fluctuate at a large rate, and the reproducibility of the measured value is deteriorated in the measurement of a sample having hysteresis. Therefore, it is desirable to make | V2−V1 | the minimum necessary especially when calculating the transfer function G during the measurement of the impedance. The output of the compensation circuit is set to some values around the value of the signal V1, the output of the amplifier circuit is measured, and the transfer function from V1 in each direction is determined, thereby confirming the nonlinearity of the transfer function. You can also. By the way, from the point P in the configuration of FIG.
The transfer function Gqp up to the point is given by the following equation (6). It is not necessary to consider the output voltage E of the signal source because only the change is considered. In fact, E may be any value. Gqp = −A · Zx / {(1 + A) Zx + Zr} (6) Here, Zx: impedance of sample Zdut + output impedance of signal source Zs Zr: impedance of reference element A: gain of operational amplifier as amplifier | Zx | ≧ If | Zr | and | A | >> 1, Gq
p is constant at about -1. As described above, when the conditions are good, the transfer function G may be obtained by the above-described operation once at the time of manufacture, and only the operation of generating a compensation signal based on the equations (2) and (3) is performed at the time of impedance measurement. Just do it. When the frequency becomes higher and the condition of | A | >> 1 is no longer satisfied, the transfer function greatly changes due to the change of the value of Zx or A, and therefore the balance operation was performed by obtaining the transfer function G for each impedance measurement. FIG. 3 shows the compensation circuit 6 in the above embodiment.
Is shown in FIG. From the output signal from the operational amplifier 5, a signal in a desired band is extracted by the band-pass filter 611, the level is adjusted by the gain adjuster 612, and then the A / D converter 613 converts the output signal to the clock from the clock generator 621. It is converted into digital data based on it. The digital data from the A / D converter 613 is written and read by an address signal generated from an address generator 620, and is written into a memory, for example, a dual port memory 614 that can execute writing and reading independently. . For example, waveform information for a plurality of cycles is written in the dual port memory 614. The digital data read from the dual port memory 614 is stored in a digital signal processing circuit (DS).
P) 615, and generates a signal corresponding to the sine wave digital compensation signal V3 having the required amplitude and phase by the above-described operation processing (detection of the output signal of the operational amplifier 5, derivation of the transfer function G, etc.). The data is stored in the dual port memory 616. That is, the digital signal processing circuit 615 calculates a new value of the output signal of the compensating circuit 6 necessary for making the output of the operational amplifier 5 zero from the output signal of the compensating circuit 6 and the output signal of the operational amplifier 5. It is calculated and output as an output signal. The processing in the digital signal processing circuit 615 is processing by a known method such as Fourier integration and the like.
Can be obtained as a vector. The data read from the dual port memory 616 is converted into an analog signal by a D / A converter 617, only a predetermined band component is extracted by a band pass filter 618, and the level is adjusted by a gain adjuster 619. The compensation signal V3 is supplied to the adder 4. The compensation signal V3 is added to the output signal from the operational amplifier 5 by the adder 4, and drives one end of the reference element 3. Here, if the processing of the digital signal processing circuit 615 is sufficiently fast, the dual port memory 614 can be omitted. The transfer function obtained by the above procedure corresponds to the transfer function from the output to the input of the DSP in this embodiment, and the characteristics of all the components such as the band-pass filter and the gain adjuster existing on the intermediate path are determined. Including. This transfer function is different from the transfer function from the output to the input of the compensation circuit 6, but when the output signal of the operational amplifier 5 is zero, DS
Since the input signal of P becomes zero, it is clear that the above-described procedure can also improve the rate of improvement of the degree of balance in this embodiment. Further, even if the characteristics of the band-pass filter and the gain adjuster are not known in advance or change, the measurement is included in the entire transfer function, so that the improvement rate of the degree of balance does not deteriorate. In the configuration shown in FIG. 3, the band-pass filters 611 and 618 are used to reduce unnecessary noise by passing only signals near the measurement signal frequency, but are not always necessary. The gain adjuster 612 includes the A / D converter 6
13 so as to compensate for the resolution of the A / D converter 613. The gain of the A / D converter 613 is adjusted according to the output signal of the amplifier circuit so that the input signal does not exceed the conversion range and changes as much as possible. Is adjusted, but not necessary. The gain adjuster 619 includes the D / A converter 6
It is used for compensating for the lack of the resolution of 17 or the range of the output signal, and adjusts the gain according to the output of the compensation circuit 6 so as to drive the D / A converter 617 with data as much as possible in the conversion range. However, it is not always necessary. The clock generator 621 generates a clock signal for determining an A / D conversion speed and a D / A conversion speed. The clock signal is supplied to A / D converters 613 and D
/ A converter 617 and an address generator 620. The address generator 620 generates addresses of the dual port memories 614 and 616 as memories. When the measurement frequency is 1 MHz, the clock frequency is
For example, it is set to 16 MHz. The address generator 620 sequentially generates 16 types of addresses in synchronization with this clock, and supplies them to the dual port memories 614 and 616. If the same addresses are used in these two memories, the phase relationship between signals in input detection and output setting of the compensation circuit 6 can be always kept constant. If addresses for a plurality of cycles are generated and the number of samples taken into the dual port memory 614 is increased, the equivalent noise level is lowered by averaging, and the operational amplifier 5
, The detection sensitivity of the output signal can be increased. If a pure binary address is used, the change frequency of the most significant bit of the address may coincide with the frequency of the measurement signal and interfere with the measurement, so that the address may be a pseudo-random signal. In addition, the clock frequency is shifted from 16 MHz which is an integral multiple of the measurement frequency, for example, to 15.5 MHz or 15.2 MHz, and each is 2 MHz.
Even if signals for five periods are stored in the storage means, interference with the measurement signal can be reduced. In this case, the number of types of sampling phases increases. Therefore, when the fundamental component of the signal is obtained by Fourier integration or the like, the harmonic component of the output signal of the amplifying means can be eliminated up to a higher order, and noise and A / A There is also an effect that the influence of the quantization error of the D conversion circuit can be reduced by the averaging operation. FIG. 4 shows an example of addresses and data when the clock frequency is 15.5 times the measurement frequency and the address is a pseudo random signal. In the above-mentioned Japanese Patent Application Laid-Open No. 4-204267, A /
A method for compensating for the lack of resolution of the D-conversion circuit and the D / A conversion circuit, a method for reducing the output noise of the operational amplifier, a method for compensating for the lack of the conversion speed of the A / D conversion circuit, Although the method of increasing the gain and the like are described with reference to FIGS. 1 to 11, it is obvious that these auxiliary methods can be used in combination with the present invention. In the above embodiment, even at a high frequency at which the gain of the amplifying means is low, a sufficient degree of balance can be obtained with a small number of repetitions of the compensation operation, so that the impedance can be measured in a short time. Also, filters and the like are provided at the input and output of the compensation circuit, and even if their transfer functions change, the rate of improvement of the degree of balance per compensation operation does not deteriorate. As described above, according to the automatic balancing apparatus of the present invention, a sufficient degree of balance can be obtained with a minimum compensation operation, and impedance measurement can be performed with high accuracy and at high speed. .
【図面の簡単な説明】
【図1】本発明による自動平衡装置の一実施例を示す構
成ブロック図である。
【図2】本実施例による処理を示す各部信号のベクトル
図である。
【図3】本実施例における補償回路6の具体的な構成ブ
ロック図である。
【図4】本実施例におけるデュアルポートメモリ614
に対して、クロック周波数を測定周波数の15.5倍に
して、アドレスを疑似ランダム信号にしたときのアドレ
スとデータ例を示す図である。
【図5】従来の自動平衡装置の一例を示す構成ブロック
図である。
【図6】従来の自動平衡装置の他の例を示す構成ブロッ
ク図である。
【図7】従来の自動平衡装置の更に他の例を示す構成ブ
ロック図である。
【符号の説明】
1 試料
2 信号源
3 基準素子
4 加算器
5 演算増幅器
6 補償回路BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram showing one embodiment of an automatic balancing device according to the present invention. FIG. 2 is a vector diagram of signals of respective parts showing processing according to the embodiment. FIG. 3 is a specific configuration block diagram of a compensation circuit 6 in the present embodiment. FIG. 4 is a dual port memory 614 according to the present embodiment.
FIG. 4 is a diagram showing an example of addresses and data when the clock frequency is set to 15.5 times the measurement frequency and the address is converted into a pseudo random signal. FIG. 5 is a configuration block diagram showing an example of a conventional automatic balancing device. FIG. 6 is a configuration block diagram showing another example of the conventional automatic balancing device. FIG. 7 is a configuration block diagram showing still another example of the conventional automatic balancing device. [Description of Signs] 1 Sample 2 Signal source 3 Reference element 4 Adder 5 Operational amplifier 6 Compensation circuit
Claims (1)
のインピーダンスをもつ基準素子と、前記基準素子と接
続されない前記試料の第2の端子に電源を供給する信号
源を有し、前記試料と前記基準素子の接続点の電位を所
定の基準電位に平衡させる自動平衡装置において、 前記試料の第1の端子からの信号を増幅する増幅手段
と、 該増幅手段の出力側に接続され、補償信号を生成して出
力する補償手段と、 該補償手段からの補償信号と前記増幅手段からの出力信
号を加算し、得られた加算信号を、前記基準素子の前記
試料と接続されていない端子に供給する加算手段と、 を備え、前記補償手段は、前記補償手段の出力から入力
に至る外部回路の伝達関数を求め、得られた伝達関数と
前記補償手段の出力信号と前記増幅手段の出力信号とに
基づいて、前記増幅手段の出力信号をゼロにするのに必
要な新たな補償信号を生成して出力することを特徴とす
る自動平衡装置。(57) Claims: 1. A reference element having a predetermined impedance connected in series to a first terminal of a sample, and a power supply connected to a second terminal of the sample not connected to the reference element. An automatic balancing device that has a signal source that supplies a signal and supplies a potential at a connection point between the sample and the reference element to a predetermined reference potential. A compensating means connected to the output side of the amplifying means for generating and outputting a compensation signal; adding the compensation signal from the compensating means and the output signal from the amplifying means; Adding means for supplying a terminal of the element not connected to the sample, wherein the compensating means receives an input from an output of the compensating means.
The transfer function of the external circuit that leads to
The output signal of the compensation means and the output signal of the amplification means
An automatic balancing device for generating and outputting a new compensation signal required to make the output signal of the amplifying means zero based on the output signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04979894A JP3474914B2 (en) | 1994-02-23 | 1994-02-23 | Automatic balancing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04979894A JP3474914B2 (en) | 1994-02-23 | 1994-02-23 | Automatic balancing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07234256A JPH07234256A (en) | 1995-09-05 |
JP3474914B2 true JP3474914B2 (en) | 2003-12-08 |
Family
ID=12841174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP04979894A Expired - Fee Related JP3474914B2 (en) | 1994-02-23 | 1994-02-23 | Automatic balancing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3474914B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5016235B2 (en) * | 2006-03-02 | 2012-09-05 | アジレント・テクノロジーズ・インク | Current-voltage converter and impedance measuring device |
JP7221670B2 (en) * | 2018-12-10 | 2023-02-14 | 矢崎総業株式会社 | Impedance measurement jig and impedance measurement method |
-
1994
- 1994-02-23 JP JP04979894A patent/JP3474914B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH07234256A (en) | 1995-09-05 |
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