JP3448015B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP3448015B2
JP3448015B2 JP2000224985A JP2000224985A JP3448015B2 JP 3448015 B2 JP3448015 B2 JP 3448015B2 JP 2000224985 A JP2000224985 A JP 2000224985A JP 2000224985 A JP2000224985 A JP 2000224985A JP 3448015 B2 JP3448015 B2 JP 3448015B2
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region
buried
type
concentration
impurity
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JP2002043562A (en
Inventor
誠治 十河
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、高耐圧特性を有し
ながらオン抵抗を低くすることができる横型半導体装置
及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral semiconductor device having a high breakdown voltage characteristic and a low on-resistance, and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】高耐圧特性を有しながらオン抵抗を低く
することができる横型半導体装置については、従来から
様々な構造が提案されており、その一例として、特許公
報第３０１６７６２号に示されている半導体装置につい
て、図６を参照しながら説明する。2. Description of the Related Art Conventionally, various structures have been proposed for a lateral semiconductor device having a high withstand voltage characteristic and a low on-resistance, and an example thereof is disclosed in Japanese Patent Publication No. 3016762. The semiconductor device which is present will be described with reference to FIG.

【０００３】図６に示すように、ｐ型の半導体基板１０
には、ｎ型領域からなるソース領域１１及びｎ型領域か
らなる延長ドレイン領域１２がそれぞれ形成されてい
る。As shown in FIG. 6, a p-type semiconductor substrate 10 is provided.
A source region 11 made of an n-type region and an extended drain region 12 made of an n-type region are formed in each.

【０００４】延長ドレイン領域１２の表面部にはｎ型高
濃度領域１３が形成されていると共に、延長ドレイン領
域１２におけるｎ型高濃度領域１３の下方にはｐ型埋め
込み領域１４が形成されている。ｎ型高濃度領域１３は
ドレイン電極１５と接続されていると共に、ｐ型埋め込
み領域１４は半導体基板１０と接続されている。An n-type high concentration region 13 is formed on the surface of the extended drain region 12, and a p-type buried region 14 is formed below the n-type high concentration region 13 in the extended drain region 12. . The n-type high concentration region 13 is connected to the drain electrode 15, and the p-type buried region 14 is connected to the semiconductor substrate 10.

【０００５】半導体基板１０の表面部にはソース領域１
１と隣接するようにｐ型の基板コンタクト領域１６が形
成されており、ソース領域１１及び基板コンタクト領域
１６はソース電極１７に接続されている。これによっ
て、ソース領域１１は半導体基板１０と同電位に設定さ
れる。また、半導体基板１０にはソース領域１１及び基
板コンタクト領域１６を囲むようにｐ型のアンチパンチ
スルー領域１８が形成されている。A source region 1 is formed on the surface of the semiconductor substrate 10.
The p-type substrate contact region 16 is formed so as to be adjacent to 1, and the source region 11 and the substrate contact region 16 are connected to the source electrode 17. As a result, the source region 11 is set to the same potential as the semiconductor substrate 10. A p-type anti-punch through region 18 is formed on the semiconductor substrate 10 so as to surround the source region 11 and the substrate contact region 16.

【０００６】半導体基板１０の上におけるソース領域１
１と延長ドレイン領域１２との間にはゲート絶縁膜を介
してゲート電極１９が形成されており、半導体基板１０
におけるゲート電極１９の下側の領域はチャネル領域と
して機能する。ゲート電極１９を含む半導体基板１０の
表面は絶縁膜２０により覆われている。Source region 1 on semiconductor substrate 10
1 and the extended drain region 12, a gate electrode 19 is formed via a gate insulating film, and the semiconductor substrate 10
The region below the gate electrode 19 in (1) functions as a channel region. The surface of the semiconductor substrate 10 including the gate electrode 19 is covered with an insulating film 20.

【０００７】前記従来例の半導体装置の特徴は、ｎ型領
域からなる延長ドレイン領域１２の内部に、ｎ型高濃度
領域１３及びｐ型埋め込み領域１４を備えていることで
ある。A characteristic of the semiconductor device of the conventional example is that an n-type high concentration region 13 and a p-type buried region 14 are provided inside an extended drain region 12 formed of an n-type region.

【０００８】ｐ型埋め込み領域１４は半導体基板１０を
介して基準電位に設定されているため、延長ドレイン領
域１２に高電圧が印加されると、延長ドレイン領域１２
と、半導体基板１０及びｐ型埋め込み領域１４とは逆バ
イアス状態になる。このため、延長ドレイン領域１２と
ｐ型埋め込み領域１４との接合部から空乏層が拡がると
共に、延長ドレイン領域１２と半導体基板１０との接合
部からも空乏層が拡がる。これらの空乏層の絶縁耐圧特
性を利用することにより、ＭＯＳ型トランジスタの高耐
圧化を図ることができる。Since the p-type buried region 14 is set to the reference potential via the semiconductor substrate 10, when a high voltage is applied to the extended drain region 12, the extended drain region 12 is formed.
Then, the semiconductor substrate 10 and the p-type buried region 14 are in a reverse bias state. Therefore, the depletion layer extends from the junction between the extended drain region 12 and the p-type buried region 14, and the depletion layer extends from the junction between the extended drain region 12 and the semiconductor substrate 10. By utilizing the breakdown voltage characteristics of these depletion layers, it is possible to increase the breakdown voltage of the MOS transistor.

【０００９】ゲート電極２０に電圧が印加されると、Ｍ
ＯＳ型トランジスタのチャネル領域が導通するので、破
線の矢印で示すように、電流は主として、延長ドレイン
領域１２の内部におけるｎ型不純物濃度が高い領域、つ
まりｎ型高濃度領域１３とｐ型埋め込み領域１４の下方
の領域とを流れる。When a voltage is applied to the gate electrode 20, M
Since the channel region of the OS-type transistor becomes conductive, the current is mainly a region having a high n-type impurity concentration inside the extended drain region 12, that is, the n-type high-concentration region 13 and the p-type buried region, as indicated by a dashed arrow. And the area below 14.

【００１０】ところで、通常行なわれているように、基
板表面からの拡散により延長ドレイン領域１２の表面部
にｐ型領域を形成すると、延長ドレイン領域１２におけ
る不純物濃度の最も高い表面部におけるｎ型不純物の濃
度は著しく低下するため、オン抵抗は高くなってしま
う。When a p-type region is formed on the surface portion of the extended drain region 12 by diffusion from the surface of the substrate as is usually done, the n-type impurity in the surface portion of the extended drain region 12 having the highest impurity concentration is formed. On the other hand, the on-resistance will be high because the concentration of H.

【００１１】そこで、前記従来例においては、延長ドレ
イン領域１２の内部にｐ型埋め込み領域１４を形成する
ことにより、延長ドレイン領域１２の表面部におけるｎ
型不純物の濃度の低下を防止して、オン抵抗の低減を図
っている。Therefore, in the above-mentioned conventional example, by forming the p-type buried region 14 inside the extended drain region 12, n at the surface portion of the extended drain region 12 is formed.
The on-resistance is reduced by preventing the concentration of the type impurities from decreasing.

【００１２】さらに、前記従来例においては、延長ドレ
イン領域１２の表面部にｎ型高濃度領域１３を設けて、
延長ドレイン領域１２の表面部におけるｎ型不純物濃度
を高くすることにより、オン抵抗の一層の低減を図って
いる。Further, in the above conventional example, an n-type high concentration region 13 is provided on the surface of the extended drain region 12.
The on-resistance is further reduced by increasing the n-type impurity concentration in the surface portion of the extended drain region 12.

【００１３】[0013]

【発明が解決しようとする課題】ところで、前記従来の
構造においては、ＭＯＳ型トランジスタが動作する際の
電流経路は、延長ドレイン領域１２における、ｎ型高濃
度領域（表面領域）１３とｐ型埋め込み領域１４の下方
の領域（底部領域）とに分かれているため、高耐圧特性
を得るためには、延長ドレイン領域１２におけるｐ型埋
め込み領域１４の下方の領域の不純物濃度を低くして、
逆バイアス電圧を印加したときに接合部から拡がる空乏
層の領域を大きくすることが好ましい。そして、延長ド
レイン領域１２におけるｐ型埋め込み領域１４の下方の
領域の不純物濃度を低くするためには、延長ドレイン領
域１２を形成する工程において、ドーピングされる不純
物の濃度を低くすると共に該不純物を熱拡散させる必要
がある。In the conventional structure described above, the current path when the MOS transistor operates is such that the extended drain region 12 has the n-type high-concentration region (surface region) 13 and the p-type buried region. Since it is divided into a region (bottom region) below the region 14, in order to obtain a high withstand voltage characteristic, the impurity concentration of the region below the p-type buried region 14 in the extended drain region 12 is lowered,
It is preferable to enlarge the region of the depletion layer that spreads from the junction when the reverse bias voltage is applied. Then, in order to lower the impurity concentration of the region below the p-type buried region 14 in the extended drain region 12, the concentration of the impurity to be doped is lowered and the impurity is heated in the process of forming the extended drain region 12. Need to spread.

【００１４】ところが、延長ドレイン領域１２における
ｐ型埋め込み領域１４の下方の領域の不純物濃度を低く
すると、オン抵抗が高くなってしまうので、延長ドレイ
ン領域１２におけるｐ型埋め込み領域１４の下方の領域
の不純物濃度を低くすることは好ましくない。従って、
高耐圧特性を確保しながらオン抵抗を低減するために
は、表面に位置するｎ型高濃度領域１３の不純物濃度を
高くしなければならない。However, if the impurity concentration in the region below the p-type buried region 14 in the extended drain region 12 is lowered, the on-resistance becomes high, so that the region below the p-type buried region 14 in the extended drain region 12 becomes. It is not preferable to reduce the impurity concentration. Therefore,
In order to reduce the on-resistance while ensuring the high breakdown voltage characteristic, the impurity concentration of the n-type high concentration region 13 located on the surface must be increased.

【００１５】しかしながら、ｎ型高濃度領域１３の不純
物濃度を高くしようとすると、ｎ型の不純物がｐ型埋め
込み領域１４に拡散してｐ型埋め込み領域１４の不純物
濃度が低下してしまうため、逆バイアス電圧を印加した
ときの空乏層の拡がりが十分でなくなるので、電界分布
が変化して高耐圧特性が劣化してしまうという問題が発
生する。このため、ｎ型高濃度領域１３の不純物濃度を
高くすることは好ましくない。However, if an attempt is made to increase the impurity concentration of the n-type high concentration region 13, the n-type impurity diffuses into the p-type buried region 14 and the impurity concentration of the p-type buried region 14 is reduced. Since the expansion of the depletion layer when the bias voltage is applied becomes insufficient, there arises a problem that the electric field distribution changes and the high breakdown voltage characteristic deteriorates. Therefore, it is not preferable to increase the impurity concentration of the n-type high concentration region 13.

【００１６】従って、前記従来の構造によると、高耐圧
特性の確保とオン抵抗の低減との両立を図っているが、
この両立は十分であるとは言えない。Therefore, according to the above-mentioned conventional structure, it is attempted to secure high withstand voltage characteristics and reduce ON resistance at the same time.
This balance cannot be said to be sufficient.

【００１７】前記に鑑み、本発明は、高耐圧特性を確保
しつつ、オン抵抗を確実に低減できるようにすることを
目的とする。In view of the above, it is an object of the present invention to surely reduce the on-resistance while ensuring high withstand voltage characteristics.

【００１８】[0018]

【課題を解決するための手段】前記の目的を達成するた
め、本発明は、延長ドレイン領域の内部における反対導
電型の埋め込み領域の上方又は下方にさらに反対導電型
の埋め込み領域を設けることにより、延長ドレイン領域
の底部における不純物濃度を低くすることなく、高耐圧
特性を向上させるものである。In order to achieve the above object, the present invention provides a buried region of opposite conductivity type above or below a buried region of opposite conductivity type inside an extended drain region. The high breakdown voltage characteristics are improved without lowering the impurity concentration at the bottom of the extended drain region.

【００１９】具体的には、本発明に係る半導体装置は、
第１導電型の半導体基板にそれぞれ形成された第２導電
型のドレイン領域及びソース領域と、ドレイン領域に互
いに間隔をおいて形成された第１導電型の不純物層から
なり、下側に位置する第１の埋め込み領域及び上側に位
置する第２の埋め込み領域と、ドレイン領域における第
１の埋め込み領域と第２の埋め込み領域との間に形成さ
れた第２導電型の高濃度不純物領域とを備えている。Specifically, the semiconductor device according to the present invention is
It is composed of a drain region and a source region of a second conductivity type respectively formed on a semiconductor substrate of a first conductivity type, and an impurity layer of the first conductivity type formed in the drain region with a space therebetween, and is located on the lower side. A first buried region and a second buried region located on the upper side; and a second conductivity type high-concentration impurity region formed between the first buried region and the second buried region in the drain region. ing.

【００２０】本発明に係る半導体装置によると、ドレイ
ン領域には、互いに間隔をおいて形成された第１導電型
の第１の埋め込み領域及び第２の埋め込み領域と、第１
の埋め込み領域と第２の埋め込み領域との間に形成され
た第２導電型の高濃度不純物領域とを備えているため、
ドレイン領域に半導体基板に対して逆バイアスとなる電
圧が印加されると、ドレイン領域と第１及び第２の埋め
込み領域との各接合部並びにドレイン領域と半導体基板
との接合部からそれぞれ空乏層が拡がるため、ＭＯＳ型
トランジスタの高耐圧特性を確保することができる。ま
た、ドレイン領域とソース領域とが導通状態になったと
きには、電流は第１の埋め込み領域と第２の埋め込み領
域との間に形成されている高濃度不純物領域を流れるた
め、オン抵抗を低減することができる。従って、本発明
に係る半導体装置によると、高耐圧特性を確保しつつ、
オン抵抗を確実に低減することができる。According to the semiconductor device of the present invention, in the drain region, the first buried region and the second buried region of the first conductivity type are formed at a distance from each other, and the first buried region is formed.
Of the second conductivity type high-concentration impurity region formed between the first buried region and the second buried region,
When a voltage that is reverse biased to the semiconductor substrate is applied to the drain region, a depletion layer is formed from each junction between the drain region and the first and second buried regions and each junction between the drain region and the semiconductor substrate. Because of the widening, the high breakdown voltage characteristic of the MOS transistor can be secured. Further, when the drain region and the source region are brought into conduction, current flows in the high-concentration impurity region formed between the first buried region and the second buried region, so that the on-resistance is reduced. be able to. Therefore, according to the semiconductor device of the present invention, while ensuring high breakdown voltage characteristics,
The on-resistance can be reliably reduced.

【００２１】本発明に係る半導体装置は、ドレイン領域
における第２の埋め込み領域の上側に形成された第２導
電型の上方高濃度不純物領域をさらに備えていることが
好ましい。It is preferable that the semiconductor device according to the present invention further includes an upper high-concentration impurity region of the second conductivity type formed above the second buried region in the drain region.

【００２２】このようにすると、ドレイン領域とソース
領域とが導通状態になったときに、電流は上方高濃度不
純物領域にも流れるため、オン抵抗を一層低減すること
ができる。With this configuration, when the drain region and the source region are brought into conduction, the current also flows in the upper high-concentration impurity region, so that the on-resistance can be further reduced.

【００２３】本発明に係る半導体装置は、ドレイン領域
における第１の埋め込み領域の下側に、該第１の埋め込
み領域との間に間隔をおいて形成された第１導電型の不
純物層からなる下方埋め込み領域と、ドレイン領域にお
ける第１の埋め込み領域と下方埋め込み領域との間に形
成された第２導電型の下方高濃度不純物領域とをさらに
備えていることが好ましい。The semiconductor device according to the present invention comprises a first conductivity type impurity layer formed below the first buried region in the drain region and spaced apart from the first buried region. It is preferable to further include a lower buried region and a second conductivity type lower high-concentration impurity region formed between the first buried region and the lower buried region in the drain region.

【００２４】このようにすると、ドレイン領域に、第１
及び第２の埋め込み領域並びに半導体基板に対して逆バ
イアスとなる電圧が印加されると、空乏層はドレイン領
域と下方埋め込み領域との接合部からも拡がるため、Ｍ
ＯＳ型トランジスタの高耐圧特性が一層向上する。ま
た、ドレイン領域とソース領域とが導通状態になったと
きには、電流は下方高濃度不純物領域をも流れるため、
オン抵抗を一層低減することができる。従って、高耐圧
特性を確保とオン抵抗の低減との両立を一層図ることが
できる。By doing so, the first region is formed in the drain region.
When a reverse bias voltage is applied to the second buried region and the semiconductor substrate, the depletion layer also spreads from the junction between the drain region and the lower buried region.
The high breakdown voltage characteristics of the OS type transistor are further improved. Further, when the drain region and the source region are brought into conduction, the current also flows through the lower high-concentration impurity region,
The on-resistance can be further reduced. Therefore, it is possible to further secure both high withstand voltage characteristics and reduction of ON resistance.

【００２５】本発明に係る半導体装置において、第１及
び第２の埋め込み領域は、半導体基板と電気的に接続さ
れていることが好ましい。In the semiconductor device according to the present invention, it is preferable that the first and second buried regions are electrically connected to the semiconductor substrate.

【００２６】このように、半導体装置が、第１及び第２
の埋め込み領域と半導体基板とが電気的に接続された構
造を有していると、ドレイン領域に半導体基板に対して
逆バイアスとなる電圧が印加されたときに、ドレイン領
域と第１及び第２の埋め込み領域との接合部から空乏層
が確実に拡がるため、ＭＯＳ型トランジスタの高耐圧特
性が向上する。As described above, the semiconductor device has the first and second semiconductor devices.
And a semiconductor substrate having a structure in which the buried region and the semiconductor substrate are electrically connected to each other, when the drain region is applied with a reverse bias voltage with respect to the semiconductor substrate, the drain region and the first and second Since the depletion layer surely spreads from the junction with the buried region, the high breakdown voltage characteristic of the MOS transistor is improved.

【００２７】本発明に係る半導体装置の製造方法は、第
１導電型の半導体基板に第２導電型のドレイン領域及び
ソース領域をそれぞれ形成する工程と、ドレイン領域に
第１導電型の第１の埋め込み領域を形成する工程と、ド
レイン領域における第１の埋め込み領域の上側に第２導
電型の高濃度不純物領域を形成する工程と、ドレイン領
域における第２導電型の高濃度不純物領域の上側に第１
導電型の第２の埋め込み領域を形成する工程とを備えて
いる。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a drain region and a source region of a second conductivity type on a semiconductor substrate of a first conductivity type, and a first conductivity type first region in the drain region. Forming a buried region; forming a second conductivity type high concentration impurity region above the first buried region in the drain region; and forming a second conductivity type high concentration impurity region above the second conductivity type in the drain region. 1
And a step of forming a conductive type second buried region.

【００２８】本発明に係る半導体装置の製造方法による
と、ドレイン領域に、互いに間隔をおいて第１導電型の
第１の埋め込み領域と第２の埋め込み領域とを形成する
ことができると共に、第１の埋め込み領域と第２の埋め
込み領域との間に第２導電型の高濃度不純物領域を形成
することができるため、高耐圧特性を確保しつつオン抵
抗を低減できる本発明に係る半導体装置を確実に製造す
ることができる。According to the method of manufacturing a semiconductor device of the present invention, it is possible to form the first buried region and the second buried region of the first conductivity type in the drain region at intervals from each other. Since the second-conductivity-type high-concentration impurity region can be formed between the first buried region and the second buried region, the semiconductor device according to the present invention can reduce the on-resistance while ensuring high breakdown voltage characteristics. It can be reliably manufactured.

【００２９】本発明に係る半導体装置の製造方法は、ド
レイン領域における第２の埋め込み領域の上側に第２導
電型の上方高濃度不純物領域を形成する工程をさらに備
えていることが好ましい。The method for manufacturing a semiconductor device according to the present invention preferably further comprises a step of forming an upper high concentration impurity region of the second conductivity type above the second buried region in the drain region.

【００３０】このようにすると、ドレイン領域とソース
領域とが導通状態になったときに、電流は上方高濃度不
純物領域にも流れるため、オン抵抗を一層低減すること
ができる。With this configuration, when the drain region and the source region are brought into conduction, the current also flows in the upper high-concentration impurity region, so that the on-resistance can be further reduced.

【００３１】本発明に係る半導体装置の製造方法におい
て、第１の埋め込み領域及び第２の埋め込み領域は、そ
れぞれイオン注入法により形成されることが好ましい。In the method of manufacturing a semiconductor device according to the present invention, it is preferable that each of the first buried region and the second buried region is formed by an ion implantation method.

【００３２】このようにすると、ドレイン領域に互いに
間隔をおいて第１の埋め込み領域と第２の埋め込み領域
とを確実に形成することができる。In this way, the first buried region and the second buried region can be reliably formed in the drain region with a space therebetween.

【００３３】この場合、高濃度不純物領域はイオン注入
法により形成されることが好ましい。In this case, the high concentration impurity region is preferably formed by the ion implantation method.

【００３４】このようにすると、ドレイン領域における
第１の埋め込み領域と第２の埋め込み領域との間に高濃
度不純物領域を確実に形成することができる。By doing so, the high-concentration impurity region can be reliably formed between the first buried region and the second buried region in the drain region.

【００３５】[0035]

【発明の実施の形態】（第１の実施形態）以下、本発明
の第１の実施形態に係る半導体装置について図１（ａ）
〜（ｃ）を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to (c).

【００３６】図１（ａ）に示すように、ｐ型の半導体基
板（不純物濃度：約１×１０14〜約３×１０14／ｃ
ｍ3 ）１００には、６．５μｍ程度の深さを有するｎ型
不純物層（不純物濃度：５×１０14／ｃｍ3 ）からなる
延長ドレイン領域１０１が形成されており、該延長ドレ
イン領域１０１は、半導体基板１００の上に形成された
絶縁膜１０９を貫通して延びるドレイン電極１１１に接
続されている。As shown in FIG. 1A, a p-type semiconductor substrate (impurity concentration: about 1 × 10 14 to about 3 × 10 14 / c) is used.
m 3 ) 100 is formed with an extended drain region 101 formed of an n-type impurity layer (impurity concentration: 5 × 10 14 / cm 3 ) having a depth of about 6.5 μm. , The drain electrode 111 extending through the insulating film 109 formed on the semiconductor substrate 100.

【００３７】延長ドレイン領域１０１における３．５μ
ｍ程度の深さの領域には第１のｐ型埋め込み領域（不純
物濃度：１．５×１０16／ｃｍ3 ）１０３Ａが形成され
ていると共に、延長ドレイン領域１０１における１．０
μｍ程度の深さの領域には第２のｐ型埋め込み領域（不
純物濃度：２．５×１０16／ｃｍ3 ）１０３Ｂが形成さ
れている。第１及び第２のｐ型埋め込み領域１０３Ａ、
１０３Ｂは、半導体基板１００と電気的に接続されてい
るか又は浮遊状態である。3.5 μ in the extended drain region 101
A first p-type buried region (impurity concentration: 1.5 × 10 16 / cm 3 ) 103A is formed in a region having a depth of about m, and 1.0 in the extended drain region 101 is formed.
A second p-type buried region (impurity concentration: 2.5 × 10 16 / cm 3 ) 103B is formed in a region having a depth of about μm. The first and second p-type buried regions 103A,
103B is electrically connected to the semiconductor substrate 100 or is in a floating state.

【００３８】延長ドレイン領域１０１における第１のｐ
型埋め込み領域１０３Ａと第２のｐ型埋め込み領域１０
３Ｂとの間には、第１のｎ型高濃度不純物領域（不純物
濃度：５．０×１０16／ｃｍ3 ）１０４Ａが形成されて
いると共に、延長ドレイン領域１０１における第２のｐ
型埋め込み領域１０３Ｂの上側には第２のｎ型高濃度領
域（不純物濃度：５．０×１０16／ｃｍ3 ）１０４Ｂが
形成されており、該第２のｎ型高濃度領域１０４Ｂは絶
縁膜１０９を貫通して延びるドレイン電極１１１に接続
されている。これによって、延長ドレイン領域１０１は
ドレイン電極１１１と電気的に接続されている。The first p in the extended drain region 101
The type embedding region 103A and the second p-type embedding region 10
3B, a first n-type high concentration impurity region (impurity concentration: 5.0 × 10 16 / cm 3 ) 104A is formed, and a second p-type in the extended drain region 101 is formed.
A second n-type high concentration region (impurity concentration: 5.0 × 10 16 / cm 3 ) 104B is formed on the upper side of the mold embedding region 103B, and the second n-type high concentration region 104B is an insulating film. It is connected to a drain electrode 111 extending through 109. As a result, the extended drain region 101 is electrically connected to the drain electrode 111.

【００３９】半導体基板１００の表面部には、延長ドレ
イン領域１０１との間に間隔をおいて、ｎ型領域からな
るソース領域１０５と、ｐ++型領域からなる基板コンタ
クト領域１０６とが形成されており、基板コンタクト領
域１０６は半導体基板１００と電気的に接続されてい
る。また、ソース領域１０５及び基板コンタクト領域１
０６は絶縁膜１０９を貫通して延びるソース電極１１２
に接続されており、ソース領域１０５は半導体基板１０
０と同電位に設定される。A source region 105 made of an n-type region and a substrate contact region 106 made of a p + + -type region are formed on the surface of the semiconductor substrate 100 at intervals from the extended drain region 101. The substrate contact region 106 is electrically connected to the semiconductor substrate 100. In addition, the source region 105 and the substrate contact region 1
Reference numeral 06 denotes a source electrode 112 extending through the insulating film 109.
And the source region 105 is connected to the semiconductor substrate 10
It is set to the same potential as 0.

【００４０】半導体基板１００の上における延長ドレイ
ン領域１０１とソース領域１０５との間にはゲート絶縁
膜１０７を介してゲート電極１０８が形成されており、
半導体基板１００におけるゲート電極１０８の下側の領
域はチャネル領域として機能する。A gate electrode 108 is formed between the extended drain region 101 and the source region 105 on the semiconductor substrate 100 via a gate insulating film 107,
A region below the gate electrode 108 in the semiconductor substrate 100 functions as a channel region.

【００４１】ソース領域１０５及び基板コンタクト領域
１０６は、半導体基板１００よりも不純物濃度が高いｐ
+ 型のアンチパンチスルー領域１０１に囲まれており、
延長ドレイン領域１０１からチャネル領域側に拡がる空
乏層はアンチパンチスルー領域１０１により拡がりが抑
制されるので、パンチスルー現象は防止される。The source region 105 and the substrate contact region 106 have a higher impurity concentration than the semiconductor substrate 100.
Surrounded by the + type anti-punch through area 101,
The depletion layer extending from the extended drain region 101 to the channel region side is suppressed by the anti-punch through region 101, so that the punch through phenomenon is prevented.

【００４２】第１の実施形態に係る半導体装置による
と、延長ドレイン領域１０１には、互いに間隔をおいて
第１のｐ型埋め込み領域１０３Ａと第２のｐ型埋め込み
領域１０３Ｂとが形成されているため、延長ドレイン領
域１０１に高電圧が印加されると、延長ドレイン領域１
０１と、半導体基板１００、第１及び第２のｐ型埋め込
み領域１０３Ａ、１０３Ｂとは互いに逆バイアス状態に
なる。このため、図１（ｂ）において破線で示すよう
に、第１のｐ型埋め込み領域１０３Ａと延長ドレイン領
域１０１及び第１のｎ型高濃度領域１０４Ａとの各接合
部、第２のｐ型埋め込み領域１０３Ｂと第１のｎ型高濃
度領域１０４Ａ及び第２のｎ型高濃度領域１０４Ｂとの
各接合部、並びに延長ドレイン領域１０１と半導体基板
１００との接合部からそれぞれ空乏層が拡がると共に、
各空乏層が互いに連続するため、空乏層の領域が大きく
なるので、ＭＯＳ型トランジスタの高耐圧化を図ること
ができる。According to the semiconductor device of the first embodiment, the extended drain region 101 is provided with the first p-type buried region 103A and the second p-type buried region 103B which are spaced from each other. Therefore, when a high voltage is applied to the extended drain region 101, the extended drain region 1
01, the semiconductor substrate 100, and the first and second p-type buried regions 103A and 103B are in a reverse bias state. Therefore, as indicated by a broken line in FIG. 1B, each junction between the first p-type buried region 103A and the extended drain region 101 and the first n-type high concentration region 104A, the second p-type buried region. A depletion layer spreads from each junction between the region 103B and the first n-type high-concentration region 104A and the second n-type high-concentration region 104B, and the junction between the extended drain region 101 and the semiconductor substrate 100.
Since the depletion layers are continuous with each other, the region of the depletion layer becomes large, so that the breakdown voltage of the MOS transistor can be increased.

【００４３】また、第１の実施形態に係る半導体装置に
よると、ゲート電極１０８に電圧が印加されて、ＭＯＳ
型トランジスタのチャネル領域が導通したときには、電
流は、図１（ｃ）において矢印で示すように、延長ドレ
イン領域１０１における、第１のｎ型高濃度領域１０４
Ａ、第２のｎ型高濃度領域１０４Ｂ及び第１のｐ型埋め
込み領域１０３Ａの下側領域をそれぞれ流れる。このよ
うに、従来の構造に比べて、電流の流れる経路が増加し
ているため、ＭＯＳ型トランジスタのオン抵抗は大きく
低減する。Further, according to the semiconductor device of the first embodiment, the voltage is applied to the gate electrode 108, and the MOS
When the channel region of the n-type transistor is made conductive, the current flows through the first n-type high concentration region 104 in the extended drain region 101 as indicated by an arrow in FIG.
A, the second n-type high-concentration region 104B, and the first p-type buried region 103A. As described above, since the paths through which the current flows are increased as compared with the conventional structure, the on-resistance of the MOS transistor is greatly reduced.

【００４４】以上説明したように、第１の実施形態によ
ると、ｎ型の延長ドレイン領域１０１にｐ型の第１及び
第２のｐ型埋め込み領域１０３Ａ、１０３Ｂを設けたと
共に、第１のｐ型埋め込み領域１０３Ａと第２のｐ型埋
め込み領域１０３Ｂとの間に第１のｎ型高濃度領域１０
４Ａを設けたため、高耐圧特性を確保しつつ、オン抵抗
を大きく低減することができる。As described above, according to the first embodiment, the n-type extended drain region 101 is provided with the p-type first and second p-type buried regions 103A and 103B, and the first p-type is also provided. The first n-type high concentration region 10 is provided between the mold embedding region 103A and the second p-type embedding region 103B.
Since 4A is provided, it is possible to greatly reduce the on-resistance while ensuring high breakdown voltage characteristics.

【００４５】以下、第１の実施形態に係る半導体装置の
製造方法について、図２（ａ）〜（ｃ）及び図３
（ａ）、（ｂ）を参照しながら説明する。Hereinafter, the manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIGS.
A description will be given with reference to (a) and (b).

【００４６】まず、図２（ａ）に示すように、１×１０
14〜３×１０14ｃｍ3 程度の不純物濃度を有するｐ型の
半導体基板１００のドレイン形成領域にｎ型不純物例え
ばリンをイオン注入すると共に、半導体基板１００のソ
ース形成領域にｐ型不純物例えばボロンをイオン注入し
た後、ｎ型及びｐ型の不純物を熱拡散させて、６．５μ
ｍ程度の深さを有するｎ型の延長ドレイン領域１０１
と、ｐ+ 型のアンチパンチスルー領域１０２とを形成す
る。First, as shown in FIG. 2A, 1 × 10
An n-type impurity such as phosphorus is ion-implanted into the drain formation region of the p-type semiconductor substrate 100 having an impurity concentration of about 14 to 3 × 10 14 cm 3, and a p-type impurity such as boron is implanted into the source formation region of the semiconductor substrate 100. After ion implantation, n-type and p-type impurities are thermally diffused to 6.5 μm.
n-type extended drain region 101 having a depth of about m
And ap + type anti-punch through region 102 are formed.

【００４７】次に、図２（ｂ）に示すように、延長ドレ
イン領域１０１にｐ型不純物例えばボロンを２．０〜
３．０ＭｅＶの注入エネルギーでイオン注入して、３．
５μｍ程度の深さの領域に第１のｐ型埋め込み領域１０
３Ａを形成した後、延長ドレイン領域１０１にｎ型不純
物例えばリンを２．０ＭｅＶの注入エネルギーでイオン
注入して、第１のｐ型埋め込み領域１０３Ａの上側に第
１のｎ型高濃度領域１０４Ａを形成する。Next, as shown in FIG. 2B, p-type impurities such as boron are added to the extended drain region 101 in an amount of 2.0 to 2.0.
2. Ion implantation is performed with an implantation energy of 3.0 MeV;
The first p-type buried region 10 is formed in a region having a depth of about 5 μm.
After forming 3A, an n-type impurity such as phosphorus is ion-implanted into the extended drain region 101 at an implantation energy of 2.0 MeV to form a first n-type high-concentration region 104A above the first p-type buried region 103A. Form.

【００４８】次に、図２（ｃ）に示すように、延長ドレ
イン領域１０１にｐ型不純物例えばボロンを１．０〜
１．５ＭｅＶの注入エネルギーでイオン注入して、１．
０μｍ程度の深さの領域に第２のｐ型埋め込み領域１０
３Ｂを形成する。次に、延長ドレイン領域１０１及びア
ンチパンチスルー領域１０２にｎ型不純物例えばリンを
１００ｋｅＶ程度の注入エネルギーでイオン注入して、
第２のｐ型埋め込み領域１０３Ｂの上側に第２のｎ型高
濃度不純物層１０４Ｂを形成すると共に、アンチパンチ
スルー領域１０２にソース領域１０５を形成する。次
に、アンチパンチスルー領域１０２にｐ型不純物例えば
ボロンを４．５×１０12／ｃｍ2 程度のドーズ量でイオ
ン注入してｐ++型の基板コンタクト領域１０６を形成す
る。Next, as shown in FIG. 2C, p-type impurities such as boron are added to the extended drain region 101 in an amount of 1.0 to 1.0.
Ion implantation is performed with an implantation energy of 1.5 MeV, and
The second p-type buried region 10 is formed in a region having a depth of about 0 μm.
Form 3B. Next, an n-type impurity such as phosphorus is ion-implanted into the extended drain region 101 and the anti-punch through region 102 with an implantation energy of about 100 keV,
A second n-type high concentration impurity layer 104B is formed above the second p-type buried region 103B, and a source region 105 is formed in the anti-punch through region 102. Next, p-type impurities such as boron are ion-implanted into the anti-punch through region 102 at a dose of about 4.5 × 10 12 / cm 2 to form a p ++ type substrate contact region 106.

【００４９】次に、図３（ａ）に示すように、半導体基
板１００の上における、延長ドレイン領域１０１とソー
ス領域１０５との間にゲート絶縁膜１０７を介してポリ
シリコン膜からなるゲート電極１０８を形成した後、半
導体基板１００の上に全面に亘って絶縁膜１０９を形成
する。Next, as shown in FIG. 3A, a gate electrode 108 made of a polysilicon film is formed on the semiconductor substrate 100 between the extended drain region 101 and the source region 105 with a gate insulating film 107 interposed therebetween. After forming, the insulating film 109 is formed over the entire surface of the semiconductor substrate 100.

【００５０】次に、図３（ｂ）に示すように、絶縁膜１
０９にコンタクトホール１１０を形成した後、絶縁膜１
０９の上にコンタクトホール１１０が埋め込まれるよう
にドレイン電極１１１及びソース電極１１２を形成する
と、第１の実施形態に係る半導体装置が得られる。Next, as shown in FIG. 3B, the insulating film 1
After forming the contact hole 110 in the insulating film 1
When the drain electrode 111 and the source electrode 112 are formed so as to fill the contact hole 110 on the 09, the semiconductor device according to the first embodiment is obtained.

【００５１】（第２の実施形態）以下、本発明の第２の
実施形態に係る半導体装置について図４（ａ）、（ｂ）
を参照しながら説明する。尚、第２の実施形態は、第１
の実施形態と比べて延長ドレイン領域１０１の構造が異
なるのみであるから、以下においては、延長ドレイン領
域１０１についてのみ説明する。(Second Embodiment) A semiconductor device according to a second embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. Incidentally, the second embodiment is the first
Since only the structure of the extended drain region 101 is different from that of the above embodiment, only the extended drain region 101 will be described below.

【００５２】延長ドレイン領域１０１の深さは６．５μ
ｍ程度であると共に、延長ドレイン領域１０１の底部の
不純物濃度は５×１０14ｃｍ3 程度であって、第１の実
施形態と同様である。The depth of the extended drain region 101 is 6.5 μm.
The impurity concentration at the bottom of the extended drain region 101 is about 5 × 10 14 cm 3 , which is similar to that of the first embodiment.

【００５３】第２の実施形態の特徴として、延長ドレイ
ン領域１０１における６．０μｍ程度の深さの領域には
第１のｐ型埋め込み領域（不純物濃度：１．０×１０16
／ｃｍ3 ）１０３Ａが形成され、延長ドレイン領域１０
１における４．０μｍ程度の深さの領域には第２のｐ型
埋め込み領域（不純物濃度：１．５×１０16／ｃｍ3）
１０３Ｂが形成され、延長ドレイン領域１０１における
１．０μｍ程度の深さの領域には第３のｐ型埋め込み領
域（不純物濃度：１．０×１０16／ｃｍ3 ）１０３Ｃが
形成されている。これら第１、第２及び第３のｐ型埋め
込み領域１０３Ａ、１０３Ｂ、１０３Ｃは、半導体基板
１００と電気的に接続されているか又は浮遊状態であ
る。A feature of the second embodiment is that the first p-type buried region (impurity concentration: 1.0 × 10 16) is formed in the region of the extended drain region 101 having a depth of about 6.0 μm.
/ Cm 3 ) 103A is formed and the extended drain region 10 is formed.
The second p-type buried region (impurity concentration: 1.5 × 10 16 / cm 3 ) is formed in the region of about 4.0 μm deep in FIG.
103B is formed, and a third p-type buried region (impurity concentration: 1.0 × 10 16 / cm 3 ) 103C is formed in a region having a depth of about 1.0 μm in the extended drain region 101. These first, second, and third p-type buried regions 103A, 103B, 103C are electrically connected to the semiconductor substrate 100 or are in a floating state.

【００５４】また、延長ドレイン領域１０１における第
１のｐ型埋め込み領域１０３Ａと第２のｐ型埋め込み領
域１０３Ｂとの間には第１のｎ型高濃度領域（不純物濃
度：５．０×１０16／ｃｍ3 ）１０４Ａが形成され、第
２のｐ型埋め込み領域１０３Ｂと第３のｐ型埋め込み領
域１０３Ｃとの間には第２のｎ型高濃度領域（不純物濃
度：５．０×１０16／ｃｍ3 ）１０４Ｂが形成され、延
長ドレイン領域１０１における第３のｐ型埋め込み領域
１０３Ｃの上側には第３のｎ型高濃度領域（不純物濃
度：５．０×１０16／ｃｍ3 ）１０４Ｃが形成されてい
る。第３のｎ型高濃度領域１０４Ｃは絶縁膜１０９を貫
通して延びるドレイン電極１１１に接続されており、こ
れによって、延長ドレイン領域１０１はドレイン電極１
１１と電気的に接続されている。A first n-type high-concentration region (impurity concentration: 5.0 × 10 16) is provided between the first p-type buried region 103A and the second p-type buried region 103B in the extended drain region 101. / Cm 3 ) 104A is formed, and a second n-type high-concentration region (impurity concentration: 5.0 × 10 16 / is formed between the second p-type buried region 103B and the third p-type buried region 103C. cm 3 ) 104B is formed, and a third n-type high concentration region (impurity concentration: 5.0 × 10 16 / cm 3 ) 104C is formed above the third p-type buried region 103C in the extended drain region 101. Has been done. The third n-type high concentration region 104C is connected to the drain electrode 111 extending through the insulating film 109, whereby the extended drain region 101 becomes the drain electrode 1.
11 is electrically connected.

【００５５】第２の実施形態の特徴は、第１の実施形態
に比べて、ｐ型埋め込み領域及びｎ型高濃度領域の数が
それぞれ多いと共に、第１及び第２のｐ型埋め込み領域
１０３Ａ、１０３Ｂに比べて不純物濃度が低い第３のｐ
型埋め込み領域１０３Ｃが設けられていることである。The features of the second embodiment are that the number of p-type buried regions and the number of n-type high-concentration regions are larger than those of the first embodiment, and that the first and second p-type buried regions 103A, The third p having a lower impurity concentration than 103B
That is, the mold embedding region 103C is provided.

【００５６】従って、延長ドレイン領域１０１に高電圧
が印加されたときには、図４（ｂ）において破線で示す
ように、空乏層が拡がる。すなわち、第１、第２及び第
３のｎ型高濃度領域１０４Ａ、１０４Ｂ、１０４Ｃの各
高さが小さいために空乏層が拡がり易い。また、不純物
濃度が低い第３のｐ型埋め込み領域１０３Ｃと、第２の
ｎ型高濃度領域１０４Ｂ及び第３のｎ型高濃度領域１０
４Ｃとの各接合部から空乏層が拡がり易い。このため、
高耐圧特性を確保し易いので、高耐圧特性の確保とオン
抵抗の低減との両立が図り易くなる。また、高耐圧特性
を確保し易いので、第１、第２及び第３のｎ型高濃度領
域１０４Ａ、１０４Ｂ、１０４Ｃの不純物濃度を高くし
てオン抵抗を低減することも容易である。Therefore, when a high voltage is applied to the extended drain region 101, the depletion layer expands as shown by the broken line in FIG. 4 (b). That is, since the height of each of the first, second, and third n-type high-concentration regions 104A, 104B, and 104C is small, the depletion layer easily expands. The third p-type buried region 103C having a low impurity concentration, the second n-type high-concentration region 104B, and the third n-type high-concentration region 10 are also included.
The depletion layer easily spreads from each junction with 4C. For this reason,
Since it is easy to secure high withstand voltage characteristics, it is easy to achieve both high withstand voltage characteristics and reduction of ON resistance. Further, since it is easy to secure high breakdown voltage characteristics, it is easy to increase the impurity concentration of the first, second and third n-type high concentration regions 104A, 104B and 104C to reduce the on-resistance.

【００５７】従って、第２の実施形態によると、高耐圧
特性の確保とオン抵抗の低減との両立を一層図り易くな
る。Therefore, according to the second embodiment, it becomes easier to secure both the high breakdown voltage characteristic and the reduction of the ON resistance.

【００５８】尚、図５に示すように、延長ドレイン領域
１０１に、第１のｐ型埋め込み領域１０３Ａ、第２のｐ
型埋め込み領域１０３Ｂ、第３のｐ型埋め込み領域１０
３Ｃ及び第４のｐ型埋め込み領域１０３Ｄを設けると共
に、第１のｎ型高濃度領域１０４Ａ、第２のｎ型高濃度
領域１０４Ｂ、第３のｎ型高濃度領域１０４Ｃ及び第４
のｎ型高濃度領域１０４Ｄを設けてもよい。As shown in FIG. 5, the extended drain region 101 has a first p-type buried region 103A and a second p-type buried region 103A.
Mold embedded region 103B, third p-type embedded region 10
3C and the fourth p-type buried region 103D are provided, and the first n-type high-concentration region 104A, the second n-type high-concentration region 104B, the third n-type high-concentration region 104C, and the fourth n-type high-concentration region 104C are provided.
The n-type high concentration region 104D may be provided.

【００５９】このようにすると、空乏層が一層拡がり易
くなるので、高耐圧特性の確保とオン抵抗の低減との両
立を一層図り易くなる。In this way, the depletion layer is more easily spread, and it is easier to achieve both high withstand voltage characteristics and reduction of on-resistance.

【００６０】[0060]

【発明の効果】本発明に係る半導体装置によると、ドレ
イン領域に、互いに間隔をおいて形成された第１導電型
の第１の埋め込み領域及び第２の埋め込み領域と、第１
の埋め込み領域と第２の埋め込み領域との間に形成され
た第２導電型の高濃度不純物領域とを備えているため、
高耐圧特性を確保しつつ、オン抵抗を確実に低減するこ
とができる。According to the semiconductor device of the present invention, the first buried region and the second buried region of the first conductivity type are formed in the drain region with a space therebetween.
Of the second conductivity type high-concentration impurity region formed between the first buried region and the second buried region,
It is possible to reliably reduce the on-resistance while ensuring high withstand voltage characteristics.

【００６１】また、本発明に係る半導体装置の製造方法
によると、高耐圧特性を確保しつつオン抵抗を低減でき
る本発明に係る半導体装置を確実に製造することができ
る。Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to reliably manufacture the semiconductor device of the present invention capable of reducing the on-resistance while ensuring high breakdown voltage characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は第１の実施形態に係る半導体装置の断
面図であり、（ｂ）は第１の実施形態に係る半導体装置
において延長ドレイン領域に高電圧が印加されたときに
空乏層が拡がる状態を示す断面図であり、（ｃ）は第１
の実施形態に係る半導体装置においてゲート電極に電圧
が印加されたときの電流経路を示す断面図である。1A is a cross-sectional view of a semiconductor device according to a first embodiment, and FIG. 1B is a depletion state when a high voltage is applied to an extended drain region in the semiconductor device according to the first embodiment. It is sectional drawing which shows the state which a layer spreads, (c) is a 1st figure.
6 is a cross-sectional view showing a current path when a voltage is applied to a gate electrode in the semiconductor device according to the exemplary embodiment. FIG.

【図２】（ａ）〜（ｃ）は第１の実施形態に係る半導体
装置の製造方法の各工程を示す断面図である。2A to 2C are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the first embodiment.

【図３】（ａ）、（ｂ）は第１の実施形態に係る半導体
装置の製造方法の各工程を示す断面図である。3A and 3B are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the first embodiment.

【図４】（ａ）は第２の実施形態に係る半導体装置の断
面図であり、（ｂ）は第２の実施形態に係る半導体装置
において延長ドレイン領域に高電圧が印加されたときに
空乏層が拡がる状態を示す断面図である。4A is a cross-sectional view of the semiconductor device according to the second embodiment, and FIG. 4B is a depletion state when a high voltage is applied to the extended drain region in the semiconductor device according to the second embodiment. It is sectional drawing which shows the state which a layer spreads.

【図５】第３の実施形態に係る半導体装置の断面図であ
る。FIG. 5 is a sectional view of a semiconductor device according to a third embodiment.

【図６】従来の半導体装置の断面図である。FIG. 6 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１００ 半導体基板 １０１ 延長ドレイン領域 １０２ アンチパンチスルー領域 １０３Ａ 第１のｐ型埋め込み領域 １０３Ｂ 第２のｐ型埋め込み領域 １０３Ｃ 第３のｐ型埋め込み領域 １０３Ｄ 第４のｐ型埋め込み領域 １０４Ａ 第１のｎ型高濃度領域 １０４Ｂ 第２のｎ型高濃度領域 １０４Ｃ 第３のｎ型高濃度領域 １０４Ｄ 第４のｎ型高濃度領域 １０５ ソース領域 １０６ 基板コンタクト領域 １０７ ゲート絶縁膜 １０８ ゲート電極 １０９ 絶縁膜 １１０ コンタクトホール １１１ ドレイン電極 １１２ ソース電極 100 semiconductor substrate 101 Extended drain region 102 Anti punch through area 103A First p-type buried region 103B Second p-type buried region 103C Third p-type buried region 103D Fourth p-type buried region 104A First n-type high concentration region 104B Second n-type high concentration region 104C Third n-type high concentration region 104D Fourth n-type high concentration region 105 Source area 106 substrate contact area 107 gate insulating film 108 gate electrode 109 insulating film 110 contact holes 111 drain electrode 112 Source electrode

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 第１導電型の半導体基板にそれぞれ形成
された第２導電型のドレイン領域及びソース領域と、 前記ドレイン領域に上下に互いに間隔をおいて形成され
た第１導電型の不純物層からなり、下側に位置する第１
の埋め込み領域及び上側に位置する第２の埋め込み領域
と、 前記ドレイン領域における前記第１の埋め込み領域と前
記第２の埋め込み領域との間に形成されており、前記ド
レイン領域の不純物濃度よりも高い不純物濃度を有する
第２導電型の高濃度不純物領域と、 前記ドレイン領域における前記第２の埋め込み領域の上
側に形成されており、前記ドレイン領域の不純物濃度よ
りも高い不純物濃度を有する第２導電型の上方高濃度不
純物領域とを 備えていることを特徴とする半導体装置。1. A drain region and a source region of a second conductivity type respectively formed on a semiconductor substrate of a first conductivity type, and an impurity layer of the first conductivity type vertically spaced from each other in the drain region. Consisting of the first located on the lower side
A second buried region located buried region and the upper are formed between the first buried region in the drain region and the second buried region, said de
And <br/> high concentration impurity region of the second conductivity type having a higher impurity concentration than the impurity concentration of the rain region, on the second buried region in the drain region
Is formed on the side of the drain region, and the impurity concentration of the drain region is
Higher impurity concentration of the second conductivity type with higher impurity concentration
A semiconductor device comprising a pure region . 【請求項２】 前記ドレイン領域における前記第１の埋
め込み領域の下側に、前記第１の埋め込み領域との間に
間隔をおいて形成された第１導電型の不純物層からなる
下方埋め込み領域と、 前記ドレイン領域における前記第１の埋め込み領域と前
記下方埋め込み領域との間に形成されており、前記ドレ
イン領域の不純物濃度よりも高い不純物濃度を有する第
２導電型の下方高濃度不純物領域とをさらに備えている
ことを特徴とする請求項１に記載の半導体装置。2. A lower buried region formed of an impurity layer of the first conductivity type, which is formed below the first buried region in the drain region and is spaced apart from the first buried region. are formed between the first buried region and the lower buried region in said drain region, said drain
2. The semiconductor device according to claim 1, further comprising: a second conductivity type lower high-concentration impurity region having an impurity concentration higher than that of the in region . 【請求項３】 前記第１及び第２の埋め込み領域は、前
記半導体基板と電気的に接続されていることを特徴とす
る請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the first and second buried regions are electrically connected to the semiconductor substrate. 【請求項４】 第１導電型の半導体基板に第２導電型の
ドレイン領域及びソース領域をそれぞれ形成する工程
と、 前記ドレイン領域に第１導電型の第１の埋め込み領域を
形成する工程と、 前記ドレイン領域における前記第１の埋め込み領域の上
側に、前記ドレイン領域の不純物濃度よりも高い不純物
濃度を有する第２導電型の高濃度不純物領域を形成する
工程と、 前記ドレイン領域における前記第２導電型の高濃度不純
物領域の上側に第１導電型の第２の埋め込み領域を形成
する工程と、 前記ドレイン領域における前記第２の埋め込み領域の上
側に前記ドレイン領域の不純物濃度よりも高い不純物濃
度を有する第２導電型の上方高濃度不純物領域を形成す
る工程と を備えていることを特徴とする半導体装置の製
造方法。4. A step of forming a second conductivity type drain region and a source region on the first conductivity type semiconductor substrate, respectively, and a step of forming a first conductivity type first buried region in the drain region. Impurities higher than the impurity concentration of the drain region above the first buried region in the drain region
Forming a high concentration impurity region of the second conductivity type having a concentration, and forming a second buried region of the first conductivity type on the upper side of the high concentration impurity region of the second conductivity type in the drain region , on the second buried region in the drain region
The impurity concentration higher than that of the drain region on the side
Forming an upper high-concentration impurity region of the second conductivity type having a certain degree
A method of manufacturing a semiconductor device, comprising: 【請求項５】 前記第１の埋め込み領域及び前記第２の
埋め込み領域は、それぞれイオン注入法により形成され
ることを特徴とする請求項４に記載の半導体装置の製造
方法。5. The method for manufacturing a semiconductor device according to claim 4 , wherein the first buried region and the second buried region are each formed by an ion implantation method. 【請求項６】 前記高濃度不純物領域及び前記上方高濃
度不純物領域はイオン注入法により形成されることを特
徴とする請求項５に記載の半導体装置の製造方法。6. The high-concentration impurity region and the upper high-concentration region
The method for manufacturing a semiconductor device according to claim 5 , wherein the impurity region is formed by an ion implantation method.
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US6555883B1 (en) 2001-10-29 2003-04-29 Power Integrations, Inc. Lateral power MOSFET for high switching speeds
US6882023B2 (en) * 2002-10-31 2005-04-19 Motorola, Inc. Floating resurf LDMOSFET and method of manufacturing same
JP3888997B2 (en) 2003-12-12 2007-03-07 松下電器産業株式会社 Semiconductor device
US7859037B2 (en) 2007-02-16 2010-12-28 Power Integrations, Inc. Checkerboarded high-voltage vertical transistor layout
US8653583B2 (en) 2007-02-16 2014-02-18 Power Integrations, Inc. Sensing FET integrated with a high-voltage transistor
US7595523B2 (en) 2007-02-16 2009-09-29 Power Integrations, Inc. Gate pullback at ends of high-voltage vertical transistor structure
US10325988B2 (en) 2013-12-13 2019-06-18 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped field plates
US9543396B2 (en) 2013-12-13 2017-01-10 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped regions

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