JP3439969B2 - High frequency input / output terminal and high frequency semiconductor element storage package - Google Patents

High frequency input / output terminal and high frequency semiconductor element storage package

Info

Publication number
JP3439969B2
JP3439969B2 JP34550897A JP34550897A JP3439969B2 JP 3439969 B2 JP3439969 B2 JP 3439969B2 JP 34550897 A JP34550897 A JP 34550897A JP 34550897 A JP34550897 A JP 34550897A JP 3439969 B2 JP3439969 B2 JP 3439969B2
Authority
JP
Japan
Prior art keywords
dielectric
conductor layer
high frequency
output terminal
dielectric substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP34550897A
Other languages
Japanese (ja)
Other versions
JPH11176988A (en
Inventor
浩 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP34550897A priority Critical patent/JP3439969B2/en
Publication of JPH11176988A publication Critical patent/JPH11176988A/en
Application granted granted Critical
Publication of JP3439969B2 publication Critical patent/JP3439969B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Waveguide Connection Structure (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はミリ波帯等の高周波
用半導体素子収納用パッケージの高周波用入出力部に使
用される高周波用入出力端子ならびにその高周波用入出
力端子を用いた高周波用半導体素子収納用パッケージに
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency input / output terminal used in a high frequency input / output section of a package for storing a high frequency semiconductor element in the millimeter wave band and the like, and a high frequency semiconductor using the high frequency input / output terminal. The present invention relates to a device storage package.

【0002】[0002]

【従来の技術】マイクロ波帯やミリ波帯等の高周波信号
を用いる高周波用半導体素子等を気密封止して収容する
高周波用半導体素子収納用パッケージの高周波信号の入
出力端子部においては、高周波伝送線路として誘電体基
板上に形成されたマイクロストリップ線路とハーメチッ
クシール部のストリップ線路を接合する構造が一般的に
用いられている。
2. Description of the Related Art A high-frequency signal input / output terminal portion of a high-frequency semiconductor element housing package for hermetically sealing a high-frequency semiconductor element using a high-frequency signal in the microwave band or millimeter wave band As a transmission line, a structure in which a microstrip line formed on a dielectric substrate and a strip line of a hermetically sealed portion are joined is generally used.

【0003】さらに、そのような入出力端子部につい
て、線路導体の特性インピーダンスを整合させて低反射
損失・低挿入損失を実現するとともに線路導体のアイソ
レーション特性を向上させるために、線路導体の両側に
等間隔で同一面接地導体層を設けて、伝送線路の形態を
グランド付のコプレーナ線路とする構造が用いられてい
る。
Furthermore, in order to realize a low reflection loss and a low insertion loss by matching the characteristic impedance of the line conductor with respect to such an input / output terminal portion and to improve the isolation characteristic of the line conductor, both sides of the line conductor are improved. There is used a structure in which the ground plane conductor layers are provided at equal intervals and the form of the transmission line is a coplanar line with a ground.

【0004】このような入出力端子部は、高周波用半導
体素子収納用パッケージの信号入出力部としてパッケー
ジに作り込まれるほかに、高周波用入出力端子として作
製されてパッケージに組み込まれて使用される。
Such an input / output terminal portion is formed in the package as a signal input / output portion of a package for housing a high frequency semiconductor element, and is also used as a high frequency input / output terminal in a package. .

【0005】上記のような構成の従来の高周波用入出力
端子は、例えばアルミナセラミック等から成る誘電体基
板の下面に下面接地導体層が、また上面に線路導体や同
一面接地導体層がタングステンやモリブデン等から成る
メタライズ金属層により形成され、その上にハーメチッ
クシール部を構成する、上面に上面接地導体層が形成さ
れた誘電体壁部材が線路導体と同一面接地導体層の一部
を挟んで接合され、あるいはハーメチックシール部の線
路部上に誘電体のコーティングを施して誘電体で成形さ
れ上面に上面接地導体層が形成されたキャップを接着し
て、しかる後、露出している線路部のメタライズ金属層
の表面に、ボンディングワイヤやボンディングリボンの
接合性を良好にするためにニッケル/金等のメッキ層を
被着することにより作製されていた。
In the conventional high-frequency input / output terminal having the above-mentioned structure, the lower surface ground conductor layer is formed on the lower surface of the dielectric substrate made of, for example, alumina ceramic, and the line conductor or the same-plane ground conductor layer is formed on the upper surface by tungsten or the like. A dielectric wall member formed of a metallized metal layer made of molybdenum or the like, on which a hermetically sealed portion is formed, and an upper surface grounding conductor layer formed on the upper surface, sandwiches a part of the grounding conductor layer on the same plane as the line conductor. Bond a cap that is bonded or coated on the line part of the hermetically sealed part with a dielectric and is molded with a dielectric and has an upper surface ground conductor layer formed on the upper surface.After that, expose the exposed line part. By depositing a plating layer of nickel / gold or the like on the surface of the metallized metal layer to improve the bondability of the bonding wire or bonding ribbon. It had been fabricated.

【0006】また、上記のような入出力端子部を有する
高周波用半導体素子収納用パッケージとしては、金属基
体および容器壁を形成する金属枠体を切り欠いて高周波
用入出力端子の取付部を形成し、この取付部に高周波用
入出力端子を嵌着したいわゆるメタルウォールタイプの
構成や、誘電体基板および容器壁を形成する誘電体枠体
を切り欠いて高周波用入出力端子の取付部を形成し、こ
の取付部に高周波用入出力端子を嵌着したいわゆるセラ
ミックウォールタイプの構成、あるいは誘電体基板およ
び金属枠体に同様に高周波用入出力端子を嵌着した構
成、誘電体基板および誘電体枠体に前記構成の高周波用
入出力端子を作り込んだ構成のもの等がある。
Further, in a package for housing a high frequency semiconductor element having the above-mentioned input / output terminal portion, a metal frame forming a metal base and a container wall is cut out to form a mounting portion for the high frequency input / output terminal. Then, the so-called metal wall type structure in which the high frequency input / output terminal is fitted to this mounting portion, or the dielectric frame body forming the dielectric substrate and the container wall is cut out to form the high frequency input / output terminal mounting portion. Then, a so-called ceramic wall type structure in which high-frequency input / output terminals are fitted to the mounting portion, or a structure in which high-frequency input / output terminals are similarly fitted to a dielectric substrate and a metal frame, a dielectric substrate and a dielectric There is a structure in which the high-frequency input / output terminal having the above-described structure is formed in the frame.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記の
ような構成の高周波用入出力端子および高周波用半導体
素子収納用パッケージの入出力端子部においては、ハー
メチックシール部において伝送線路の線路導体の両側に
同一面接地導体層を形成していることから、誘電体基板
と誘電体壁部材もしくは誘電体枠体との接合強度が低下
してしまい、デラミネーションが発生したり、半導体素
子の実装やキャップシールあるいは2次実装の際などに
熱ストレスが加わった場合にハーメチックシール部のシ
ールが破損したりするなど、ハーメチックシール部とし
て十分な接合強度を確保することが困難となるという問
題点があった。
However, in the high-frequency input / output terminal and the input / output terminal of the high-frequency semiconductor element accommodating package having the above-mentioned structure, the hermetically sealed portion is provided on both sides of the line conductor of the transmission line. Since the ground plane conductor layer is formed on the same surface, the bonding strength between the dielectric substrate and the dielectric wall member or the dielectric frame is reduced, resulting in delamination, mounting of semiconductor elements or cap sealing. Alternatively, there is a problem that it is difficult to secure sufficient bonding strength as the hermetically sealed portion, such as the seal of the hermetically sealed portion being damaged when heat stress is applied during secondary mounting.

【0008】これに対し、誘電体基板と誘電体壁部材も
しくは誘電体枠体との接合強度を確保するために、ハー
メチックシール部において同一面接地導体層を形成せ
ず、この部位で同一面接地導体層を分離させることが行
なわれている。
On the other hand, in order to secure the bonding strength between the dielectric substrate and the dielectric wall member or the dielectric frame, the same-plane ground conductor layer is not formed in the hermetic seal portion, and the same-plane ground is formed at this portion. Separation of the conductor layers is practiced.

【0009】しかしながら、この場合には同一面接地導
体層がハーメチックシール部において不連続となり、こ
の部分の伝送線路がストリップ線路の形態となることか
ら、グランド付のコプレーナ線路とストリップ線路とを
接合する形態となり、ハーメチックシール部で電磁界分
布が不連続となることにより、反射損失・挿入損失が増
大して高周波信号の伝送特性を悪化させてしまうという
問題点があった。
However, in this case, the ground conductor layer on the same surface is discontinuous in the hermetically sealed portion, and the transmission line in this portion is in the form of a strip line. Therefore, the coplanar line with ground and the strip line are joined. However, since the electromagnetic field distribution becomes discontinuous at the hermetically sealed portion, reflection loss and insertion loss increase, which deteriorates the transmission characteristics of high-frequency signals.

【0010】本発明は上記問題点に鑑みて案出されたも
のであり、その目的は、グランド付コプレーナ線路の形
態のハーメチックシール部を有し、高周波信号の伝搬モ
ードを揃えて反射損失・挿入損失を低減したすぐれた伝
送特性を有しつつ誘電体基板と誘電体壁部材との良好な
接合強度を有する高周波用入出力端子を提供することに
ある。
The present invention has been devised in view of the above problems, and an object thereof is to have a hermetic seal portion in the form of a coplanar line with a ground, and to make reflection modes and insertion of high frequency signals in the same propagation mode. An object of the present invention is to provide a high frequency input / output terminal having excellent transmission characteristics with reduced loss and good bonding strength between the dielectric substrate and the dielectric wall member.

【0011】また本発明の目的は、入出力端子部におい
てグランド付コプレーナ線路の形態のハーメチックシー
ル部を有し、高周波信号の伝搬モードを揃えて反射損失
・挿入損失を低減したすぐれた伝送特性を有しつつ誘電
体基板と誘電体壁部材との良好な接合強度を有する高周
波用半導体素子収納用パッケージを提供することにあ
る。
Another object of the present invention is to provide an excellent transmission characteristic in which the input / output terminal section has a hermetically sealed section in the form of a coplanar line with a ground and the high-frequency signal propagation modes are aligned to reduce reflection loss and insertion loss. An object of the present invention is to provide a package for housing a high-frequency semiconductor element, which has good bonding strength between the dielectric substrate and the dielectric wall member.

【0012】[0012]

【課題を解決するための手段】本発明の高周波用入出力
端子は、下面に下面接地導体層が、上面に線路導体とこ
の線路導体の両側に等間隔で配設された同一面接地導体
層とがそれぞれ形成された誘電体基板と、この誘電体基
板上に前記線路導体および同一面接地導体層の一部を挟
んで接合され、上面に上面接地導体層が形成された誘電
体壁部材とから成る高周波用入出力端子であって、前記
同一面接地導体層のうち前記誘電体基板と前記誘電体壁
部材とに挟まれた部位で、前記線路導体側の辺を除く領
域に導体非形成領域を設けたことを特徴とするものであ
る。
In the high frequency input / output terminal of the present invention, a lower surface ground conductor layer is provided on the lower surface, a line conductor is provided on the upper surface, and the same surface ground conductor layer is provided on both sides of the line conductor at equal intervals. And a dielectric substrate on which the line conductor and a part of the same-face ground conductor layer are sandwiched and joined on the dielectric substrate, and a top-face ground conductor layer is formed on the upper surface of the dielectric wall member. A high-frequency input / output terminal comprising a non-conductor in a region of the same-plane ground conductor layer that is sandwiched between the dielectric substrate and the dielectric wall member, except for a side on the line conductor side. It is characterized in that a region is provided.

【0013】また、本発明の高周波用入出力端子は、上
記構成において、前記導体非形成領域が、一辺が0.15m
m以上の矩形状または短径が0.15mm以上の楕円形状ま
たは面積が0.0225mm2 以上の円形状であることを特徴
とするものである。
Further, in the high frequency input / output terminal of the present invention, in the above structure, the conductor non-formation region has a side of 0.15 m.
It is characterized by having a rectangular shape with m or more, an elliptical shape with a minor axis of 0.15 mm or more, or a circular shape with an area of 0.0225 mm 2 or more.

【0014】本発明の第1の高周波用半導体素子収納用
パッケージは、上面に高周波用半導体素子を搭載するた
めの搭載部を有する基板と、この基板上に前記搭載部を
囲むように接合された枠体と、この枠体を切り欠いて形
成され、その側面および底面を導電性とした入出力端子
取付部と、この入出力端子取付部に嵌着された上記各構
成の高周波用入出力端子とから成ることを特徴とするも
のである。
The first package for housing a high-frequency semiconductor element according to the present invention is a substrate having a mounting portion for mounting a high-frequency semiconductor element on an upper surface, and is joined to the substrate so as to surround the mounting portion. A frame body, an input / output terminal mounting portion formed by cutting out the frame body and having conductive side and bottom surfaces, and a high-frequency input / output terminal of each of the above configurations fitted to the input / output terminal mounting portion. It consists of and.

【0015】また、本発明の第2の高周波用半導体素子
収納用パッケージは、下面に下面接地導体層が形成さ
れ、上面に高周波用半導体素子を搭載するための搭載部
を有する誘電体基板と、この誘電体基板の上面に前記搭
載部近傍から誘電体基板の外周近傍にかけて形成された
線路導体およびこの線路導体の両側に等間隔で配設され
た同一面接地導体層と、前記誘電体基板上に前記搭載部
を囲むとともに前記線路導体および前記同一面接地導体
層の一部を挟んで接合され、上面に上面接地導体層が形
成された誘電体枠体とを具備し、前記同一面接地導体層
のうち前記誘電体基板と前記誘電体枠体とに挟まれた部
位で、前記線路導体側の辺を除く領域に導体非形成領域
を設けたことを特徴とするものである。
A second high frequency semiconductor element housing package of the present invention is a dielectric substrate having a lower surface ground conductor layer formed on a lower surface and a mounting portion for mounting a high frequency semiconductor element on an upper surface. A line conductor formed on the upper surface of the dielectric substrate from near the mounting portion to near the outer periphery of the dielectric substrate, and coplanar ground conductor layers arranged on both sides of the line conductor at equal intervals. And a dielectric frame body surrounding the mounting part and sandwiching the line conductor and a part of the same-plane ground conductor layer, and forming a top-face ground conductor layer on the upper surface thereof. A conductor non-formation region is provided in a region of the layer sandwiched between the dielectric substrate and the dielectric frame, except for a side on the line conductor side.

【0016】さらに、本発明の第2の高周波用半導体素
子収納用パッケージは、上記構成において、前記導体非
形成領域が、一辺が0.15mm以上の矩形状または短径が
0.15mm以上の楕円形状または面積が0.0225mm2 以上
の円形状であることを特徴とするものである。
Further, in the second package for housing a semiconductor element for high frequency of the present invention, in the above structure, the conductor non-forming region has a rectangular shape with one side of 0.15 mm or more or a short diameter.
It is characterized by having an elliptical shape of 0.15 mm or more or a circular shape having an area of 0.0225 mm 2 or more.

【0017】本発明の高周波用入出力端子によれば、線
路導体の両側に等間隔で同一面接地導体層を配設し、そ
の同一面接地導体層のうち誘電体基板と誘電体壁部材と
に挟まれた部位で、線路導体側の辺を除く領域に導体非
形成領域を設けたことから、誘電体基板上に露出した部
分における伝送線路の形態と、誘電体基板と誘電体壁部
材とに挟まれた部分における伝送線路の形態とがいずれ
もコプレーナ線路構造となり、高周波信号の伝搬モード
が同様のモードとなって変化がなくなるため、ハーメチ
ックシール部において伝搬モードの相違による反射損失
や挿入損失が発生することがなくなって高周波信号に対
する良好な伝送特性を得ることができるとともに、導体
非形成領域において誘電体基板と誘電体壁部材とを強固
に接合させることができ、熱ストレスが加わった場合で
もハーメチックシール部のシールが破損したりすること
がなくなり、十分な接合強度を確保することができる。
According to the high frequency input / output terminal of the present invention, the ground conductor layers on the same plane are arranged at equal intervals on both sides of the line conductor, and the dielectric substrate and the dielectric wall member among the ground conductor layers on the same plane. Since the conductor non-formation area is provided in the area sandwiched between the areas other than the side on the line conductor side, the form of the transmission line in the exposed portion on the dielectric substrate, the dielectric substrate and the dielectric wall member The transmission line in the part sandwiched between the two forms a coplanar line structure, and the propagation mode of the high-frequency signal becomes the same mode and does not change.Therefore, reflection loss and insertion loss due to the difference in the propagation mode in the hermetic seal part. And the good transmission characteristics for high frequency signals can be obtained, and the dielectric substrate and the dielectric wall member can be firmly joined in the conductor non-formed area. Can, it is not possible to even if thermal stress is applied hermetic seal portion of the seal is damaged, it is possible to secure a sufficient bonding strength.

【0018】特に、導体非形成領域を一辺が0.15mm以
上の矩形状または短径が0.15mm以上の楕円形状または
面積が0.0225mm2 以上の円形状とした場合には、誘電
体基板と誘電体壁部材との良好な接合強度を確保するの
に十分な面積の導体非形成領域を有するとともに、高周
波信号の伝搬モードの変化も効果的に抑制することがで
きるものとなり、高信頼性でかつ良好な伝送特性を有す
る高周波用入出力端子となる。
In particular, in the case where the conductor non-formation area has a rectangular shape with one side of 0.15 mm or more, an elliptical shape with a minor axis of 0.15 mm or more, or a circular shape with an area of 0.0225 mm 2 or more, the dielectric substrate and the dielectric In addition to having a conductor non-formation area of an area sufficient to secure good joint strength with the wall member, it is also possible to effectively suppress changes in the propagation mode of the high frequency signal, which is highly reliable and good. It becomes a high frequency input / output terminal having excellent transmission characteristics.

【0019】また、本発明の第1の高周波用半導体素子
収納用パッケージによれば、その入出力端子部の構造と
して上記の本発明に係る高周波用入出力端子を用いてい
ることから、上記と同様にハーメチックシール部におけ
る伝搬モードの相違による反射損失や挿入損失が発生す
ることがなくなって高周波信号に対する良好な伝送特性
を有するとともに、導体非形成領域において誘電体基板
と誘電体壁部材とを強固に接合させることができ、熱ス
トレスに対しても十分な接合強度を確保することができ
る高信頼性の入出力端子部を備えた高周波用半導体素子
収納用パッケージとなる。
Further, according to the first package for housing a high frequency semiconductor element of the present invention, since the high frequency input / output terminal according to the present invention is used as the structure of the input / output terminal portion, Similarly, reflection loss and insertion loss due to the difference in the propagation mode in the hermetically sealed portion do not occur, and good transmission characteristics for high frequency signals are achieved, and the dielectric substrate and the dielectric wall member are firmly formed in the conductor non-formed area. A high-frequency semiconductor element housing package including a highly reliable input / output terminal portion that can be bonded to a substrate and can secure sufficient bonding strength against heat stress.

【0020】また、本発明の第2の高周波用半導体素子
収納用パッケージによれば、上記の高周波用入出力端子
ならびに第1の高周波用半導体素子収納用パッケージと
同様に、誘電体基板と誘電体枠体とから成るハーメチッ
クシール部における伝搬モードの相違による反射損失や
挿入損失が発生することがなくなって高周波信号に対す
る良好な伝送特性を有するとともに、導体非形成領域に
おいて誘電体基板と誘電体枠体とを強固に接合させるこ
とができ、熱ストレスに対しても十分な接合強度を確保
することができる高信頼性の入出力端子部を備えた高周
波用半導体素子収納用パッケージとなる。
Further, according to the second high frequency semiconductor element accommodating package of the present invention, similar to the above high frequency input / output terminal and the first high frequency semiconductor element accommodating package, the dielectric substrate and the dielectric are used. The hermetically sealed part consisting of the frame does not cause reflection loss or insertion loss due to the difference in the propagation mode, and has good transmission characteristics for high frequency signals, and the dielectric substrate and the dielectric frame in the conductor non-formation area. And a high-reliability input / output terminal portion capable of firmly bonding and to secure sufficient bonding strength against heat stress.

【0021】[0021]

【発明の実施の形態】以下、本発明を図面に基づき説明
する。なお、本発明は以下の例に限定されるものではな
く、本発明の要旨を逸脱しない範囲で変更・改良を施す
ことは何ら差し支えない。
DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings. The present invention is not limited to the following examples, and modifications and improvements may be made without departing from the scope of the present invention.

【0022】図1は本発明の高周波用入出力端子の実施
の形態の一例を示す分解斜視であり、同図において、1
は誘電体基板、2は誘電体壁部材であり、これらは高周
波回路用パッケージの信号入出力部においてハーメチッ
クシール部(気密封止部)としても利用される。誘電体
基板1の下面には下面接地導体層3が、上面には線路導
体4とこの線路導体4の両側に等間隔で配設された同一
面接地導体層5とがそれぞれ形成されている。
FIG. 1 is an exploded perspective view showing an example of an embodiment of a high frequency input / output terminal of the present invention. In FIG.
Is a dielectric substrate, and 2 is a dielectric wall member, and these are also used as a hermetic seal portion (airtight sealing portion) in a signal input / output portion of a high frequency circuit package. A lower surface ground conductor layer 3 is formed on the lower surface of the dielectric substrate 1, and a line conductor 4 and a same-plane ground conductor layer 5 arranged on both sides of the line conductor 4 at equal intervals are formed on the upper surface.

【0023】一方、誘電体壁部材2は、その上面に上面
接地導体層6が形成されており、図1中に誘電体基板1
上に点線で示した部位に、誘電体基板1とともに線路導
体4および同一面接地導体層5の一部を挟むように接合
されている。
On the other hand, the dielectric wall member 2 has an upper surface ground conductor layer 6 formed on the upper surface thereof, and the dielectric substrate 1 is shown in FIG.
The line conductor 4 and a part of the same-plane grounding conductor layer 5 are joined together with the dielectric substrate 1 at the portion shown by the dotted line above.

【0024】なお、この例では線路導体4の線幅を誘電
体基板1上で露出している部位に対して誘電体基板1と
誘電体壁部材2とに挟まれた部位で狭くしており、これ
によりハーメチックシール部とその前後における線路導
体4の特性インピーダンスの整合をとるようにしてい
る。
In this example, the line width of the line conductor 4 is made narrower at the portion sandwiched between the dielectric substrate 1 and the dielectric wall member 2 than at the portion exposed on the dielectric substrate 1. As a result, the characteristic impedances of the line conductor 4 before and after the hermetic seal portion are matched.

【0025】また、この例では誘電体基板1の側面には
下部側面接地導体層7が、誘電体壁部材2の側面には上
部側面接地導体層8が形成されており、下面接地導体層
3と同一面接地導体層5と上面接地導体層6とは、下部
側面接地導体層7と上部側面接地導体層8により電気的
に接続されて同電位の接地面を形成している。これら下
部側面接地導体層7および上部側面接地導体層8を設け
た場合には、線路導体4aの周囲を接地導体層で囲むこ
ととなって高周波信号に対するシールドとすることがで
きる。
In this example, the lower side ground conductor layer 7 is formed on the side surface of the dielectric substrate 1, and the upper side ground conductor layer 8 is formed on the side surface of the dielectric wall member 2. The same-plane ground conductor layer 5 and the upper-face ground conductor layer 6 are electrically connected by the lower-side ground conductor layer 7 and the upper-side ground conductor layer 8 to form a ground plane of the same potential. When the lower side ground conductor layer 7 and the upper side ground conductor layer 8 are provided, the line conductor 4a is surrounded by the ground conductor layer, so that a shield can be made for a high frequency signal.

【0026】なお、下部側面接地導体層7および上部側
面接地導体層8は必ずしも必要とするものではなく、こ
れらの代わりに、例えば誘電体基板1内および誘電体壁
部材2内にそれぞれスルーホール導体やビア導体等の貫
通導体を形成して各接地導体層3・5・6を電気的に接
続してもよく、この高周波用入出力端子をパッケージに
組み込んだ際に他の導電手段により電気的に接続しても
よい。
The lower side ground conductor layer 7 and the upper side ground conductor layer 8 are not necessarily required, and instead of these, for example, through-hole conductors are provided in the dielectric substrate 1 and the dielectric wall member 2, respectively. A through conductor such as a via conductor or a via conductor may be formed to electrically connect the ground conductor layers 3, 5 and 6 to each other. When the high frequency input / output terminal is incorporated in a package, it is electrically connected by another conductive means. You may connect to.

【0027】そして、本発明の高周波用入出力端子にお
いては、同一面接地導体層5のうち、誘電体基板1と誘
電体壁部材2とに挟まれた部位で、線路導体4側の辺を
除く領域に、矩形状等の導体非形成領域9を設けたこと
が特徴である。このように、同一面接地導体層5のうち
誘電体基板1と誘電体壁部材2とに挟まれた部位に導体
非形成領域9を設けたことにより、導体非形成領域9に
おいては同一面接地導体層5を介することなく誘電体基
板1と誘電体壁部材2とを直接に強固に接合させること
ができ、ハーメチックシール部においてデラミネーショ
ンが発生したり、この高周波用入出力端子を使用したパ
ッケージにおける半導体素子の実装やキャップシールあ
るいは2次実装の際などに熱ストレスが加わった場合に
ハーメチックシール部のシールが破損したりすることが
なくなり、十分な接合強度を有する接合信頼性の高い高
周波用入出力端子となる。
In the high frequency input / output terminal of the present invention, the side of the ground conductor layer 5 on the side of the line conductor 4 at the portion sandwiched between the dielectric substrate 1 and the dielectric wall member 2 is connected. The feature is that a conductor-free area 9 having a rectangular shape or the like is provided in the area other than the area. In this way, the conductor non-formation region 9 is provided in a portion of the same plane ground conductor layer 5 sandwiched between the dielectric substrate 1 and the dielectric wall member 2, so that the conductor non-formation region 9 is grounded on the same face. The dielectric substrate 1 and the dielectric wall member 2 can be directly and firmly bonded to each other without the intermediary of the conductor layer 5, delamination occurs in the hermetic seal portion, and a package using this high frequency input / output terminal. For high-frequency waves with sufficient bonding strength and high reliability with which the seal of the hermetically sealed part will not be damaged when heat stress is applied during mounting of semiconductor elements, cap sealing or secondary mounting in It becomes an input / output terminal.

【0028】また、矩形状等の導体非形成領域9を線路
導体4側の辺を除く領域に設けたことから、同一面接地
導体層5を連続的な一様な接地面として線路導体4と対
向させることができ、これにより、誘電体基板1上に露
出した部分における伝送線路の形態と、誘電体基板1と
誘電体壁部材2とに挟まれた部分、すなわちハーメチッ
クシール部における伝送線路の形態とがいずれもコプレ
ーナ線路構造となり、高周波信号の伝搬モードが同様の
モードとなってその変化がなくなるため、ハーメチック
シール部において伝搬モードの相違による反射損失や挿
入損失が発生することがなくなって高周波信号に対する
良好な伝送特性を得ることができる高周波特性の良好な
高周波用入出力端子となる。
Further, since the conductor-free area 9 having a rectangular shape or the like is provided in the area excluding the side on the line conductor 4 side, the same-plane ground conductor layer 5 is used as a continuous and uniform ground plane to form the line conductor 4. It is possible to make them face each other, and thereby, the form of the transmission line in the exposed portion on the dielectric substrate 1 and the portion sandwiched between the dielectric substrate 1 and the dielectric wall member 2, that is, the transmission line in the hermetically sealed portion. Both forms have a coplanar line structure, and the propagation mode of the high-frequency signal becomes the same mode and its change disappears, so that reflection loss and insertion loss due to the difference of the propagation mode do not occur in the hermetically sealed portion, and the high-frequency signal is not generated. It becomes a high-frequency input / output terminal with good high-frequency characteristics that can obtain good transmission characteristics for signals.

【0029】本発明の高周波用入出力端子において、誘
電体基板1および誘電体壁部材2としては、例えばアル
ミナやムライト等のセラミックス材料、あるいはガラス
セラミックス、あるいはテフロン(PTFE)・ガラス
エポキシ・ポリイミド等の樹脂系材料などが用いられ
る。
In the high frequency input / output terminal of the present invention, as the dielectric substrate 1 and the dielectric wall member 2, for example, a ceramic material such as alumina or mullite, glass ceramics, Teflon (PTFE), glass epoxy, polyimide or the like is used. Resin-based materials and the like are used.

【0030】これら誘電体の厚みや幅・長さは、伝送さ
れる高周波信号の周波数や特性インピーダンスなどに応
じて適宜設定される。本発明においては、誘電体基板1
の厚みは比較的薄い方がよく、例えば0.1 〜1.0 mm、
好適には0.1 〜0.5 mm程度とすることで、誘電体損が
小さくなって伝送損失が小さくなり、一層良好なものと
なる。誘電体基板1の厚みが0.1 mm未満となると実際
に製造が困難となる傾向があり、他方、1.0 mmを超え
ると誘電体損が大きくなって伝送損失が大きくなる傾向
がある。
The thickness, width and length of these dielectrics are appropriately set according to the frequency and characteristic impedance of the transmitted high frequency signal. In the present invention, the dielectric substrate 1
It is better that the thickness of is relatively thin, for example 0.1-1.0 mm,
Preferably, by setting the thickness to about 0.1 to 0.5 mm, the dielectric loss becomes small, the transmission loss becomes small, and it becomes even better. If the thickness of the dielectric substrate 1 is less than 0.1 mm, it tends to be difficult to actually manufacture it. On the other hand, if it exceeds 1.0 mm, the dielectric loss becomes large and the transmission loss tends to become large.

【0031】また誘電体基板1の幅は比較的小さい方が
よく、例えば0.5 〜3.0 mm程度とすることで、共振周
波数を高くできて、一層良好なものとなる。誘電体基板
1の幅が0.5 mm未満となると実際に製造が困難となる
傾向があり、他方、3.0 mmを超えるとスロット共振が
発生しやすくなって共振周波数を高くできなくなる傾向
がある。
It is preferable that the width of the dielectric substrate 1 is relatively small. For example, by setting the width to about 0.5 to 3.0 mm, the resonance frequency can be increased, which is more favorable. If the width of the dielectric substrate 1 is less than 0.5 mm, it tends to be difficult to actually manufacture it. On the other hand, if it exceeds 3.0 mm, slot resonance is likely to occur and the resonance frequency cannot be increased.

【0032】また、誘電体基板1の長さは比較的短い方
がよく、例えば1.5 〜5.0 mm程度とすることで、伝送
損失を小さくできて、一層良好なものとなる。誘電体基
板1の長さが1.5 mm未満となると実際に製造が困難と
なる傾向があり、他方、5.0mmを超えると導体損が大
きくなって伝送損失が大きくなる傾向がある。
Further, it is preferable that the length of the dielectric substrate 1 is relatively short. For example, by setting it to about 1.5 to 5.0 mm, the transmission loss can be reduced, and it becomes even better. If the length of the dielectric substrate 1 is less than 1.5 mm, it tends to be difficult to actually manufacture it. On the other hand, if it exceeds 5.0 mm, the conductor loss tends to increase and the transmission loss tends to increase.

【0033】誘電体壁部材2の厚みは比較的薄い方がよ
く、例えば0.2 〜1.0 mm程度とすることで、また誘電
体基板1より厚くすることが好ましく、これにより誘電
体損が小さくなって伝送損失が小さくなるとともに共振
周波数を高くでき、一層良好なものとなる。誘電体壁部
材2の厚みが0.2 mm未満となると実際に製造が困難と
なる傾向があり、他方、1.0 mmを超えると誘電体損が
大きくなって伝送損失が大きくなるとともにスロット共
振が発生しやすくなって共振周波数を高くできなくなる
傾向がある。
It is preferable that the thickness of the dielectric wall member 2 is relatively thin. For example, it is preferable that the thickness of the dielectric wall member 2 is about 0.2 to 1.0 mm, and that the dielectric wall member 2 is thicker than the dielectric substrate 1. This reduces the dielectric loss. The transmission loss can be reduced and the resonance frequency can be increased, which is even better. If the thickness of the dielectric wall member 2 is less than 0.2 mm, it tends to be difficult to actually manufacture it. On the other hand, if it exceeds 1.0 mm, the dielectric loss becomes large, the transmission loss becomes large, and slot resonance easily occurs. Therefore, there is a tendency that the resonance frequency cannot be increased.

【0034】また誘電体壁部材2の幅は比較的小さい方
がよく、例えば0.5 〜3.0 mm程度とすることで、共振
周波数を高くできて、一層良好なものとなる。誘電体壁
部材2の幅が0.5 mm未満となると実際に製造が困難と
なる傾向があり、他方、3.0mmを超えるとスロット共
振が発生しやすくなって共振周波数を高くできなくなる
傾向がある。
It is preferable that the width of the dielectric wall member 2 is relatively small. For example, by setting the width to about 0.5 to 3.0 mm, the resonance frequency can be increased, which is more favorable. If the width of the dielectric wall member 2 is less than 0.5 mm, it tends to be difficult to actually manufacture it. On the other hand, if it exceeds 3.0 mm, slot resonance is likely to occur and the resonance frequency cannot be increased.

【0035】また、誘電体壁部材2の長さは比較的短い
方がよく、例えば0.3 〜1.5 mm程度とすることで、誘
電体基板1との接合部におけるリークやクラックの発生
を防止しつつ伝送損失を小さくでき、また共振周波数を
高くできて、一層良好なものとなる。誘電体壁部材2の
長さが0.3 mm未満となると誘電体基板1との接合部に
おけるリークやクラックが発生しやすくなる傾向があ
り、他方、1.5 mmを超えると導体損や誘電体損が大き
くなって伝送損失が大きくなり、また共振周波数を高く
することができなくなる傾向がある。
The length of the dielectric wall member 2 is preferably relatively short. For example, by setting it to about 0.3 to 1.5 mm, it is possible to prevent the occurrence of leaks and cracks at the joint with the dielectric substrate 1. The transmission loss can be reduced, and the resonance frequency can be increased, which is even better. If the length of the dielectric wall member 2 is less than 0.3 mm, leaks and cracks tend to occur at the joint with the dielectric substrate 1, while if it exceeds 1.5 mm, the conductor loss and dielectric loss are large. Therefore, the transmission loss tends to increase, and the resonance frequency cannot be increased.

【0036】なお、誘電体壁部材2は誘電体基板1と同
じ材料を用いればよいが、異なる材料を用いて誘電体壁
部材2の誘電率と誘電体基板1の誘電率とを異ならせて
もよい。この場合は、例えば、誘電体基板1よりも誘電
体壁部材2の誘電率が低い方が好ましく、誘電体壁部材
2の誘電率をなるべく真空の誘電率に近づけるのがよ
く、それらにより、誘電体基板1と誘電体壁部材2との
接合部分とそれ以外の部分とにおける伝搬モードの変化
が小さくなり、伝送損失が小さくなるという点で好まし
いものとなる。
The dielectric wall member 2 may be made of the same material as the dielectric substrate 1, but different materials may be used to make the dielectric constant of the dielectric wall member 2 different from that of the dielectric substrate 1. Good. In this case, for example, the dielectric constant of the dielectric wall member 2 is preferably lower than that of the dielectric substrate 1, and it is preferable to make the dielectric constant of the dielectric wall member 2 as close as possible to that of the vacuum. This is preferable in that the change in the propagation mode at the joining portion between the body substrate 1 and the dielectric wall member 2 and the other portion is small, and the transmission loss is small.

【0037】線路導体4および同一面接地導体層5は、
高周波線路導体用の金属材料、例えばCuやMoMn+
Ni+Au、W+Ni+Au、Cr+Cu、Cr+Cu
+Ni+Au、Ta2 N+NiCr+Au、Ti+Pd
+Au、NiCr+Pd+Auなどを用いて厚膜印刷法
あるいは各種の薄膜形成方法やメッキ処理法などにより
形成され、その厚みや幅も伝送される高周波信号の周波
数や特性インピーダンスなどに応じて適宜設定される。
The line conductor 4 and the same-plane ground conductor layer 5 are
Metallic materials for high frequency line conductors, such as Cu and MoMn +
Ni + Au, W + Ni + Au, Cr + Cu, Cr + Cu
+ Ni + Au, Ta 2 N + NiCr + Au, Ti + Pd
+ Au, NiCr + Pd + Au and the like are formed by a thick film printing method, various thin film forming methods, a plating method or the like, and the thickness and width thereof are also appropriately set according to the frequency of the high frequency signal to be transmitted, the characteristic impedance and the like.

【0038】図1の例のように誘電体壁部材2と誘電体
基板1との接合部において線路導体4の線路幅をそれ以
外の部分での線路幅よりも狭くする場合、それらの幅
は、理想とする特性インピーダンスに対応する幅からそ
れ以外の部分での線路幅までの間で必要とする仕様に応
じて適宜設定される。
When the line width of the line conductor 4 at the junction between the dielectric wall member 2 and the dielectric substrate 1 is made narrower than the line width at the other portions as in the example of FIG. , Is appropriately set in accordance with the required specifications between the width corresponding to the ideal characteristic impedance and the line width in other portions.

【0039】また、線路導体4と同一面接地導体層5と
の間隔は、一般的な同一面接地導体層5を設ける場合の
標準的な設定とすればよい。そして、誘電体壁部材2と
誘電体基板1との接合部において同一面接地導体層5を
線路導体4に向けて等間隔に突出させるなどして特性イ
ンピーダンスの整合をより精密に行なってもよく、その
ような場合には電磁界的影響度を考慮して必要とする特
性に応じて適宜設定すればよい。
The distance between the line conductor 4 and the same-plane grounding conductor layer 5 may be set to a standard setting when a general same-plane grounding conductor layer 5 is provided. Then, the characteristic impedance matching may be performed more precisely by, for example, projecting the same-plane grounding conductor layer 5 toward the line conductor 4 at equal intervals at the joint between the dielectric wall member 2 and the dielectric substrate 1. In such a case, it may be appropriately set in consideration of the electromagnetic field influence degree according to the required characteristics.

【0040】同一面接地導体層5に導体非形成領域9を
設けるには、例えば厚膜印刷法においてその部分に導体
を印刷しないようにしたり、各種の薄膜形成方法におい
て適当なマスクを用いて導体を形成しないようにした
り、一様な同一面接地導体層5を形成した後にフォトリ
ソグラフィ法などにより導体層の一部をエッチングして
除去したりすることにより、所望の位置に所定の形状・
寸法で設ければよい。
In order to provide the conductor non-formation region 9 in the same-plane ground conductor layer 5, for example, the conductor is not printed in the thick film printing method, or the conductor is formed by using an appropriate mask in various thin film forming methods. Not to be formed, or by forming a uniform ground conductor layer 5 on the same surface and then etching away a part of the conductor layer by a photolithography method or the like, thereby forming a predetermined shape at a desired position.
The size may be provided.

【0041】そして、導体非形成領域9の形状および寸
法としては、誘電体基板1と誘電体壁部材2との接合部
分に挟まれる部位の同一面接地導体層5の面積が、誘電
体基板1と誘電体壁部材2との接合部分でのクラックに
よるリークの発生を防止するとともに伝送損失を小さく
しておく必要性から、通常は0.05〜1.5 mm2 程度に設
定されることから、その部位中で、一辺が0.15mm以上
の矩形状、または短径が0.15mm以上の楕円形状、また
は面積が0.0225mm2 以上の円形状とすれば、同一面接
地導体層5として必要な機能を維持しつつこの導体非形
成領域9において誘電体基板1と誘電体壁部材2との間
で強固な接合強度を得ることができ、ハーメチックシー
ル部としての良好な接合強度を確保できるとともに高周
波信号の伝搬モードの変化も効果的に抑制することがで
き、高信頼性でかつ良好な伝送特性を有する高周波用入
出力端子となる。
As for the shape and size of the conductor non-forming region 9, the area of the same-plane ground conductor layer 5 at the portion sandwiched between the joint portion between the dielectric substrate 1 and the dielectric wall member 2 is the dielectric substrate 1 Since it is necessary to prevent the occurrence of leakage due to cracks at the joint between the dielectric wall member 2 and the dielectric wall member 2 and to reduce the transmission loss, it is usually set to about 0.05 to 1.5 mm 2 , With a rectangular shape with one side of 0.15 mm or more, an elliptical shape with a minor axis of 0.15 mm or more, or a circular shape with an area of 0.0225 mm 2 or more, while maintaining the function required as the same-plane ground conductor layer 5. In the conductor non-forming region 9, a strong joint strength can be obtained between the dielectric substrate 1 and the dielectric wall member 2, a good joint strength as a hermetic seal portion can be secured, and a high-frequency signal propagation mode can be obtained. change Can be effectively suppressed, and high-frequency input and output terminals with high reliability and and good transmission characteristics.

【0042】下面接地導体層3・上部接地導体層6およ
び下部側面接地導体層7・上部側面接地導体層8は、線
路導体4および同一面接地導体層5と同様の材料を用い
て同様の方法により誘電体基板1の下面・誘電体壁部材
2の上面およびそれらの側面のほぼ全面に被着形成され
る。その厚みは、例えば厚膜であれば20μm程度、薄膜
であれば5μm程度に設定される。
The lower ground conductor layer 3, the upper ground conductor layer 6, the lower side ground conductor layer 7, and the upper side ground conductor layer 8 are made of the same materials as the line conductor 4 and the same-plane ground conductor layer 5, and are processed in the same manner. As a result, the lower surface of the dielectric substrate 1, the upper surface of the dielectric wall member 2 and substantially the entire side surfaces thereof are deposited. The thickness is set to, for example, about 20 μm for a thick film and about 5 μm for a thin film.

【0043】なお、下面接地導体層3や上面接地導体層
6・下部側面接地導体層7・上部側面接地導体層8は、
上記のように金属被膜層として形成される場合の他に、
金属板や金属ブロックを取着することにより形成される
場合もある。
The lower ground conductor layer 3, the upper ground conductor layer 6, the lower side ground conductor layer 7, and the upper side ground conductor layer 8 are
In addition to the case where it is formed as a metal coating layer as described above,
It may be formed by attaching a metal plate or a metal block.

【0044】次に、本発明の第1の高周波用半導体素子
収納用パッケージについて図2に基づいて説明する。図
2は本発明の第1の高周波用半導体素子収納用パッケー
ジの実施の形態の一例を示す分解斜視図である。
Next, the first package for housing a high frequency semiconductor element of the present invention will be described with reference to FIG. FIG. 2 is an exploded perspective view showing an example of an embodiment of the first high-frequency semiconductor element housing package of the present invention.

【0045】同図において11は誘電体または金属等から
成る基板であり、その上面には高周波用半導体素子(図
示せず)を搭載するための搭載部11aを有している。本
例は搭載部11aを基板11上に平坦面として形成した例で
あるが、搭載部11aは凹状に形成したものであってもよ
い。12は、誘電体基板11上に点線で示した位置に、基板
11上に搭載部11aを囲むように接合された枠体であり、
基板11と同様に誘電体または金属等から成る。
In the figure, reference numeral 11 is a substrate made of a dielectric or metal, etc., and has a mounting portion 11a on its upper surface for mounting a high frequency semiconductor element (not shown). In this example, the mounting portion 11a is formed as a flat surface on the substrate 11, but the mounting portion 11a may be formed in a concave shape. 12 is the substrate at the position shown by the dotted line on the dielectric substrate 11.
It is a frame body joined on 11 so as to surround the mounting portion 11a,
Like the substrate 11, it is made of a dielectric material, a metal, or the like.

【0046】また、13は枠体12を切り欠いて形成され、
その側面および底面を導電性とした入出力端子取付部で
ある。なお、入出力端子取付部13を形成するために、基
板11にも同様の切欠きを設けてもよい。この入出力端子
取付部13の側面および底面は、基板11および枠体13が金
属から成る場合は導電性であるが、基板11および枠体13
が誘電体から成る場合には導体層を被着形成することに
よって導電性とする。これら側面と底面とは、いずれも
基板11および枠体12あるいはそれらに被着形成された接
地導体層(図示せず)を介して接地されている。
Further, 13 is formed by cutting out the frame body 12,
It is an input / output terminal mounting portion whose side and bottom surfaces are made conductive. In addition, in order to form the input / output terminal attachment portion 13, the board 11 may be provided with a similar notch. The side surface and the bottom surface of the input / output terminal mounting portion 13 are electrically conductive when the substrate 11 and the frame body 13 are made of metal, but the substrate 11 and the frame body 13 are electrically conductive.
When is made of a dielectric material, it is made conductive by depositing a conductor layer. Both the side surface and the bottom surface are grounded via the substrate 11 and the frame body 12 or the ground conductor layer (not shown) formed and adhered to them.

【0047】そして、14は入出力端子取付部13に図2中
に一点鎖線で示すように嵌着され、基板11上に点線で示
した位置に枠体12とともに接合された前述の本発明に係
る高周波用入出力端子である。この高周波用入出力端子
14において、15は誘電体基板、16は誘電体壁部材、17は
誘電体基板15の下面の下面接地導体層、18は誘電体基板
15の上面に形成された線路導体、19は線路導体18の両側
に等間隔で配設された同一面接地層、20は誘電体壁部材
16の上面に形成された上面接地導体層、21は下部側面接
地導体層、22は上部側面接地導体層である。
Further, 14 is fitted to the input / output terminal mounting portion 13 as shown by the one-dot chain line in FIG. 2, and is joined with the frame 12 at the position shown by the dotted line on the substrate 11 in the above-mentioned present invention. It is such a high frequency input / output terminal. This high frequency input / output terminal
In FIG. 14, reference numeral 15 is a dielectric substrate, 16 is a dielectric wall member, 17 is a lower surface ground conductor layer on the lower surface of the dielectric substrate 15, and 18 is a dielectric substrate.
Line conductors formed on the upper surface of 15; 19 are ground planes on the same plane, which are arranged on both sides of the line conductor 18 at equal intervals; and 20 are dielectric wall members.
The upper surface ground conductor layer is formed on the upper surface of 16, 21 is a lower side surface ground conductor layer, and 22 is an upper side surface ground conductor layer.

【0048】下面接地導体層17と同一面接地層19と上面
接地導体層20とは、下部側面接地導体層21および上部側
面接地導体層22と電気的に接続されて同電位の接地面を
形成している。誘電体壁部材16は誘電体基板15上に線路
導体18および同一面接地導体層19の一部を挟んで接合さ
れており、その接合部位における同一面接地導体層19の
線路導体18側の辺を除く領域には前述のような導体非形
成領域(図示せず)が設けられている。
The lower surface ground conductor layer 17, the same surface ground layer 19, and the upper surface ground conductor layer 20 are electrically connected to the lower side surface ground conductor layer 21 and the upper side surface ground conductor layer 22 to form a ground plane of the same potential. ing. The dielectric wall member 16 is joined on the dielectric substrate 15 with a part of the line conductor 18 and the same-plane ground conductor layer 19 interposed therebetween, and the side of the same-plane ground conductor layer 19 on the line conductor 18 side at the joint portion. Areas other than that are provided with the above-mentioned conductor non-formation areas (not shown).

【0049】このような本発明の第1の高周波用半導体
素子収納用パッケージによれば、その高周波用入出力端
子部の構造として前述の本発明に係る高周波用入出力端
子14を用いていることから、パッケージ内部に収容され
た高周波用半導体素子と外部電気回路との間における高
周波信号の伝送において高周波用入出力端子14における
伝搬モードの相違による反射損失や挿入損失が生ずるこ
とがなく高周波信号に対する良好な伝送特性を有すると
ともに、高周波用入出力端子14の誘電体基板15と誘電体
壁部材16とが同一面接地導体層19の導体非形成領域を介
して強固に接合し、ハーメチックシール部として高い接
合信頼性を有する高周波用入出力端子部を備えた、いわ
ゆるメタルウォールタイプの高周波用半導体素子収納用
パッケージとなる。
According to the first package for accommodating high frequency semiconductor elements of the present invention, the high frequency input / output terminal 14 according to the present invention is used as the structure of the high frequency input / output terminal portion. Therefore, in the transmission of the high frequency signal between the high frequency semiconductor element housed inside the package and the external electric circuit, there is no reflection loss or insertion loss due to the difference in the propagation mode at the high frequency input / output terminal 14 While having good transmission characteristics, the dielectric substrate 15 of the high-frequency input / output terminal 14 and the dielectric wall member 16 are firmly joined to each other through the conductor non-forming region of the ground conductor layer 19 on the same surface, and as a hermetic seal portion. This is a so-called metal wall type package for storing high-frequency semiconductor elements, which is provided with a high-frequency input / output terminal portion having high joint reliability.

【0050】そして、線路導体18を搭載部11aに搭載さ
れる高周波用半導体素子の端子電極ならびに外部電気回
路の配線導体にボンディングワイヤやリボン等を介して
接続してパッケージ内部の高周波用半導体素子と外部電
気回路とを電気的に接続し、枠体12の上面にFe−Ni
−CoやFe−Ni42アロイ等のFe−Ni合金・無酸
素銅・アルミニウム・ステンレス・Cu−W合金・Cu
−Mo合金などから成る蓋体を、半田・AuSnろう等
の低融点金属ろう材やAuGeロウ等の高融点金属ろう
材、あるいはシームウェルド(溶接)等により取着する
ことによって高周波用半導体素子がパッケージ内部に気
密封止して収容され、製品としての高周波用半導体装置
となる。
Then, the line conductor 18 is connected to the terminal electrode of the high frequency semiconductor element mounted on the mounting portion 11a and the wiring conductor of the external electric circuit via a bonding wire, a ribbon or the like to form a high frequency semiconductor element inside the package. It is electrically connected to an external electric circuit, and Fe-Ni is attached on the upper surface of the frame body 12.
Fe-Ni alloy such as -Co and Fe-Ni42 alloy, oxygen-free copper, aluminum, stainless steel, Cu-W alloy, Cu
-A high-frequency semiconductor element can be obtained by attaching a lid made of Mo alloy or the like with a low melting point metal brazing material such as solder or AuSn brazing, a high melting point metal brazing material such as AuGe brazing, or seam welding. It is hermetically sealed and housed inside the package, and becomes a high frequency semiconductor device as a product.

【0051】基板11および枠体12としては、パッケージ
の仕様に応じて高周波用入出力端子14の誘電体と同様の
誘電体あるいは上記の蓋体と同じ金属を用い、誘電体か
ら成る場合には少なくとも入出力端子取付部13の側面お
よび底面を導電性とする。
As the substrate 11 and the frame 12, the same dielectric as the dielectric of the high frequency input / output terminal 14 or the same metal as the lid is used according to the package specifications. At least the side surface and the bottom surface of the input / output terminal mounting portion 13 are made conductive.

【0052】また、基板11と枠体12とはAgCuろう・
AuSnろう・AuGeろう等の高融点金属ろう材によ
り接合される。また、高周波用入出力端子14は入出力端
子取付部13に嵌着され、枠体12および基板11に同様の高
融点金属ろう材により接合される。
The substrate 11 and the frame 12 are made of AgCu solder.
It is joined by a high melting point metal brazing material such as AuSn brazing / AuGe brazing. Further, the high frequency input / output terminal 14 is fitted in the input / output terminal mounting portion 13 and is joined to the frame 12 and the substrate 11 by a similar high melting point metal brazing material.

【0053】なお、誘電体壁部材16の上面は、入出力端
子取付部13を枠体12の上面に達する切欠きとして枠体12
の上面と同一面となるようにしてもよく、このようにす
ればこれらの上面に蓋体を直接あるいは枠状の金属シー
ル等を介して取着することにより、搭載部11aに搭載し
た高周波用半導体素子を内部に容易に気密封止して収容
できる。また、このとき誘電体壁部材16の上面と枠体12
の上面とが同一面とならない場合は、その段差を埋める
ような形状とした蓋体により、あるいは金属シールを介
することにより同様に高周波用半導体素子を内部に気密
封止して収容できる。
The upper surface of the dielectric wall member 16 is formed as a notch reaching the upper surface of the frame body 12 with the input / output terminal mounting portion 13 as a notch.
It may be flush with the upper surface of the above, and by doing so, by attaching the lid body to these upper surfaces directly or via a frame-shaped metal seal or the like, for high frequency mounted on the mounting portion 11a. The semiconductor element can be easily hermetically sealed inside. At this time, the upper surface of the dielectric wall member 16 and the frame 12
If it is not flush with the upper surface of the high frequency semiconductor element, the high frequency semiconductor element can be similarly hermetically sealed and housed inside by a lid body shaped to fill the step or via a metal seal.

【0054】また、本例では基板11の両側に高周波用入
出力端子14を1つずつ取り付けているが、必要に応じて
他の位置にも、あるいは1つの側に複数の端子を取り付
けてもよく、この場合には入出力端子取付部13を複数設
けて高周波用入出力端子14を並列的に複数取り付ければ
よい。
In this example, one high-frequency input / output terminal 14 is attached to each side of the board 11, but a plurality of terminals may be attached to another position or to one side if necessary. Of course, in this case, a plurality of input / output terminal mounting portions 13 may be provided and a plurality of high frequency input / output terminals 14 may be mounted in parallel.

【0055】また、下面接地導体層17や上面接地導体層
20あるいは下部側面接地導体層21や上部接地導体層22
は、金属被膜層として形成する場合の他に、貫通導体を
多数並べることにより、あるいはそれらを連結させるこ
とにより、ほぼ連続した接地導体層として被膜層と同様
に機能させるようにしてもよいし、金属板や金属ブロッ
クを取着することにより形成してもよい。
The bottom ground conductor layer 17 and the top ground conductor layer 17
20 or lower side ground conductor layer 21 or upper side ground conductor layer 22
In addition to the case where it is formed as a metal coating layer, by arranging a large number of through conductors or connecting them, they may function as a substantially continuous ground conductor layer in the same manner as the coating layer, It may be formed by attaching a metal plate or a metal block.

【0056】次に、本発明の第2の高周波用半導体素子
収納用パッケージについて図3に基づいて説明する。図
3は本発明の第2の高周波用半導体素子収納用パッケー
ジの実施の形態の一例を示す分解斜視図である。
Next, the second package for housing a high frequency semiconductor element of the present invention will be described with reference to FIG. FIG. 3 is an exploded perspective view showing an example of an embodiment of a second high-frequency semiconductor element housing package of the present invention.

【0057】同図において、31は誘電体基板であり、前
述の誘電体基板1あるいは誘電体壁部材2と同様の材料
から成り、その上面には高周波用半導体素子(図示せ
ず)を搭載するための搭載部31aを有している。本例で
は搭載部31aを平坦面状に形成した例を示したが、搭載
部31aは凹状に形成してもよい。32は誘電体基板31の上
面に搭載部31a近傍から誘電体基板31の外周近傍にかけ
て形成された線路導体、33はその線路導体32の両側に等
間隔で配設された同一面接地導体層であり、34は誘電体
基板31上に搭載部31aを囲むとともに線路導体32および
同一面接地導体層33の一部を挟んで接合された誘電体枠
体である。また、35は誘電体基板31の下面に線路導体32
および同一面接地導体層33に対向して形成された下面接
地導体層、36は誘電体枠体34の上面に形成された上面接
地導体層である。37は下面接地導体層35と同一面接地導
体層33とを接続する下部接続導体層、38は同一面接地導
体層33と上面接地導体層36とを接続する上部接続導体層
であり、それぞれ前述の下部側面接地導体層21および上
部側面接地導体層22に相当するものである。
In the figure, reference numeral 31 denotes a dielectric substrate, which is made of the same material as that of the dielectric substrate 1 or the dielectric wall member 2 described above, and a high frequency semiconductor element (not shown) is mounted on the upper surface thereof. It has a mounting part 31a for. Although the mounting portion 31a is formed in a flat surface in this example, the mounting portion 31a may be formed in a concave shape. Reference numeral 32 denotes a line conductor formed on the upper surface of the dielectric substrate 31 from the vicinity of the mounting portion 31a to the vicinity of the outer periphery of the dielectric substrate 31, and 33 is a same-plane ground conductor layer arranged on both sides of the line conductor 32 at equal intervals. Reference numeral 34 denotes a dielectric frame body which is mounted on the dielectric substrate 31 so as to surround the mounting portion 31a and sandwich a part of the line conductor 32 and the same-plane grounding conductor layer 33. Further, 35 is a line conductor 32 on the lower surface of the dielectric substrate 31.
Also, a lower surface ground conductor layer formed to face the same surface ground conductor layer 33, and an upper surface ground conductor layer 36 formed on the upper surface of the dielectric frame 34. Reference numeral 37 denotes a lower connecting conductor layer that connects the lower surface ground conductor layer 35 and the same surface ground conductor layer 33, and 38 denotes an upper connecting conductor layer that connects the same surface ground conductor layer 33 and the upper surface ground conductor layer 36. Of the lower side ground conductor layer 21 and the upper side ground conductor layer 22.

【0058】そして、本発明の第2の高周波用半導体素
子収納用パッケージにおいては、誘電体枠体34は誘電体
基板31上に線路導体32および同一面接地導体層33の一部
を挟んで接合されており、その接合部位における同一面
接地導体層33の線路導体32側の辺を除く領域には前述の
ような導体非形成領域39が設けられている。
In the second package for accommodating high frequency semiconductor elements of the present invention, the dielectric frame 34 is joined on the dielectric substrate 31 with the line conductor 32 and a part of the same-plane grounding conductor layer 33 sandwiched therebetween. The conductor non-formation region 39 as described above is provided in a region of the joint portion except the side of the ground conductor layer 33 on the side of the line conductor 32.

【0059】このような構成の本発明の第2の高周波用
半導体素子収納用パッケージによれば、前述の本発明に
係る高周波用入出力端子と同様の構成の高周波信号の入
出力端子部を備えたことから、パッケージ内部に収容さ
れた高周波用半導体素子と外部電気回路との間における
高周波信号の伝送において高周波用入出力端子部におけ
る伝搬モードの相違による反射損失や挿入損失が生ずる
ことがなく高周波信号に対する良好な伝送特性を有する
とともに、高周波用入出力端子部の誘電体基板31と誘電
体枠体34とが同一面接地導体層33の導体非形成領域39を
介して強固に接合し、熱ストレスに対しても十分な接合
強度を確保することができる、ハーメチックシール部と
しての接合信頼性が高い高周波用入出力端子部を備え
た、いわゆるセラミックウォールタイプの高周波用半導
体素子収納用パッケージとなる。
According to the second package for accommodating high frequency semiconductor elements of the present invention having such a structure, the high frequency signal input / output terminal portion having the same structure as the high frequency input / output terminal according to the present invention is provided. Therefore, in the transmission of high frequency signals between the high frequency semiconductor element housed inside the package and the external electric circuit, there is no reflection loss or insertion loss due to the difference in the propagation mode at the high frequency input / output terminal section In addition to having good transmission characteristics for signals, the dielectric substrate 31 and the dielectric frame 34 of the high frequency input / output terminal portion are firmly joined via the conductor non-formed region 39 of the ground conductor layer 33 on the same plane, A so-called ceramic board equipped with a high-frequency input / output terminal section that has high joint reliability as a hermetic seal section that can secure sufficient joint strength against stress. The wall type of high-frequency semiconductor element storage package.

【0060】特に、導体非形成領域39を一辺が0.15mm
以上の矩形状または短径が0.15mm以上の楕円形状また
は面積が0.0225mm2 以上の円形状とした場合には、誘
電体基板31と誘電体枠体34との良好な接合強度を確保す
るのに十分な面積の導体非形成領域39を有するととも
に、高周波信号の伝搬モードの変化も効果的に抑制する
ことができるものとなり、高信頼性でかつ良好な伝送特
性を有する高周波用入出力端子部を備えた高周波用半導
体素子収納用パッケージとなる。
In particular, the conductor non-forming area 39 has a side of 0.15 mm.
When the rectangular shape or the elliptical shape having a minor axis of 0.15 mm or more or the circular shape having an area of 0.0225 mm 2 or more is used, good bonding strength between the dielectric substrate 31 and the dielectric frame 34 is ensured. In addition to having a conductor-unformed region 39 having a sufficient area, it is possible to effectively suppress changes in the propagation mode of the high-frequency signal, and the high-frequency input / output terminal section has high reliability and good transmission characteristics. And a package for housing a high frequency semiconductor device.

【0061】そして、この本発明の第2の高周波用半導
体素子収納用パッケージによれば、線路導体32を搭載部
31aに搭載される高周波用半導体素子の端子電極ならび
に外部電気回路の配線導体にボンディングワイヤやリボ
ン等を介して接続してパッケージ内部の高周波用半導体
素子と外部電気回路とを電気的に接続し、誘電体枠体34
の上面に前述の材料から成る蓋体を前述の取着方法によ
り取着することによって高周波用半導体素子がパッケー
ジ内部に気密封止して収容され、製品としての高周波用
半導体装置となる。
According to the second high-frequency semiconductor element accommodating package of the present invention, the line conductor 32 is mounted on the mounting portion.
The terminal electrodes of the high-frequency semiconductor element mounted on 31a and the wiring conductors of the external electric circuit are connected via bonding wires or ribbons to electrically connect the high-frequency semiconductor element inside the package and the external electric circuit. Dielectric frame 34
By attaching the lid made of the above-mentioned material to the upper surface of the above by the above-mentioned attaching method, the high-frequency semiconductor element is hermetically sealed and housed inside the package, and the high-frequency semiconductor device as a product is obtained.

【0062】誘電体基板31および誘電体枠体34として
は、パッケージの仕様に応じて前述の本発明に係る高周
波用入出力端子の誘電体と同様の誘電体を用いればよ
い。また、誘電体基板31の下面には下面接地導体層35と
同様に接地導体層をほぼ全面に形成しておくことが、下
面接地導体層35を理想的なグランド状態とすることが必
要な点から望ましい。
As the dielectric substrate 31 and the dielectric frame 34, the same dielectric as the dielectric of the high frequency input / output terminal according to the present invention may be used according to the package specifications. In addition, it is necessary to form a ground conductor layer on the lower surface of the dielectric substrate 31 almost entirely like the lower surface ground conductor layer 35 in order to make the lower surface ground conductor layer 35 in an ideal ground state. From desirable.

【0063】また、誘電体基板31と誘電体枠体34とは、
別個に作製したものを接合するほかにも、例えば焼成後
に誘電体基板31および誘電体枠体34となるセラミックグ
リーンシートを積層して焼成して一体化することにより
接合してもよい。また、線路導体32・同一面接地導体層
33・下面接地導体層35・上面接地導体層36は、例えばそ
れぞれ誘電体基板31・誘電体枠体34に導体ペーストを所
定パターンに印刷塗布あるいは埋設して誘電体基板31・
誘電体枠体34に焼成して一体化することにより被着形成
される。
The dielectric substrate 31 and the dielectric frame 34 are
In addition to joining the separately prepared ones, the ceramic green sheets to be the dielectric substrate 31 and the dielectric frame 34 after firing may be laminated and fired to be joined together. Also, the line conductor 32 and the ground conductor layer on the same plane
33, the lower surface ground conductor layer 35, and the upper surface ground conductor layer 36 are, for example, a dielectric substrate 31 and a dielectric frame 34, respectively, which are formed by printing or embedding a conductor paste in a predetermined pattern on the dielectric substrate 31.
The dielectric frame 34 is fired and integrated to be adhered and formed.

【0064】なお、本例では誘電体枠体34の高周波用入
出力端子部における前述の誘電体壁部材に相当する部分
は誘電体枠体34と一体としてその上面が誘電体枠体34の
上面と同一面となるようにしているが、このようにすれ
ばこれらの上面に蓋体(図示せず)を直接あるいは枠状
の金属シール等を介して取着することにより、搭載部31
aに搭載した高周波用半導体素子を内部に容易に気密封
止して収容できる。また前述のように段差があっても差
し支えない。
In this example, the portion corresponding to the above-mentioned dielectric wall member in the high frequency input / output terminal portion of the dielectric frame 34 is integrated with the dielectric frame 34 and its upper surface is the upper surface of the dielectric frame 34. However, if a lid (not shown) is attached to these upper surfaces directly or via a frame-shaped metal seal or the like, the mounting portion 31
The high-frequency semiconductor element mounted on a can be easily hermetically sealed inside. Further, there is no problem even if there is a step as described above.

【0065】また、誘電体壁部材に相当する部分の誘電
率を誘電体枠体34の他の部分と異ならせ、例えば低いも
のとすることにより、ハーメチックシール部とその前後
における高周波信号の伝搬モードをより近いものとし
て、反射損失・挿入損失を効果的に低減させることがで
きるものとすることもできる。
Further, by making the dielectric constant of the portion corresponding to the dielectric wall member different from that of the other portions of the dielectric frame 34, for example, to make it low, the propagation mode of the high frequency signal in the hermetic seal portion and in the front and rear thereof. Can be made closer, and reflection loss and insertion loss can be effectively reduced.

【0066】また、本例では誘電体基板31の両側に高周
波用入出力端子部を1つずつ設けているが、必要に応じ
て他の位置にも、あるいは1つの側に複数の入出力端子
部を設けてもよい。
Further, in this example, one high frequency input / output terminal portion is provided on each side of the dielectric substrate 31, but a plurality of input / output terminals may be provided at another position or on one side as required. You may provide a part.

【0067】さらに、この本発明の高周波用半導体素子
収納用パッケージにおいても、高周波用入出力端子部の
誘電体壁部材に相当する誘電体枠体34に下部接続導体層
37ならびに上部接続導体層38を設けた場合には、線路導
体32aの周囲を接地導体層で囲むこととなって高周波信
号に対するシールドとすることができる。
Further, also in the package for housing the high frequency semiconductor element of the present invention, the lower connecting conductor layer is provided on the dielectric frame 34 corresponding to the dielectric wall member of the high frequency input / output terminal portion.
When 37 and the upper connection conductor layer 38 are provided, the line conductor 32a is surrounded by the ground conductor layer, so that the line conductor 32a can be shielded against a high frequency signal.

【0068】また、下面接地導体層35や上面接地導体層
36、あるいは下部接続導体層37や上部接続導体層38も、
金属被膜層として形成する場合の他に貫通導体を多数並
べることにより、あるいはそれらを連結させることによ
り、ほぼ連続した接地導体層として被膜層と同様に機能
させるようにしてもよいし、金属板や金属ブロックを取
着することにより形成してもよい。
In addition, the bottom ground conductor layer 35 and the top ground conductor layer
36, or the lower connecting conductor layer 37 and the upper connecting conductor layer 38,
In addition to the case of forming the metal coating layer, a large number of through conductors may be arranged or connected to each other so as to function as a substantially continuous ground conductor layer in the same manner as the coating layer. It may be formed by attaching a metal block.

【0069】[0069]

【発明の効果】本発明の高周波用入出力端子によれば、
線路導体の両側に等間隔で同一面接地導体層を配設し、
その同一面接地導体層のうち誘電体基板と誘電体壁部材
とに挟まれた部位で、線路導体側の辺を除く領域に導体
非形成領域を設けたことから、ハーメチックシール部と
その前後における伝送線路の形態がいずれもコプレーナ
線路構造となり、高周波信号の伝搬モードの相違による
反射損失や挿入損失が発生することがなくなって高周波
信号に対する良好な伝送特性を得ることができるととも
に、導体非形成領域において誘電体基板と誘電体壁部材
とを強固に接合させることができ、熱ストレスが加わっ
た場合でもハーメチックシール部のシールが破損したり
することがない十分な接合強度を確保することができ
る。
According to the high frequency input / output terminal of the present invention,
Arrange equal-surface ground conductor layers at equal intervals on both sides of the line conductor,
Since the conductor non-formation area is provided in the area between the dielectric substrate and the dielectric wall member in the same-plane ground conductor layer except for the side on the line conductor side, All the transmission lines have a coplanar line structure, so that reflection loss and insertion loss due to the difference in the propagation mode of high frequency signals do not occur and good transmission characteristics for high frequency signals can be obtained, and the conductor non-formation area In (1), the dielectric substrate and the dielectric wall member can be firmly bonded to each other, and sufficient bonding strength can be secured without damaging the seal of the hermetically sealed portion even when heat stress is applied.

【0070】特に、導体非形成領域を一辺が0.15mm以
上の矩形状または短径が0.15mm以上の楕円形状または
面積が0.0225mm2 以上の円形状とした場合には、誘電
体基板と誘電体壁部材との良好な接合強度を確保するの
に十分な面積の導体非形成領域を有するとともに、高周
波信号の伝搬モードの変化も効果的に抑制することがで
きるものとなり、高信頼性でかつ良好な伝送特性を有す
る高周波用入出力端子となる。
In particular, in the case where the conductor non-formation region has a rectangular shape with one side of 0.15 mm or more, an elliptical shape with a minor axis of 0.15 mm or more, or a circular shape with an area of 0.0225 mm 2 or more, the dielectric substrate and the dielectric In addition to having a conductor non-formation area of an area sufficient to secure good joint strength with the wall member, it is also possible to effectively suppress changes in the propagation mode of the high frequency signal, which is highly reliable and good. It becomes a high frequency input / output terminal having excellent transmission characteristics.

【0071】また、本発明の第1の高周波用半導体素子
収納用パッケージによれば、その入出力端子部の構造と
して上記の本発明の高周波用入出力端子を用いているこ
とから、同様にハーメチックシール部における伝搬モー
ドの相違による反射損失や挿入損失が発生することがな
くなって高周波信号に対する良好な伝送特性を有すると
ともに、導体非形成領域において誘電体基板と誘電体壁
部材とを強固に接合させることができ、熱ストレスに対
しても十分な接合強度を確保できる高信頼性の入出力端
子部を備えた高周波用半導体素子収納用パッケージとな
る。
Further, according to the first high frequency semiconductor device housing package of the present invention, since the high frequency input / output terminal of the present invention is used as the structure of the input / output terminal portion, the hermetic Reflection loss and insertion loss due to the difference in the propagation mode in the seal portion do not occur, and it has good transmission characteristics for high frequency signals, and firmly joins the dielectric substrate and the dielectric wall member in the conductor non-formation region. A package for housing a high-frequency semiconductor element, which is provided with a highly reliable input / output terminal portion capable of ensuring sufficient bonding strength against heat stress.

【0072】また、本発明の第2の高周波用半導体素子
収納用パッケージによれば、その高周波入出力端子部に
おいて誘電体基板と誘電体枠体とに挟まれた部位の同一
面接地導体層の線路導体側の辺を除く領域に導体非形成
領域を設けたことから、上記の本発明の高周波用入出力
端子ならびに第1の高周波用半導体素子収納用パッケー
ジと同様に、誘電体基板と誘電体枠体とから成るハーメ
チックシール部における伝搬モードの相違による反射損
失や挿入損失が発生することがなくなって高周波信号に
対する良好な伝送特性を有するとともに、導体非形成領
域において誘電体基板と誘電体枠体とを強固に接合させ
ることができ、熱ストレスに対しても十分な接合強度を
確保することができる高信頼性の入出力端子部を備えた
高周波用半導体素子収納用パッケージとなる。
Further, according to the second package for accommodating a high frequency semiconductor element of the present invention, in the high frequency input / output terminal portion of the same-plane grounding conductor layer at a portion sandwiched between the dielectric substrate and the dielectric frame body. Since the conductor non-formed region is provided in the region other than the side on the side of the line conductor, the dielectric substrate and the dielectric body are provided similarly to the high frequency input / output terminal of the present invention and the first high frequency semiconductor device housing package. The hermetically sealed part consisting of the frame does not cause reflection loss or insertion loss due to the difference in the propagation mode, and has good transmission characteristics for high frequency signals, and the dielectric substrate and the dielectric frame in the conductor non-formation area. And a high-frequency semiconductor element having a highly reliable input / output terminal portion capable of firmly joining and to secure sufficient joining strength against heat stress. A package for housing.

【0073】以上により、本発明によれば、グランド付
コプレーナ線路の形態のハーメチックシール部を有し、
高周波信号の伝搬モードを揃えて反射損失・挿入損失を
低減したすぐれた伝送特性を有しつつ誘電体基板と誘電
体壁部材との良好な接合強度を有する高周波用入出力端
子を提供することができた。
As described above, according to the present invention, the hermetically sealed portion in the form of a coplanar line with a ground is provided,
(EN) It is possible to provide a high-frequency input / output terminal having excellent transmission characteristics in which the propagation modes of high-frequency signals are aligned and the reflection loss and insertion loss are reduced, while having good bonding strength between the dielectric substrate and the dielectric wall member. did it.

【0074】また、本発明によれば、入出力端子部にお
いてグランド付コプレーナ線路の形態のハーメチックシ
ール部を有し、高周波信号の伝搬モードを揃えて反射損
失・挿入損失を低減したすぐれた伝送特性を有しつつ誘
電体基板と誘電体壁部材との良好な接合強度を有する高
周波用半導体素子収納用パッケージを提供することがで
きた。
Further, according to the present invention, the input / output terminal portion has a hermetically sealed portion in the form of a coplanar line with a ground, and the transmission mode of a high frequency signal is made uniform to reduce reflection loss and insertion loss, which is excellent transmission characteristics. It was possible to provide a package for housing a high-frequency semiconductor element, which has good bonding strength between the dielectric substrate and the dielectric wall member while having the above.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の高周波用入出力端子の実施の形態の一
例を示す分解斜視図である。
FIG. 1 is an exploded perspective view showing an example of an embodiment of a high frequency input / output terminal of the present invention.

【図2】本発明の第1の高周波用半導体素子収納用パッ
ケージの実施の形態の一例を示す分解斜視図である。
FIG. 2 is an exploded perspective view showing an example of an embodiment of a first high frequency semiconductor element housing package of the present invention.

【図3】本発明の第2の高周波用半導体素子収納用パッ
ケージの実施の形態の一例を示す分解斜視図である。
FIG. 3 is an exploded perspective view showing an example of an embodiment of a second high-frequency semiconductor element housing package of the present invention.

【符号の説明】[Explanation of symbols]

1、15、31・・・・・誘電体基板 2、12、16・・・・・誘電体壁部材 3、17、35・・・・・下面接地導体層 4、18、32・・・・・線路導体 5、19、33・・・・・同一面接地導体層 6、20、36・・・・・上面接地導体層 9、39・・・・・・・導体非形成領域 11・・・・・・・・・基板 11a、31a・・・・・搭載部 12・・・・・・・・・枠体 13・・・・・・・・・入出力端子取付部 14・・・・・・・・・高周波用入出力端子 13・・・・・・・・・入出力端子取付部 14・・・・・・・・・高周波用入出力端子 1, 15, 31 ... Dielectric substrate 2, 12, 16 ... Dielectric wall member 3, 17, 35 ... Bottom ground conductor layer 4, 18, 32 ... Line conductor 5, 19, 33 ... Same-side ground conductor layer 6, 20, 36 ... Top ground conductor layer 9 ・ 39 ・ ・ ・ ・ ・ ・ Conductor-free area 11 ・ ・ ・ ・ ・ ・ ・ ・ Substrate 11a, 31a ... Mounting part 12 ・ ・ ・ ・ ・ ・ ・ ・ Frame 13 ・ ・ ・ ・ ・ ・ I / O terminal mounting part 14 ... High-frequency input / output terminal 13 ・ ・ ・ ・ ・ ・ I / O terminal mounting part 14 ... High-frequency input / output terminals

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 下面に下面接地導体層が、上面に線路導
体と該線路導体の両側に等間隔で配設された同一面接地
導体層とがそれぞれ形成された誘電体基板と、該誘電体
基板上に前記線路導体および同一面接地導体層の一部を
挟んで接合され、上面に上面接地導体層が形成された誘
電体壁部材とから成る高周波用入出力端子であって、前
記同一面接地導体層のうち前記誘電体基板と前記誘電体
壁部材とに挟まれた部位で、前記線路導体側の辺を除く
領域に導体非形成領域を設けたことを特徴とする高周波
用入出力端子。
1. A dielectric substrate having a lower surface ground conductor layer formed on a lower surface thereof, a line conductor formed on an upper surface thereof, and a same-plane ground conductor layer arranged on both sides of the line conductor at equal intervals, and the dielectric substrate. A high-frequency input / output terminal comprising a dielectric wall member having a line conductor and a part of the same-plane grounding conductor layer sandwiched on a substrate, and having an upper surface grounding conductor layer formed on the upper surface thereof. A high frequency input / output terminal characterized in that a conductor non-forming region is provided in a region of the ground conductor layer sandwiched between the dielectric substrate and the dielectric wall member, except for a side on the line conductor side. .
【請求項2】 前記導体非形成領域が、一辺が0.15mm
以上の矩形状または短径が0.15mm以上の楕円形状また
は面積が0.0225mm2 以上の円形状であることを特徴と
する請求項1記載の高周波用入出力端子。
2. The conductor non-formation area has a side of 0.15 mm.
2. The high frequency input / output terminal according to claim 1, wherein the rectangular shape or the elliptical shape having a minor axis of 0.15 mm or more or the circular shape having an area of 0.0225 mm 2 or more.
【請求項3】 上面に高周波用半導体素子を搭載するた
めの搭載部を有する基板と、該基板上に前記搭載部を囲
むように接合された枠体と、該枠体を切り欠いて形成さ
れ、その側面および底面を導電性とした入出力端子取付
部と、該入出力端子取付部に嵌着された請求項1または
請求項2記載の高周波用入出力端子とから成ることを特
徴とする高周波用半導体素子収納用パッケージ。
3. A substrate having a mounting portion for mounting a high frequency semiconductor element on an upper surface thereof, a frame body joined to the substrate so as to surround the mounting portion, and the frame body cut out to be formed. And an input / output terminal mounting portion whose side and bottom surfaces are electrically conductive, and the high-frequency input / output terminal according to claim 1 or 2 fitted to the input / output terminal mounting portion. Package for housing high frequency semiconductor devices.
【請求項4】 下面に下面接地導体層が形成され、上面
に高周波用半導体素子を搭載するための搭載部を有する
誘電体基板と、該誘電体基板の上面に前記搭載部近傍か
ら誘電体基板の外周近傍にかけて形成された線路導体お
よび該線路導体の両側に等間隔で配設された同一面接地
導体層と、前記誘電体基板上に前記搭載部を囲むととも
に前記線路導体および前記同一面接地導体層の一部を挟
んで接合され、上面に上面接地導体層が形成された誘電
体枠体とを具備し、前記同一面接地導体層のうち前記誘
電体基板と前記誘電体枠体とに挟まれた部位で、前記線
路導体側の辺を除く領域に導体非形成領域を設けたこと
を特徴とする高周波用半導体素子収納用パッケージ。
4. A dielectric substrate having a lower surface grounding conductor layer formed on a lower surface and a mounting portion for mounting a high frequency semiconductor element on an upper surface, and a dielectric substrate on the upper surface of the dielectric substrate in the vicinity of the mounting portion. A line conductor formed near the outer periphery of the line conductor, and a coplanar ground conductor layer disposed at equal intervals on both sides of the line conductor; and the line conductor and the coplanar ground line surrounding the mounting portion on the dielectric substrate. And a dielectric frame body having an upper surface ground conductor layer formed on the upper surface, the dielectric frame body being joined with a part of the conductor layer sandwiched between the dielectric substrate and the dielectric frame body in the same-plane ground conductor layer. A package for accommodating a high-frequency semiconductor element, characterized in that a conductor non-formation region is provided in a region excluding the side on the line conductor side in the sandwiched region.
【請求項5】 前記導体非形成領域が、一辺が0.15mm
以上の矩形状または短径が0.15mm以上の楕円形状また
は面積が0.0225mm2 以上の円形状であることを特徴と
する請求項4記載の高周波用半導体素子収納用パッケー
ジ。
5. The conductor non-formation region has a side of 0.15 mm.
The package for housing a high-frequency semiconductor element according to claim 4, wherein the rectangular shape or the elliptical shape having a minor axis of 0.15 mm or more or the circular shape having an area of 0.0225 mm 2 or more is used.
JP34550897A 1997-12-15 1997-12-15 High frequency input / output terminal and high frequency semiconductor element storage package Expired - Lifetime JP3439969B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34550897A JP3439969B2 (en) 1997-12-15 1997-12-15 High frequency input / output terminal and high frequency semiconductor element storage package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34550897A JP3439969B2 (en) 1997-12-15 1997-12-15 High frequency input / output terminal and high frequency semiconductor element storage package

Publications (2)

Publication Number Publication Date
JPH11176988A JPH11176988A (en) 1999-07-02
JP3439969B2 true JP3439969B2 (en) 2003-08-25

Family

ID=18377061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34550897A Expired - Lifetime JP3439969B2 (en) 1997-12-15 1997-12-15 High frequency input / output terminal and high frequency semiconductor element storage package

Country Status (1)

Country Link
JP (1) JP3439969B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4522010B2 (en) * 2001-03-16 2010-08-11 京セラ株式会社 I / O terminal and semiconductor element storage package and semiconductor device
JP4502543B2 (en) * 2001-04-24 2010-07-14 京セラ株式会社 Ceramic terminal and semiconductor device storage package
JP4540249B2 (en) * 2001-04-24 2010-09-08 京セラ株式会社 Ceramic terminal and semiconductor device storage package
JP4530579B2 (en) * 2001-05-22 2010-08-25 京セラ株式会社 Package for storing semiconductor elements
FR2864864B1 (en) 2004-01-07 2006-03-17 Thomson Licensing Sa MICROWAVE DEVICE OF THE LINE-SLIT TYPE WITH A PHOTONIC PROHIBITED BAND STRUCTURE
JP2010153547A (en) * 2008-12-25 2010-07-08 Nippon Telegr & Teleph Corp <Ntt> High frequency ic package
EP2485253B1 (en) 2009-09-29 2019-12-18 Kyocera Corporation Device housing package
JP2016171157A (en) * 2015-03-12 2016-09-23 株式会社東芝 High frequency semiconductor package
JP6672878B2 (en) * 2016-02-23 2020-03-25 三菱電機株式会社 Optical semiconductor device

Also Published As

Publication number Publication date
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