JP3376051B2 - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the sameInfo
- Publication number
- JP3376051B2 JP3376051B2 JP30406393A JP30406393A JP3376051B2 JP 3376051 B2 JP3376051 B2 JP 3376051B2 JP 30406393 A JP30406393 A JP 30406393A JP 30406393 A JP30406393 A JP 30406393A JP 3376051 B2 JP3376051 B2 JP 3376051B2
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- Japan
- Prior art keywords
- film
- amorphous silicon
- gate insulating
- forming
- sih
- Prior art date
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- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜トランジスタおよび
その製造方法に関し、特に液晶表示装置に用いられる薄
膜トランジスタ及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method, and more particularly to a thin film transistor used in a liquid crystal display device and its manufacturing method.
【０００２】[0002]
【従来の技術】図４に、従来の液晶表示装置を用いる薄
膜トランジスタの構造断面図を示す。図５はその等価回
路、図６は平面図であり、図４は図６のＸ−Ｘ断面図で
ある。ガラス基板１上に形成されたゲート電極５、画素
電極４が、その上にゲート絶縁膜の窒化珪素膜７が，そ
の上にソースバスライン１７が形成されている。このゲ
ート絶縁膜７上にノンドープの非晶質シリコン膜９、更
にその上にチャネル保護膜の窒化珪素膜１０のパターン
が、更にその上にＰをドープした非晶質シリコン膜１１
と、その上にソース電極１２及びドレイン電極１３が形
成されており、その上に保護膜１４が形成されている。2. Description of the Related Art FIG. 4 is a structural sectional view of a thin film transistor using a conventional liquid crystal display device. 5 is an equivalent circuit thereof, FIG. 6 is a plan view, and FIG. 4 is a sectional view taken along line XX of FIG. The gate electrode 5 and the pixel electrode 4 are formed on the glass substrate 1, the silicon nitride film 7 of the gate insulating film is formed thereon, and the source bus line 17 is formed thereon. A non-doped amorphous silicon film 9 is further formed on the gate insulating film 7, a pattern of a silicon nitride film 10 of a channel protective film is further formed thereon, and a P-doped amorphous silicon film 11 is further formed thereon.
Then, the source electrode 12 and the drain electrode 13 are formed thereon, and the protective film 14 is formed thereon.
【０００３】次に、この装置の動作を説明する。ソース
電極１３とドレイン電極１４間に電圧が印加されている
場合、ゲート電極に印加された電圧がある閾値をこえる
と、ノンドープ非晶質シリコン膜９のソース，ドレイン
間にチャネルが形成されこのチャネルを通じて電流が流
れる。上記のＰドープ非晶質シリコン層は、ソース，ド
レイン電極１３、１４とノンドープ非晶質シリコン層間
のオーミック接続のためのものである。又チャネル保護
膜１０は電流の路となるノンドープ非晶質シリコン層を
ソース，ドレイン間の分離のエッチングの際の損傷から
守り、膜質を保護するためのものである。Next, the operation of this device will be described. When a voltage is applied between the source electrode 13 and the drain electrode 14 and the voltage applied to the gate electrode exceeds a certain threshold value, a channel is formed between the source and the drain of the non-doped amorphous silicon film 9, and this channel is formed. An electric current flows through it. The P-doped amorphous silicon layer is for ohmic connection between the source / drain electrodes 13 and 14 and the non-doped amorphous silicon layer. The channel protective film 10 protects the non-doped amorphous silicon layer, which serves as a current path, from damage during the etching for separating the source and drain, and protects the film quality.
【０００４】図４により従来の薄膜トランジスタの製造
方法を説明する。図４に示すようにガラス基板１上にス
パッタ法によりＩＴＯ膜（インジウムティンオキサイ
ド）を成膜しこれをフォトエッチング法でパターニング
して画素電極４を又、スパッタ法でＣｒを成膜し、これ
をパターニングしてゲート電極５を形成する。又、次
に、ＣＶＤ法によりゲート絶縁膜の窒化珪素７、ノンド
ープの非晶質シリコン膜９、チャネル保護膜１１のＳｉ
Ｎを成膜する。A conventional method of manufacturing a thin film transistor will be described with reference to FIG. As shown in FIG. 4, an ITO film (indium tin oxide) is formed on the glass substrate 1 by a sputtering method and is patterned by a photo etching method to form a pixel electrode 4 and a Cr film by a sputtering method. Is patterned to form the gate electrode 5. Next, the silicon nitride 7 of the gate insulating film, the non-doped amorphous silicon film 9, and the Si of the channel protective film 11 are formed by the CVD method.
A film of N is formed.
【０００５】ゲート絶縁膜７は、成膜温度３００℃〜３
５０℃、高周波電力０．２〜０．４Ｗ／ｃｍ2、圧力１
３０〜１６０Ｐａで、成膜ガスにＮ2、ＳｉＨ4、ＮＨ3
の混合ガスを用い、ＮＨ3／ＳｉＨ4流量比を０．５〜２
として窒化珪素膜を３０００〜５０００オングストロー
ム成膜する。The gate insulating film 7 has a film forming temperature of 300 ° C. to 3 ° C.
50 ° C., high frequency power 0.2 to 0.4 W / cm 2 , pressure 1
In 30~160Pa, N 2, SiH 4, NH 3 in the film forming gas
NH 3 / SiH 4 flow rate ratio of 0.5 to 2
As a silicon nitride film, a film having a thickness of 3000 to 5000 angstrom is formed.
【０００６】次に上記絶縁膜７上にノンドープ非晶質シ
リコン膜１０を、成膜温度２５０〜２８０℃、高周波電
力０．０１〜０．０３Ｗ／ｃｍ2、圧力８０〜１６０Ｐ
ａで、成膜ガスにＳｉＨ4、Ｈ2の混合ガスを用いて５０
０〜２０００オングストローム成膜する。Next, a non-doped amorphous silicon film 10 is formed on the insulating film 7 at a film forming temperature of 250 to 280 ° C., a high frequency power of 0.01 to 0.03 W / cm 2 , and a pressure of 80 to 160 P.
a, using a mixed gas of SiH 4 and H 2 as a film forming gas,
A film of 0 to 2000 angstrom is formed.
【０００７】上記非晶質シリコン膜上にＣＶＤ法により
成膜温度３００℃で窒化珪素膜によるチャネル保護膜１
１を形成し、これをＲＩＥ（反応性イオンエッチング）
法によりコンタクトホール１８を形成する。A channel protective film 1 made of a silicon nitride film is formed on the amorphous silicon film by a CVD method at a film forming temperature of 300 ° C.
1 is formed, and this is RIE (reactive ion etching)
The contact hole 18 is formed by the method.
【０００８】次にチャネル保護膜１１の上にＰをドープ
した非晶質シリコン膜１２をＣＶＤ法により成膜温度２
５０〜２８０℃で成膜後、ＲＩＥ法によりコンタクトホ
ール１９，２０を形成し、この上にスパッタ法によりＡ
ｌ−Ｓｉ−Ｃｕ膜１３，１４を成膜し、その後ウェット
エッチング法により上記Ａｌ−Ｓｉ−Ｃｕ膜をパターニ
ング後ＲＩＥ法によりＰドープ非晶質シリコン膜１２を
パターニングしてソース電極１３及びドレイン電極１４
を形成する。Next, an amorphous silicon film 12 doped with P is formed on the channel protection film 11 by a CVD method at a film forming temperature 2
After forming the film at 50 to 280 ° C., the contact holes 19 and 20 are formed by the RIE method, and A is formed on the contact holes 19 and 20 by the sputtering method.
l-Si-Cu films 13 and 14 are formed, and then wet
The Al-Si-Cu film is patterned by an etching method.
After the etching, the P-doped amorphous silicon film 12 is patterned by the RIE method to form the source electrode 13 and the drain electrode 14.
To form.
【０００９】最後にこの上に、ＣＶＤ法により成膜温度
３００〜３５０℃、高周波電力０．２〜０．４Ｗ／ｃｍ
2、圧力１３０〜１６０Ｐａで成膜ガスにＳｉＨ4、ＮＨ
3、Ｎ2の混合ガスを用いて成膜する。Finally, a film-forming temperature of 300-350 ° C. and a high-frequency power of 0.2-0.4 W / cm are formed on this by a CVD method.
2 , SiH 4 and NH in the film forming gas at a pressure of 130 to 160 Pa
A film is formed using a mixed gas of 3 and N 2 .
【００１０】[0010]
【発明が解決しようとする課題】（１）従来の薄膜トラ
ンジスタは上記の様に構成されているが、ゲート絶縁膜
の窒化珪素膜はＣＶＤ法により単層成膜されている。高
電界効果移動度をうるためには上記ゲート絶縁膜中の含
有水素量を多くする必要があった。これは、ノンドープ
非晶質シリコン膜９の電界効果移動度が、ゲート絶縁膜
７との界面における欠陥準位の影響を大きく受けるた
め、窒化珪素膜中の含有水素量を多くすることにより非
晶質シリコン膜９のダングリングボンド欠陥をゲート絶
縁膜の中の水素により補償して界面準位を減らすためで
ある。図７ａに窒化珪素成膜における材料ガスＮＨ3／
ＳｉＨ4流量比と電界効果移動度の関係を示し、又図７
ｂに窒化珪素成膜におけるＮＨ3／ＳｉＨ4流量比に対す
るフーリエ変換赤外分光法で求めた窒化珪素膜７中のＳ
ｉ−Ｈ結合数、あるいはＮ−Ｈ結合による単位体積当た
りの水素量（ＩSi-H，ＩN-H）の関係を示す。(1) Although the conventional thin film transistor is constructed as described above, the silicon nitride film of the gate insulating film is formed as a single layer by the CVD method. In order to obtain high field effect mobility, it is necessary to increase the amount of hydrogen contained in the gate insulating film. This is because the field-effect mobility of the non-doped amorphous silicon film 9 is greatly affected by the defect level at the interface with the gate insulating film 7, and thus the amorphous silicon content is increased by increasing the amount of hydrogen contained in the silicon nitride film. This is because the dangling bond defect of the silicon film 9 is compensated by hydrogen in the gate insulating film to reduce the interface state. In FIG. 7a, the material gas NH 3 /
Fig. 7 shows the relationship between the SiH 4 flow rate ratio and the field effect mobility.
b in the silicon nitride film formed on the silicon nitride film 7 obtained by Fourier transform infrared spectroscopy with respect to the NH 3 / SiH 4 flow rate ratio.
The relationship between the number of i-H bonds or the amount of hydrogen per unit volume (I Si-H , I NH ) due to N-H bonds is shown.
【００１１】しかし、図８に示す窒化珪素膜中の単位体
積当たりの水素量ＩN-Hと窒化珪素膜のドライエッチン
グレートとの関係からＩN-Hがある値以上大きくなる
と、窒化珪素膜のドライエッチングレートは急激に大き
くなり、非晶質シリコン膜９，１１をドライエッチング
をするときに、窒化珪素膜に対する非晶質シリコン膜
９，１１のエッチング選択比がとれなくなる。エッチン
グ選択比がとれないと、非晶質シリコン膜９，１１をパ
ターニングする時に下地のゲート絶縁膜の窒化珪素膜が
オーバーエッチングされる。従って下地のゲート絶縁膜
の窒化珪素膜７が薄くなり、かつ膜厚分布が大きくな
る。又ピンホール発生の原因にもなり得る。However, from the relationship between the amount of hydrogen I NH per unit volume in the silicon nitride film and the dry etching rate of the silicon nitride film shown in FIG. 8, when I NH exceeds a certain value, the dry etching rate of the silicon nitride film is increased. Becomes abruptly large, and when the amorphous silicon films 9 and 11 are dry-etched, the etching selection ratio of the amorphous silicon films 9 and 11 to the silicon nitride film cannot be obtained. If the etching selection ratio cannot be obtained, the silicon nitride film of the underlying gate insulating film is over-etched when the amorphous silicon films 9 and 11 are patterned. Therefore, the silicon nitride film 7 of the underlying gate insulating film becomes thin and the film thickness distribution becomes large. It can also cause pinholes.
【００１２】（２）従来の薄膜トランジスタにおけるノ
ンドープ非晶質シリコン膜９は図４に示されている単層
成膜されており、例えば０．８ｃｍ2／Ｖ・Ｓ以上の高
電界効果移動度をうるためには図９に示すノンドープ非
晶質シリコン膜中のＳｉ−Ｈ2結合数／Ｓｉ−Ｈ結合数
に対する電界効果移動度の関係、或いは図１０ａに示す
ＣＶＤ法における成膜時の高周波電力とノンドープ非晶
質シリコン膜中のＳｉ−Ｈ2結合数／Ｓｉ−Ｈ結合数と
の関係、或いは図１０ｂに示すＣＶＤ法の材料ガスＨ2
／ＳｉＨ4流量比とノンドープ非晶質シリコン膜中のＳ
ｉ−Ｈ2結合数／Ｓｉ−Ｈ結合数の関係で示されるよう
にＳｉＨ2結合数／Ｓｉ−Ｈ結合数を０．０５以下と小
さくする必要がある。従って、ノンドープ非晶質シリコ
ン膜９を低高周波電力あるいはＨ2／ＳｉＨ4流量比を大
きくして、低いデポレートの成膜条件で長い成膜時間で
成膜することが必要であった。(2) The non-doped amorphous silicon film 9 in the conventional thin film transistor is formed as a single layer as shown in FIG. 4, and has a high field effect mobility of, for example, 0.8 cm 2 / V · S or more. To achieve this, the relationship between the number of Si—H 2 bonds / the number of Si—H bonds in the non-doped amorphous silicon film shown in FIG. 9 and the field effect mobility, or the high frequency power during film formation in the CVD method shown in FIG. non-doped amorphous silicon film of Si-H 2 bond number / Si-H relationship between bonding number, or material gas of H 2 CVD method shown in FIG. 10b
/ SiH 4 flow rate ratio and S in non-doped amorphous silicon film
As shown by the relationship of i-H 2 bond number / Si-H bond number, it is necessary to reduce the SiH 2 bond number / Si-H bond number to 0.05 or less. Therefore, it was necessary to form the non-doped amorphous silicon film 9 with low high frequency power or with a large H 2 / SiH 4 flow rate ratio and under long deposition time under low deposition rate conditions.
【００１３】しかし、高周波電力が低いほど、あるいは
Ｈ2／ＳｉＨ4流量比が大きいほど、ノンドープの非晶質
シリコン膜のデポレートは小さくなり、成膜時間が長く
なる。また、従来の製造方法においては、ダングリング
ボンドを少なくする最適の形成、温度が２５０〜２８０
℃とされていたのでノンドープの非晶質シリコン膜の成
膜温度をゲート絶縁膜の窒化珪素膜７およびチャネル保
護膜１１の成膜温度より低くしていたために、冷却、加
熱に要する時間だけ、成膜の所要時間が大きいという問
題があった。However, the lower the high frequency power or the larger the H 2 / SiH 4 flow rate ratio, the smaller the deposition rate of the non-doped amorphous silicon film and the longer the film forming time. Further, in the conventional manufacturing method, the optimum formation for reducing the dangling bonds, the temperature is 250 to 280.
Since the temperature is set to be ° C, the film forming temperature of the non-doped amorphous silicon film is set lower than the film forming temperatures of the silicon nitride film 7 and the channel protective film 11 of the gate insulating film. There is a problem that the time required for film formation is long.
【００１４】又、薄膜トランジスタを形成後、保護膜１
５の成膜を行うと、その成膜温度に依存して電界効果移
動度が著しく減少するという問題がある。図７に保護膜
１５の成膜温度と移動度の減少率との関係を示す。After forming the thin film transistor, the protective film 1 is formed.
When the film formation of No. 5 is performed, there is a problem that the field effect mobility remarkably decreases depending on the film formation temperature. FIG. 7 shows the relationship between the deposition temperature of the protective film 15 and the mobility reduction rate.
【００１５】この発明は上記のような問題点を解決する
ためになされたもので、ノンドープ非晶質シリコン層の
電界効果移動度を高く維持しながら、成膜工程の所要時
間を短縮することを目的とする。The present invention has been made to solve the above problems, and it is possible to shorten the time required for the film forming step while maintaining the field effect mobility of the non-doped amorphous silicon layer high. To aim.
【００１６】[0016]
【課題を解決するための手段】この発明に係る請求項１
記載の薄膜トランジスタの製造方法は、薄膜トランジス
タの製造方法であって、絶縁基板上にゲート電極を形成
する工程と、上記ゲート電極上に材料ガスのＮＨ３／Ｓ
ｉＨ４の流量比が４を越えないようにして窒化珪素膜か
ら成る第１のゲート絶縁膜を形成する工程と、上記第１
のゲート絶縁膜上に材料ガスのＮＨ３／ＳｉＨ４の流量
比が４を下回らないようにして窒化珪素膜から成る第２
のゲート絶縁膜を形成する工程と、上記第２のゲート絶
縁膜上に非晶質シリコン膜を形成する工程とを有したも
のである。According to this invention SUMMARY OF] claim 1
The method of manufacturing the thin film transistor described is a method of manufacturing a thin film transistor <br/> data, forming a gate electrode on an insulating substrate, NH 3 / S of the material gas on the gate electrode
a step of forming a first gate insulating film made of a silicon nitride film so that a flow rate ratio of iH 4 does not exceed 4;
On the gate insulating film of No. 2 made of a silicon nitride film so that the flow rate ratio of NH 3 / SiH 4 of the material gas does not fall below 4
And a step of forming an amorphous silicon film on the second gate insulating film.
【００１７】またこの発明に係る請求項２記載の薄膜ト
ランジスタは、絶縁基板上に形成されたゲート電極と、
上記ゲート電極上に形成された第１のゲート絶縁膜と、
該第１のゲート絶縁膜上に形成された第２のゲート絶縁
膜と、該第２のゲート絶縁膜上に形成された第１の非晶
質シリコン膜と、該第１の非晶質シリコン膜上に形成さ
れた第２の非晶質シリコン膜とを有し、上記第１のゲー
ト絶縁膜は、膜中の水素含有量が上記第２のゲート絶縁
膜中の水素含有量よりも少ない窒化珪素膜で構成され、
上記第２のゲート絶縁膜は、膜中のＮ−Ｈ結合数が４０
〜６０ｃｍ −１ の窒化珪素膜で構成され、上記第１の非
晶質シリコン膜は、膜中のＳｉ−Ｈ結合数に対するＳｉ
−Ｈ ２ 結合数の比が０より大きく０．０５以下であり、
上記第２の非晶質シリコン膜は、上記第１の非晶質シリ
コン膜に比して膜厚が厚く、しかも膜中のＳｉ−Ｈ結合
数に対するＳｉ−Ｈ ２ 結合数の比が大きいものである。
また、この発明に係る請求項３記載の薄膜トランジスタ
の製造方法は、請求項２記載の薄膜トランジスタの製造
方法であって、第２のゲート絶縁膜上に、高周波電力が
０．０１５〜０．０２Ｗ／ｃｍ２で、或いは材料ガスの
流量比Ｈ２／ＳｉＨ４が８〜２０の成膜条件で化学気相
成長法により第１の非晶質シリコン膜を形成する工程
と、上記第１の非晶質シリコン膜上に、該第１の非晶質
シリコン膜の成膜条件範囲よりも高周波電力を高く、或
いは材料ガスの流量比Ｈ２／ＳｉＨ４を低くして、該第
１の非晶質シリコン膜よりも大きな成膜速度で第２の非
晶質シリコン膜を形成する工程とを有するものである。 A thin film device according to claim 2 of the present invention.
The transistor is a gate electrode formed on an insulating substrate,
A first gate insulating film formed on the gate electrode,
Second gate insulation formed on the first gate insulation film
Film and a first amorphous film formed on the second gate insulating film
Formed on the first silicon film and the first silicon film.
And a second amorphous silicon film formed on the first amorphous silicon film.
The gate insulating film has a hydrogen content in the film which is the second gate insulating film.
Composed of a silicon nitride film having a hydrogen content lower than that of the film,
The number of N—H bonds in the second gate insulating film is 40.
Composed of a silicon nitride film of about 60 cm −1 ,
The crystalline silicon film has a Si content corresponding to the number of Si-H bonds in the film.
The ratio of the number of —H 2 bonds is more than 0 and 0.05 or less,
The second amorphous silicon film is the first amorphous silicon film.
The film thickness is thicker than the con film, and the Si-H bond in the film
The ratio of the number of Si—H 2 bonds to the number is large.
The manufacturing method of a thin film transistor according to claim 3, wherein according to the invention is a manufacturing method of a thin film transistor according to claim 2, on the second gate insulating film, a high-frequency power 0.015～0.02W / cm 2 or the step of forming the first amorphous silicon film by the chemical vapor deposition method under the film forming conditions where the flow rate ratio H 2 / SiH 4 of the material gas is 8 to 20, and the first amorphous state. The high-frequency power is made higher than the film forming condition range of the first amorphous silicon film or the flow rate ratio H 2 / SiH 4 of the material gas is made lower on the high quality silicon film to make the first amorphous silicon film. And a step of forming the second amorphous silicon film at a film forming rate higher than that of the silicon film.
【００１８】[0018]
【実施例】実施例１．図１に本願発明の液晶表示装置に
用いる薄膜トランジスタの構造断面図を示す。基本的な
部分は従来装置と共通するので等価回路図、及び平面図
及び共通する部分の説明は省略する。ガラス基板１上に
形成されたゲート電極５、画素電極４とこの上に形成さ
れた膜中の水素含有量が少ないＳｉＮ膜による第１のゲ
ート絶縁膜６と、その上に形成されたソースバスライン
１７と、この上に形成された膜中の水素含有量が多いＳ
ｉＮによる第２のゲート絶縁膜７が形成されている。例
えば第２のゲート絶縁膜７は膜中のＮ−Ｈ結合数が４０
〜６０ｃｍ-1のＳｉＮ膜を５０〜１５０オングストロー
ムと、第１のゲート絶縁膜６は、膜中のＮ−Ｈ結合数が
３０〜４０ｃｍ-1のＳｉＮ膜で膜厚が第１と第２を合わ
せて３０００〜５０００オングストロームのものが形成
されている。EXAMPLES Example 1. FIG. 1 shows a structural cross-sectional view of a thin film transistor used in the liquid crystal display device of the present invention. Since the basic part is common to the conventional device, an equivalent circuit diagram, a plan view and description of common parts are omitted. The gate electrode 5 and the pixel electrode 4 formed on the glass substrate 1, the first gate insulating film 6 made of a SiN film having a low hydrogen content in the film formed thereon, and the source bus formed thereon. Line 17 and S containing a large amount of hydrogen in the film formed thereon
The second gate insulating film 7 made of iN is formed. For example, the number of N—H bonds in the second gate insulating film 7 is 40.
The SiN film having a thickness of -60 cm -1 is 50 to 150 angstroms, and the first gate insulating film 6 is a SiN film having a number of NH bonds in the film of 30 to 40 cm -1 and the first and second film thicknesses. A total of 3000 to 5000 angstroms are formed.
【００１９】この実施例１では第１及び第２のゲート絶
縁膜にＳｉＮ膜を有する２層構造のゲート絶縁膜の場合
について記載したが、３層以上のゲート絶縁膜が形成さ
れた装置においては、非晶質シリコン膜と界面を形成す
るゲート絶縁膜を窒化珪素膜とし膜中の含有水素量を多
くする。Although the first embodiment describes the case of the gate insulating film having the two-layer structure having the SiN films as the first and second gate insulating films, the device having three or more layers of the gate insulating films is described. A silicon nitride film is used as a gate insulating film that forms an interface with the amorphous silicon film to increase the amount of hydrogen contained in the film .
【００２０】この第２のゲート絶縁膜７上に界面準位を
少なくした第１のノンドープ非晶質シリコン膜９、例え
ば膜中のＳｉ−Ｈ結合数に対するＳｉ−Ｈ2結合数の比
を０．０５以下とした膜が膜厚２００オングストローム
形成されており、その上に第２のノンドープ非晶質シリ
コン膜が上記第１及び第２の膜を合わせて膜厚５００〜
２０００オングストローム成膜されている。A first non-doped amorphous silicon film 9 having a reduced interface state on the second gate insulating film 7, for example, the ratio of the number of Si-H 2 bonds to the number of Si-H bonds in the film is 0. A film with a thickness of 0.05 or less is formed to a thickness of 200 angstroms, and a second non-doped amorphous silicon film is formed on the film to a thickness of 500 to 500 nm.
2000 angstrom film is formed.
【００２１】この上にＳｉＮによるチャネル保護膜１１
が形成されており、その上にＰをドープした非晶質シリ
コン膜１２と、その上にソース電極１３及びドレイン電
極１４が形成されている。ソース電極１３及びドレイン
電極１４下のＰをドープした非晶質シリコン膜１２はそ
れぞれ、チャネル保護膜１１にあけられたコンタクトホ
ールを通じてノンドープ非晶質シリコン膜１０と接続さ
れている。又、ドレイン電極１４は、コンタクトホール
を通じ画素電極４と接続されている。又ソース電極１３
は、コンタクトホールを通じ、ソースバスライン１７と
接続されている。On top of this, a channel protection film 11 of SiN is formed.
Are formed, and a P-doped amorphous silicon film 12 is formed thereon, and a source electrode 13 and a drain electrode 14 are formed thereon. The P-doped amorphous silicon film 12 under the source electrode 13 and the drain electrode 14 is connected to the non-doped amorphous silicon film 10 through contact holes formed in the channel protective film 11. The drain electrode 14 is connected to the pixel electrode 4 through a contact hole. In addition, the source electrode 13
Is connected to the source bus line 17 through a contact hole.
【００２２】この装置の動作は、基本的に従来装置のと
ころで説明したものと同じであるので説明を省略する。Since the operation of this device is basically the same as that described in the conventional device, the description thereof will be omitted.
【００２３】本願の構造は次の作用を有する
（１）２層構造のゲート絶縁膜に関し、第１のノンドー
プ非晶質シリコン膜９と接する第２のＳｉＮ膜７の膜中
の水素含有量を多くし膜中のＮ−Ｈ結合数を４０〜６０
ｃｍ-1と大きくしているので、第２のＳｉＮ膜７から水
素を供給し第１のノンドープ非晶質シリコン膜９界面に
おけるダングリングボンドを補償し、界面準位を減らす
だけの充分な水素を供給する働きをする。この結果図７
ａ、ｂで示される様にＳｉＮ膜中の水素量ＩN-Hの増加
により高い電界効果移動度の非晶質シリコン膜９が得ら
れる。The structure of the present application relates to (1) a gate insulating film having a two-layer structure having the following effects. The hydrogen content in the film of the second SiN film 7 in contact with the first non-doped amorphous silicon film 9 is Increase the number of NH bonds in the membrane to 40-60
Since it is made as large as cm −1 , hydrogen is supplied from the second SiN film 7 to compensate for the dangling bond at the interface of the first non-doped amorphous silicon film 9 and to reduce the interface state. To supply. As a result of this, FIG.
As shown by a and b, an amorphous silicon film 9 having a high field effect mobility can be obtained by increasing the hydrogen amount I NH in the SiN film.
【００２４】（２）又２層構造のノンドープ非晶質シリ
コン膜に関し、第２のゲート絶縁膜７と接する第１のノ
ンドープ非晶質シリコン膜９は、膜中のＳｉ−Ｈ2結合
数／ＳｉＨ結合数を０．０５以下となる様にしているの
で、ダングリングボンドによる界面準位が少ない膜が得
られ図９に示すように高い電界効果移動度の膜が得られ
る。(2) Regarding the non-doped amorphous silicon film having a two-layer structure, the first non-doped amorphous silicon film 9 in contact with the second gate insulating film 7 has the number of Si--H 2 bonds in the film / Since the number of SiH bonds is set to 0.05 or less, a film having a small number of interface states due to dangling bonds can be obtained, and a film having high field effect mobility can be obtained as shown in FIG.
【００２５】次にこの装置の製造方法について説明す
る。従来装置と共通する部分の説明は省略する。まず図
２によりゲート絶縁膜の製造方法を説明する。第１及び
第２のゲート絶縁膜のＳｉＮ膜６，７及び第１及び第２
のノンドープ非晶質シリコン膜９，１０及びチャネル保
護膜１１をＣＶＤ法により大気に開放せず連続成膜を行
う。図２ａに示すようにガラス基板１上に形成されたゲ
ート５上に第１のゲート絶縁膜のＳｉＮ膜６を、成膜温
度３００℃、高周波電力密度０．２〜０．４Ｗ／ｃ
ｍ2、圧力１３０〜１６０Ｐａ、成膜ガスＮ2、Ｓｉ
Ｈ4、ＮＨ3の混合ガスを用いてＮＨ3／ＳｉＨ4流量比
０．５〜２で膜厚５０〜１５０オングストローム成膜す
る。次に図２ｂに示すように非晶質シリコン膜９と接す
る第２のゲート絶縁膜のＳｉＮ膜７を大気開放せず連続
で第１のＳｉＮ６と同じ成膜温度で、高周波電力密度
０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６０Ｐａ、
成膜ガスにＮ2、ＳｉＨ4、ＮＨ3の混合ガスを用いてＮ
Ｈ3／ＳｉＨ4流量比４〜８で第１及び第２のＳｉＮの膜
厚を合わせて３０００〜５０００オングストローム成膜
する。以上のような製造方法をとることにより、図８に
示される様に第１のＳｉＮ膜のドライエッチングレート
は大きくないので、ａ−Ｓｉ／ＳｉＮのエッチング選択
比は４〜５程度と維持することが出来る。Next, a method of manufacturing this device will be described. The description of the parts common to the conventional device will be omitted. First, a method of manufacturing a gate insulating film will be described with reference to FIG. SiN films 6 and 7 of the first and second gate insulating films and the first and second
The non-doped amorphous silicon films 9 and 10 and the channel protection film 11 are continuously formed by the CVD method without being exposed to the atmosphere. As shown in FIG. 2a, a SiN film 6 as a first gate insulating film is formed on a gate 5 formed on a glass substrate 1 at a film forming temperature of 300 ° C. and a high frequency power density of 0.2 to 0.4 W / c.
m 2 , pressure 130 to 160 Pa, film forming gas N 2 , Si
A mixed gas of H 4 and NH 3 is used to form a film with a film thickness of 50 to 150 Å at an NH 3 / SiH 4 flow rate ratio of 0.5 to 2. Next, as shown in FIG. 2B, the SiN film 7 of the second gate insulating film which is in contact with the amorphous silicon film 9 is continuously exposed to the atmosphere at the same film forming temperature as that of the first SiN 6 at a high frequency power density of 0.2. ~ 0.4 W / cm 2 , pressure 130-160 Pa,
Using a mixed gas of N 2 , SiH 4 , and NH 3 as a film forming gas,
At a H 3 / SiH 4 flow rate ratio of 4 to 8, the first and second SiN films are combined to form a film having a thickness of 3000 to 5000 angstroms. Since the dry etching rate of the first SiN film is not large as shown in FIG. 8 by using the above manufacturing method, the etching selection ratio of a-Si / SiN should be maintained at about 4-5. Can be done.
【００２６】次にノンドープ非晶質シリコン膜の成膜方
法について説明する。図２ｃに示すように第２のＳｉＮ
膜７と界面を形成する第１のノンドープ非晶質シリコン
膜９は、ＣＶＤ法により成膜温度３００℃、圧力８０〜
１６０Ｐａ、高周波電力０．０１５〜０．０２Ｗ／ｃｍ
2、或いは材料ガスＨ2／ＳｉＨ4の流量比を８〜２０と
して、デポレートが８０（オングストローム／分）以下
に相当する成膜条件で５０〜２００オングストローム成
膜する。次に第２のノンドープ非晶質シリコン膜１０を
大気開放せず連続で第１の非晶質シリコン膜９と同じ温
度で高周波電力０．０４〜０．０６Ｗ／ｃｍ2、圧力８
０〜１６０Ｐａ、成膜ガスにＳｉＨ4、Ｈ2の混合ガスを
用いてデポレートが２００（オングストローム／分）以
上に相当する成膜速度で膜厚を第１及び第２の膜を合わ
せて５００〜２０００オングストローム成膜する。Next, a method for forming a non-doped amorphous silicon film will be described. The second SiN as shown in FIG. 2c
The first non-doped amorphous silicon film 9 forming an interface with the film 7 is formed by a CVD method at a film forming temperature of 300 ° C. and a pressure of 80 to 80 ° C.
160 Pa, high frequency power 0.015 to 0.02 W / cm
2 or a material gas H 2 / SiH 4 flow rate ratio of 8 to 20 and 50 to 200 angstrom film is formed under the film forming conditions corresponding to a deposition rate of 80 (angstrom / min) or less. Next, the second non-doped amorphous silicon film 10 is continuously exposed to the atmosphere at the same temperature as the first amorphous silicon film 9 and the high frequency power is 0.04 to 0.06 W / cm 2 , and the pressure is 8.
0 to 160 Pa, a mixed gas of SiH 4 and H 2 is used as a film forming gas, and the total film thickness of the first film and the second film is 500 to 500 at a film forming rate corresponding to a deposition rate of 200 (angstrom / min) or more. 2000 angstrom film is formed.
【００２７】以上の様な製造方法をとることにより図
８、図９、図１０より第１のノンドープ非晶質シリコン
膜は０．８５ｃｍ2／Ｖ・ｓｅｃ以上の高い電界効果移
動度を達成することが出来る。By adopting the above manufacturing method, the first non-doped amorphous silicon film according to FIGS. 8, 9 and 10 achieves a high field effect mobility of 0.85 cm 2 / V · sec or more. You can
【００２８】次に図２ｄに示すようにＣＶＤ法でＳｉＮ
を成膜し、チャネル保護膜１１を成膜し、図２ｅに示す
ようにフォトリソグラフィによりコンタクトホールを形
成する。次に図３ａに示すように、その上にＣＶＤ法に
よりＰをドープした非晶質シリコン膜１２を成膜し、そ
の上にスパッタ法によりＡｌ−Ｓｉ−Ｃｕ膜を成膜１
３，１４、次に図３ｂに示すようにウェットエッチング
法によりＡｌ−Ｓｉ−Ｃｕ膜１３，１４をパターニング
後、ＲＩＥ法により上記Ｐドープ非晶質シリコン膜１２
をパターニングしてソース電極１３及びドレイン電極１
４を形成する。Next, as shown in FIG. 2d, SiN is formed by the CVD method.
Is formed, a channel protective film 11 is formed, and a contact hole is formed by photolithography as shown in FIG. 2e. Next, as shown in FIG. 3A, a P-doped amorphous silicon film 12 is formed thereon by a CVD method, and an Al-Si-Cu film is formed thereon by a sputtering method 1
3, 14, then wet etching as shown in Figure 3b
Patterning the Al-Si-Cu films 13 and 14 by the method
After that, the P-doped amorphous silicon film 12 is formed by the RIE method.
It is patterned source electrode 13 and the drain electrode 1
4 is formed.
【００２９】次に図３ｃに示すように保護膜１５をＣＶ
Ｄ法によりＳｉＮ膜を成膜温度３００℃、高周波電力
０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６０Ｐａで
材料ガスＳｉＨ4、ＮＨ3、Ｎ2の混合ガスを用いて成膜
する。Next, as shown in FIG. 3c, the protective film 15 is covered with CV.
A SiN film is formed by the D method at a film forming temperature of 300 ° C., a high frequency power of 0.2 to 0.4 W / cm 2 , and a pressure of 130 to 160 Pa, using a mixed gas of material gases SiH 4 , NH 3 , and N 2 .
【００３０】第１の発明の構造は、上記実施例１の図１
に示されている様に、ガラス基板１上に形成されたゲー
ト電極５、画素電極４とこの上に形成された膜中の水素
含有量が少ないＳｉＮ膜による第１のゲート絶縁膜６
と、この上に形成された膜中の水素含有量が多いＳｉＮ
による第２のゲート絶縁膜７が形成されている。例えば
第２のゲート絶縁膜７は膜中のＮ−Ｈ結合数が４０〜６
０ｃｍ-1のＳｉＮ膜を５０〜１５０オングストローム
と、第１のゲート絶縁膜６は、膜中のＮ−Ｈ結合数が３
０〜４０ｃｍ-1のＳｉＮ膜で膜厚が第１と第２を合わせ
て３０００〜５０００オングストロームのものが形成さ
れている。The structure of the first invention is similar to that of the first embodiment shown in FIG.
As shown in FIG. 1, the gate electrode 5 and the pixel electrode 4 formed on the glass substrate 1 and the first gate insulating film 6 made of a SiN film having a small hydrogen content in the film formed thereon.
And SiN containing a large amount of hydrogen in the film formed thereon.
To form the second gate insulating film 7. For example, the number of N—H bonds in the second gate insulating film 7 is 40 to 6
The SiN film of 0 cm −1 has a thickness of 50 to 150 Å, and the first gate insulating film 6 has a number of N—H bonds of 3 in the film.
A SiN film having a thickness of 0 to 40 cm −1 and having a total film thickness of 3000 to 5000 angstroms is formed.
【００３１】上記第１の発明は次の作用を有する。第１
のノンドープ非晶質シリコン膜９と接する第２のＳｉＮ
膜７の膜中の水素含有量を多くし膜中のＮ−Ｈ結合数を
４０〜６０ｃｍ-1と大きくしているので、第２のＳｉＮ
膜７から第１のノンドープ非晶質シリコン膜９水素を供
給し界面におけるダングリングボンドを補償し、界面準
位を減らすだけの充分な水素を供給する働きをする。こ
の結果図７ａ、ｂで示される様にＳｉＮ膜中の水素量Ｉ
N-Hの増加により高い電界効果移動度の非晶質シリコン
膜９が得られる。又、第１のＳｉＮ膜の膜中のＮ−Ｈ係
合数を３０〜４０ｃｍ-1と小さくしたので、図７及び図
８からＳｉＮ膜のエッチングレートが小さいので、非晶
質シリコン／ＳｉＮ膜のエッチング選択比を４〜５程度
と維持することができる。以上から非晶質シリコン膜９
の高移動度を得るとともに非晶質シリコン／ＳｉＮ膜の
エッチング選択比を維持することが出来る。The above-mentioned first invention has the following effects. First
Second SiN contacting the non-doped amorphous silicon film 9 of
Since the hydrogen content in the film of the film 7 is increased and the number of NH bonds in the film is increased to 40 to 60 cm -1 , the second SiN
The first non-doped amorphous silicon film 9 supplies hydrogen from the film 7 to compensate for dangling bonds at the interface and to supply sufficient hydrogen to reduce the interface state. As a result, as shown in FIGS. 7a and 7b, the amount of hydrogen in the SiN film I
An amorphous silicon film 9 having a high field effect mobility can be obtained by increasing NH . Also, since the number of N—H engagements in the first SiN film is reduced to 30 to 40 cm −1 , the etching rate of the SiN film is small as shown in FIGS. 7 and 8, so that the amorphous silicon / SiN film is The etching selection ratio can be maintained at about 4 to 5. From the above, the amorphous silicon film 9
It is possible to obtain a high mobility and to maintain the etching selection ratio of the amorphous silicon / SiN film.
【００３２】第２の発明の製造方法は、図２ａに示すよ
うにガラス基板１上に形成されたゲート５上に第１のゲ
ート絶縁膜のＳｉＮ膜６を、成膜温度３００℃、高周波
電力密度０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６
０Ｐａ、成膜ガスＮ2、ＳｉＨ4、ＮＨ3の混合ガスを用
いてＮＨ3／ＳｉＨ4流量比０．５〜２で膜厚５０〜１５
０オングストローム成膜する。次に図２ｂに示すように
非晶質シリコン膜９と接する第２のゲート絶縁膜のＳｉ
Ｎ膜７を大気開放せず連続で第１のＳｉＮ６と同じ成膜
温度で、高周波電力密度０．２〜０．４Ｗ／ｃｍ2、圧
力１３０〜１６０Ｐａ、成膜ガスにＮ2、ＳｉＨ4、ＮＨ
3の混合ガスを用いてＮＨ3／ＳｉＨ4流量比４〜８で第
１及び第２のＳｉＮの膜厚を合わせて３０００〜５００
０オングストローム成膜する。As shown in FIG. 2a, the manufacturing method of the second invention comprises forming the SiN film 6 of the first gate insulating film on the gate 5 formed on the glass substrate 1, forming temperature 300 ° C., high frequency power. Density 0.2 to 0.4 W / cm 2 , pressure 130 to 16
0 Pa, the film thickness in NH 3 / SiH 4 flow ratio from 0.5 to 2 using a mixed gas of the film forming gas N 2, SiH 4, NH 3 50~15
A 0 Å film is formed. Next, as shown in FIG. 2b, Si of the second gate insulating film contacting the amorphous silicon film 9 is formed.
The N film 7 is continuously exposed to the atmosphere at the same film forming temperature as that of the first SiN 6, the high frequency power density is 0.2 to 0.4 W / cm 2 , the pressure is 130 to 160 Pa, the film forming gas is N 2 , SiH 4 , and NH
Using a mixed gas of 3 and a flow rate ratio of NH 3 / SiH 4 of 4 to 8, the film thicknesses of the first and second SiN are combined to be 3000 to 500.
A 0 Å film is formed.
【００３３】上記第２の発明は次の作用を有する。第１
のＳｉＮ膜６を材料ガスＮＨ3／ＳｉＨ4の流量比を０．
５〜２で成膜したので、図７ｂから第１の膜中の水素量
ＩN-Hは３７〜４２と小さいが図８の関係からＳｉＮ膜
のエッチングレートが小さいので、非晶質シリコン／Ｓ
ｉＮ膜のエッチング選択比を４〜５程度と維持すること
が出来る。又、第２のＳｉＮ膜７を材料ガスＮＨ3／Ｓ
ｉＨ4の流量比を４〜８としたので図７ａから高い電界
効果移動度の非晶質シリコン膜９が得られる。以上から
非晶質シリコン膜９の高移動度をうるとともに非晶質シ
リコン／ＳｉＮ膜のエッチング選択比を維持することが
出来る。The above-mentioned second invention has the following effects. First
In the SiN film 6 of No. 3 , the flow rate ratio of the material gas NH 3 / SiH 4 is set to 0.
Having formed by 5-2, since the amount of hydrogen I NH in the first layer from Figure 7b is small a small etching rate of the SiN film from the relationship shown in FIG. 8 and 37 to 42, amorphous silicon / S
The etching selection ratio of the iN film can be maintained at about 4-5. In addition, the second SiN film 7 is replaced with the material gas NH 3 / S.
Since the flow rate ratio of iH 4 is set to 4 to 8, an amorphous silicon film 9 having a high field effect mobility can be obtained from FIG. 7a. From the above, the high mobility of the amorphous silicon film 9 can be obtained and the etching selection ratio of the amorphous silicon / SiN film can be maintained.
【００３４】第３の発明の構造は、図１に示されている
様にガラス基板１上に形成されたゲート電極５、画素電
極４とこの上に形成された膜中の水素含有量が少ないＳ
ｉＮ膜による第１のゲート絶縁膜６と、この上に形成さ
れた膜中の水素含有量が多いＳｉＮによる第２のゲート
絶縁膜７が形成されている。例えば第２のゲート絶縁膜
７は膜中のＮ−Ｈ結合数が４０〜６０ｃｍ-1のＳｉＮ膜
を５０〜１５０オングストロームと、第１のゲート絶縁
膜６は、膜中のＮ−Ｈ結合数が３０〜４０ｃｍ-1のＳｉ
Ｎ膜で膜厚が第１と第２を合わせて３０００〜５０００
オングストロームのものが形成されている。この第２の
ゲート絶縁膜７上に界面準位を少なくした第１のノンド
ープ非晶質シリコン膜９、例えば膜中のＳｉ−Ｈ結合数
に対するＳｉ−Ｈ2結合数の比を０．０５以下とした膜
が膜厚２００オングストローム形成されており、その上
に第２のノンドープ非晶質シリコン膜が上記第１及び第
２の膜を合わせて膜厚５００〜２０００オングストロー
ム成膜されている。In the structure of the third invention, as shown in FIG. 1, the gate electrode 5, the pixel electrode 4 formed on the glass substrate 1 and the hydrogen content in the film formed thereon are small. S
A first gate insulating film 6 made of an iN film and a second gate insulating film 7 made of SiN having a large hydrogen content in the film formed thereon are formed. For example, the second gate insulating film 7 is a SiN film having an N—H bond number of 40 to 60 cm −1 of 50 to 150 Å, and the first gate insulating film 6 is an N—H bond number of the film. Is 30-40 cm -1 of Si
N film with a total thickness of 3000 to 5000
Angstroms are formed. The ratio of the number of Si—H 2 bonds to the number of Si—H bonds in the first non-doped amorphous silicon film 9 having a reduced interface state on the second gate insulating film 7, for example, is 0.05 or less. Is formed to a film thickness of 200 angstroms, and a second non-doped amorphous silicon film is formed thereon to a film thickness of 500 to 2000 angstroms including the first and second films.
【００３５】上記第３の発明の構造は、次の作用を有す
る。２層構造のゲート絶縁膜に関し、第１のノンドープ
非晶質シリコン膜９と接する第２のＳｉＮ膜７の膜中の
水素含有量を多くし膜中のＮ−Ｈ結合数を４０〜６０ｃ
ｍ-1と大きくしているので、第２のＳｉＮ膜７から水素
を供給し第１のノンドープ非晶質シリコン膜９界面にお
けるダングリングボンドを補償し、界面準位を減らすだ
けの充分な水素を供給する働きをする。この結果図７
ａ、ｂで示される様にＳｉＮ膜中の水素量ＩN-Hの増加
により高い電界効果移動度の非晶質シリコン膜９が得ら
れる。第１のノンドープ非晶質シリコン膜９は、膜中の
Ｓｉ−Ｈ2結合数／ＳｉＨ結合数を０．０５以下となる
様にしているので、ダングリングボンドによる界面準位
が少ない膜が得られ図９に示すように高い電界効果移動
度の膜が得られる。上記第１のノンドープ非晶質シリコ
ン膜９と上記第２のゲート絶縁膜７が界面を形成してい
るので、上記ノンドープ非晶質シリコン膜９の界面に上
記第２のゲート絶縁膜７から水素が供給されることによ
り更に界面準位が減少し、高移動度の膜が得られる。The structure of the third invention has the following effects. Regarding the two-layer structure gate insulating film, the hydrogen content of the second SiN film 7 in contact with the first non-doped amorphous silicon film 9 is increased to increase the number of NH bonds in the film to 40 to 60c.
Since it is set to m −1 , the hydrogen is supplied from the second SiN film 7 to compensate for the dangling bond at the interface of the first non-doped amorphous silicon film 9, and to reduce the interface state. To supply. As a result of this, FIG.
As shown by a and b, an amorphous silicon film 9 having a high field effect mobility can be obtained by increasing the hydrogen amount I NH in the SiN film. The first non-doped amorphous silicon film 9 has a Si-H 2 bond number / SiH bond number of 0.05 or less in the film, so that a film having a small number of interface states due to dangling bonds can be obtained. As a result, a film having a high field effect mobility is obtained as shown in FIG. Since the first non-doped amorphous silicon film 9 and the second gate insulating film 7 form an interface, hydrogen is removed from the second gate insulating film 7 at the interface of the non-doped amorphous silicon film 9. Is further supplied, the interface state is further reduced, and a high-mobility film is obtained.
【００３６】第４の発明の製造方法は図２ａに示すよう
にガラス基板１上に形成されたゲート５上に第１のゲー
ト絶縁膜のＳｉＮ膜６を、成膜温度３００℃、高周波電
力密度０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６０
Ｐａ、成膜ガスＮ2、ＳｉＨ4、ＮＨ3の混合ガスを用い
てＮＨ3／ＳｉＨ4流量比０．５〜２で膜厚５０〜１５０
オングストローム成膜する。次に図２ｂに示すように非
晶質シリコン膜９と接する第２のゲート絶縁膜のＳｉＮ
膜７を大気開放せず連続で第１のＳｉＮ６と同じ成膜温
度で、高周波電力密度０．２〜０．４Ｗ／ｃｍ2、圧力
１３０〜１６０Ｐａ、成膜ガスにＮ2、ＳｉＨ4、ＮＨ3
の混合ガスを用いてＮＨ3／ＳｉＨ4流量比４〜８で第１
及び第２のＳｉＮの膜厚を合わせて３０００〜５０００
オングストローム成膜する。次に図２ｃに示すように第
２のＳｉＮ膜７と界面を形成する第１のノンドープ非晶
質シリコン膜９は、ＣＶＤ法により成膜温度３００℃、
圧力８０〜１６０Ｐａ、高周波電力０．０１５〜０．０
２Ｗ／ｃｍ2、或いは材料ガスＨ2／ＳｉＨ4の流量比を
８〜２０として、デポレートが８０（オングストローム
／分）以下に相当する成膜条件で５０〜２００オングス
トローム成膜する。次に第２のノンドープ非晶質シリコ
ン膜１０を大気開放せず連続で第１の非晶質シリコン膜
９と同じ温度で高周波電力０．０４〜０．０６Ｗ／ｃｍ
2、圧力８０〜１６０Ｐａ、成膜ガスにＳｉＨ4、Ｈ2の
混合ガスを用いてデポレートが２００（オングストロー
ム／分）以上に相当する成膜速度で膜厚を第１及び第２
の膜を合わせて５００〜２０００オングストローム成膜
する。According to the manufacturing method of the fourth invention, as shown in FIG. 2a, the SiN film 6 of the first gate insulating film is formed on the gate 5 formed on the glass substrate 1 at the film forming temperature of 300 ° C. and the high frequency power density. 0.2-0.4 W / cm 2 , pressure 130-160
A mixed gas of Pa, a film forming gas N 2 , SiH 4 , and NH 3 is used, and a film thickness is 50 to 150 at an NH 3 / SiH 4 flow rate ratio of 0.5 to 2.
Angstrom film is formed. Next, as shown in FIG. 2b, SiN of the second gate insulating film in contact with the amorphous silicon film 9 is formed.
The film 7 is continuously exposed to the atmosphere at the same film forming temperature as the first SiN 6, the high frequency power density is 0.2 to 0.4 W / cm 2 , the pressure is 130 to 160 Pa, and the film forming gas is N 2 , SiH 4 , and NH. 3
With a mixed gas of NH 3 / SiH 4 at a flow rate ratio of 4 to 8
And the total thickness of the second SiN are 3000 to 5000
Angstrom film is formed. Next, as shown in FIG. 2c, the first non-doped amorphous silicon film 9 forming an interface with the second SiN film 7 is formed at a film forming temperature of 300 ° C. by a CVD method.
Pressure 80-160Pa, high frequency power 0.015-0.0
A film thickness of 50 to 200 angstroms is formed under film forming conditions corresponding to a deposition rate of 80 (angstrom / min) or less with a flow rate ratio of 2 W / cm 2 or a material gas H 2 / SiH 4 of 8 to 20. Next, the second non-doped amorphous silicon film 10 is continuously exposed to the atmosphere at the same temperature as the first amorphous silicon film 9 and the high frequency power is 0.04 to 0.06 W / cm.
2, the pressure 80~160Pa, SiH 4 into the film forming gas, H deposition rate of 200 using a mixed gas of 2 (Å / min) or more first thickness at a deposition rate corresponding to the and second
The above films are combined to form a film of 500 to 2000 angstroms.
【００３７】上記第４の発明の製造方法は次の作用を有
する。第１のＳｉＮ膜６を材料ガスＮＨ3／ＳｉＨ4の流
量比を０．５〜２で成膜したので、図７ｂから第１の膜
中の水素量ＩN-Hは３７〜４２と小さいが図８の関係か
らＳｉＮ膜のエッチングレートが小さいので、非晶質シ
リコン／ＳｉＮ膜のエッチング選択比を４〜５程度と維
持することが出来る。又、第２のＳｉＮ膜７を材料ガス
ＮＨ3／ＳｉＨ4の流量比を４〜８としたので図７ａから
高い電界効果移動度の非晶質シリコン膜９が得られる。
以上から非晶質シリコン膜９の高移動度をうるとともに
非晶質シリコン／ＳｉＮ膜のエッチング選択比を維持す
ることが出来る。又薄い第１の非晶質シリコン膜を低デ
ポレートで形成し、残りの厚い第２の非晶質シリコン膜
を高デポレートで成膜するので、成膜所要時間を大巾に
短縮することができる。The manufacturing method of the fourth invention has the following effects. Since the first SiN film 6 is formed with the flow rate ratio of the material gas NH 3 / SiH 4 of 0.5 to 2, the hydrogen amount I NH in the first film is as small as 37 to 42 from FIG. 7b. Since the etching rate of the SiN film is small from the relationship of 8, the etching selection ratio of the amorphous silicon / SiN film can be maintained at about 4 to 5. Since the flow rate ratio of the material gas NH 3 / SiH 4 to the second SiN film 7 is set to 4 to 8, the amorphous silicon film 9 having high field effect mobility can be obtained from FIG. 7a.
From the above, the high mobility of the amorphous silicon film 9 can be obtained and the etching selection ratio of the amorphous silicon / SiN film can be maintained. Further, since the thin first amorphous silicon film is formed with a low deposition rate and the remaining thick second amorphous silicon film is deposited with a high deposition rate, the film formation time can be greatly shortened. .
【００３８】第５の発明の製造方法を図２により説明す
る。第１及び第２のゲート絶縁膜のＳｉＮ膜６，７及び
第１及び第２のノンドープ非晶質シリコン膜９，１０及
びチャネル保護膜１１をＣＶＤ法により大気に開放せず
連続成膜を行う。図２ａに示すようにガラス基板１上に
形成されたゲート５上に第１のゲート絶縁膜のＳｉＮ膜
６を、成膜温度３００℃、高周波電力密度０．２〜０．
４Ｗ／ｃｍ2、圧力１３０〜１６０Ｐａ、成膜ガスＮ2、
ＳｉＨ4、ＮＨ3の混合ガスを用いてＮＨ3／ＳｉＨ4流量
比０．５〜２で膜厚５０〜１５０オングストローム成膜
する。次に図２ｂに示すように非晶質シリコン膜９と接
する第２のゲート絶縁膜のＳｉＮ膜７を大気開放せず連
続で第１のＳｉＮ６と同じ成膜温度で、高周波電力密度
０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６０Ｐａ、
成膜ガスにＮ2、ＳｉＨ4、ＮＨ3の混合ガスを用いてＮ
Ｈ3／ＳｉＨ4流量比４〜８で第１及び第２のＳｉＮの膜
厚を合わせて３０００〜５０００オングストローム成膜
する。図２ｃに示すように第２のＳｉＮ膜７と界面を形
成する第１のノンドープ非晶質シリコン膜９は、ＣＶＤ
法により成膜温度３００℃、圧力８０〜１６０Ｐａ、高
周波電力０．０１５〜０．０２Ｗ／ｃｍ2、或いは材料
ガスＨ2／ＳｉＨ4の流量比を８〜２０として、デポレー
トが８０（オングストローム／分）以下に相当する成膜
条件で５０〜２００オングストローム成膜する。次に第
２のノンドープ非晶質シリコン膜１０を大気に開放せず
連続で第１の非晶質シリコン膜９と同じ温度で高周波電
力０．０４〜０．０６Ｗ／ｃｍ2、圧力８０〜１６０Ｐ
ａ、成膜ガスにＳｉＨ4、Ｈ2の混合ガスを用いてデポレ
ートが２００（オングストローム／分）以上に相当する
成膜速度で膜厚さ第１及び第２の膜を合わせて５００〜
２０００オングストローム成膜する。次に図２ｄに示す
ようにＣＶＤ法で成膜温度３００℃でＳｉＮを成膜し、
チャネル保護膜１１を成膜する。The manufacturing method of the fifth invention will be described with reference to FIG. The SiN films 6 and 7 of the first and second gate insulating films, the first and second non-doped amorphous silicon films 9 and 10, and the channel protective film 11 are continuously formed by the CVD method without being exposed to the atmosphere. . As shown in FIG. 2a, a SiN film 6 as a first gate insulating film is formed on a gate 5 formed on a glass substrate 1 at a film forming temperature of 300 ° C. and a high frequency power density of 0.2 to 0.
4 W / cm 2 , pressure 130 to 160 Pa, film forming gas N 2 ,
A mixed gas of SiH 4 and NH 3 is used to form a film having a film thickness of 50 to 150 Å at an NH 3 / SiH 4 flow rate ratio of 0.5 to 2. Next, as shown in FIG. 2B, the SiN film 7 of the second gate insulating film which is in contact with the amorphous silicon film 9 is continuously exposed to the atmosphere at the same film forming temperature as that of the first SiN 6 at a high frequency power density of 0.2. ~ 0.4 W / cm 2 , pressure 130-160 Pa,
Using a mixed gas of N 2 , SiH 4 , and NH 3 as a film forming gas,
At a H 3 / SiH 4 flow rate ratio of 4 to 8, the first and second SiN films are combined to form a film having a thickness of 3000 to 5000 angstroms. As shown in FIG. 2c, the first non-doped amorphous silicon film 9 forming an interface with the second SiN film 7 is formed by CVD.
Film deposition temperature of 300 ° C., pressure of 80 to 160 Pa, high frequency power of 0.015 to 0.02 W / cm 2 , or flow rate ratio of material gas H 2 / SiH 4 of 8 to 20, the deposition rate is 80 (angstrom / min. ) 50 to 200 angstrom film is formed under the film forming conditions corresponding to the following. Next, the second non-doped amorphous silicon film 10 is continuously exposed to the atmosphere at the same temperature as the first amorphous silicon film 9 and the high frequency power is 0.04 to 0.06 W / cm 2 and the pressure is 80 to 160 P.
a, using a mixed gas of SiH 4 and H 2 as a film-forming gas and depositing the first and second films at a film-forming rate corresponding to a deposition rate of 200 (angstrom / min) or more, the total thickness is 500 to 500
2000 angstrom film is formed. Next, as shown in FIG. 2d, a SiN film is formed by a CVD method at a film forming temperature of 300 ° C.,
The channel protection film 11 is formed.
【００３９】次に上記第５の発明の製造方法の作用を示
す。本願の製造工程では第２のＳｉＮ膜１９、第１の非
晶質シリコン膜９、及び第２の非晶質シリコン膜１０及
びチャネル保護膜１１の成膜温度を３００℃と共通に
し、連続成膜をするようにした。この様にすることによ
り例えば従来第２のＳｉＮ膜９及びチャネル保護膜１１
を３００℃、非晶質シリコン膜９、１０を２５０℃で成
膜していた場合に比べ加熱、冷却に要する時間を削減
し、例えば従来の２段階の温度で成膜していた場合の４
２分の成膜時間を６分程度と成膜所要時間を大幅に短縮
することができた。図１１に薄膜トランジスタの多層膜
の成膜温度設定方式に対する電界効果移動度の値を示
す。このことから成膜温度を共通化することにより高い
移動度が得られることがわかる。即ち左端は非晶質シリ
コン膜を高デポレートで成膜した時の移動度を示したも
ので、界面準位等の影響で低い移動度を示している。真
中の２段階成膜とはゲート絶縁膜７及びチャネル保護膜
１１の成膜温度を３００℃とし、非晶質シリコン膜９、
１０の成膜温度を２５０℃とした場合の移動度を示す。
右端はゲート絶縁膜７、非晶質シリコン膜９、１０及び
チャネル保護膜を３００℃と共通にしたものである。こ
れは従来３００℃で非晶質シリコン膜の水素結合がとれ
てダングリングボンドが増え、移動度が減少すると考え
られていたものが、Ｓｉ−Ｓｉ結合により移動度の減少
がないことがわかり、成膜温度の共通化が可能となった
ものである。上記の製造方法により、高い電界効果移動
度をうると共に、成膜所要時間を大巾に短縮することが
可能である。Next, the operation of the manufacturing method of the fifth invention will be described. In the manufacturing process of the present application, the deposition temperature of the second SiN film 19, the first amorphous silicon film 9, the second amorphous silicon film 10 and the channel protection film 11 is set to 300 ° C. in common, and the continuous deposition is performed. I tried to make a membrane. By doing so, for example, the second SiN film 9 and the channel protection film 11 of the related art are used.
Compared with the case where the amorphous silicon films 9 and 10 are formed at 300 ° C. and the film formation at 250 ° C., the time required for heating and cooling is reduced.
The film formation time was reduced from 2 minutes to about 6 minutes, which was a significant reduction in film formation time. FIG. 11 shows the value of the field effect mobility with respect to the method of setting the deposition temperature of the multilayer film of the thin film transistor. From this, it is understood that high mobility can be obtained by making the film forming temperature common. That is, the left end shows the mobility when the amorphous silicon film is formed with a high deposition rate, and shows the low mobility due to the influence of the interface state and the like. The middle two-stage film formation means that the film formation temperature of the gate insulating film 7 and the channel protection film 11 is 300 ° C., the amorphous silicon film 9,
The mobility when the film forming temperature of No. 10 is 250 ° C. is shown.
At the right end, the gate insulating film 7, the amorphous silicon films 9, 10 and the channel protective film are common to 300 ° C. Although it was conventionally thought that the hydrogen bond of the amorphous silicon film was broken at 300 ° C. to increase the dangling bond and the mobility was decreased, it was found that the mobility was not decreased by the Si—Si bond. The film forming temperature can be standardized. By the above-mentioned manufacturing method, it is possible to obtain a high field-effect mobility and to significantly shorten the film formation required time.
【００４０】第６の発明の製造方法を図２及び図３によ
り説明する。第１及び第２のゲート絶縁膜のＳｉＮ膜
６，７及び第１及び第２のノンドープ非晶質シリコン膜
９，１０及びチャネル保護膜１１をＣＶＤ法により大気
に開放せず連続成膜を行う。図２ａに示すようにガラス
基板１上に形成されたゲート５上に第１のゲート絶縁膜
のＳｉＮ膜６を、成膜温度３００℃、高周波電力密度
０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６０Ｐａ、
成膜ガスＮ2、ＳｉＨ4、ＮＨ3の混合ガスを用いてＮＨ3
／ＳｉＨ4流量比０．５〜２で膜厚５０〜１５０オング
ストローム成膜する。次に図２ｂに示すように非晶質シ
リコン膜９と接する第２のゲート絶縁膜のＳｉＮ膜７を
大気開放せず連続で第１のＳｉＮ６と同じ成膜温度で、
高周波電力密度０．２〜０．４Ｗ／ｃｍ2、圧力１３０
〜１６０Ｐａ、成膜ガスにＮ2、ＳｉＨ4、ＮＨ3の混合
ガスを用いてＮＨ3／ＳｉＨ4流量比４〜８で第１及び第
２のＳｉＮの膜厚を合わせて３０００〜５０００オング
ストローム成膜する。以上のような製造方法をとること
により、図８に示される様に第１のＳｉＮ膜のドライエ
ッチングレートは大きくないので、ａ−Ｓｉ／ＳｉＮの
エッチング選択比は４〜５程度と維持することが出来
る。次にノンドープ非晶質シリコン膜の成膜方法につい
て説明する。図２ｃに示すように第２のＳｉＮ膜７と界
面を形成する第１のノンドープ非晶質シリコン膜９は、
ＣＶＤ法により成膜温度３００℃、圧力８０〜１６０Ｐ
ａ、高周波電力０．０１５〜０．０２Ｗ／ｃｍ2、或い
は材料ガスＨ2／ＳｉＨ4の流量比を８〜２０として、デ
ポレートが８０（オングストローム／分）以下に相当す
る成膜条件で５０〜２００オングストローム成膜する。
次に第２のノンドープ非晶質シリコン膜１０を大気開放
せず連続で第１の非晶質シリコン膜９と同じ温度で高周
波電力０．０４〜０．０６Ｗ／ｃｍ2、圧力８０〜１６
０Ｐａ、成膜ガスにＳｉＨ4、Ｈ2の混合ガスを用いてデ
ポレートが２００（オングストローム／分）以上に相当
する成膜速度で膜厚を第１及び第２の膜を合わせて５０
０〜２０００オングストローム成膜する。次に図２ｄに
示すようにＣＶＤ法でＳｉＮを成膜し、チャネル保護膜
１１を成膜し、図２ｅに示すようにフォトリソグラフィ
によりコンタクトホールを形成する。次に図３ａに示す
ように、その上にＣＶＤ法によりＰをドープした非晶質
シリコン膜１２を成膜し、その上にスパッタ法によりＡ
ｌ−Ｓｉ−Ｃｕ膜を成膜１３，１４、次に図３ｂに示す
ようにウェットエッチング法によりＡｌ−Ｓｉ−Ｃｕ膜
１３，１４をパターニング後ＲＩＥ法により上記Ｐドー
プ非晶質シリコン膜１２をパターニングしてソース電極
１３及びドレイン電極１４を形成する。次に図３ｃに示
すように保護膜１５をＣＶＤ法によりＳｉＮ膜を成膜温
度３００℃、高周波電力０．２〜０．４Ｗ／ｃｍ2、圧
力１３０〜１６０Ｐａで材料ガスＳｉＨ4、ＮＨ3、Ｎ2
の混合ガスを用いて成膜する。The manufacturing method of the sixth invention will be described with reference to FIGS. The SiN films 6 and 7 of the first and second gate insulating films, the first and second non-doped amorphous silicon films 9 and 10, and the channel protective film 11 are continuously formed by the CVD method without being exposed to the atmosphere. . As shown in FIG. 2a, a SiN film 6 as a first gate insulating film is formed on a gate 5 formed on a glass substrate 1 at a film forming temperature of 300 ° C., a high frequency power density of 0.2 to 0.4 W / cm 2 , Pressure 130-160Pa,
NH 3 using a mixed gas of the film forming gas N 2, SiH 4, NH 3
A film thickness of 50 to 150 Å is formed at a flow rate ratio of / SiH 4 of 0.5 to 2. Next, as shown in FIG. 2b, the SiN film 7 of the second gate insulating film which is in contact with the amorphous silicon film 9 is continuously exposed to the atmosphere at the same film forming temperature as that of the first SiN 6,
High frequency power density 0.2 to 0.4 W / cm 2 , pressure 130
˜160 Pa, a mixed gas of N 2 , SiH 4 , and NH 3 is used as a film forming gas, and an NH 3 / SiH 4 flow rate ratio of 4 to 8 is used to combine the film thicknesses of the first and second SiN layers to 3000 to 5000 angstroms. To film. Since the dry etching rate of the first SiN film is not large as shown in FIG. 8 by using the above manufacturing method, the etching selection ratio of a-Si / SiN should be maintained at about 4-5. Can be done. Next, a method for forming a non-doped amorphous silicon film will be described. As shown in FIG. 2c, the first non-doped amorphous silicon film 9 forming an interface with the second SiN film 7 is
Film formation temperature is 300 ° C. and pressure is 80 to 160 P by CVD method.
a, high frequency power 0.015 to 0.02 W / cm 2 , or a material gas H 2 / SiH 4 flow rate ratio of 8 to 20, and a deposition rate of 50 to 50 (angstrom / min) or less. A 200 angstrom film is formed.
Next, the second non-doped amorphous silicon film 10 is continuously exposed to the atmosphere at the same temperature as the first amorphous silicon film 9 and the high frequency power is 0.04 to 0.06 W / cm 2 and the pressure is 80 to 16.
0 Pa, a mixed gas of SiH 4 and H 2 is used as a film forming gas, and the film thickness of the first film and the second film is 50 at a film forming rate corresponding to a deposition rate of 200 (angstrom / min) or more.
A film of 0 to 2000 angstrom is formed. Next, as shown in FIG. 2d, SiN is formed into a film by a CVD method, a channel protective film 11 is formed, and a contact hole is formed by photolithography as shown in FIG. 2e. Next, as shown in FIG. 3A, a P-doped amorphous silicon film 12 is formed thereon by a CVD method, and A is formed thereon by a sputtering method.
An l-Si-Cu film is formed 13, 14 and then an Al-Si-Cu film is formed by a wet etching method as shown in FIG. 3b.
After patterning 13 and 14, the P-doped amorphous silicon film 12 is patterned by the RIE method to form the source electrode 13 and the drain electrode 14. Then film formation temperature 300 ° C. The SiN film by CVD protective film 15 as shown in FIG. 3c, a high frequency power 0.2~0.4W / cm 2, the material gas SiH 4 at a pressure 130~160Pa, NH 3, N 2
A film is formed using the mixed gas of.
【００４１】次に第６の発明の方法による作用を示す。
保護膜１５の成膜温度を、前記第１及び第２のＳｉＮ膜
７、第１及び第２の非晶質シリコン膜９、１０、チャネ
ル保護膜１１の成膜温度と同一或いはそれ以下に設定す
ることにより、図１２に示されている非晶質シリコン膜
の電界効果移動度の高温成膜による減少を防止すること
が可能となり高い電界効果移動度の非晶質シリコン膜が
得られる。Next, the operation of the method of the sixth invention will be described.
The film forming temperature of the protective film 15 is set to be equal to or lower than the film forming temperature of the first and second SiN films 7, the first and second amorphous silicon films 9 and 10, and the channel protective film 11. By doing so, it is possible to prevent the field effect mobility of the amorphous silicon film shown in FIG. 12 from decreasing due to high temperature film formation, and an amorphous silicon film having a high field effect mobility can be obtained.
【００４２】実施例２．この実施例２は、第７の発明の
製造方法の実施例を示すもので実施例１で示した第２の
ゲート絶縁膜７と界面を形成する第１の非晶質シリコン
膜９をより高速に成膜に形成する製造方法に関するもの
である。図２ａに示すようにガラス基板１上に形成され
たゲート５上に第１のゲート絶縁膜のＳｉＮ膜６を、成
膜温度３００℃、高周波電力密度０．２〜０．４Ｗ／ｃ
ｍ2、圧力１３０〜１６０Ｐａ、成膜ガスＮ2、Ｓｉ
Ｈ4、ＮＨ3の混合ガスを用いてＮＨ3／ＳｉＨ4流量比
０．５〜２で膜厚５０〜１５０オングストローム成膜す
る。次に図２ｂに示すように非晶質シリコン膜９と接す
る第２のゲート絶縁膜のＳｉＮ膜７を大気開放せず連続
で第１のＳｉＮ６と同じ成膜温度で、高周波電力密度
０．２〜０．４Ｗ／ｃｍ2、圧力１３０〜１６０Ｐａ、
成膜ガスにＮ2、ＳｉＨ4、ＮＨ3の混合ガスを用いてＮ
Ｈ3／ＳｉＨ4流量比４〜８で第１及び第２のＳｉＮの膜
厚を合わせて３０００〜５０００オングストローム成膜
する。次にノンドープ非晶質シリコン膜の成膜方法につ
いて説明する。図２ｃに示すように第２のＳｉＮ膜７と
界面を形成する第１のノンドープ非晶質シリコン膜９
は、ＣＶＤ法により成膜温度３００℃、圧力８０〜１６
０Ｐａ、高周波電力０．０１５〜０．０２Ｗ／ｃｍ2、
或いは材料ガスＨ2／ＳｉＨ4の流量比を８〜２０とし
て、デポレートが８０（オングストローム／分）以下に
相当する成膜条件で５０〜２００オングストローム成膜
する。Example 2. This second embodiment shows an embodiment of the manufacturing method of the seventh invention, and the first amorphous silicon film 9 forming an interface with the second gate insulating film 7 shown in the first embodiment is formed at a higher speed. The present invention relates to a manufacturing method for forming a film. As shown in FIG. 2a, a SiN film 6 as a first gate insulating film is formed on a gate 5 formed on a glass substrate 1 at a film forming temperature of 300 ° C. and a high frequency power density of 0.2 to 0.4 W / c.
m2, the pressure 130～160Pa, the film forming gas N 2, Si
A mixed gas of H 4 and NH 3 is used to form a film with a film thickness of 50 to 150 Å at an NH 3 / SiH 4 flow rate ratio of 0.5 to 2. Next, as shown in FIG. 2B, the SiN film 7 of the second gate insulating film which is in contact with the amorphous silicon film 9 is continuously exposed to the atmosphere at the same film forming temperature as that of the first SiN 6 at a high frequency power density of 0.2. ~ 0.4 W / cm 2 , pressure 130-160 Pa,
Using a mixed gas of N 2 , SiH 4 , and NH 3 as a film forming gas,
At a H 3 / SiH 4 flow rate ratio of 4 to 8, the first and second SiN films are combined to form a film having a thickness of 3000 to 5000 angstroms. Next, a method for forming a non-doped amorphous silicon film will be described. As shown in FIG. 2c, a first non-doped amorphous silicon film 9 forming an interface with the second SiN film 7 is formed.
Is a film forming temperature of 300 ° C. and a pressure of 80 to 16 by the CVD method.
0 Pa, high frequency power 0.015 to 0.02 W / cm 2 ,
Or the flow rate of the material gas H 2 / SiH 4 as 8-20, deposition rate is 50 to 200 Angstroms formed in the deposition conditions corresponding to 80 (Å / min) or less.
【００４３】ここで上記高周波電力の印加方法を図１３
を用いて説明する。図１３ａは従来の方法で、良質の非
晶質膜形成のため１３．５６ＭＨＺの高周波電力が印加
されていた。しかし、この方式ではデポレートが低く問
題であった。ここで第７の発明による方法を図１３ｂ〜
図１３ｄで説明する。図１３ｂは上記の高周波電力０．
０１〜０．０３Ｗ／ｃｍ2の高周波電力印加に対し、成
膜開始１０秒以下だけパルス電力０．０４Ｗ／ｃｍ2以
上の高周波を同期させ、予備放電を起こすことにより低
い高周波電力で安定に放電させ、成膜温度２８０〜３５
０℃、圧力８０〜１６０Ｐａで、成膜ガスにＳｉＨ4、
Ｈ2の混合ガスを用いてデポレートが８０（オングスト
ローム／分）以下の成膜条件で５０〜２００オングスト
ローム成膜することができる。図１３ｃは高周波電力の
通常の例えば３倍とし、高周波でＯＮ、ＯＦＦを繰り返
すことにより約３倍の高いデポレートで良質な膜の成膜
が可能である。図８ｄは通常の高周波電力に３０ＭＨＺ
以上の高周波パルスを重畳する方法を示したもので、上
記と同様に高速のデポレートをうることができる。Here, the method of applying the high frequency power will be described with reference to FIG.
Will be explained. FIG. 13a shows a conventional method, in which a high frequency power of 13.56 MHZ was applied to form a good quality amorphous film. However, this method has a problem of low deposition rate. The method according to the seventh invention is now described in FIGS.
This will be described with reference to FIG. 13d. FIG. 13b shows the above high frequency power 0.
High frequency power of 0.01 to 0.03 W / cm 2 is applied, and high frequency of pulse power 0.04 W / cm 2 or more is synchronized for 10 seconds or less to start film formation and stable discharge is performed with low high frequency power by causing preliminary discharge. And the film forming temperature of 280 to 35
SiH 4 is used as a film forming gas at 0 ° C. and a pressure of 80 to 160 Pa.
It is possible to form a film of 50 to 200 angstroms by using a mixed gas of H 2 under the film forming condition of a deposition rate of 80 (angstrom / min) or less. In FIG. 13C, the high frequency power is set to, for example, three times as high as usual, and by repeating ON and OFF at a high frequency, it is possible to form a good quality film with a high deposition rate of about three times. Fig. 8d shows 30 MHz for normal high frequency power.
The method for superimposing the high frequency pulses described above is shown, and a high-speed deposition rate can be obtained as in the above.
【００４４】第７の発明による方法の作用を示す。図１
３ｂの方法は、周期的に単一パルスを印加することによ
り、予備放電が生じ、これにより立ち上がりの速い放電
開始が得られるので高速成膜が可能となる。図１３ｃの
方法は、同じ平均電力でも放電に有効な高圧のパルスが
多く印加されるので、放電が加速され高速成膜が可能と
なる。図１３ｄの方法は、３０ＭＨＺの高周波を重畳す
ることにより放電開始電圧周辺の放電を有効に活用で
き、安定した高能率の成膜が可能となる。以上の方法を
用いることにより、従来低いデポレートの第１の非晶質
シリコン膜の成膜を高速化できる。The operation of the method according to the seventh invention will be described. Figure 1
In the method of 3b, by applying a single pulse periodically, a preliminary discharge is generated, whereby a fast rising discharge start can be obtained, so that high speed film formation is possible. In the method of FIG. 13c, since many high-voltage pulses effective for discharge are applied even with the same average power, discharge is accelerated and high-speed film formation is possible. In the method of FIG. 13d, by superimposing a high frequency of 30 MHZ, the discharge around the discharge start voltage can be effectively utilized, and stable high-efficiency film formation becomes possible. By using the above method, it is possible to speed up the formation of the first amorphous silicon film having a conventionally low deposition rate.
【００４５】[0045]
【発明の効果】第１の発明により、第１および第２の絶
縁膜中の水素量を制御できて、第２のゲート絶縁膜中の
水素を非晶質シリコン界面に供給し、界面準位を減少さ
せて高電界効果移動度を得るとともに、第１のゲート絶
縁膜により非晶質シリコン膜とのドライエッチングの選
択比を確保することができる。また、第２の発明では、
第２のゲート絶縁膜中の水素を非晶質シリコン界面に供
給し、界面準位を減少させて高電界効果移動度を得ると
ともに、第１のゲート絶縁膜により非晶質シリコン膜と
のドライエッチングの選択比を確保することができる。
また界面準位を少なく形成された第１の非晶質シリコン
膜を、さらに第２のゲート絶縁膜中の水素で界面準位を
減少させ高電界効果移動度がえられる。また非晶質シリ
コン膜をデポレートの低い薄い第１の非晶質シリコン膜
とデポレートの高い厚い第２の非晶質シリコン膜とで構
成することにより、全体で成膜時間を短縮できる。ま
た、第３の発明では、第１の非晶質シリコン膜中のＳｉ
−Ｈ結合数に対するＳｉ−Ｈ２結合数の比を制御するこ
とで移動度を高く制御できるとともに、デポレートの高
い第２の非晶質シリコン膜の形成で、全体で成膜時間を
短縮できる。According to the first aspect of the invention, the first and second isolations are provided.
The amount of hydrogen in the edge film can be controlled, hydrogen in the second gate insulating film is supplied to the amorphous silicon interface, the interface state is reduced to obtain high field effect mobility, and the first gate The insulating film can ensure the dry etching selectivity with respect to the amorphous silicon film. In the second invention,
The hydrogen in the second gate insulating film is supplied to the amorphous silicon interface.
To reduce the interface state and obtain high field effect mobility.
In both cases, an amorphous silicon film is formed by the first gate insulating film.
The dry etching selectivity can be secured.
Further , the first amorphous silicon film formed with a small number of interface states is further reduced in hydrogen by the hydrogen in the second gate insulating film, so that the high field effect mobility can be obtained. Further, by forming the amorphous silicon film by the thin first amorphous silicon film having a low deposition rate and the thick second amorphous silicon film having a high deposition rate, the deposition time can be shortened as a whole. Further, in the third invention, Si in the first amorphous silicon film is
The mobility can be controlled to be high by controlling the ratio of the number of Si—H 2 bonds to the number of —H bonds, and the formation time of the second amorphous silicon film having a high deposition rate can be shortened as a whole.
【図１】本願発明の薄膜トランジスタの構造断面図。FIG. 1 is a structural cross-sectional view of a thin film transistor of the present invention.
【図２】本願発明の薄膜トランジスタの製造工程図
（１）。FIG. 2 is a manufacturing process diagram (1) of the thin film transistor of the invention.
【図３】本願発明の薄膜トランジスタの製造工程図
（２）。FIG. 3 is a manufacturing process diagram (2) of the thin film transistor of the invention.
【図４】従来の薄膜トランジスタの構造断面図。FIG. 4 is a structural cross-sectional view of a conventional thin film transistor.
【図５】従来の薄膜トランジスタの等価回路図。FIG. 5 is an equivalent circuit diagram of a conventional thin film transistor.
【図６】従来の薄膜トランジスタの平面図。FIG. 6 is a plan view of a conventional thin film transistor.
【図７】ＳｉＮ膜成膜の材料ガスＮＨ3／ＳｉＨ4流量比
に対する（ａ）非晶質シリコン膜の電界効果移動度と、
（ｂ）ＳｉＮ膜中のＮ−Ｈ結合量及びＳｉ−Ｈ結合によ
る単位体積あたりの水素量の関係を示す図。FIG. 7 shows (a) field effect mobility of an amorphous silicon film with respect to a material gas NH 3 / SiH 4 flow rate ratio for forming a SiN film,
(B) The figure which shows the relationship between the amount of NH bonds in a SiN film, and the amount of hydrogen per unit volume by Si-H bonds.
【図８】ＳｉＮ膜のＮ−Ｈ結合による水素量と膜のエッ
チングレートの関係を示す図。FIG. 8 is a diagram showing the relationship between the amount of hydrogen due to N—H bonds in a SiN film and the etching rate of the film.
【図９】非晶質シリコン膜中のＳｉ−Ｈ2結合数／Ｓｉ
−Ｈ結合数と電界効果移動度との関係を示す図。FIG. 9 is the number of Si—H 2 bonds in the amorphous silicon film / Si
The figure which shows the relationship between the number of -H bonds, and field effect mobility.
【図１０】ａ．ＣＶＤ法の高周波電力と非晶質シリコン
膜中のＳｉ−Ｈ2結合数／Ｓｉ−Ｈ結合数の関係を示す
図。
ｂ．ＣＶＤ法による非晶質シリコン膜成膜の材料ガスＨ
2／ＳｉＨ4流量比に対する非晶質シリコン膜中のＳｉ−
Ｈ2結合数／Ｓｉ−Ｈ結合数の関係を示す図。FIG. 10 a. It illustrates a Si-H 2 bond number / Si-H bonds relationship between the number of high-frequency power and the amorphous silicon film in a CVD method. b. Material gas H for forming an amorphous silicon film by the CVD method
Si-in the amorphous silicon film with respect to the 2 / SiH 4 flow rate ratio
Shows of H 2 bond number / Si-H bond number relationship.
【図１１】薄膜トランジスタの成膜温度設定方式と電界
効果移動度との関係を示す図。FIG. 11 is a diagram showing a relationship between a film formation temperature setting method of a thin film transistor and field effect mobility.
【図１２】保護膜成膜温度と移動度減少率の関係を示す
図。FIG. 12 is a diagram showing a relationship between a protective film forming temperature and a mobility decreasing rate.
【図１３】ＣＶＤ法の高周波電力への予備電力印加方
式。FIG. 13 is a method of applying standby power to high frequency power of the CVD method.
１ 基板 ４ 画素電極 ５ ゲート電極 ６、７ ゲート絶縁膜 ９、１０ ノンドープ非晶質シリコン膜 １１ チャネル保護膜 １２ Ｐドープ非晶質シリコン膜 １３ ソース電極 １４ ドレイン電極 １５ 保護膜（パッシベーション） １６ 隣接ゲートバスライン １７ ソースバスライン １８、１９、２０ コンタクトホール 1 substrate 4 pixel electrodes 5 Gate electrode 6, 7 Gate insulation film 9, 10 Non-doped amorphous silicon film 11 channel protective film 12 P-doped amorphous silicon film 13 Source electrode 14 drain electrode 15 Protective film (passivation) 16 Adjacent gate bus line 17 Source Bus Line 18, 19, 20 contact holes
───────────────────────────────────────────────────── フロントページの続き (72)発明者 羽山 昌宏 熊本県菊池郡西合志町御代志997番地 株式会社アドバンスト・ディスプレイ内 (56)参考文献 特開 平３−36769（ＪＰ，Ａ) 特開 平２−25074（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/786 H01L 21/205 H01L 21/31 H01L 21/318 H01L 21/336 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masahiro Hayama Inventor Masahiro Hayama 997 Miyoshi, Nishigoshi-cho, Kikuchi-gun, Kumamoto Inside Advanced Display Co., Ltd. (56) Reference JP-A-3-36769 (JP, A) JP-A-2-36 25074 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 29/786 H01L 21/205 H01L 21/31 H01L 21/318 H01L 21/336
Claims (3)
と、上記ゲート電極上に材料ガスのＮＨ３／ＳｉＨ４の
流量比が４を越えないようにして窒化珪素膜から成る第
１のゲート絶縁膜を形成する工程と、上記第１のゲート
絶縁膜上に材料ガスのＮＨ３／ＳｉＨ４の流量比が４を
下回らないようにして窒化珪素膜から成る第２のゲート
絶縁膜を形成する工程と、上記第２のゲート絶縁膜上に
非晶質シリコン膜を形成する工程とを有したことを特徴
とする薄膜トランジスタの製造方法。1. A step of forming a gate electrode on an insulating substrate, and a first gate made of a silicon nitride film so that a flow rate ratio of NH 3 / SiH 4 of a material gas does not exceed 4 on the gate electrode. Step of forming an insulating film, and forming a second gate insulating film made of a silicon nitride film on the first gate insulating film so that the flow rate ratio of NH 3 / SiH 4 of the material gas does not fall below 4 process and method of the second thin film transistor you characterized by having a step of forming an amorphous silicon film on the gate insulating film.
上記ゲート電極上に形成された第１のゲート絶縁膜と、
該第１のゲート絶縁膜上に形成された第２のゲート絶縁
膜と、該第２のゲート絶縁膜上に形成された第１の非晶
質シリコン膜と、該第１の非晶質シリコン膜上に形成さ
れた第２の非晶質シリコン膜とを有し、上記第１のゲー
ト絶縁膜は、膜中の水素含有量が上記第２のゲート絶縁
膜中の水素含有量よりも少ない窒化珪素膜で構成され、
上記第２のゲート絶縁膜は、膜中のＮ−Ｈ結合数が４０
〜６０ｃｍ −１ の窒化珪素膜で構成され、上記第１の非
晶質シリコン膜は、膜中のＳｉ−Ｈ結合数に対するＳｉ
−Ｈ ２ 結合数の比が０より大きく０．０５以下であり、
上記第２の非晶質シリコン膜は、上記第１の非晶質シリ
コン膜に比して膜厚が厚く、しかも膜中のＳｉ−Ｈ結合
数に対するＳｉ−Ｈ ２ 結合数の比が大きいことを特徴と
する薄膜トランジスタ。2. A gate electrode formed on an insulating substrate,
A first gate insulating film formed on the gate electrode,
Second gate insulation formed on the first gate insulation film
Film and a first amorphous film formed on the second gate insulating film
Formed on the first silicon film and the first silicon film.
And a second amorphous silicon film formed on the first amorphous silicon film.
The gate insulating film has a hydrogen content in the film which is the second gate insulating film.
Composed of a silicon nitride film having a hydrogen content lower than that of the film,
The number of N—H bonds in the second gate insulating film is 40.
Composed of a silicon nitride film of about 60 cm −1 ,
The crystalline silicon film has a Si content corresponding to the number of Si-H bonds in the film.
The ratio of the number of —H 2 bonds is more than 0 and 0.05 or less,
The second amorphous silicon film is the first amorphous silicon film.
The film thickness is thicker than the con film, and the Si-H bond in the film
A thin film transistor and a ratio of Si-H 2 bonds having a large number to the number.
０．０１５〜０．０２Ｗ／ｃｍ２で、或いは材料ガスの
流量比Ｈ２／ＳｉＨ４が８〜２０の成膜条件で化学気相
成長法により第１の非晶質シリコン膜を形成する工程
と、上記第１の非晶質シリコン膜上に、該第１の非晶質
シリコン膜の成膜条件範囲よりも高周波電力を高く、或
いは材料ガスの流量比Ｈ２／ＳｉＨ４を低くして、該第
１の非晶質シリコン膜よりも大きな成膜速度で第２の非
晶質シリコン膜を形成する工程とを有することを特徴と
する請求項２記載の薄膜トランジスタの製造方法。3. Chemical deposition on the second gate insulating film under high-frequency power of 0.015 to 0.02 W / cm 2 or a material gas flow rate ratio H 2 / SiH 4 of 8 to 20. A step of forming a first amorphous silicon film by a vapor phase epitaxy method, and a high-frequency power on the first amorphous silicon film higher than a film forming condition range of the first amorphous silicon film. Forming a second amorphous silicon film at a film forming rate higher than that of the first amorphous silicon film by increasing the flow rate ratio H 2 / SiH 4 of the material gas to a higher value. The method for manufacturing a thin film transistor according to claim 2, wherein
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| JP30406393A JP3376051B2 (en) | 1993-12-03 | 1993-12-03 | Thin film transistor and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| Publication Number | Publication Date |
|---|---|
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| JP3376051B2 true JP3376051B2 (en) | 2003-02-10 |
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| JP4562835B2 (en) * | 1999-11-05 | 2010-10-13 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| KR100641627B1 (en) * | 2000-07-19 | 2006-11-02 | 엘지.필립스 엘시디 주식회사 | Amorphous-Silicon Thin Film Transistor and method for fabricating the same |
| TW525216B (en) | 2000-12-11 | 2003-03-21 | Semiconductor Energy Lab | Semiconductor device, and manufacturing method thereof |
| JP5331407B2 (en) * | 2007-08-17 | 2013-10-30 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP5308019B2 (en) | 2007-12-19 | 2013-10-09 | 三菱電機株式会社 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE |
| WO2010084657A1 (en) * | 2009-01-26 | 2010-07-29 | シャープ株式会社 | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal device |
| JP5762575B2 (en) | 2012-01-30 | 2015-08-12 | 京セラ株式会社 | Method for manufacturing photoelectric conversion element and photoelectric conversion element |
| JP5779690B2 (en) * | 2014-05-02 | 2015-09-16 | 株式会社半導体エネルギー研究所 | Display device and electronic device |
| JP2017142537A (en) * | 2017-05-11 | 2017-08-17 | 株式会社半導体エネルギー研究所 | Semiconductor device and electronic apparatus |
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