JP3374685B2 - Phase synchronization controller - Google Patents
Phase synchronization controllerInfo
- Publication number
- JP3374685B2 JP3374685B2 JP32956296A JP32956296A JP3374685B2 JP 3374685 B2 JP3374685 B2 JP 3374685B2 JP 32956296 A JP32956296 A JP 32956296A JP 32956296 A JP32956296 A JP 32956296A JP 3374685 B2 JP3374685 B2 JP 3374685B2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- phase difference
- voltage
- control device
- synchronization control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Ac-Ac Conversion (AREA)
- Inverter Devices (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、インバータのよう
な交流出力電力変換装置の出力電圧位相を他の交流電源
の電圧位相に同期させるための同期制御回路に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization control circuit for synchronizing the output voltage phase of an AC output power converter such as an inverter with the voltage phase of another AC power supply.
【0002】[0002]
【従来の技術】図11は、例えば特開昭55−3485
1号公報に示された従来の同期制御回路を示すブロック
図である。図において、1は入力電圧に応じて発振周波
数が変化する可変周波数発振器(以下、VCOと呼
ぶ)、2はVCO1の出力パルスを計数して位相信号θ
0 を生成するカウンタ、21は位相信号θ0 に基づいて
VCO1の出力に同期した2相信号V0a、V0bを生成す
る2相信号生成回路、22は3相信号R、S、Tをこれ
に同期した2相信号Va 、Vb に変換する3相/2相変
換回路、6’は3相/2相変換回路22と2相信号生成
回路21からのVa 、Vb とV0a、V0bとから両者の位
相差Δθを生成する位相差検出回路、9はループフィル
タである。2. Description of the Related Art FIG. 11 shows, for example, JP-A-55-3485.
FIG. 6 is a block diagram showing a conventional synchronization control circuit shown in Japanese Patent Laid-Open No. In the figure, 1 is a variable frequency oscillator whose oscillation frequency changes according to an input voltage (hereinafter referred to as VCO), and 2 is a phase signal θ obtained by counting output pulses of VCO 1.
A counter that generates 0 , 21 is a two-phase signal generation circuit that generates two-phase signals V 0a and V 0b synchronized with the output of VCO 1 based on the phase signal θ 0 , and 22 is a three-phase signal R, S, and T A three-phase / two-phase conversion circuit for converting into two-phase signals V a and V b synchronized with, and 6 ′ is V a , V b and V 0a from the three-phase / two-phase conversion circuit 22 and the two-phase signal generation circuit 21. , V 0b and a phase difference detection circuit for generating a phase difference Δθ between them and 9 is a loop filter.
【0003】次に動作について説明する。3相/2相変
換回路22は3相信号R、S、Tの電圧Vr 、Vs 、V
t を次式に基づいて2相信号Va 、Vb に変換する。
Va =Vr (1)
Vb =(Vs−Vt)/√3 (2)
この変換により、例えば
Vr =Vcosθ1 (3)
Vs =Vcos(θ1−2π/3) (4)
Vt =Vcos(θ1+2π/3) (5)
のとき
Va =Vcosθ1 (6)
Vb =Vsinθ1 (7)
となる。但し、Vは振幅、θ1 は位相である。Next, the operation will be described. 3-phase / 2-phase conversion circuit 22 are three-phase signals R, S, the voltage of the T V r, V s, V
Convert t into two-phase signals V a and V b based on the following equation. V a = V r (1) V b = (V s -V t) / √3 (2) This conversion, for example V r = Vcosθ 1 (3) V s = Vcos (θ 1 -2π / 3) ( 4) When V t = V cos (θ 1 + 2π / 3) (5) V a = V cos θ 1 (6) V b = V sin θ 1 (7) However, V is amplitude and θ 1 is phase.
【0004】2相信号生成回路21は、位相信号θ0 か
ら次式に基づいて2相信号V0a、V0bを生成する。
V0a=cosθ0 (8)
V0b=sinθ0 (9)
この2相信号V0a、V0bを2相信号Va 、Vb とともに
位相差検出回路6’へ入力し、次式に基づいて位相差Δ
θ(=θ1−θ0)を生成する。
Δθ=sin-1((V0aVb−V0bVa)/√(Va 2+Vb 2)) (10)The two-phase signal generation circuit 21 generates two-phase signals V 0a and V 0b from the phase signal θ 0 based on the following equation. V 0a = cos θ 0 (8) V 0b = sin θ 0 (9) The two-phase signals V 0a and V 0b are input to the phase difference detection circuit 6 ′ together with the two-phase signals V a and V b , and based on the following equation. Phase difference Δ
θ (= θ 1 −θ 0 ) is generated. Δθ = sin −1 ((V 0a V b −V 0b V a ) / √ (V a 2 + V b 2 )) (10)
【0005】この位相差Δθをループフィルタ9を介し
てVCO1に加える。位相差信号Δθが零となるような
フィードバックループを構成しており、VCO1が3相
信号R、S、Tと同期する周波数パルスを生成し、これ
を交流出力の電力変換装置などにおける同期制御に利用
している。This phase difference Δθ is added to the VCO 1 via the loop filter 9. The feedback loop is configured so that the phase difference signal Δθ becomes zero, and the VCO 1 generates a frequency pulse that synchronizes with the three-phase signals R, S, T, and this is used for synchronization control in an AC output power converter or the like. We are using.
【0006】[0006]
【発明が解決しようとする課題】従来の同期制御回路は
上記のように構成されているので、次のような問題があ
った。第一に、位相差検出回路6’では位相差Δθを逆
正弦函数(sin-1 )を用いて求めるため、位相差Δθ
は、逆正弦函数の主値である−π≦Δθ≦π(ラジア
ン)となる。このため、実際の位相差が±πの範囲を超
えると位相差Δθの符号が反転することになる。このた
め、制御開始時に3相信号R、S、Tの周波数とVCO
1の自走発振周波数との差が大きくしかも制御系の応答
が遅いと、VCO1の出力周波数がVCO1の自走発振
周波数付近で振動し、同期制御回路の周波数を3相信号
の周波数に引き込めず、安定した同期制御を実現できな
い。Since the conventional synchronous control circuit is constructed as described above, it has the following problems. First, since the phase difference detection circuit 6 ′ obtains the phase difference Δθ using the inverse sine function (sin −1 ), the phase difference Δθ
Is the principal value of the arc sine function, −π ≦ Δθ ≦ π (radian). Therefore, when the actual phase difference exceeds the range of ± π, the sign of the phase difference Δθ is inverted. Therefore, at the start of control, the frequencies of the three-phase signals R, S and T and the VCO
If the difference from the free-running oscillation frequency of 1 is large and the response of the control system is slow, the output frequency of VCO1 oscillates near the free-running oscillation frequency of VCO1 and the frequency of the synchronous control circuit is pulled in to the frequency of the three-phase signal. Therefore, stable synchronization control cannot be realized.
【0007】第二には、2相信号Va 、Vb からΔθを
求めるためにソフトウェアによって位相差検出回路
6’、ループフィルタ9を構成しようとすると、三角関
数の演算あるいは三角関数の数値テーブルを必要とする
ため、CPUの負荷が増加し、あるいはデータメモリを
大量に必要とすることになり、インバータ等の電力変換
装置における制御演算を行うCPUにこれらの機能を負
担させることができなくなり、上述の機能を分担するた
めのCPUを追加する必要が生じることである。Secondly, if the phase difference detecting circuit 6'and the loop filter 9 are to be constructed by software in order to obtain Δθ from the two-phase signals V a and V b , trigonometric function calculation or trigonometric function numerical table is performed. Therefore, the load on the CPU increases or a large amount of data memory is required, and it becomes impossible for the CPU that performs control calculation in the power conversion device such as an inverter to bear these functions. It is necessary to add a CPU for sharing the above-mentioned functions.
【0008】第三の問題点は、同期対象である3相信号
R、S、Tに波形のひずみや3相不平衡があると、3相
/2相変換回路22の出力に3相信号R、S、Tの周期
の1/2の周期を有するリップルが発生し、ループフィ
ルタ7を介してVCO1の入力にリップルを含むことに
なり、VCO1の出力が周期の安定したパルスになら
ず、カウンタ2の出力である位相信号θ0 にもリップル
の影響が現れることである。The third problem is that if the three-phase signals R, S, and T to be synchronized have waveform distortion or three-phase imbalance, the three-phase / two-phase conversion circuit 22 outputs the three-phase signal R. , S, and T have a half cycle, and the input of VCO1 contains a ripple through the loop filter 7, so that the output of VCO1 does not become a stable cycle pulse, and the counter That is, the influence of the ripple appears on the phase signal θ 0 which is the output of 2.
【0009】この発明は上述のような問題点を解決する
ためになされたもので、制御開始時のVCO1の出力と
3相信号R、S、Tとの周波数差が大きく、あるいは3
相信号R、S、Tに不平衡や波形ひずみが存在しても、
3相信号R、S、Tに対して安定した位相同期の得られ
る同期制御回路を提供することを目的とする。The present invention has been made to solve the above-mentioned problems, and the frequency difference between the output of the VCO 1 and the three-phase signals R, S, T at the start of control is large, or 3
Even if there is imbalance or waveform distortion in the phase signals R, S, T,
An object of the present invention is to provide a synchronization control circuit that can obtain stable phase synchronization with respect to three-phase signals R, S, and T.
【0010】[0010]
【課題を解決するための手段】3相交流電源の電圧位相
に基づいて3相電力変換装置の制御基準位相を生成する
位相同期制御装置において、3相交流電源の電圧を3相
電力変換装置の出力電圧位相に同期したd−q回転座標
上の直流成分に変換し、このd−q回転座標上で3相交
流電源の電圧位相と3相電力変換装置の出力電圧位相の
位相差を生成するとともに、この位相差を所定の値に制
限した補正位相差を生成する位相差補正回路とループフ
ィルタを介して可変周波数発振器に入力し制御基準位相
を生成するようにした。In a phase synchronization control device for generating a control reference phase of a three-phase power converter based on a voltage phase of a three-phase AC power supply, the voltage of the three-phase AC power supply is controlled by the three-phase power converter. It is converted into a DC component on the dq rotation coordinates synchronized with the output voltage phase, and a phase difference between the voltage phase of the three-phase AC power supply and the output voltage phase of the three-phase power converter is generated on the dq rotation coordinates. At the same time, the control reference phase is generated by inputting it to a variable frequency oscillator through a phase difference correction circuit and a loop filter that generate a corrected phase difference that limits this phase difference to a predetermined value.
【0011】また、3相交流電源の電圧と3相電力変換
装置の出力電圧を定周波数発振器の出力に同期したd−
q回転座標上の直流成分に変換し、d−q回転座標上で
3相交流電源の電圧と3相電力変換装置の出力電圧の位
相差を生成し、この位相差を所定の値に制限した補正位
相差を生成する位相差補正回路とループフィルタを介し
て可変周波数発振器に入力し前記制御基準位相を生成す
るようにした。Further, d- in which the voltage of the three-phase AC power supply and the output voltage of the three-phase power converter are synchronized with the output of the constant frequency oscillator
It is converted into a DC component on the q-rotational coordinate, a phase difference between the voltage of the three-phase AC power supply and the output voltage of the three-phase power converter is generated on the dq rotational coordinate, and this phase difference is limited to a predetermined value. The control reference phase is generated by inputting it to a variable frequency oscillator through a phase difference correction circuit that generates a corrected phase difference and a loop filter.
【0012】さらにまた、位相差の生成に三角函数の近
似多項式を用いた。Furthermore, an approximation polynomial of trigonometric function is used for generating the phase difference.
【0013】さらにまた、位相差補正回路において位相
差とその変化量の履歴に基づいて補正値を生成するよう
にした。Furthermore, in the phase difference correction circuit, the correction value is generated based on the history of the phase difference and its change amount.
【0014】さらにまた、位相差あるいは補正位相差に
対して3相交流電源の1周期間における移動平均値を生
成する移動平均回路を備えた。Furthermore, a moving average circuit for generating a moving average value for one cycle of the three-phase AC power source is provided for the phase difference or the corrected phase difference.
【0015】[0015]
【発明の実施の形態】以下、図を用いてこの発明による
同期制御装置の実施形態を説明する。各図に用いる符号
は、図11で説明した従来の同期制御装置と同一もしく
は相当する部分に同一の符号を付し、そのくり返しの説
明は省略する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a synchronization control device according to the present invention will be described below with reference to the drawings. The reference numerals used in each figure are the same as or equivalent to those of the conventional synchronization control device described in FIG. 11, and the same description is omitted.
【0016】実施形態1.図1は、本発明による同期制
御装置の第1の実施形態におけるブロック図、図2は位
相差検出回路の特性図、図3は位相差補正回路の状態遷
移図である。3は3相正弦波発生回路でありカウンタ2
の生成する位相信号θ0 からVCO1の出力に同期した
3相正弦波を生成する。4はd−q座標変換回路で、3
相正弦波発生回路3の出力および3相信号R、S、Tか
ら、次式に示す同期回転座標であるd−q回転座標上の
d軸およびq軸の各成分Vd、Vqを生成する。
Vd=√(2/3)(Vr・sin(θ0)+Vs・sin(θ0−2π/3)
+Vt・sin(θ0+2π/3)) (11)
Vq=√(2/3)(Vr・cos(θ0)+Vs・cos(θ0−2π/3)
+Vt・cos(θ0+2π/3)) (12)Embodiment 1. 1 is a block diagram in a first embodiment of a synchronization control device according to the present invention, FIG. 2 is a characteristic diagram of a phase difference detection circuit, and FIG. 3 is a state transition diagram of a phase difference correction circuit. 3 is a three-phase sine wave generator circuit
The three-phase sine wave synchronized with the output of the VCO 1 is generated from the phase signal θ 0 generated by. 4 is a dq coordinate conversion circuit, 3
From the output of the phase sine wave generation circuit 3 and the three-phase signals R, S, and T, the d-axis and q-axis components V d and V q on the dq rotation coordinates, which are the synchronous rotation coordinates shown in the following equation, are generated. To do. V d = √ (2/3) (V r · sin (θ 0 ) + V s · sin (θ 0 −2π / 3) + V t · sin (θ 0 + 2π / 3)) (11) V q = √ ( 2/3) ( Vr · cos (θ 0 ) + V s · cos (θ 0 −2π / 3) + V t · cos (θ 0 + 2π / 3)) (12)
【0017】5はd−q座標変換回路4の後段に設けた
低域通過フィルタ(以下、LPFと呼ぶ)であり、3相
信号R、S、Tの波形ひずみを除去する。6は位相差検
出回路で、d−q座標変換回路4で生成したVd 、Vq
からVq /Vd の逆正接関数(tan-1 )の主値として得
られる位相差Δθを生成する。7はLPF5および位相
差検出回路6の後段に設けた移動平均回路で、3相信号
R、S、Tの不平衡を原因とするd−q座標変換回路4
の出力に生じる周期的な変動を除去するために位相差Δ
θの移動平均をとる。なお、このd−q座標変換回路4
の出力の変動周期は3相信号R、S、Tの周期と等しい
ので、位相差Δθの移動平均における平均化区間を3相
信号R、S、Tの周期の1/2にとればよい。8は位相
差補正回路であり、位相差Δθの履歴に基づいて位相差
Δθを補正した補正位相差Δφを生成する。図2に位相
差Δθと補正位相差Δφの関係を示す。補正位相差Δφ
は位相差Δθを所定のリミット値(±LMT)で制限し
たものになる。図では系の典型的な応答性に基づいて、
リミット値を±1.2とした場合を示している。Reference numeral 5 is a low-pass filter (hereinafter referred to as LPF) provided in the subsequent stage of the dq coordinate conversion circuit 4 and removes waveform distortion of the three-phase signals R, S and T. Reference numeral 6 denotes a phase difference detection circuit, which is V d and V q generated by the dq coordinate conversion circuit 4.
To generate a phase difference Δθ obtained as the principal value of the arctangent function (tan −1 ) of V q / V d . Reference numeral 7 denotes a moving average circuit provided at the subsequent stage of the LPF 5 and the phase difference detection circuit 6 and a dq coordinate conversion circuit 4 caused by the imbalance of the three-phase signals R, S, and T.
Phase difference Δ to eliminate the periodic fluctuation that occurs in the output of
Take the moving average of θ. The dq coordinate conversion circuit 4
Since the fluctuation cycle of the output of is equal to the cycle of the three-phase signals R, S, T, the averaging section in the moving average of the phase difference Δθ may be set to 1/2 of the cycle of the three-phase signals R, S, T. A phase difference correction circuit 8 generates a corrected phase difference Δφ in which the phase difference Δθ is corrected based on the history of the phase difference Δθ. FIG. 2 shows the relationship between the phase difference Δθ and the corrected phase difference Δφ. Corrected phase difference Δφ
Is the phase difference Δθ limited by a predetermined limit value (± LMT). In the figure, based on the typical response of the system,
The case where the limit value is ± 1.2 is shown.
【0018】位相補正回路8は図3に示すように4つの
動作モードをもち、Δθに応じて各モード間を遷移す
る。各モードにおいて生成する補正位相差Δφは次のよ
うになる。
モード1:Δφ=Δθ
モード2:Δφ=Δθ
モード3:Δφ=−LMT
モード4:Δφ=+LMT
各モード間の遷移条件は、図中の遷移を示す矢印に付し
ているとおり
モード1→モード2:Δθ>0
モード2→モード1:Δθ<0
モード1→モード3:Δθ=−LMT
モード3→モード1:−LMT<Δθ<0
モード2→モード4:Δθ=+LMT
モード4→モード2:0<Δθ<+LMT
である。The phase correction circuit 8 has four operation modes as shown in FIG. 3, and transitions between the modes according to Δθ. The correction phase difference Δφ generated in each mode is as follows. Mode 1: Δφ = Δθ Mode 2: Δφ = Δθ Mode 3: Δφ = −LMT Mode 4: Δφ = + LMT The transition conditions between the modes are as shown in the arrows in FIG. 2: Δθ> 0 Mode 2 → Mode 1: Δθ <0 Mode 1 → Mode 3: Δθ = −LMT Mode 3 → Mode 1: −LMT <Δθ <0 Mode 2 → Mode 4: Δθ = + LMT Mode 4 → Mode 2 : 0 <Δθ <+ LMT.
【0019】次に、上述のように構成した同期制御装置
の動作を説明する。いま、VCO1の出力周波数よりも
3相信号R、S、Tの周波数が低く、制御開始時に補正
位相差Δφが+LMTとなって、カウンタ2が生成する
位相信号θ0 が3相信号R、S、Tより遅れて見える場
合を考える。なお、このような状態で、位相差補正回路
8がないと、位相信号θ0 を進めることになり、VCO
1の出力周波数は高くなって位相同期が得られない。Next, the operation of the synchronous control device configured as described above will be described. Now, the frequencies of the three-phase signals R, S, and T are lower than the output frequency of the VCO 1, the correction phase difference Δφ becomes + LMT at the start of control, and the phase signal θ 0 generated by the counter 2 is the three-phase signals R and S. , T appear later than T. In this state, if the phase difference correction circuit 8 is not provided, the phase signal θ 0 is advanced and the VCO
The output frequency of 1 becomes high and phase synchronization cannot be obtained.
【0020】制御開始時にはΔθ>+LMTであるため
位相差補正回路8はモード4の状態にあり、Δφ=+L
MTを生成しVCO1の出力周波数を高くするが、3相
信号R、S、Tの周波数は低いのでθは減少し、やがて
Δθ<+LMTとなってモード2へ移行し、さらにΔθ
<0となりモード1へ、さらにΔθ=−LMTとなって
モード3へ遷移する。VCO1の出力周波数が3相信号
R、S、Tの周波数よりも低くなるまでモード1もしく
はモード3の状態に留まるため、Δθの符号によらずΔ
φは負となり、VCO1の出力周波数は低下する。VC
O1の出力周波数が3相信号R、S、Tの周波数より低
くなると、Δθ>0となるためモード2へ遷移してVC
O1の出力周波数は高くなる。そして、モード1とモー
ド2の間を遷移しながら徐々に位相が同期する。このよ
うな状態遷移を繰返すことにより、交流出力の電力変換
装置の出力と同期対象である3相信号R、S、Tとの制
御開始時における周波数差が大きくかつ制御系の応答が
遅い場合でも、位相を同期させることができる。なお、
この同期制御回路において、ループフィルタ7にPI制
御を用いれば如何なる周波数でも同期することができ
る。なお、移動平均回路7をLPF5および位相差検出
回路6の後段に設けるものとして説明したが、位相差補
正回路8の後段に設けても同等の効果が得られる。Since Δθ> + LMT at the start of control, the phase difference correction circuit 8 is in the mode 4 state, and Δφ = + L
MT is generated and the output frequency of the VCO 1 is increased, but since the frequencies of the three-phase signals R, S, and T are low, θ decreases, and eventually Δθ <+ LMT, and the mode 2 shifts to Δθ.
When <0, the mode 1 is entered, and when Δθ = −LMT, the mode 3 is entered. Since the VCO 1 stays in the mode 1 or the mode 3 until the output frequency of the VCO 1 becomes lower than the frequencies of the three-phase signals R, S, and T, Δ regardless of the sign of Δθ.
φ becomes negative, and the output frequency of VCO1 decreases. VC
When the output frequency of O1 becomes lower than the frequencies of the three-phase signals R, S, and T, Δθ> 0, and therefore the mode 2 shifts to VC.
The output frequency of O1 becomes high. Then, the phases are gradually synchronized while transitioning between the mode 1 and the mode 2. By repeating such state transition, even when the frequency difference between the output of the AC power converter and the three-phase signals R, S, and T to be synchronized at the start of control is large and the response of the control system is slow. , The phases can be synchronized. In addition,
In this synchronization control circuit, if the loop filter 7 uses PI control, any frequency can be synchronized. Although the moving average circuit 7 is provided after the LPF 5 and the phase difference detection circuit 6, the same effect can be obtained by providing the moving average circuit 7 after the phase difference correction circuit 8.
【0021】図1〜3を用いて説明した構成では、位相
差検出回路6でVq /Vd の逆正接関数の主値として得
られる位相差Δθを生成し、位相差補正回路8で位相差
Δθを所定のリミット値で制限した補正位相差Δφを生
成するものとしたが、近似位相差Δθ’を次の近似式に
よって生成し、図1〜3を用いて説明したのと同じ位相
差補正回路によって近似補正位相差Δφ’を生成するよ
うにしてもよい。
Δθ’=Vq/Vd (13)
Vq /Vd と位相差Δθ、近似位相差Δθ’および近似
補正位相差Δφ’の関係を図4に示す。近似位相差Δ
θ’の演算には逆三角関数の演算や関数テーブルの装備
を必要とせず、かつ高速に演算できるうえ、動作も図1
〜3を用いて説明したものとほとんど変わらない。な
お、近似位相差Δθ’を求める演算式として式13を示
したが、以上に述べた動作を実現するVq /Vd につい
ての任意の多項式を用いてよいことはいうまでもない。In the configuration described with reference to FIGS. 1 to 3, the phase difference detection circuit 6 generates the phase difference Δθ obtained as the main value of the arctangent function of V q / V d , and the phase difference correction circuit 8 calculates the phase difference Δθ. The correction phase difference Δφ is generated by limiting the phase difference Δθ with a predetermined limit value. However, the approximate phase difference Δθ ′ is generated by the following approximate expression and the same phase difference as described using FIGS. The approximate correction phase difference Δφ ′ may be generated by the correction circuit. Δθ ′ = V q / V d (13) FIG. 4 shows the relationship between V q / V d and the phase difference Δθ, the approximate phase difference Δθ ′, and the approximate corrected phase difference Δφ ′. Approximate phase difference Δ
The calculation of θ ′ does not require the calculation of the inverse trigonometric function or the equipping of a function table, and the calculation can be performed at high speed.
It is almost the same as the one described by using 3 to 3. Although Equation 13 is shown as an arithmetic expression for obtaining the approximate phase difference Δθ ′, it goes without saying that an arbitrary polynomial for V q / V d that realizes the above-described operation may be used.
【0022】Vq /Vd の多項式の一例として
(Vq/Vd)/√(1+(2/π)2(Vq/Vd)2) (14)
を用いた場合のVq /Vd 、近似位相差Δθ”および近
似補正位相差Δφ”の関係を図5に示す。なお、以上の
説明では位相差の生成に逆正接函数を用いるものとした
が、他の三角函数やその近似多項式を用いて構成するこ
とが可能なことはいうまでもない。[0022] V q / V d (V q / V d) as an example of the polynomial / √ (1+ (2 / π ) 2 (V q / V d) 2) in the case of using the (14) V q / FIG. 5 shows the relationship between V d , the approximate phase difference Δθ ″, and the approximate corrected phase difference Δφ ″. In the above description, the arctangent function is used to generate the phase difference, but it goes without saying that it can be configured using another trigonometric function or its approximate polynomial.
【0023】上述した同期制御回路では、3相信号R、
S、Tのもつ波形ひずみの影響を除去するためにLPF
5を設けるものとしたが、波形ひずみの影響が無視でき
るなら省略することができる。また、3相交流入力R、
S、Tの不平衡によってd−q座標変換回路4の出力に
生じる周期的変動を防止するために移動平均回路9を設
けるものとしたが、d−q座標変換回路4の出力におけ
る周期的変動が無視できるならやはり省略することがで
きる。LPF5のみを設けた場合と、LPF5、移動平
均回路7をともに省略した場合をそれぞれ図7、図8に
示す。In the above synchronization control circuit, the three-phase signal R,
LPF to eliminate the influence of waveform distortion of S and T
Although 5 is provided, it can be omitted if the effect of waveform distortion can be ignored. Also, three-phase AC input R,
Although the moving average circuit 9 is provided in order to prevent the periodical fluctuation occurring in the output of the dq coordinate conversion circuit 4 due to the imbalance of S and T, the periodical fluctuation in the output of the dq coordinate conversion circuit 4 is provided. Can be omitted if is negligible. 7 and 8 show the case where only the LPF 5 is provided and the case where both the LPF 5 and the moving average circuit 7 are omitted.
【0024】以上の説明では、位相差補正回路8におい
て、モード1からモード3への遷移、モード2からモー
ド4への遷移はΔθ<0およびΔθ>0の条件のみによ
るものとしたが、位相Δθをより速く収束させるため
に、遷移条件としてΔθ<0およびΔθ>0の条件に位
相差Δθの変化率(微分値)を加えて、制御量が大きく
かつ安定するように構成すればよい。図6にこのように
構成した位相差補正回路の状態遷移条件を示す。遷移条
件を次のようにすればよい。
モード1→モード2:Δθ>0
モード2→モード1:Δθ<0
モード1→モード3:Δθ<−LMT
モード3→モード1:−LMT<Δθ<0かつdΔθ/
dt>0
モード2→モード4:Δθ>+LMT
モード4→モード2:0<Δθ<+LMTかつdΔθ/
dt<0In the above description, in the phase difference correction circuit 8, the transition from the mode 1 to the mode 3 and the transition from the mode 2 to the mode 4 are based only on the condition of Δθ <0 and Δθ> 0. In order to converge Δθ faster, the change rate (differential value) of the phase difference Δθ may be added to the condition of Δθ <0 and Δθ> 0 as a transition condition so that the control amount is large and stable. FIG. 6 shows the state transition conditions of the phase difference correction circuit configured as described above. The transition condition may be set as follows. Mode 1 → Mode 2: Δθ> 0 Mode 2 → Mode 1: Δθ <0 Mode 1 → Mode 3: Δθ <−LMT Mode 3 → Mode 1: −LMT <Δθ <0 and dΔθ /
dt> 0 Mode 2 → Mode 4: Δθ> + LMT Mode 4 → Mode 2: 0 <Δθ <+ LMT and dΔθ /
dt <0
【0025】実施形態2.この発明の第1の実施形態に
あっては、VCO1の出力に同期したd−q回転座標変
換を用いる場合について説明したが、非同期のd−q回
転座標上で位相差検出を行うようにした同期制御回路の
ブロック図を図9に示す。図において10は3相電力変
換装置であり、VCO1の出力信号に応じた周波数の3
相信号R0 、S0 、T0 を生成する。11は周波数の一
定な基準周波数発振器で、この出力パルスをカウンタ2
で計数してd−q座標変換回路4a、4bの基準位相を
生成する。d−q座標変換回路4aおよび4bは、それ
ぞれ3相信号R、S、Tおよび3相電力変換装置10の
出力R0 、S0 、T0 をd−q回転座標変換し、Vd 、
Vq およびV0d、V0qを生成する。このVd 、Vq およ
びV0d、V0qをLPF5aおよび5bを介して位相差検
出回路6aへ入力し、位相差検出回路6aが次式に基づ
いて位相差Δθを生成する。これにより、非同期のd−
q回転座標を用いた場合でも周波数引き込み範囲が広い
同期制御回路を構成できる。
Δθ=sin-1((V0dVq−V0qVd)
/(√(Vd 2+Vq 2)・√(V0d 2+V0q 2)) (15)
なお、式15の演算で、逆正弦函数の引数が小さい場合
はΔθが引数に等しいとおいてもよい。Embodiment 2. In the first embodiment of the present invention, the case of using the dq rotational coordinate conversion synchronized with the output of the VCO 1 has been described, but the phase difference detection is performed on the asynchronous dq rotational coordinate. A block diagram of the synchronization control circuit is shown in FIG. In the figure, 10 is a three-phase power converter, which has a frequency of 3 depending on the output signal of the VCO 1.
Generate phase signals R 0 , S 0 , T 0 . Reference numeral 11 is a reference frequency oscillator having a constant frequency.
To generate reference phases for the dq coordinate conversion circuits 4a and 4b. d-q coordinate converter 4a and 4b, three-phase signals R, respectively, S, the output R 0, S 0, T 0 T and three-phase power converting apparatus 10 converts d-q rotational coordinate, V d,
V q and V 0d, generates a V 0q. The V d, V q and V 0d, input to the phase difference detection circuit 6a through LPF5a and 5b the V 0q, the phase difference detection circuit 6a generates a phase difference Δθ based on the following equation. This allows asynchronous d-
A synchronization control circuit having a wide frequency pull-in range can be configured even when q rotational coordinates are used. Δθ = sin -1 ((V 0d V q -V 0q V d) / (√ (V d 2 + V q 2) · √ (V 0d 2 + V 0q 2)) (15) In the calculation of the formula 15, When the argument of the inverse sine function is small, Δθ may be set equal to the argument.
【0026】以上の説明では、逆正弦函数を用いて位相
差Δθを求めるものとしたが、図10に示すように原点
から(V0d、V0q)の方向にX軸、これと直交する方向
にY軸をとり、Vx 、Vy を次式で示すように定義し、
Vx 、Vy をVd 、Vq のかわりに用いることによって
第1の実施形態において説明した位相差検出回路によっ
て位相差Δθの演算を高速に実行できる。
Vx=VdV0d/√(V0d 2+V0q 2)
+VqV0q/√(V0d 2+V0q 2) (16)
Vy=−VdV0q/√(V0d 2+V0q 2)
+VqV0d/√(V0d 2+V0q 2) (17)[0026] In the above description, it is assumed to determine the phase difference Δθ using arc sine function, X-axis direction from the origin as shown in FIG. 10 (V 0d, V 0q) , a direction perpendicular thereto Take the Y-axis to define V x and V y as shown in the following equation,
By using V x and V y instead of V d and V q , the phase difference Δθ can be calculated at high speed by the phase difference detection circuit described in the first embodiment. V x = V d V 0d / √ (V 0d 2 + V 0q 2) + V q V 0q / √ (V 0d 2 + V 0q 2) (16) V y = -V d V 0q / √ (V 0d 2 + V 0q 2) + V q V 0d / √ (V 0d 2 + V 0q 2) (17)
【0027】[0027]
【発明の効果】請求項1の発明によれば、3相交流電源
の電圧位相に基づいて3相電力変換装置の制御基準位相
を生成する位相同期制御装置において、3相交流電源の
電圧を3相電力変換装置の出力電圧位相に同期したd−
q回転座標上の直流成分に変換し、このd−q回転座標
上で3相交流電源の電圧位相と3相電力変換装置の出力
電圧位相の位相差を生成するとともに、この位相差を所
定の値に制限した補正位相差を生成する位相差補正回路
とループフィルタを介して可変周波数発振器に入力し制
御基準位相を生成するようにしたので、位相同期制御装
置の周波数を3相交流電源の電圧の周波数に確実に引き
込むことができ、安定した同期制御を実現できる。According to the first aspect of the invention, in the phase synchronization control device for generating the control reference phase of the three-phase power converter based on the voltage phase of the three-phase AC power supply, the voltage of the three-phase AC power supply is set to three. D- synchronized with the output voltage phase of the phase power converter
The phase difference between the voltage phase of the three-phase AC power supply and the output voltage phase of the three-phase power converter is generated on the d-q rotation coordinates, and this phase difference is converted to a predetermined value. Since the control reference phase is generated by inputting it to the variable frequency oscillator through the phase difference correction circuit that generates the corrected phase difference limited to the value and the loop filter, the frequency of the phase synchronization controller is set to the voltage of the three-phase AC power supply. The frequency can be surely pulled in, and stable synchronization control can be realized.
【0028】請求項2の発明によれば、3相交流電源の
電圧位相に基づいて3相電力変換装置の制御基準位相を
生成する位相同期制御装置において、3相交流電源の電
圧と3相電力変換装置の出力電圧を定周波数発振器の出
力に同期したd−q回転座標上の直流成分に変換し、d
−q回転座標上で3相交流電源の電圧と3相電力変換装
置の出力電圧の位相差を生成し、この位相差を所定の値
に制限した補正位相差を生成する位相差補正回路とルー
プフィルタを介して可変周波数発振器に入力し制御基準
位相を生成するようにしたので、位相同期制御装置の周
波数を3相交流電源の電圧の周波数に確実に引き込むこ
とができ、安定した同期制御を実現できる。According to the second aspect of the present invention, in the phase synchronization control device for generating the control reference phase of the three-phase power converter based on the voltage phase of the three-phase AC power supply, the voltage of the three-phase AC power supply and the three-phase power supply. The output voltage of the converter is converted into a direct current component on dq rotation coordinates synchronized with the output of the constant frequency oscillator, and d
A phase difference correction circuit and a loop that generate a phase difference between the voltage of the three-phase AC power supply and the output voltage of the three-phase power converter on the −q rotation coordinate and limit the phase difference to a predetermined value to generate a corrected phase difference. Since the control reference phase is generated by inputting it to the variable frequency oscillator through the filter, the frequency of the phase synchronization control device can be reliably pulled into the frequency of the voltage of the three-phase AC power supply, and stable synchronization control is realized. it can.
【0029】請求項3の発明によれば、位相差の生成に
三角函数の近似多項式を用いたので、位相差の演算には
逆三角関数の演算や関数テーブルの装備を必要とせず、
かつ高速に演算できる。According to the invention of claim 3, since the approximation polynomial of the trigonometric function is used for the generation of the phase difference, the calculation of the phase difference does not require the calculation of the inverse trigonometric function or the equipping of the function table.
And it can be calculated at high speed.
【0030】請求項4の発明によれば、位相差補正回路
において前記位相差とその変化量の履歴に基づいて補正
値を生成するようにしたので、制御量が大きくかつ安定
するので、位相同期制御装置の周波数を3相交流電源の
電圧の周波数に確実にかつすばやく引き込むことができ
る。According to the fourth aspect of the present invention, since the correction value is generated in the phase difference correction circuit based on the history of the phase difference and its change amount, the control amount is large and stable. The frequency of the control device can be reliably and quickly drawn into the frequency of the voltage of the three-phase AC power supply.
【0031】請求項5の発明によれば、位相差あるいは
補正位相差に対して前記3相交流電源の1周期間におけ
る移動平均値を生成する移動平均回路を備えたので、3
相交流電源に不平衡があっても位相同期制御装置の周波
数を3相交流電源の電圧の周波数に確実に引き込むこと
ができ、安定した同期制御を実現できる。According to the invention of claim 5, since the moving average circuit is provided for generating the moving average value for one cycle of the three-phase AC power source with respect to the phase difference or the corrected phase difference, 3
Even if the phase AC power supply is unbalanced, the frequency of the phase synchronization control device can be reliably pulled into the frequency of the voltage of the three-phase AC power supply, and stable synchronization control can be realized.
【図1】 この発明の第1の実施形態を示す同期制御装
置のブロック図である。FIG. 1 is a block diagram of a synchronization control device showing a first embodiment of the present invention.
【図2】 図1の位相差検出回路6における特性図であ
る。FIG. 2 is a characteristic diagram of the phase difference detection circuit 6 of FIG.
【図3】 図1の位相差補正回路8における状態遷移図
である。FIG. 3 is a state transition diagram in the phase difference correction circuit 8 of FIG.
【図4】 この発明による同期制御装置の位相差検出回
路の変形例での特性図である。FIG. 4 is a characteristic diagram of a modified example of the phase difference detection circuit of the synchronization control device according to the present invention.
【図5】 この発明による同期制御装置の位相差検出回
路の他の変形例での特性図である。FIG. 5 is a characteristic diagram of another modification of the phase difference detection circuit of the synchronization control device according to the present invention.
【図6】 この発明による同期制御装置の位相差補正回
路の変形例での状態遷移図である。FIG. 6 is a state transition diagram in a modified example of the phase difference correction circuit of the synchronization control device according to the present invention.
【図7】 この発明による同期制御装置の変形例におけ
るブロック図である。FIG. 7 is a block diagram of a modification of the synchronization control device according to the present invention.
【図8】 この発明による同期制御装置の他の変形例に
おけるブロック図である。FIG. 8 is a block diagram showing another modification of the synchronization control device according to the present invention.
【図9】 この発明の第2の実施形態を示す同期制御装
置のブロック図である。FIG. 9 is a block diagram of a synchronization control device showing a second embodiment of the present invention.
【図10】 図9の位相差検出回路6aにおける動作を
説明するための電圧ベクトル図である。FIG. 10 is a voltage vector diagram for explaining the operation of the phase difference detection circuit 6a in FIG.
【図11】 従来の同期制御装置におけるブロック図で
ある。FIG. 11 is a block diagram of a conventional synchronization control device.
1 可変周波数発振器(VCO) 2 カウンタ
3 3相正弦波発生回路 4 d−q座標変
換回路
5 低域通過フィルタ(LPF) 6 位相差検出回
路
7 移動平均回路 8 位相差補正回
路
9 ループフィルタ 10 3相電力変換
装置
11 基準周波数発振器1 Variable Frequency Oscillator (VCO) 2 Counter 3 3 Phase Sine Wave Generation Circuit 4 dq Coordinate Conversion Circuit 5 Low Pass Filter (LPF) 6 Phase Difference Detection Circuit 7 Moving Average Circuit 8 Phase Difference Correction Circuit 9 Loop Filter 10 3 Phase power converter 11 Reference frequency oscillator
Claims (5)
電力変換装置の制御基準位相を生成する位相同期制御装
置において、 前記3相交流電源の電圧を前記3相電力変換装置の出力
電圧位相に同期したd−q回転座標上の直流成分に変換
し、このd−q回転座標上で前記3相交流電源の電圧位
相と前記3相電力変換装置の出力電圧位相の位相差を生
成するとともに、この位相差を所定の値に制限した補正
位相差を生成する位相差補正回路とループフィルタを介
して可変周波数発振器に入力し前記制御基準位相を生成
することを特徴とする位相同期制御装置。1. A phase synchronization control device for generating a control reference phase of a three-phase power converter based on a voltage phase of a three-phase AC power supply, wherein the voltage of the three-phase AC power supply is an output voltage of the three-phase power converter. It is converted into a DC component on the dq rotation coordinates synchronized with the phase, and a phase difference between the voltage phase of the three-phase AC power supply and the output voltage phase of the three-phase power converter is generated on the dq rotation coordinates. At the same time, the phase synchronization control device is characterized in that the control reference phase is generated by inputting it to a variable frequency oscillator via a phase difference correction circuit for generating a corrected phase difference in which the phase difference is limited to a predetermined value and a loop filter. .
電力変換装置の制御基準位相を生成する位相同期制御装
置において、 前記3相交流電源の電圧と前記3相電力変換装置の出力
電圧を定周波数発振器の出力に同期したd−q回転座標
上の直流成分に変換し、前記d−q回転座標上で前記3
相交流電源の電圧と前記3相電力変換装置の出力電圧の
位相差を生成し、この位相差を所定の値に制限した補正
位相差を生成する位相差補正回路とループフィルタを介
して可変周波数発振器に入力し前記制御基準位相を生成
することを特徴とする位相同期制御装置。2. A phase synchronization control device for generating a control reference phase of a three-phase power converter based on a voltage phase of a three-phase AC power supply, the voltage of the three-phase AC power supply and an output voltage of the three-phase power converter. Is converted into a DC component on the dq rotation coordinate synchronized with the output of the constant frequency oscillator, and the 3 component is converted on the dq rotation coordinate.
A variable frequency is generated via a phase difference correction circuit and a loop filter that generate a phase difference between the voltage of the three-phase AC power supply and the output voltage of the three-phase power converter, and generate a corrected phase difference by limiting the phase difference to a predetermined value. A phase synchronization control device, characterized in that it is input to an oscillator to generate the control reference phase.
式を用いたことを特徴とする請求項1または請求項2の
いずれかに記載の位相同期制御装置。3. The phase synchronization control device according to claim 1, wherein an approximation polynomial of trigonometric function is used for generating the phase difference.
とその変化量の履歴に基づいて補正値を生成するように
したことを特徴とする請求項1または請求項2のいずれ
かに記載の位相同期制御装置。4. The phase according to claim 1, wherein the phase difference correction circuit is configured to generate a correction value based on a history of the phase difference and its change amount. Synchronous control device.
前記3相交流電源の1周期間における移動平均値を生成
する移動平均回路を備えたことを特徴とする請求項1ま
たは請求項2のいずれかに記載の位相同期制御装置。5. A moving average circuit for generating a moving average value for one cycle of the three-phase AC power source with respect to the phase difference or the corrected phase difference, according to claim 1 or 2. The phase synchronization control device according to any one.
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JP32956296A JP3374685B2 (en) | 1996-12-10 | 1996-12-10 | Phase synchronization controller |
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JP32956296A JP3374685B2 (en) | 1996-12-10 | 1996-12-10 | Phase synchronization controller |
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JP3374685B2 true JP3374685B2 (en) | 2003-02-10 |
Family
ID=18222751
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