JP3363065B2 - Method of manufacturing chip supporting substrate for semiconductor package and semiconductor device - Google Patents
Method of manufacturing chip supporting substrate for semiconductor package and semiconductor deviceInfo
- Publication number
- JP3363065B2 JP3363065B2 JP12697897A JP12697897A JP3363065B2 JP 3363065 B2 JP3363065 B2 JP 3363065B2 JP 12697897 A JP12697897 A JP 12697897A JP 12697897 A JP12697897 A JP 12697897A JP 3363065 B2 JP3363065 B2 JP 3363065B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor package
- support substrate
- semiconductor
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケージ
用チップ支持基板の製造法及び半導体装置に関する。The present invention relates to relates to the production method and a semiconductor device of a semiconductor package chip supporting substrate.
【０００２】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
が代表的である。これを多端子化する場合は、端子ピッ
チを縮小することが必要であるが、０．５ｍｍピッチ以
下の領域では、配線板との接続に高度な技術が必要にな
る。後者のアレイタイプは比較的大きなピッチで端子配
列が可能なため、多ピン化に適している。従来、アレイ
タイプは接続ピンを有するＰＧＡ（ＰｉｎＧｒｉｄ Ａ
ｒｒａｙ）が一般的であるが、配線板との接続は挿入型
となり、表面実装には適していない。このため、表面実
装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と称
するパッケージが開発されている。2. Description of the Related Art The number of input / output terminals has increased as the degree of integration of semiconductors has improved. Therefore, a semiconductor package having a large number of input / output terminals has been required. Generally, I / O terminals are arranged in a row around the package,
There is a type that arranges not only the periphery but also the interior in multiple rows.
The former is QFP (Quad Flat Package)
Is typical. When the number of terminals is increased, it is necessary to reduce the terminal pitch, but in the area of 0.5 mm pitch or less, a high level technique is required for connection with the wiring board. The latter array type is suitable for increasing the number of pins because the terminals can be arranged at a relatively large pitch. Conventionally, the array type is a PGA (Pin Grid A) having a connection pin.
However, the connection with the wiring board is an insertion type and is not suitable for surface mounting. Therefore, a surface mountable package called BGA (Ball Grid Array) has been developed.
【０００３】一方、電子機器の小型化に伴って、パッケ
ージサイズの更なる小型化の要求が強くなってきた。こ
の小型化に対応するものとして、半導体チップとほぼ同
等サイズの、いわゆるチップサイズパッケージ（ＣＳ
Ｐ； Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案され
ている。これは、半導体チップの周辺部でなく、実装領
域内に外部配線基板との接続部を有するパッケージであ
る。具体例としては、バンプ付きポリイミドフィルムを
半導体チップの表面に接着し、チップと金リード線によ
り電気的接続を図った後、エポキシ樹脂などをポッティ
ングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩＡ
ＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．１４
０，ｐ１８−１９）や、仮基板上に半導体チップ及び外
部配線基板との接続部に相当する位置に金属バンプを形
成し、半導体チップをフェースダウンボンディング後、
仮基板上でトランスファーモールドしたもの（Ｓｍａｌ
ｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃｋａｇ
ｅ ＣＳＰ； ＴｈｅＳｅｃｏｎｄ ＶＬＳＩ Ｐａｃｋａ
ｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐａｎ，ｐ４６
−５０，１９９４）などがある。On the other hand, with the miniaturization of electronic equipment, there is an increasing demand for further miniaturization of the package size. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) has been proposed. This is a package having a connection portion with an external wiring board in the mounting area, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, an electrical connection is made between the chip and a gold lead wire, and then epoxy resin is potted and sealed (NIKKEI MATERIA).
LS & TECHNOLOGY 94.4, No. 14
0, p18-19), or a metal bump is formed on the temporary substrate at a position corresponding to the connection portion with the semiconductor chip and the external wiring board, and after the semiconductor chip is face-down bonded,
Transfer-molded on a temporary substrate (Smal
Lest Flip-Chip-Like Packag
e CSP; TheSecond VLSI Pack
ging Workshop of Japan, p46
-50, 1994).
【０００４】[0004]
【発明が解決しようとする課題】従来より製造されてい
るＣＳＰの場合、支持基板の穴加工は一般的にドリル加
工、パンチング加工およびレーザ加工など機械的に行う
のが一般的であった。このため、機械的な穴加工工程お
よび穴加工後の材料の貼り合せ工程が必要となり余分な
費用が発生していた。一方、支持基板を化学的に穴加工
する方法として穴加工しようとする支持基板表面に配線
回路と異なる銅はくを積層または圧着し、この銅箔に穴
を施した後支持基板を化学的に処理する方法があるが、
あらかじめ銅箔に穴を施す工程が必要であった。このよ
うに各種提案されているＣＳＰのなかでポリイミドフィ
ルム基板を用いたＣＳＰは信頼性とコストを両立できる
ものとして期待されている。しかしながら、ポリイミド
フィルム基板に外部接続用はんだボール搭載穴を穴明け
する工程は、穴数が多いために問題がある。パンチング
では金型が高価であり寿命が短い。また、ドリルやレー
ザでは加工時間が長くなる。したがって、低コスト化可
能な生産性のよい穴明けが重要な課題である。本発明は
低価格の小型半導体パッケージ用チップ支持基板および
これを用いたパッケージを提供するものである。In the case of the conventionally manufactured CSP, the supporting substrate is generally drilled mechanically by drilling, punching, laser machining or the like. For this reason, a mechanical hole drilling process and a material laminating process after the hole drilling are required, resulting in extra cost. On the other hand, as a method of chemically drilling a supporting substrate, a copper foil different from the wiring circuit is laminated or pressure-bonded on the surface of the supporting substrate to be drilled, and after the copper foil is drilled, the supporting substrate is chemically removed. There is a way to handle it,
A step of previously making holes in the copper foil was necessary. As described above, among the various types of CSPs that have been proposed, CSPs using a polyimide film substrate are expected to have both reliability and cost. However, the process of forming the solder ball mounting holes for external connection on the polyimide film substrate is problematic because of the large number of holes. In punching, the die is expensive and has a short life. In addition, a drill or a laser increases processing time. Therefore, it is an important issue to make holes with good productivity that can reduce costs. The present invention provides a package using a chip support substrate and this for the small-sized semiconductor package of lower prices.
【０００５】[0005]
【課題を解決するための手段】本発明は金属箔にポリイ
ミド層と感光性樹脂層をこの順に形成する工程Ａ、感光
性樹脂層を露光・現像してアウター接続部が設けられる
箇所に開口部を有するエッチングレジストを形成する工
程Ｂ、前記エッチングレジスト開口部のポリイミド層を
エタノール、純水、エチレンジアミン及び水酸化カリウ
ムを含む有機アルカリ系エッチング液を用いてエッチン
グする工程Ｃ、金属箔をエッチングし絶縁性支持基板の
一表面に半導体チップ電極と接続するインナー接続部及
び外部接続端子と導通するアウター接続部を有する配線
を形成する工程Ｄを備えることを特徴とする半導体パッ
ケージ用チップ支持基板の製造法に関する。The present invention SUMMARY OF] The polyimide layer on the metal foil of the photosensitive resin layer step A are formed in this order, a photosensitive resin layer at a position outer connecting portion is exposed and developed is Ru are found provided Step B of forming an etching resist having an opening, Step C of etching the polyimide layer of the etching resist opening with an organic alkaline etching solution containing ethanol, pure water, ethylenediamine and potassium hydroxide, etching the metal foil And a step D of forming wiring having an inner connecting portion connected to the semiconductor chip electrode and an outer connecting portion electrically connected to the external connecting terminal on one surface of the insulating supporting substrate. Regarding manufacturing method.
【０００６】本発明の半導体パッケージ用チップ支持基
板の製造法は、具体的には、工程Ａ→工程Ｂ→工程Ｃ→
工程Ｄを順に行う工程、工程Ａ→工程Ｄ→工程Ｂ→工程
Ｃを順に行う工程、工程Ａ→工程Ｂ→工程Ｄ→工程Ｃを
順に行う工程のいずれかを含む前記半導体パッケージ用
チップ支持基板の製造法に関する。The method of manufacturing a semiconductor package chip supporting substrate of the present invention is specifically, step A → step B → step C →
For the semiconductor package , including any one of a step of performing step D , a step of A, a step of D, a step of B, a step of C, and a step of A, a step of B, a step of D, and a step of C.
The present invention relates to a method for manufacturing a chip support substrate .
【０００７】本発明においては、金属箔にポリイミド層
と感光性樹脂層を備えるフィルムを圧着したり、ポリイ
ミド層に金属箔を蒸着とめっきでメタライズして形成
し、反対面に感光性樹脂層を形成したりすることが好ま
しい。 In the present invention, a polyimide layer is formed on the metal foil.
And a film equipped with a photosensitive resin layer
Formed by metalizing metal foil on the mid layer by vapor deposition and plating
However, it is preferable to form a photosensitive resin layer on the opposite side.
Good
【０００８】また本発明の半導パッケージ用チップ支持
基板の製造法は、絶縁性支持基板の一表面に複数組の配
線を形成し、前記配線は更に半導体チップ搭載領域部を
有するようにすることが好ましい。 A chip support for a semiconductor package according to the present invention
The method of manufacturing the substrate is to arrange multiple sets on one surface of the insulating support substrate.
A wire is formed, and the wiring further defines a semiconductor chip mounting area.
It is preferable to have it.
【０００９】以上のように本発明は、半導体パッケージ
用チップ支持基板において、支持基板の穴を焼付・現像
・樹脂エッチング等化学的に形成しドリル等機械的な方
法で行わないことを特徴とし、従来技術の問題点を解決
しようとするものである。[0009] As described above, the present invention provides a semiconductor package chip support substrate, characterized in that it does not take place in the holes in the supporting substrate is formed such chemically baking, developing, resin etching drill mechanical method Therefore, the problem of the conventional technology is to be solved.
【００１０】[0010]
【発明の実施の形態】本発明の半導体パッケージ用チッ
プ支持基板は、所定の厚さの金属箔に感光性樹脂層とポ
リイミド層の２層構造を持つフィルムを圧着し、感光性
樹脂層に必要な穴加工を施しこれをエッチングレジスト
としてポリイミド層に穴を形成した後、ポリイミド層を
そのまま保持基板とする半導体パッケージ用チップ支持
基板である。また金属箔に必要な導体回路を形成した
後、感光性樹脂層に必要な穴加工を施しこれをエッチン
グレジストとしてポリイミド層に穴を形成した後、ポリ
イミド層をそのまま支持基板とすることも出来る。 The semiconductor package chip support substrate of the embodiment of the present invention is a photosensitive resin layer and a port on a metal foil having a predetermined thickness
A film having a two-layer structure of a Liimide layer is pressure-bonded to make it photosensitive .
After this subjecting the drilling necessary to the resin layer to form a hole in a polyimide layer as an etching resist, a semiconductor package chip supporting substrate to directly hold a substrate a polyimide layer. Also after forming the conductor circuits necessary for the metal foil, after it performs the drilling necessary to the photosensitive resin layer to form a hole in a polyimide layer as an etching resist, poly
The imide layer can be used as it is as a supporting substrate .
【００１１】絶縁性支持基板としてのポリイミド層は、
カプトン（東レデュポン（株）製商品名）、アピカル
（鐘淵化学（株）製商品名）、ユーピレックス（宇部興
産（株）製商品名）、エスパネックス（新日鉄化学
（株）製商品名）、カバーレイフィルムＳＦＰ（新日鉄
化学（株）製商品名））等が使用できる。絶縁性支持基
板の一表面に複数組の配線を形成するには、銅箔をエッ
チングする方法、所定の箇所に銅めっきをする方法、そ
れらを併用する方法等が使用できる。絶縁性支持基板に
外部接続部、貫通穴などの開口を設けるにはエッチング
法を用いる。エッチング液としては、有機アルカリ系エ
ッチング液を用いる。インナー接続部と導通するアウタ
ー接続部は、絶縁性支持基板開口部にハンダボール、め
っき等によりバンプ等を形成することにより作成するこ
とができる。これは外部の基板等に接続される。[0011] polyimide layer as an insulating support substrate,
Kapton (trade name of Toray DuPont Co., Ltd.), Apical (trade name of Kanefuchi Chemical Co., Ltd.), Upilex (trade name of Ube Industries Ltd.), Espanex (trade name of Nippon Steel Chemical Co., Ltd.), Coverlay film SFP (trade name, manufactured by Nippon Steel Chemical Co., Ltd.) and the like can be used. The form a plurality sets of wiring on one surface of the insulating support substrate, a method of etching a copper foil, a method of copper plating to a predetermined position, a method in which a combination of them can be used. An etching method is used to provide openings such as external connection portions and through holes in the insulating support substrate. The etchant, organic alkaline et
Use a etching solution . Outer is conducting with inner over connecting portion
The connection portion can be formed by forming bumps or the like on the insulating support substrate opening by solder balls, plating, or the like. This is connected to an external board or the like.
【００１２】本発明の半導体パッケージ用チップ支持基
板を使用して半導体装置を製造するには、本発明の半導
体パッケージ用チップ支持基板のチップ搭載域に液状ま
たはフィルム状接着剤を用いて半導体チップを接着し、
半導体チップ電極を支持基板のインナー接続部とワイヤ
ーボンディング等により接続する。さらに半導体チップ
の少なくとも半導体チップ電極面を樹脂封止し、アウタ
ー接続部にはんだボールを搭載することにより半導体装
置を製造することが出来る。[0012] Using the semiconductor package chip supporting substrate of the present invention in manufacturing a semiconductor device, using a liquid or film adhesive on the chip mounting area of the semiconductor package chip supporting substrate of the present invention Glue the semiconductor chip,
The semiconductor chip electrodes are connected by inner over connecting portion and the wire bonding or the like of the supporting substrate. Further, at least the semiconductor chip electrode surface of the semiconductor chip is resin-sealed, and solder balls are mounted on the outer connecting portions, whereby a semiconductor device can be manufactured.
【００１３】１８μｍ厚銅はくに２５μｍの絶縁層と感
光層を有する新日鉄化学社製フォトカバーレイフィルム
（ＳＦＰ）をラミネータで圧着し、感光層を焼付し現像
で穴加工を施しこれをエッチングレジストとしてポリイ
ミド層をエッチングして穴を形成した後、この絶縁層を
そのまま支持基板として銅はくに回路を形成しＣＳＰ
（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）基板を製造する
ことができる。又１８μｍ厚銅はくに日立化成工業株式
会社製感光性ポリアミドイミド ソルダレジストを２５
μｍの厚みで塗布し、半硬化させた後パターンを基板に
直接焼付し現像で基板に穴を形成し、ポリアミドイミド
ソルダレジストをそのまま支持基板として銅はくに回
路を形成しＣＳＰ基板を製造することができる。Photocoverlay film (SFP) manufactured by Nippon Steel Chemical Co., Ltd. having an insulating layer and a photosensitive layer of 25 μm thick on 18 μm thick copper foil is pressure-bonded with a laminator, the photosensitive layer is baked and holes are formed by development, and this is used as an etching resist. After the polyimide layer is etched to form holes, the insulating layer is used as it is as a supporting substrate to form a circuit on a copper foil to form a CSP.
A (Chip Size Package) substrate can be manufactured. The 18μm thick copper is country Hitachi Kasei Kogyo stock
The company manufactured photosensitive polyamide-imide solder resist 25
Applying to a thickness of μm, semi-curing, baking the pattern directly on the substrate and forming holes in the substrate by development, using polyamide-imide solder resist as a supporting substrate as it is to form a circuit on copper foil to manufacture a CSP substrate You can
【００１４】[0014]
【実施例】実施例
図１により説明する。厚さ５０μｍのカプトン（東レデ
ュポン）４１に１８μｍの銅を蒸着とめっきでメタライ
ズ４２した基板（東洋メタライズ）を用い（図１ａ）、
インナー接続部及び展開配線４３を通常のエッチング法
で形成する（図１ｂ）。次に、配線反対面にドライフィ
ルムレジストを貼り、アウター接続用開口穴部分をネガ
型マスクを用いて露光、現像する。ついで、エッチング
液（エタノール６５重量部、純水２０重量部、エチレン
ジアミン１０重量部、水酸化カリウム５重量部）中で７
０℃で５分間、開口部に垂直に液を吹付け穴明け加工
（アウター接続用開口部４）を行った後、洗浄し（図１
ｃ）、レジストを剥離する（図１ｄ）。さらに、露出し
ている配線に無電解ニッケルめっき（膜厚：５μｍ）、
無電解金めっき（膜厚：０．８μｍ）を順次施す（不図
示）。ここでは、無電解めっきを使用したが、電解めっ
きを用いてもよい。次に打ち抜き金型を用いてフレーム
状に打ち抜き、複数組のインナー接続部、展開配線、ア
ウター接続部を形成した支持基板を準備する。次にパッ
ケージ組み立てを行う。まず、支持基板の半導体チップ
搭載領域に、ダイボンドフィルム４５（日立化成工業株
式会社製、商品名：ＤＦ−３３５、厚み０．０１５ｍ
ｍ）を接着する。接着の条件は、例えば温度１６０℃、
時間５秒、圧力３ｋｇｆ／ｃｍ2である。次に、半導体
チップ４６を支持基板の所定の位置に接着する。接着条
件は、例えば温度２２０℃、時間５秒、圧力３００ｇｆ
／ｃｍ2である。さらに、半導体チップ電極とインナー
接続部を、金ワイヤ４７をボンディングして電気的に接
続する（図１ｅ）。このようにして形成したものをトラ
ンスファモールド金型に装填し、半導体封止用エポキシ
樹脂４８（日立化成工業（株）製、商品名：ＣＬ−７７
００）を用いて各々封止する（図１ｆ）。その後、アウ
ター接続部にはんだボール４９を配置し溶融させ、パン
チにより個々のパッケージに分離し半導体装置が得られ
る（図１ｇ）。EXAMPLES be illustrated by the examples Figure 1. Thickness 50μm Kapton (Toray) 41 to using a substrate metallized 42 18μm of copper plating and vapor deposition (Toyo metallization) (Figure 1 a),
An inner connecting portion and the expansion wire 43 is formed in a conventional etching method (Fig. 1 b). Next, a dry film resist is attached to the surface opposite to the wiring, and the outer connection opening hole portion is exposed and developed using a negative mask. Then, in an etching solution (65 parts by weight of ethanol, 20 parts by weight of pure water, 10 parts by weight of ethylenediamine, 5 parts by weight of potassium hydroxide)
The liquid is sprayed perpendicularly to the opening at 0 ° C. for 5 minutes to make a hole (outer connection opening 4) and then washed (FIG. 1 ).
c), the removing the resist (FIG. 1 d). Furthermore, the exposed wiring is electroless nickel plated (film thickness: 5 μm),
Electroless gold plating (film thickness: 0.8 μm) is sequentially applied (not shown). Although electroless plating is used here, electrolytic plating may be used. Next, using a punching die, punching is performed in a frame shape to prepare a support substrate on which a plurality of sets of inner connecting portions, developed wirings, and outer connecting portions are formed. Next, the package is assembled. First, a die-bonding film 45 (manufactured by Hitachi Chemical Co., Ltd., product name: DF-335, thickness 0.015 m) is provided in the semiconductor chip mounting area of the support substrate.
Adhere m). The bonding conditions are, for example, a temperature of 160 ° C.,
The time is 5 seconds and the pressure is 3 kgf / cm 2 . Next, the semiconductor chip 46 is bonded to a predetermined position on the support substrate. The adhesion conditions are, for example, a temperature of 220 ° C., a time of 5 seconds, and a pressure of 300 gf.
/ Cm 2 . Further, the semiconductor chip electrode and the inner connection portion is electrically connected to the bonding gold wires 47 (FIG. 1 e). The thus-formed product is loaded into a transfer mold, and epoxy resin 48 for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-77).
00) to seal each (FIG. 1f). After that, the solder balls 49 are placed on the outer connecting portions and melted , and separated into individual packages by punching to obtain a semiconductor device (FIG. 1g).
【００１５】[0015]
【発明の効果】本発明では、支持基板の穴加工を特定な
エッチング液を用いて化学的に形成することにより、多
数の穴加工を同時に迅速に行い低価格で実現することが
出来た。又本発明により、多数の穴明け加工が必要な半
導体パッケージ用支持基板において、多数パッケージ分
の支持基板を一括で加工出来るため、安価に大量生産す
ることが出来る。本発明はＴＡＢ方式よりむしろパネル
方式の製造において有効である。According to the present invention, a large number of holes can be formed simultaneously at a low cost by forming holes in the supporting substrate chemically using a specific etching solution. Further, according to the present invention, in a supporting substrate for a semiconductor package which requires a large number of drilling processes, the supporting substrates for a large number of packages can be processed at one time, so that mass production can be performed at low cost. The present invention is effective in the panel type manufacturing rather than the TAB type manufacturing.
【図１】 本発明の実施例を説明するための半導体パッ
ケージ用支持基板の製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor package support substrate for explaining an embodiment of the present invention.
４１．ポリイミドフィルム ４２．銅箔 ４３．インナー接続部及び展開配線 ４４．アウター接続開口部 ４５．ダイボンドフィルム ４６．半導体チップ ４７．金ワイヤ ４８．半導体封止用エポキシ樹脂 ４９．はんだボール41. Polyimide film 42. Copper foil 43. Inner connection part and development wiring 44. Outer connection opening 45. Die bond film 46. Semiconductor chip 47. Gold wire 48. Epoxy resin for semiconductor encapsulation 49. Solder balls
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大畑 洋人 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (56)参考文献 特開 平７−235765（ＪＰ，Ａ) 特開 平７−249711（ＪＰ，Ａ) 特開 平８−307033（ＪＰ，Ａ) 特開 平９−17828（ＪＰ，Ａ) 国際公開95／26047（ＷＯ，Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroto Ohata 48 Wadai, Tsukuba, Ibaraki Prefecture, Hitachi Chemical Co., Ltd. Tsukuba Development Laboratory (56) Reference JP-A-7-235765 (JP, A) JP-A 7-249711 (JP, A) JP-A-8-307033 (JP, A) JP-A-9-17828 (JP, A) International Publication 95/26047 (WO, A1) (58) Fields investigated (Int.Cl) . 7 , DB name) H01L 23/12
Claims (6)
この順に形成する工程Ａ、感光性樹脂層を露光・現像し
てアウター接続部が設けられる箇所に開口部を有するエ
ッチングレジストを形成する工程Ｂ、前記エッチングレ
ジスト開口部のポリイミド層をエタノール、純水、エチ
レンジアミン及び水酸化カリウムを含む有機アルカリ系
エッチング液を用いてエッチングする工程Ｃ、金属箔を
エッチングし絶縁性支持基板の一表面に半導体チップ電
極と接続するインナー接続部及び外部接続端子と導通す
るアウター接続部を有する配線を形成する工程Ｄを備え
ることを特徴とする半導体パッケージ用チップ支持基板
の製造法。And 1. A metal foil to the polyimide layer step A of the photosensitive resin layer are formed in this order, an etching resist having the opening of the photosensitive resin layer at a position outer connecting portion is exposed and developed is Ru are found provided Step B of forming, Step C of etching the polyimide layer of the etching resist opening with an organic alkaline etching solution containing ethanol, pure water, ethylenediamine and potassium hydroxide, etching of the metal foil A method of manufacturing a chip support substrate for a semiconductor package, which comprises a step D of forming a wiring having an inner connecting portion connected to a semiconductor chip electrode and an outer connecting portion electrically connected to an external connecting terminal on a surface thereof.
域部を有するものである請求項１記載の半導体パッケー
ジ用チップ支持基板の製造法。2. The method for manufacturing a chip support substrate for a semiconductor package according to claim 1, wherein the wiring further has a semiconductor chip mounting area portion.
行う工程、工程Ａ→工程Ｄ→工程Ｂ→工程Ｃを順に行う
工程、及び工程Ａ→工程Ｂ→工程Ｄ→工程Ｃを順に行う
工程のいずれかを含む請求項１又は２記載の半導体パッ
ケージ用チップ支持基板の製造法。3. A process A, a process B, a process C, a process D, a process A, a process D, a process B, a process C, and a process A, a process B, a process D, and a process C. The method for manufacturing a chip support substrate for a semiconductor package according to claim 1 or 2, including any of the steps sequentially performed.
めっきでメタライズして形成し、反対面に感光性樹脂層
を形成する工程である請求項１〜３何れか記載の半導体
パッケージ用チップ支持基板の製造法。4. The semiconductor package chip according to claim 1, wherein the step A is a step of forming a metal foil on the polyimide layer by metalization by vapor deposition and plating, and forming a photosensitive resin layer on the opposite surface. Support substrate manufacturing method.
された半導パッケージ用チップ支持基板。5. A chip supporting substrate for a semiconductor package manufactured by the manufacturing method according to claim 1.
支持基板に半導体チップを搭載するとともに、絶縁性支
持基板の開口に外部接続端子を形成した半導体装置。6. A semiconductor device in which a semiconductor chip is mounted on the chip support substrate for a semiconductor package according to claim 5, and an external connection terminal is formed in an opening of the insulating support substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12697897A JP3363065B2 (en) | 1997-05-16 | 1997-05-16 | Method of manufacturing chip supporting substrate for semiconductor package and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12697897A JP3363065B2 (en) | 1997-05-16 | 1997-05-16 | Method of manufacturing chip supporting substrate for semiconductor package and semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002040773A Division JP2002270651A (en) | 2002-02-18 | 2002-02-18 | Chip-supporting substrate for semiconductor package, method for manufacturing the same and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10321751A JPH10321751A (en) | 1998-12-04 |
| JP3363065B2 true JP3363065B2 (en) | 2003-01-07 |
Family
ID=14948619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12697897A Expired - Fee Related JP3363065B2 (en) | 1997-05-16 | 1997-05-16 | Method of manufacturing chip supporting substrate for semiconductor package and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3363065B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3876953B2 (en) | 1998-03-27 | 2007-02-07 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| JP4984253B2 (en) * | 2007-12-25 | 2012-07-25 | 大日本印刷株式会社 | Manufacturing method of semiconductor device and manufacturing method of substrate for semiconductor device |
-
1997
- 1997-05-16 JP JP12697897A patent/JP3363065B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10321751A (en) | 1998-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6486549B1 (en) | Semiconductor module with encapsulant base | |
| JP4862848B2 (en) | Manufacturing method of semiconductor package | |
| US6908794B1 (en) | Method of making a semiconductor package device that includes a conductive trace with recessed and non-recessed portions | |
| KR100537972B1 (en) | Chip scale ball grid array for integrated circuit package | |
| US6544813B1 (en) | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment | |
| US6403460B1 (en) | Method of making a semiconductor chip assembly | |
| US6987034B1 (en) | Method of making a semiconductor package device that includes singulating and trimming a lead | |
| JP4029910B2 (en) | Manufacturing method of semiconductor package and semiconductor package | |
| JP3363065B2 (en) | Method of manufacturing chip supporting substrate for semiconductor package and semiconductor device | |
| US6551861B1 (en) | Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive | |
| JPH09107046A (en) | Semiconductor package | |
| JP3915226B2 (en) | Chip support substrate for semiconductor package and semiconductor package | |
| JPH08288316A (en) | Semiconductor device | |
| US20120225521A1 (en) | Board on chip package substrate and manufacturing method thereof | |
| JP4140555B2 (en) | Manufacturing method of semiconductor package | |
| JP3661822B2 (en) | Chip support substrate for semiconductor packaging | |
| JP3393026B2 (en) | Chip support substrate for semiconductor package | |
| JP3606275B2 (en) | Semiconductor package and manufacturing method thereof | |
| US8907468B2 (en) | Semiconductor device | |
| JP3445895B2 (en) | Chip support substrate for semiconductor package | |
| JP3402416B2 (en) | Manufacturing method of semiconductor package | |
| JP2002270651A (en) | Chip-supporting substrate for semiconductor package, method for manufacturing the same and semiconductor device | |
| JP4390908B2 (en) | Wiring member manufacturing method | |
| JP2005328057A (en) | Manufacturing method of semiconductor package, and the semiconductor package | |
| JP3685203B2 (en) | Semiconductor device mounting substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 5 Free format text: PAYMENT UNTIL: 20071025 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081025 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091025 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091025 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20101025 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111025 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20121025 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20131025 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131025 Year of fee payment: 11 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |