JP3361067B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3361067B2 JP3361067B2 JP36278898A JP36278898A JP3361067B2 JP 3361067 B2 JP3361067 B2 JP 3361067B2 JP 36278898 A JP36278898 A JP 36278898A JP 36278898 A JP36278898 A JP 36278898A JP 3361067 B2 JP3361067 B2 JP 3361067B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- gate
- gates
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＯＳ型トランジ
スタを有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a MOS transistor.
【０００２】[0002]
【従来の技術】従来よりＭＯＳ型トランジスタにおいて
は、ゲート電極及びソース・ドレイン拡散層の抵抗を低
減するために、セルファラインシリサイデーション技術
によりゲート電極及びソース・ドレイン拡散層上に珪化
金属化合物が形成されている。2. Description of the Related Art Conventionally, in a MOS transistor, in order to reduce the resistance of a gate electrode and a source / drain diffusion layer, a metal silicide compound is formed on the gate electrode and the source / drain diffusion layer by self-alignment silicidation technology. Has been formed.
【０００３】図６に示すように、Ｐ型のシリコン基板１
１は、例えばメモリセルが形成される領域Ａと、例えば
周辺回路が形成される領域Ｂとを有している。このシリ
コン基板１１の領域Ａ内には選択的にディープトレンチ
型のキャパシタ１２が形成される。このキャパシタ１２
はトレンチ１２ａの周辺にキャパシタ絶縁膜１３が形成
され、トレンチ１２ａの内部にストレージノード１２ｂ
を形成する、例えばポリシリコンが充填されている。ま
た、シリコン基板１１内には例えばシリコン酸化膜から
なるＳＴＩ（Shallow Trench Isolation）構造の素子分
離領域１４が形成される。As shown in FIG. 6, a P-type silicon substrate 1
1 has an area A in which, for example, a memory cell is formed and an area B in which, for example, a peripheral circuit is formed. Deep trench type capacitors 12 are selectively formed in the region A of the silicon substrate 11. This capacitor 12
A capacitor insulating film 13 is formed around the trench 12a, and the storage node 12b is formed inside the trench 12a.
Are filled with, for example, polysilicon. In addition, an element isolation region 14 having an STI (Shallow Trench Isolation) structure made of, for example, a silicon oxide film is formed in the silicon substrate 11.
【０００４】次に、シリコン基板１１上にゲート酸化膜
１５が形成され、このゲート酸化膜１５上にポリシリコ
ンからなるゲート１６ａ、１６ｂ、１６ｃ、１６ｄが選
択的に形成される。この際、領域Ａに形成されたゲート
の相互間隔をＳ３、領域Ｂに形成されたゲートの相互間
隔をＳ４とする。また、このゲート１６ａ、１６ｂ、１
６ｃ、１６ｄ表面にはシリコン酸化膜１７が形成され
る。Next, a gate oxide film 15 is formed on the silicon substrate 11, and gates 16a, 16b, 16c and 16d made of polysilicon are selectively formed on the gate oxide film 15. At this time, the mutual distance between the gates formed in the region A is S3, and the mutual distance between the gates formed in the region B is S4. Also, the gates 16a, 16b, 1
A silicon oxide film 17 is formed on the surfaces of 6c and 16d.
【０００５】次に、ゲート１６ａ、１６ｂ、１６ｃ、１
６ｄと自己整合的にイオン注入及び拡散が行われ、ソー
ス・ドレイン領域に低不純物濃度のＮ型拡散層１８ａ、
１８ｂが形成される。ここで、拡散層１８ｃはキャパシ
タ１２の電荷を読み出す領域であり、例えば、ストレー
ジノード１２ｂから不純物を外方拡散したり、別途不純
物をイオン注入して形成される。Next, the gates 16a, 16b, 16c, 1
Ion implantation and diffusion are performed in a self-aligned manner with 6d, and a low impurity concentration N-type diffusion layer 18a is formed in the source / drain regions.
18b is formed. Here, the diffusion layer 18c is a region for reading out the charge of the capacitor 12, and is formed, for example, by outwardly diffusing the impurity from the storage node 12b or by separately implanting the impurity.
【０００６】次に、図７に示すように、全面に厚さＴが
例えば０．０７μｍの例えばシリコン窒化膜のような絶
縁膜１９が形成される。Next, as shown in FIG. 7, an insulating film 19 such as a silicon nitride film having a thickness T of 0.07 μm is formed on the entire surface.
【０００７】更に、図８に示すように、異方性エッチン
グ技術により、ゲート１６ａ、１６ｂ、１６ｃ、１６ｄ
の各側壁部分に絶縁膜１９が残るように絶縁膜１９が選
択的に除去され、ゲート側壁絶縁膜１９ａが形成され
る。Further, as shown in FIG. 8, gates 16a, 16b, 16c and 16d are formed by an anisotropic etching technique.
The insulating film 19 is selectively removed so that the insulating film 19 remains on each side wall portion, and a gate side wall insulating film 19a is formed.
【０００８】次に、ゲート１６ａ、１６ｂ、１６ｃ、１
６ｄ及びゲート側壁絶縁膜１９ａと自己整合的にイオン
注入及び拡散が行われ、拡散層１８ａ、１８ｂの不純物
濃度よりも高不純物濃度のＮ型拡散層２０が形成され、
ＬＤＤ（Lightly DopedDrain）構造のＭＯＳ型トランジ
スタが形成される。Next, the gates 16a, 16b, 16c, 1
6d and the gate sidewall insulating film 19a are self-aligned with ion implantation and diffusion to form an N-type diffusion layer 20 having an impurity concentration higher than that of the diffusion layers 18a and 18b.
A MOS transistor having an LDD (Lightly Doped Drain) structure is formed.
【０００９】次に、ウエットエッチングにより拡散層２
０、及びゲート１６ａ、１６ｂ、１６ｃ、１６ｄ上のゲ
ート酸化膜１５が除去される。その後、全面に金属膜と
して例えばコバルト薄膜が形成される。次に、シリコン
と化学的反応が起こる温度までアニールすることによ
り、シリコンを含有するゲート１６ａ、１６ｂ、１６
ｃ、１６ｄ及びシリコン基板１１とコバルト薄膜とが接
している領域ではコバルトとシリコンが反応し、図９に
示すように、コバルトシリサイド膜２１ａ、２１ｂ、２
１ｃが形成される。この際、絶縁膜でシリコンが覆われ
ているゲート側壁絶縁膜１９ａ上にコバルトシリサイド
膜は形成されない。Next, the diffusion layer 2 is formed by wet etching.
0 and the gate oxide film 15 on the gates 16a, 16b, 16c and 16d is removed. After that, for example, a cobalt thin film is formed as a metal film on the entire surface. Then, the silicon-containing gates 16a, 16b, 16 are annealed to a temperature at which a chemical reaction with silicon occurs.
c and 16d and in the region where the silicon substrate 11 and the cobalt thin film are in contact with each other, cobalt reacts with silicon and, as shown in FIG. 9, cobalt silicide films 21a, 21b, 2
1c is formed. At this time, the cobalt silicide film is not formed on the gate sidewall insulating film 19a whose silicon is covered with the insulating film.
【００１０】この後、図９に示すように、エッチング技
術によりコバルトシリサイド膜２１ａ、２１ｂ、２１ｃ
以外の未反応のコバルト薄膜が選択的に除去される。こ
のように、領域Ａ及び領域Ｂにおいても拡散層領域上に
コバルトシリサイド膜２１ｂ、２１ｃが形成される。Thereafter, as shown in FIG. 9, the cobalt silicide films 21a, 21b and 21c are formed by an etching technique.
Other than the unreacted cobalt thin film is selectively removed. Thus, the cobalt silicide films 21b and 21c are formed on the diffusion layer regions in the regions A and B as well.
【００１１】[0011]
【発明が解決しようとする課題】ところで、拡散層領域
上にコバルトシリサイド膜２１ｂ、２１ｃのような珪化
金属化合物を形成することは、拡散層領域の導電領域の
抵抗値を低下させ、信号処理を高速化することを目的と
している。By forming a metal silicide compound such as cobalt silicide films 21b and 21c on the diffusion layer region, the resistance value of the conductive region of the diffusion layer region is lowered, and signal processing is performed. The purpose is to speed up.
【００１２】ところが、拡散層領域の上面に珪化金属化
合物を形成すると、ＰＮ接合のリーク電流が増加すると
いう問題点がある。そのため、キャパシタ１２の電荷が
読み出される拡散層１８ａ上に珪化金属化合物が形成さ
れると、キャパシタ１２の電荷保持特性が劣化する。従
って、拡散層１８ａ上には、コバルトシリサイド膜２１
ｃが形成されない方が望ましい。However, when a metal silicide compound is formed on the upper surface of the diffusion layer region, there is a problem that the leak current of the PN junction increases. Therefore, when the metal silicide compound is formed on the diffusion layer 18a from which the charge of the capacitor 12 is read, the charge retention characteristic of the capacitor 12 deteriorates. Therefore, the cobalt silicide film 21 is formed on the diffusion layer 18a.
It is desirable that c is not formed.
【００１３】つまり、領域Ａにおいてはキャパシタ１２
の電荷保持特性を向上させるためにリーク電流を抑える
ことが重要となり、また、領域Ｂにおいては抵抗を抑え
高速動作を可能とする必要がある。従って、このような
場合、領域Ａのリーク電流を抑えたい部分の拡散層領域
上にはコバルトシリサイド膜を形成しない方が望まし
い。That is, in the area A, the capacitor 12
It is important to suppress the leak current in order to improve the charge retention characteristics of the device, and it is necessary to suppress the resistance in the region B to enable high speed operation. Therefore, in such a case, it is desirable not to form the cobalt silicide film on the diffusion layer region in the portion where the leakage current in the region A is desired to be suppressed.
【００１４】しかし、上記従来の製造方法では、ゲート
の相互間隔Ｓ３、Ｓ４が（Ｓ３、Ｓ４）＞２×Ｔ（Ｔ：
シリコン窒化膜１９の膜厚）の箇所では、拡散層領域上
にコバルトシリサイド膜が形成される。従って、コバル
トシリサイド膜が形成されない領域をシリコン窒化膜１
９の膜厚Ｔと独立に拡散層上に設けることができなかっ
た。However, in the above conventional manufacturing method, the mutual distances S3 and S4 of the gates are (S3, S4)> 2 × T (T:
At the location (thickness of the silicon nitride film 19), a cobalt silicide film is formed on the diffusion layer region. Therefore, the region where the cobalt silicide film is not formed is formed on the silicon nitride film 1
It could not be provided on the diffusion layer independently of the film thickness T of 9.
【００１５】本発明は上記課題を解決するためになされ
たものであり、その目的とするところは、珪化金属化合
物の影響で発生するＰＮ接合リーク電流を抑えることが
でき、かつ信号処理の高速性を確保することができる半
導体装置の製造方法を提供することにある。The present invention has been made to solve the above problems, and an object of the present invention is to suppress a PN junction leak current generated due to the influence of a metal silicide compound and to achieve high-speed signal processing. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of ensuring the above.
【００１６】[0016]
【課題を解決するための手段】本発明は、前記目的を達
成するために以下に示す手段を用いている。The present invention uses the following means in order to achieve the above object.
【００１７】本発明の半導体装置は、半導体基板上に形
成され、第１の相互間隔を有する複数の第１のゲート
と、前記半導体基板上に形成され、前記第１の相互間隔
より広い第２の相互間隔を有する複数の第２のゲート
と、前記第１のゲートの側壁に形成され、前記第１のゲ
ート相互間を埋める第１の側壁絶縁膜と、前記第２のゲ
ートの側壁に互いに離れて形成された第２の側壁絶縁膜
と、前記第１の側壁絶縁膜下の前記半導体基板表面に形
成された第１の拡散層と、前記第２の側壁絶縁膜相互間
の前記半導体基板表面に形成された第２の拡散層と、前
記第２の拡散層上に形成された第１の珪化金属化合物
と、前記第１、第２のゲート上に形成され、前記第１の
珪化金属化合物と同一材料からなる第２の珪化金属化合
物とを有する。A semiconductor device according to the present invention includes a plurality of first gates formed on a semiconductor substrate and having a first mutual spacing, and a second gate formed on the semiconductor substrate and wider than the first mutual spacing. A plurality of second gates having a mutual gap between them, a first sidewall insulating film formed on sidewalls of the first gate and filling a gap between the first gates, and a second sidewall on the sidewalls of the second gate. A second side wall insulating film formed separately, a first diffusion layer formed on the surface of the semiconductor substrate below the first side wall insulating film, and the semiconductor substrate between the second side wall insulating films. a second diffusion layer formed on the surface, before
A first metal silicide compound formed on the second diffusion layer
And formed on the first and second gates, the first
The second metal silicide compound composed of the same material as the metal silicide compound
With things .
【００１８】前記第２の拡散層は、前記第１の拡散層よ
りも高濃度である。The concentration of the second diffusion layer is higher than that of the first diffusion layer.
【００１９】[0019]
【００２０】前記第１のゲートの相互間隔をＳ１、前記
第２のゲートの相互間隔をＳ２、前記第１及び第２の側
壁絶縁膜となる絶縁膜の堆積時の膜厚をＴ１とした時、
Ｓ１＜２×Ｔ１＜Ｓ２の関係を満たす。When the mutual distance between the first gates is S1, the mutual distance between the second gates is S2, and the thickness of the insulating film to be the first and second sidewall insulating films at the time of deposition is T1. ,
The relationship of S1 <2 × T1 <S2 is satisfied.
【００２１】前記半導体基板内にはキャパシタが形成さ
れ、このキャパシタは前記第１の拡散層に接続される。A capacitor is formed in the semiconductor substrate, and the capacitor is connected to the first diffusion layer.
【００２２】本発明の半導体装置の製造方法は、半導体
基板上にゲート酸化膜を形成する工程と、前記ゲート酸
化膜上に第１の相互間隔を有する複数の第１のゲートと
前記第１の相互間隔より広い第２の相互間隔を有する複
数の第２のゲートを選択的に形成する工程と、前記第
１、第２のゲートをマスクとして前記半導体基板表面に
第１の拡散層を形成する工程と、全面に第１の膜厚の絶
縁膜を堆積する工程と、前記絶縁膜を等方性エッチング
により前記第１の膜厚よりも薄い第２の膜厚までエッチ
ングする工程と、前記絶縁膜をエッチングして前記第１
のゲートの側壁に前記半導体基板表面を覆う第１の側壁
絶縁膜を形成し、かつ前記第２のゲートの側壁に前記半
導体基板表面を露出して第２の側壁絶縁膜を形成する工
程と、前記第１、第２のゲート及び第１、第２の側壁絶
縁膜をマスクとして前記半導体基板表面に不純物を導入
し、前記第１の拡散層よりも高濃度の第２の拡散層を形
成する工程とを具備する。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate oxide film on a semiconductor substrate, a plurality of first gates having a first mutual interval on the gate oxide film, and the first gate. A step of selectively forming a plurality of second gates having a second mutual spacing wider than the mutual spacing, and forming a first diffusion layer on the surface of the semiconductor substrate using the first and second gates as masks A step of depositing an insulating film having a first film thickness on the entire surface, and etching the insulating film to a second film thickness smaller than the first film thickness by isotropic etching. And a step of etching the insulating film
Forming a first side wall insulating film on the side wall of the gate to cover the surface of the semiconductor substrate, and exposing a surface of the semiconductor substrate on the side wall of the second gate to form a second side wall insulating film; Impurities are introduced into the surface of the semiconductor substrate using the first and second gates and the first and second sidewall insulating films as a mask to form a second diffusion layer having a higher concentration than that of the first diffusion layer. And a process.
【００２３】前記第２の側壁絶縁膜を形成する工程にお
けるエッチングは、異方性エッチングである。The etching in the step of forming the second side wall insulating film is anisotropic etching.
【００２４】前記第１の拡散層よりも高濃度の前記第２
の拡散層を形成する工程の後に、前記第２の側壁絶縁膜
相互間の前記第２の拡散層及び前記第１、第２のゲート
上に珪化金属化合物を形成する工程を具備する。The second diffusion layer having a concentration higher than that of the first diffusion layer
Forming a diffusion layer, and forming a metal silicide compound on the second diffusion layer and the first and second gates between the second sidewall insulating films. To do.
【００２５】前記第１のゲートの相互間隔をＳ１、前記
第２のゲートの相互間隔をＳ２、前記絶縁膜の前記第１
の膜厚をＴ１とした時、Ｓ１＜２×Ｔ１＜Ｓ２の関係を
満たすように形成されている。The mutual spacing of the first gate is S1, the mutual spacing of the second gate is S2, and the first spacing of the insulating film is S1.
When the film thickness of T1 is T1, it is formed so as to satisfy the relationship of S1 <2 × T1 <S2.
【００２６】[0026]
【発明の実施の形態】本発明の実施の形態を以下に図面
を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００２７】図１に示すように、１つの半導体装置にＰ
Ｎ接合のリーク電流を特に抑制したい領域Ａと、従来通
りの拡散層構造及び拡散層部の導電領域の抵抗値を得た
い領域Ｂが存在し、領域Ａ、Ｂには後述する複数のゲー
ト配線が平行に配置されている。ここで、領域Ａは例え
ばメモリセルが形成される領域に相当し、領域Ｂは高速
な信号処理が要求される周辺回路領域に相当する。As shown in FIG. 1, P is added to one semiconductor device.
There are a region A in which the leak current of the N-junction is particularly desired to be suppressed and a region B in which the resistance value of the conventional conductive region of the diffusion layer structure and the diffusion layer is desired to be obtained. Are arranged in parallel. Here, the region A corresponds to, for example, a region in which memory cells are formed, and the region B corresponds to a peripheral circuit region that requires high-speed signal processing.
【００２８】まず、シリコン基板１１の領域Ａ内には選
択的にディープトレンチ型のキャパシタ１２が形成され
る。このキャパシタ１２はトレンチ１２ａの周辺にキャ
パシタ絶縁膜１３が形成され、トレンチ１２ａの内部に
ストレージノード１２ｂを形成する、例えばポリシリコ
ンが充填されている。また、シリコン基板１１内には例
えばシリコン酸化膜からなるＳＴＩ（Shallow Trench I
solation）構造の素子分離領域１４が形成される。First, the deep trench type capacitor 12 is selectively formed in the region A of the silicon substrate 11. In this capacitor 12, a capacitor insulating film 13 is formed around the trench 12a, and the inside of the trench 12a is filled with, for example, polysilicon which forms a storage node 12b. In the silicon substrate 11, an STI (Shallow Trench I) made of, for example, a silicon oxide film is used.
An element isolation region 14 having a solation structure is formed.
【００２９】次に、シリコン基板１１上にゲート酸化膜
１５が形成され、このゲート酸化膜１５上にポリシリコ
ンからなるゲート１６ａ、１６ｂ、１６ｃ、１６ｄが選
択的に形成される。この際、領域Ａにおける隣り合うゲ
ート１６ａ、１６ｂ間の距離の最大値Ｓ１は例えば０．
２５μｍ、領域Ｂにおける隣り合うゲート１６ｃ、１６
ｄ間の最小値Ｓ２は例えば０．２８μｍであり、例えば
図示せぬ領域Ａのゲートと領域Ｂのゲートの相互間隔も
Ｓ２とされている。その後、ゲート１６ａ、１６ｂ、１
６ｃ、１６ｄの表面にシリコン酸化膜１７が形成され
る。Next, a gate oxide film 15 is formed on the silicon substrate 11, and gates 16a, 16b, 16c and 16d made of polysilicon are selectively formed on the gate oxide film 15. At this time, the maximum value S1 of the distance between the adjacent gates 16a and 16b in the region A is, for example, 0.
25 μm, adjacent gates 16c, 16 in region B
The minimum value S2 between d is, for example, 0.28 μm, and the mutual interval between the gate of the region A and the gate of the region B (not shown) is also S2. After that, the gates 16a, 16b, 1
A silicon oxide film 17 is formed on the surfaces of 6c and 16d.
【００３０】次に、ソース・ドレイン領域にゲート１６
ａ、１６ｂ、１６ｃ、１６ｄと自己整合的にイオン注入
及び拡散が行われ、低不純物濃度のＮ型拡散層１８ａ、
１８ｂが形成される。ここで、拡散層１８ｃはキャパシ
タ１２の電荷を読み出す領域であり、例えば、ストレー
ジノード１２ｂから不純物を外方拡散したり、別途不純
物をイオン注入して形成される。Next, the gate 16 is formed in the source / drain region.
I-implantation and diffusion are performed in a self-aligned manner with a, 16b, 16c, and 16d, and N-type diffusion layers 18a having a low impurity concentration
18b is formed. Here, the diffusion layer 18c is a region for reading out the charge of the capacitor 12, and is formed, for example, by outwardly diffusing the impurity from the storage node 12b or by separately implanting the impurity.
【００３１】次に、図２に示すように、全面に例えばシ
リコン窒化膜のような絶縁膜１９が形成される。この絶
縁膜１９の膜厚Ｔ１は例えば０．１３５μｍである。こ
の絶縁膜１９の厚さＴ１と、ゲート間隔Ｓ１、Ｓ２には
式（１）に示す関係がある。Next, as shown in FIG. 2, an insulating film 19 such as a silicon nitride film is formed on the entire surface. The film thickness T1 of the insulating film 19 is, for example, 0.135 μm. The thickness T1 of the insulating film 19 and the gate spacings S1 and S2 have the relationship shown in Expression (1).
【００３２】Ｓ１＜２×Ｔ１＜Ｓ２…（１）
次に、図３に示すように、絶縁膜１９は例えばウエット
エッチングのような等方性エッチングによりエッチング
され、その厚さＴ２が０．０７μｍとされる。この際、
絶縁膜１９の厚さＴ２は一例であり、ＭＯＳトランジス
タの性能が要求を満たすような厚さに形成されればよ
い。S1 <2 × T1 <S2 (1) Next, as shown in FIG. 3, the insulating film 19 is etched by isotropic etching such as wet etching, and its thickness T2 is 0.07 μm. It is said that On this occasion,
The thickness T2 of the insulating film 19 is an example, and the thickness T2 may be formed to satisfy the performance of the MOS transistor.
【００３３】次に、図４に示すように、例えばＲＩＥ等
の異方性エッチング技術により、ゲート１６ａ、１６
ｂ、１６ｃ、１６ｄの各側壁部分に絶縁膜１９が残るよ
うに絶縁膜１９が選択的に除去され、ゲート側壁絶縁膜
１９ａ、１９ｂが形成される。この際、領域Ａのゲート
１６ａとゲート１６ｂのように相互間隔が狭い部分は絶
縁膜１９が多く残るため、ゲート酸化膜１５が露出され
ずにゲート側壁絶縁膜１９ｂが形成される。また、領域
Ｂのゲート１６ｃとゲート１６ｄのように相互間隔が広
い領域はゲート酸化膜１５が露出されてゲート側壁絶縁
膜１９ａが形成される。Next, as shown in FIG. 4, the gates 16a, 16 are formed by an anisotropic etching technique such as RIE.
The insulating film 19 is selectively removed so that the insulating film 19 remains on the side wall portions of b, 16c, and 16d, and gate side wall insulating films 19a and 19b are formed. At this time, since a large amount of the insulating film 19 remains in the region A where the mutual spacing is narrow, such as the gate 16a and the gate 16b, the gate sidewall insulating film 19b is formed without exposing the gate oxide film 15. The gate oxide film 15 is exposed and the gate sidewall insulating film 19a is formed in the region B where the mutual distance is wide like the gate 16c and the gate 16d.
【００３４】次に、ゲート１６ａ、１６ｂ、１６ｃ、１
６ｄ及びゲート側壁絶縁膜１９ａをマスクとして高濃度
の不純物イオンが注入され、この後、注入された不純物
が拡散される。従って、拡散層１８ｂの不純物濃度より
も高不純物濃度のＮ型拡散層２０が形成され、ＬＤＤ構
造のＭＯＳ型トランジスタが形成される。Next, the gates 16a, 16b, 16c, 1
High-concentration impurity ions are implanted using 6d and the gate sidewall insulating film 19a as a mask, and then the implanted impurities are diffused. Therefore, the N-type diffusion layer 20 having an impurity concentration higher than that of the diffusion layer 18b is formed, and the MOS-type transistor having the LDD structure is formed.
【００３５】次に、図５に示すように、全面に金属膜と
して例えばコバルト薄膜が形成される。ここで、金属膜
はコバルトに限定されず、例えばチタン等でもよい。そ
の後、シリコンと化学的反応が起こる温度までアニール
することにより、コバルト薄膜とシリコンを含有するゲ
ート１６ａ、１６ｂ、１６ｃ、１６ｄ及びシリコン基板
１１と接している領域ではコバルトとシリコンが反応
し、コバルトシリサイド膜２１ａ、２１ｂが自己整合的
に形成される。この際、絶縁膜で覆われるゲート１６
ａ、１６ｂの相互間、及びゲート側壁絶縁膜１９ａ、１
９ｂ上にコバルトシリサイド膜は形成されない。Next, as shown in FIG. 5, a cobalt thin film, for example, is formed as a metal film on the entire surface. Here, the metal film is not limited to cobalt and may be titanium, for example. Then, by annealing to a temperature at which a chemical reaction with silicon occurs, cobalt reacts with silicon in the regions in contact with the cobalt thin film and the silicon-containing gates 16a, 16b, 16c, 16d and the silicon substrate 11, and cobalt silicide is formed. The films 21a and 21b are formed in a self-aligned manner. At this time, the gate 16 covered with the insulating film
a, 16b, and the gate sidewall insulating films 19a, 1b.
No cobalt silicide film is formed on 9b.
【００３６】その後、エッチング技術により未反応のコ
バルト薄膜が選択的に除去される。これより、領域Ａの
ゲート相互間隔の狭い部分にはコバルトシリサイド膜が
形成されず、領域Ａ及び領域Ｂのゲートの相互間隔が広
い部分にコバルトシリサイド膜が形成されたＭＯＳトラ
ンジスタが形成される。また、領域Ａにおいては、コバ
ルトシリサイド膜が形成された部分に例えばビット線が
接続される。After that, the unreacted cobalt thin film is selectively removed by the etching technique. As a result, the cobalt silicide film is not formed in the region A where the gates are close to each other, and the MOS transistor is formed in which the cobalt silicide film is formed in the region A and the region B where the gates are wide. Further, in the region A, for example, a bit line is connected to the portion where the cobalt silicide film is formed.
【００３７】上記実施形態によれば、領域Ａでは拡散層
上にシリサイド膜が形成されないため、リーク電流を低
く抑えることができる。従って、キャパシタの電荷保持
特性が改善できる。一方、領域Ｂでは従来例と同じ構造
に形成できるため、拡散層の構造及び拡散層部の導電領
域の抵抗値も従来通りのものが得られる。従って、領域
Ｂにおいては従来通り抵抗を抑えることにより信号処理
の高速性を確保することができる。According to the above embodiment, since the silicide film is not formed on the diffusion layer in the region A, the leak current can be suppressed low. Therefore, the charge retention characteristics of the capacitor can be improved. On the other hand, since the region B can be formed to have the same structure as that of the conventional example, the structure of the diffusion layer and the resistance value of the conductive region of the diffusion layer portion can be the same as the conventional one. Therefore, in the area B, high speed of signal processing can be ensured by suppressing the resistance as in the conventional case.
【００３８】また、領域Ａのシリサイドを形成しない領
域を自己整合的に形成できるため、例えば、シリサイド
膜を形成しない領域を予め覆うような工程を省くことが
できる。従って、工程数の増加を抑えることができる。Further, since the region where the silicide is not formed in the region A can be formed in a self-aligned manner, it is possible to omit the step of previously covering the region where the silicide film is not formed, for example. Therefore, an increase in the number of steps can be suppressed.
【００３９】その他、本発明は、その要旨を逸脱しない
範囲で、種々変形して実施することが可能である。In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.
【００４０】[0040]
【発明の効果】以上説明したように本発明によれば、珪
化金属化合物の影響で発生するＰＮ接合リーク電流を抑
えることができ、かつ信号処理の高速性を確保すること
ができる半導体装置の製造方法を提供できる。As described above, according to the present invention, it is possible to manufacture a semiconductor device capable of suppressing a PN junction leak current generated by the influence of a metal silicide compound and ensuring high speed of signal processing. A method can be provided.
【図１】本発明に係わる半導体装置の製造工程の断面
図。FIG. 1 is a sectional view of a manufacturing process of a semiconductor device according to the present invention.
【図２】本発明に係わる半導体装置の製造工程の断面
図。FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device according to the present invention.
【図３】本発明に係わる半導体装置の製造工程の断面
図。FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor device according to the present invention.
【図４】本発明に係わる半導体装置の製造工程の断面
図。FIG. 4 is a sectional view of a manufacturing process of a semiconductor device according to the present invention.
【図５】本発明に係わる半導体装置の製造工程の断面
図。FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device according to the invention.
【図６】従来技術による半導体装置の製造工程の断面
図。FIG. 6 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.
【図７】従来技術による半導体装置の製造工程の断面
図。FIG. 7 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.
【図８】従来技術による半導体装置の製造工程の断面
図。FIG. 8 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.
【図９】従来技術による半導体装置の製造工程の断面
図。FIG. 9 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.
１１…シリコン基板、 １２…キャパシタ、 １２ａ…トレンチ、 １２ｂ…ストレージノード、 １３…絶縁膜、 １４…素子分離領域、 １５…ゲート酸化膜、 １６ａ、１６ｂ、１６ｃ、１６ｄ…ゲート、 １７…シリコン酸化膜、 １８ａ、１８ｂ、１８ｃ…拡散層（低濃度）、 １９…絶縁膜、 １９ａ、１９ｂ…ゲート側壁絶縁膜、 ２０…拡散層（高濃度）、 ２１ａ、２１ｂ…コバルトシリサイド膜。 11 ... Silicon substrate, 12 ... Capacitor, 12a ... trench, 12b ... storage node, 13 ... Insulating film, 14 ... Element isolation region, 15 ... Gate oxide film, 16a, 16b, 16c, 16d ... Gate, 17 ... Silicon oxide film, 18a, 18b, 18c ... Diffusion layer (low concentration), 19 ... Insulating film, 19a, 19b ... Gate sidewall insulating film, 20 ... Diffusion layer (high concentration), 21a, 21b ... Cobalt silicide film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 成瀬 宏 神奈川県横浜市磯子区新杉田町８番地 株式会社東芝横浜事業所内 (72)発明者 国分 弘一 神奈川県横浜市磯子区新杉田町８番地 株式会社東芝横浜事業所内 (72)発明者 桜井 正臣 神奈川県横浜市磯子区新杉田町８番地 株式会社東芝横浜事業所内 (56)参考文献 特開 平10−223849（ＪＰ，Ａ) 特開 平９−232427（ＪＰ，Ａ) 特開 平10−74894（ＪＰ，Ａ) 特開 平５−136368（ＪＰ，Ａ) 特開 平１−191473（ＪＰ，Ａ) 特開2000−68472（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/085 - 27/092 H01L 21/8234 - 21/8238 H01L 27/108 H01L 21/302 H01L 21/28 - 21/288 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Naruse 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Toshiba Corporation Yokohama office (72) Inventor, Koichi Kokubun 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Toshiba Corporation Inside the Yokohama Works (72) Masaomi Sakurai, 8 Shinsita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Yokohama Works (56) References JP-A-10-223849 (JP, A) JP-A-9-232427 (JP) , A) JP 10-74894 (JP, A) JP 5-136368 (JP, A) JP 1-191473 (JP, A) JP 2000-68472 (JP, A) (58) Survey Fields (Int.Cl. 7 , DB name) H01L 27/085-27/092 H01L 21/8234-21/8238 H01L 27/108 H01L 21/302 H01L 21/28-21/288
Claims (5)
工程と、 前記ゲート酸化膜上に第１の相互間隔を有する複数の第
１のゲートと前記第１の相互間隔より広い第２の相互間
隔を有する複数の第２のゲートを選択的に形成する工程
と、 前記第１、第２のゲートをマスクとして前記半導体基板
表面に第１の拡散層を形成する工程と、 全面に第１の膜厚の絶縁膜を堆積する工程と、 前記絶縁膜を等方性エッチングにより前記第１の膜厚よ
りも薄い第２の膜厚までエッチングする工程と、 前記絶縁膜をエッチングして前記第１のゲートの側壁に
前記半導体基板表面を覆う第１の側壁絶縁膜を形成し、
かつ前記第２のゲートの側壁に前記半導体基板表面を露
出して第２の側壁絶縁膜を形成する工程と、 前記第１、第２のゲート及び第１、第２の側壁絶縁膜を
マスクとして前記半導体基板表面に不純物を導入し、前
記第１の拡散層よりも高濃度の第２の拡散層を形成する
工程とを具備することを特徴とする半導体装置の製造方
法。1. A step of forming a gate oxide film on a semiconductor substrate, a plurality of first gates having a first mutual spacing on the gate oxide film and a second mutual gate wider than the first mutual spacing. A step of selectively forming a plurality of second gates having an interval; a step of forming a first diffusion layer on the surface of the semiconductor substrate using the first and second gates as a mask ; depositing a film thickness of the insulating film is a thickness of the first film by isotropic etching the insulating film
Etching to a thinner second film thickness , etching the insulating film to form a first sidewall insulating film on the sidewall of the first gate to cover the surface of the semiconductor substrate,
And exposing the surface of the semiconductor substrate to the sidewalls of the second gate to form a second sidewall insulating film, and using the first and second gates and the first and second sidewall insulating films as a mask. And a step of introducing an impurity into the surface of the semiconductor substrate to form a second diffusion layer having a higher concentration than the first diffusion layer.
おけるエッチングは、異方性エッチングであることを特
徴とする請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1 , wherein the etching in the step of forming the second sidewall insulating film is anisotropic etching.
２の拡散層を形成する工程の後に、前記第２の側壁絶縁
膜相互間の前記第２の拡散層及び前記第１、第２のゲー
ト上に珪化金属化合物を形成する工程を具備することを
特徴とする請求項１記載の半導体装置の製造方法。3. The second diffusion layer and the first diffusion layer between the second sidewall insulating films are formed after the step of forming the second diffusion layer having a higher concentration than the first diffusion layer. the method of manufacturing a semiconductor device according to claim 1, characterized by including the step of forming a metal silicide compound on the second gate.
記第２のゲートの相互間隔をＳ２、前記絶縁膜の前記第
１の膜厚をＴ１とした時、Ｓ１＜２×Ｔ１＜Ｓ２の関係
を満たすように形成されていることを特徴とする請求項
１記載の半導体装置の製造方法。Wherein said first mutual spacing of gates S1, the mutual spacing of the second gate S2, the first of said insulating film
When 1 of the film thickness was set to T1, claims, characterized in that it is formed to satisfy the relationship of S1 <2 × T1 <S2
1. The method for manufacturing a semiconductor device according to 1 .
層及び前記第１、第２のゲート上に同一材料で同時に形
成されることを特徴とする請求項３記載の半導体装置の
製造方法。5. The method of manufacturing a semiconductor device according to claim 3 , wherein the metal silicide compound is formed simultaneously on the second diffusion layer and the first and second gates with the same material. .
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| TW088122035A TW429411B (en) | 1998-12-21 | 1999-12-15 | Semiconductor device and its manufacture |
| KR1019990059311A KR100320778B1 (en) | 1998-12-21 | 1999-12-20 | Semiconductor device and a method of making thereof |
| US09/467,078 US6339237B1 (en) | 1998-12-21 | 1999-12-20 | Semiconductor device having a memory cell region and peripheral circuit region and method of manufacturing the same |
| US09/817,275 US6551882B2 (en) | 1998-12-21 | 2001-03-27 | Semiconductor device manufacturing method permitting suppression of leak current through the PN junction |
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|---|---|---|---|
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| JP3361067B2 true JP3361067B2 (en) | 2003-01-07 |
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| KR100443241B1 (en) * | 2001-12-24 | 2004-08-04 | 주식회사 하이닉스반도체 | Method for fabricating of mask Read Only Memory Device |
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| KR100947566B1 (en) * | 2002-12-30 | 2010-03-15 | 매그나칩 반도체 유한회사 | Method for manufacturing maskrom cell transistor |
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-
1998
- 1998-12-21 JP JP36278898A patent/JP3361067B2/en not_active Expired - Fee Related
-
1999
- 1999-12-20 KR KR1019990059311A patent/KR100320778B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000048262A (en) | 2000-07-25 |
| KR100320778B1 (en) | 2002-01-17 |
| JP2000188337A (en) | 2000-07-04 |
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