JP3349166B2 - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JP3349166B2 JP3349166B2 JP3281892A JP3281892A JP3349166B2 JP 3349166 B2 JP3349166 B2 JP 3349166B2 JP 3281892 A JP3281892 A JP 3281892A JP 3281892 A JP3281892 A JP 3281892A JP 3349166 B2 JP3349166 B2 JP 3349166B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- plating
- pad portion
- nickel
- wire bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemically Coating (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、混成集積回路等に使用
される回路基板に関するものである。The present invention relates to relates to a circuitry substrate that is used in hybrid integrated circuits or the like.
【０００２】[0002]
【従来の技術】金属ベース回路基板は、ベース金属板上
に絶縁層を介して銅回路パターンを形成したものである
が、特に混成集積回路等に使用される金属ベース回路基
板の場合は、銅回路パターンに、電子部品を半田付けす
るためのパッド部と、ボンディングワイヤー（アルミニ
ウム細線）を超音波接続するためのパッド部の両方を設
ける必要がある。2. Description of the Related Art A metal base circuit board is formed by forming a copper circuit pattern on a base metal plate with an insulating layer interposed therebetween. In particular, in the case of a metal base circuit board used for a hybrid integrated circuit or the like, copper It is necessary to provide both a pad portion for soldering an electronic component and a pad portion for ultrasonically connecting a bonding wire (a thin aluminum wire) to a circuit pattern.
【０００３】しかし銅表面は、半田付けを行うことは容
易であるが、ワイヤーボンディングを行うことが難しい
ので、従来、この種の金属ベース回路基板においては、
半田付け用のパッド部は銅をそのまま露出させ、ワイヤ
ーボンディング用のパッド部はニッケルメッキを施した
構造としてある（特公昭52-3461 号公報）。[0003] However, it is easy to perform soldering on the copper surface, but it is difficult to perform wire bonding.
The pad for soldering has copper exposed as it is, and the pad for wire bonding has a nickel-plated structure (Japanese Patent Publication No. 52-3461).
【０００４】その基本構造を図３に示す。この金属ベー
ス回路基板は、アルミニウム板等からなるベース金属板
11上に、エポキシ樹脂等からなる絶縁層13を介して、銅
回路パターン15を形成したものである。銅回路パターン
15は通常、銅箔のパターンエッチングにより形成され
る。銅回路パターン15には半田付け用のパッド部15ａと
ワイヤーボンディング用のパッド部15ｂとが設けられて
いるが、半田付け用パッド部15ａはそのまま銅表面を露
出させ、ワイヤーボンディング用のパッド部15ｂはその
表面にニッケルメッキ17が施されている。なお19はパッ
ド部以外の面に印刷されたソルダーレジストである。FIG. 3 shows the basic structure. This metal base circuit board is a base metal plate made of aluminum plate etc.
A copper circuit pattern 15 is formed on an intervening insulating layer 13 made of epoxy resin or the like. Copper circuit pattern
15 is usually formed by pattern etching of a copper foil. The copper circuit pattern 15 is provided with a pad portion 15a for soldering and a pad portion 15b for wire bonding. However, the pad portion 15a for soldering exposes the copper surface as it is and the pad portion 15b for wire bonding. Has a nickel plating 17 on its surface. Reference numeral 19 denotes a solder resist printed on a surface other than the pad portion.
【０００５】[0005]
【発明が解決しようとする課題】従来の、同一基板上に
銅表面の半田付け用パッド部とニッケルメッキしたワイ
ヤーボンディング用パッド部を形成した回路基板は、半
田付け用パッド部にニッケルメッキがのらないようにし
てワイヤーボンディング用パッド部のみにニッケルメッ
キを施すか、あるいは全てのパッド部にニッケルメッキ
を施した後、半田付け用パッド部のニッケルメッキを除
去することが必要であり、製造がきわめて面倒であっ
た。このため同じ表面でも半田付けもワイヤーボンディ
ングもできる回路基板の開発が望まれていた。BRIEF Problems to be Solved] The conventional circuit substrate formed with soldering pad portion and the nickel-plated wire bonding pad portion of the copper surface on the same substrate is nickel-plated soldering pad portion It is necessary to apply nickel plating only to the wire bonding pads so that they do not stick, or to apply nickel plating to all the pads, and then remove the nickel plating from the soldering pads. Was very troublesome. Therefore also soldering the development of the circuit board that can be wire-bonded by the same surface has been desired.
【０００６】上記の課題を解決するための一つの手段と
しては、すべてのパッド部にニッケルメッキを施すこと
が考えられるが、ニッケルメッキ面は半田付け性がわる
いという問題がある。また他の手段としては、すべての
パッド部に金メッキを施すことも考えられる。しかし金
メッキ面は、ニッケルメッキ面よりワイヤーボンディン
グ性がわるいという問題がある（前記公報）。このよう
に単一金属のメッキでは半田付け性とワイヤーボンディ
ング性の両方を満足することは困難である。As one means for solving the above problem, it is conceivable to apply nickel plating to all the pad portions, but there is a problem that the nickel plated surface has poor solderability. As another means, gold plating may be applied to all the pad portions. However, there is a problem that the gold-plated surface has a poorer wire bonding property than the nickel-plated surface (the aforementioned publication). Thus, it is difficult to satisfy both the solderability and the wire bonding property by plating with a single metal.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記のような
課題を解決した回路基板を提供するもので、その構成
は、銅回路パターンに半田付け用のパッド部とワイヤー
ボンディング用のパッド部とが設けられた回路基板にお
いて、前記銅回路パターンの半田付け用パッド部および
ワイヤーボンディング用パッド部の両方にニッケルメッ
キを施し、その上に、厚さ0.2μm以下の金メッキを施し
たことを特徴とするものである。The present invention SUMMARY OF] is intended to provide a circuitry substrate which solves the above problems, the construction, the pad portion for soldering to the copper circuit pattern and the wire bonding in circuits substrate provided with the pad portion, the soldering pads of the copper circuit pattern and a nickel-plated on both wire bonding pad portion, thereon, was subjected to the following gold thickness 0.2μm It is characterized by the following.
【０００８】[0008]
【作用】この回路基板は、半田付け用パッド部の表面に
もニッケルメッキが施されているが、その上に金メッキ
が施されているため、ニッケルメッキの半田濡れ性のわ
るさは改善され、半田付け性は良好である。また金メッ
キは従来、ワイヤーボンディング性がわるいとされてき
たが、ニッケルメッキの上に厚さ0.2μm以下のきわめて
薄い金メッキを設けた場合には、良好なワイヤーボンデ
ィング特性が得られることが確認された。ただし金メッ
キの厚さは、あまり薄過ぎるとニッケルメッキ面の半田
濡れ性改善の効果が低下するため、0.01μm以上にする
ことが望ましい。[Action] This circuitry substrate is nickel-plated on the surface of the soldering pad portion has been subjected, since the gold plating is performed thereon, the solder wettability of Waru of nickel plating improvement And the solderability is good. Also, conventionally, gold plating has been considered to have poor wire bonding properties, but it has been confirmed that when a very thin gold plating having a thickness of 0.2 μm or less is provided on nickel plating, good wire bonding characteristics can be obtained. . However, if the thickness of the gold plating is too small, the effect of improving the solder wettability on the nickel plating surface is reduced.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面を参照して詳細
に説明する。図１は本発明の一実施例を示す。この金属
ベース回路基板は、アルミニウム板等のベース金属板11
上に絶縁層13を介して銅回路パターン15を形成し、銅回
路パターン15に半田付け用のパッド部15ａとワイヤーボ
ンディング用のパッド部15ｂとを設けた点では図３に示
した従来の金属ベース回路基板と同じであるが、銅回路
パターン15の半田付け用パッド部15ａおよびワイヤーボ
ンディング用パッド部15ｂの両方にニッケルメッキ17を
施し、その上に厚さ0.2 μm 以下の金メッキ21を施した
点に特徴を有するものである。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. This metal base circuit board is a base metal plate 11 such as an aluminum plate.
The conventional metal circuit shown in FIG. 3 in that a copper circuit pattern 15 is formed on the insulating layer 13 and a pad part 15a for soldering and a pad part 15b for wire bonding are provided on the copper circuit pattern 15. The same as the base circuit board, except that both the soldering pad portion 15a and the wire bonding pad portion 15b of the copper circuit pattern 15 were plated with nickel 17 and gold plating 21 having a thickness of 0.2 μm or less was placed thereon. It is characterized by points.
【００１０】この金属ベース回路基板は、半田付け用パ
ッド部15ａの表面が金メッキ21となっているため、半田
付け性は良好である。またワイヤーボンディング用パッ
ド部15ｂの表面が、従来ワイヤーボンディング性がわる
いとされていた金メッキ21となっているが、ニッケルメ
ッキ17の上に厚さ0.2 μm 以下のきわめて薄い金メッキ
21を設けた場合には、後述するように良好なワイヤーボ
ンディング特性が得られる。The metal base circuit board has good solderability because the surface of the solder pad 15a is gold-plated. Also, the surface of the wire bonding pad portion 15b is made of gold plating 21 which was conventionally considered to have poor wire bonding properties.
When 21 is provided, good wire bonding characteristics can be obtained as described later.
【００１１】金メッキ21の厚さは、ワイヤーボンディン
グ特性の面からは出来るだけ薄いことが好ましいが、あ
まり薄過ぎるとニッケルメッキ17面の半田濡れ性を改善
する効果が低下するため、0.01μm 以上にすることが望
ましい。The thickness of the gold plating 21 is preferably as small as possible from the viewpoint of wire bonding characteristics. However, if the thickness is too small, the effect of improving the solder wettability on the nickel plating 17 surface is reduced. It is desirable to do.
【００１２】ニッケルメッキ17および金メッキ21は無電
解メッキにより形成することが望ましい。無電解メッキ
によりニッケルメッキ17および金メッキ21を形成する場
合には、パッド部15ａ、15ｂ以外の面をソルダーレジス
ト19で覆った後に、ソルダーレジスト19をメッキレジス
トと兼用させて無電解メッキを行い、ソルダーレジスト
19に覆われていない銅回路パターン15の表面（すなわち
パッド部）全面にニッケルメッキ17および金メッキ21を
形成すれば、製造工程を少なくでき、生産性が向上す
る。The nickel plating 17 and the gold plating 21 are desirably formed by electroless plating. When the nickel plating 17 and the gold plating 21 are formed by electroless plating, the surfaces other than the pad portions 15a and 15b are covered with a solder resist 19, and then the solder resist 19 is also used as a plating resist to perform electroless plating. Solder resist
If the nickel plating 17 and the gold plating 21 are formed on the entire surface (that is, the pad portion) of the copper circuit pattern 15 not covered with 19, the number of manufacturing steps can be reduced, and the productivity is improved.
【００１３】またベース金属板としては一般にアルミニ
ウム板が使用されるが、銅、鉄、銅−インバー等の金属
板を使用することもできる。Although an aluminum plate is generally used as the base metal plate, a metal plate of copper, iron, copper-invar, etc. may be used.
【００１４】図２はベース金属板として銅板11Ｃを使用
した本発明の他の実施例を示す。銅板は、アルミニウム
板に比べ伝熱性、放熱性が優れているが、耐食性が劣る
という理由でベース金属板として使用される例は少なか
ったが、図２のようにベース金属板として銅板11Ｃを使
用し、銅回路パターン15のパッド部15ａ、15ｂにニッケ
ルメッキ17および金メッキ21を施すときに、銅板11Ｃの
表面にも同時にニッケルメッキ17および金メッキ21を施
せば、銅板11Ｃの耐食性を大幅に改善することができ、
ベース金属板にアルミニウム板を使用したものより放熱
性の良好な金属ベース回路基板が得られる。FIG. 2 shows another embodiment of the present invention using a copper plate 11C as a base metal plate. Copper plate is superior in heat conductivity and heat dissipation compared to aluminum plate, but there are few examples of copper plate used as base metal plate because of poor corrosion resistance, but copper plate 11C is used as base metal plate as shown in FIG. When the nickel plating 17 and the gold plating 21 are applied to the pad portions 15a and 15b of the copper circuit pattern 15 and the nickel plating 17 and the gold plating 21 are applied to the surface of the copper plate 11C at the same time, the corrosion resistance of the copper plate 11C is greatly improved. It is possible,
A metal base circuit board having better heat dissipation than that obtained by using an aluminum plate as the base metal plate can be obtained.
【００１５】次に、半田付け性とワイヤーボンディング
性の実験結果を説明する。実験では、ベース金属板とし
て厚さ２mmのアルミニウム板を使用し、これに厚さ100
μm のエポキシ系絶縁層を介して厚さ35μm の銅箔を張
り付けた金属ベース銅張り板を出発材料とした。Next, the results of experiments on solderability and wire bonding properties will be described. In the experiment, a 2 mm thick aluminum plate was used as the base metal plate,
The starting material was a metal-base copper-clad plate with a 35-μm-thick copper foil attached via a μm-epoxy insulating layer.
【００１６】比較例１は金属ベース銅張り板そのままの
ものである。比較例２は銅箔上に厚さ５μm のニッケル
メッキを施したものである。比較例３は銅箔上に厚さ５
μm のニッケルメッキを施し、その上に厚さ２μmの金
メッキを施したものである。Comparative Example 1 is a metal-base copper-clad plate as it is. In Comparative Example 2, a copper foil was plated with nickel having a thickness of 5 μm. Comparative Example 3 has a thickness of 5 on a copper foil.
A nickel plating of μm was applied, and a gold plating of 2 μm thickness was applied thereon.
【００１７】実施例１は銅箔上に厚さ５μm のニッケル
メッキを施し、その上に厚さ 0.02μm の金メッキを施
したものである。実施例２は銅箔上に厚さ５μm のニッ
ケルメッキを施し、その上に厚さ 0.05μm の金メッキ
を施したものである。実施例３は銅箔上に厚さ５μm の
ニッケルメッキを施し、その上に厚さ 0.1μm の金メッ
キを施したものである。実施例４は銅箔上に厚さ５μm
のニッケルメッキを施し、その上に厚さ 0.15μm の金
メッキを施したものである。In the first embodiment, a copper foil is plated with nickel having a thickness of 5 μm, and a gold plating having a thickness of 0.02 μm is formed thereon. In the second embodiment, a copper foil is plated with nickel having a thickness of 5 μm, and a gold plating is deposited thereon with a thickness of 0.05 μm. In the third embodiment, a copper foil is plated with nickel having a thickness of 5 μm, and a gold plating having a thickness of 0.1 μm is formed thereon. Example 4 has a thickness of 5 μm on a copper foil.
Is nickel-plated and then gold-plated with a thickness of 0.15 μm.
【００１８】いずれもニッケルメッキおよび金メッキは
電気メッキにより施した。これらの各サンプルにつき、
半田濡れ性試験、ワイヤーボンディング性試験を行っ
た。その結果を表１に示す。In both cases, nickel plating and gold plating were performed by electroplating. For each of these samples,
A solder wettability test and a wire bonding test were performed. Table 1 shows the results.
【００１９】なお半田濡れ性試験は、原サンプルと、26
0 ℃半田バス上に１分間浮かべた後の半田耐熱サンプル
の各々について、JISC5012.8.4に準じて試験を行い、半
田濡れ面積が、原サンプル、半田耐熱サンプルとも95％
以上のものを○、原サンプルのみ95％以上のものを△、
ともに95％未満のものを×とした。またワイヤーボンデ
ィング性試験は、直径200 μm のアルミニウムワイヤー
をボンディングした後、加熱前と 200℃×1000時間加熱
後にプル試験を行い、強度が加熱前に比べ70％以上のも
のを○、70％未満のものを△、加熱前の段階で強度がで
ないものを×とした。The solder wettability test was carried out on the original sample and 26
Perform a test in accordance with JISC5012.8.4 for each of the solder heat-resistant samples after floating on a 0 ° C solder bath for 1 minute.
○ for those above, △ for only 95% of the original sample,
Both were less than 95% as x. In the wire bonding test, after bonding an aluminum wire with a diameter of 200 μm, a pull test is performed before heating and after heating at 200 ° C for 1000 hours. The sample was evaluated as Δ, and the sample with no strength at the stage before heating was evaluated as ×.
【００２０】[0020]
【表１】 ※：原サンプルの半田濡れ性は比較例２より優れてい
る。[Table 1] *: The solder wettability of the original sample is better than Comparative Example 2.
【００２１】以上の結果より、実施例は比較例に比べ両
特性とも優れていることが明らかである。From the above results, it is clear that the example is superior in both characteristics to the comparative example.
【００２２】次に、前記金属ベース銅張り板を使用し、
銅箔をパターンエッチングして回路を形成した後、パッ
ド部を残してソルダーレジストを印刷し、その後、パッ
ド部に無電解メッキにより厚さ５μm のニッケルメッキ
を施し、さらに無電解メッキにより厚さ0.05μm の金メ
ッキを施したサンプルについて、半田濡れ性試験および
ワイヤーボンディング性試験を行った。その結果はいず
れも良好であった。Next, using the metal-based copper-clad board,
After forming a circuit by pattern etching of the copper foil, a solder resist is printed leaving the pad portion, and then the pad portion is plated with nickel by a thickness of 5 μm by electroless plating, and furthermore, a thickness of 0.05 μm by the electroless plating. A sample having a gold plating of μm was subjected to a solder wettability test and a wire bonding test. The results were all good.
【００２３】ここで前記無電解メッキは、無電解メッキ
法の一つとして工業的に一般的に行われている置換メッ
キ法を適用している。この置換メッキ法ではメッキ厚が
せいぜい0.2 μm が限界であるが、この点本発明のメッ
キ厚の上限と一致しており、この点からも有効な手段と
いえる。Here, the electroless plating employs a displacement plating method which is generally performed industrially as one of the electroless plating methods. In this displacement plating method, the plating thickness has a limit of 0.2 μm at most, but this point coincides with the upper limit of the plating thickness of the present invention, and it can be said that this is also an effective means.
【００２４】[0024]
【発明の効果】以上説明したように本発明によれば、半
田付け用パッド部とワイヤーボンディング用パッド部に
同じメッキを施して、半田付け性およびワイヤーボンデ
ィングが共に良好な回路基板を得ることができる。した
がって半田付け用パッド部とワイヤーボンディング用パ
ッド部の両方を有する回路基板の製造がきわめて容易に
なり、コストダウンを図ることができる。According to the present invention as described above, according to the present invention, by performing the same plating soldering pad portion and the wire bonding pad portion, the solderability and wire bonding obtain both good circuits board Can be. Thus the production of that circuitry substrate having a both soldering pad portion and the wire bonding pad portion is extremely easy, the cost can be reduced.
【図１】 本発明の一実施例に係る金属ベース回路基板
の断面図。FIG. 1 is a cross-sectional view of a metal-based circuit board according to one embodiment of the present invention.
【図２】 本発明の他の実施例に係る金属ベース回路基
板の断面図。FIG. 2 is a cross-sectional view of a metal-based circuit board according to another embodiment of the present invention.
【図３】 従来の金属ベース回路基板の断面図。FIG. 3 is a cross-sectional view of a conventional metal-based circuit board.
11：ベース金属板 11Ｃ：銅板（ベー
ス金属板） 13：絶縁層 15：銅回路パター
ン 15ａ：半田付け用パッド部 15ｂ：ワイヤーボ
ンディング用パッド部 17：ニッケルメッキ 19：ソルダーレジ
スト 21：金メッキ11: Base metal plate 11C: Copper plate (base metal plate) 13: Insulating layer 15: Copper circuit pattern 15a: Pad portion for soldering 15b: Pad portion for wire bonding 17: Nickel plating 19: Solder resist 21: Gold plating
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−121360（ＪＰ，Ａ) 特開 昭63−73697（ＪＰ，Ａ) 特開 平４−221881（ＪＰ，Ａ) 特開 昭59−188997（ＪＰ，Ａ) 特開 昭63−156391（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/24 C23C 18/52 H01L 21/60 H01L 23/12 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-121360 (JP, A) JP-A-63-73697 (JP, A) JP-A-4-221188 (JP, A) JP-A-59-1983 188997 (JP, A) JP-A-63-156391 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/24 C23C 18/52 H01L 21/60 H01L 23/12
Claims (5)
とワイヤーボンディング用のパッド部とが設けられた回
路基板において、前記銅回路パターンの半田付け用パッ
ド部およびワイヤーボンディング用パッド部の両方にニ
ッケルメッキを施し、その上に、厚さ0.2μm以下の金メ
ッキを施したことを特徴とする回路基板。1. A round <br/> circuit board and the pad portion is provided in the pad portion and the wire bonding for soldering to the copper circuit pattern, for soldering pad portion and the wire bonding of the copper circuit pattern plated with nickel on both the pad portion, on which, you characterized in that subjected to the following gold thickness 0.2μm circuitry board.
厚さが0.01μm以上であるもの。2. In circuitry substrate according to claim 1, wherein, as the thickness of the gold plating is 0.01μm or more.
ルダーレジストに覆われていない銅回路パターンの全表
面に無電解メッキによるニッケルメッキおよび金メッキ
が施されていることを特徴とするもの。3. In circuits substrate according to claim 1 or 2, wherein, which is characterized in that nickel plating and gold by electroless plating on the entire surface of the copper circuit pattern which is not covered with the solder resist is applied .
で、回路基板がベース金属板上に絶縁層を介して銅回路
パターンが形成された金属ベース回路基板であるもの。4. In circuits board according to claim 1, wherein the copper circuit via an insulating layer on the circuit board base metal board
A metal-based circuit board on which a pattern is formed .
ベース金属板が銅板であり、この銅板の表面にもニッケ
ルメッキ及び金メッキが施されていることを特徴とする
もの。 5. The metal-based circuit board according to claim 4, wherein
The base metal plate is a copper plate, and the surface of the copper plate is also plated with nickel and gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3281892A JP3349166B2 (en) | 1992-01-24 | 1992-01-24 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3281892A JP3349166B2 (en) | 1992-01-24 | 1992-01-24 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05206620A JPH05206620A (en) | 1993-08-13 |
| JP3349166B2 true JP3349166B2 (en) | 2002-11-20 |
Family
ID=12369417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3281892A Ceased JP3349166B2 (en) | 1992-01-24 | 1992-01-24 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3349166B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7108014B2 (en) | 2002-04-26 | 2006-09-19 | Mikuni Corporation | Liquid diluting device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1009202B1 (en) * | 1997-06-04 | 2007-10-17 | Ibiden Co., Ltd. | Soldering member for printed wiring boards |
| JP3226489B2 (en) | 1998-02-19 | 2001-11-05 | 日東電工株式会社 | Suspension board with circuit |
| JP4667637B2 (en) * | 2001-05-02 | 2011-04-13 | 古河電気工業株式会社 | Bonding method of electronic parts |
| KR100396787B1 (en) * | 2001-11-13 | 2003-09-02 | 엘지전자 주식회사 | Wire bonding pad structure of semiconductor package pcb |
| JP4817418B2 (en) * | 2005-01-31 | 2011-11-16 | オンセミコンダクター・トレーディング・リミテッド | Circuit device manufacturing method |
-
1992
- 1992-01-24 JP JP3281892A patent/JP3349166B2/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7108014B2 (en) | 2002-04-26 | 2006-09-19 | Mikuni Corporation | Liquid diluting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05206620A (en) | 1993-08-13 |
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