JP3331666B2 - Solid-state imaging device and defect detection and correction method for solid-state imaging device - Google Patents
Solid-state imaging device and defect detection and correction method for solid-state imaging deviceInfo
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- JP3331666B2 JP3331666B2 JP07462893A JP7462893A JP3331666B2 JP 3331666 B2 JP3331666 B2 JP 3331666B2 JP 07462893 A JP07462893 A JP 07462893A JP 7462893 A JP7462893 A JP 7462893A JP 3331666 B2 JP3331666 B2 JP 3331666B2
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Description
【０００１】[0001]
【産業上の利用分野】本発明はＣＣＤ固体撮像素子等を
使用した固体撮像装置及び固体撮像装置の欠陥検出補正
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using a CCD solid-state imaging device and the like, and a method for detecting and correcting defects in the solid-state imaging device.
【０００２】[0002]
【従来の技術】一般にＣＣＤ等の半導体で形成した固体
撮像素子では、半導体の局部的な結晶欠陥等によって感
度が低下する欠陥画素が生じることがあり、このような
場合、その欠陥画素が画質を劣化させる原因となること
が知られている。この欠陥画素に起因する画質劣化をな
くすために、ＣＣＤ等を用いた固体撮像装置において従
来より欠陥補正が行われていた。2. Description of the Related Art In general, in a solid-state imaging device formed of a semiconductor such as a CCD, a defective pixel whose sensitivity is reduced due to a local crystal defect or the like of the semiconductor may occur. In such a case, the defective pixel reduces the image quality. It is known to cause deterioration. In order to eliminate image quality deterioration due to the defective pixels, defect correction has been conventionally performed in a solid-state imaging device using a CCD or the like.
【０００３】従来の欠陥補正においては、固体撮像素子
の出荷選別時に、その固体撮像素子に含まれる欠陥画素
を検出し、その欠陥画素に関する欠陥データをＲＯＭに
記憶させ、このＲＯＭをこの固体撮像素子と対にして出
荷し、通常の撮像時に、このＲＯＭに記憶保持された欠
陥データに基づいて、この固体撮像素子の欠陥画素を特
定し、その欠陥画素についての画素信号に対して欠陥補
正を行うようにしていた。In the conventional defect correction, a defective pixel included in the solid-state imaging device is detected when the solid-state imaging device is sorted for shipment, and defect data relating to the defective pixel is stored in a ROM. During normal imaging, a defective pixel of the solid-state imaging device is specified based on the defect data stored and held in the ROM, and defect correction is performed on a pixel signal of the defective pixel. Was like that.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
欠陥補正では、この固体撮像素子の出荷選別段階でＲＯ
Ｍに記憶保持した欠陥データを用いて欠陥補正を行うよ
うにしていたので、半導体の局部的な結晶欠陥等に伴う
画素欠陥には対応できるものの、この固体撮像素子のビ
デオカメラへの組込み時の静電破壊や、ビデオカメラの
搭載後の経時変化に伴う欠陥変化には対応できない不都
合があった。However, in the conventional defect correction, the RO is required at the stage of selecting the shipment of the solid-state imaging device.
Since the defect correction is performed using the defect data stored and held in M, it can cope with a pixel defect caused by a local crystal defect or the like of a semiconductor, but when this solid-state imaging device is incorporated into a video camera, There is an inconvenience that it cannot cope with electrostatic destruction or a defect change due to a temporal change after mounting a video camera.
【０００５】また、この固体撮像素子とＲＯＭとを対に
したものでは製造に手間がかかると共にこのＲＯＭが付
属となることから価格が高くなり、且つ全体のサイズが
大きくなる不都合があった。[0005] Further, in the case where the solid-state image pickup device and the ROM are paired, there is a problem that the production is troublesome and the ROM is attached, thereby increasing the price and increasing the overall size.
【０００６】本発明は斯る点に鑑み固体撮像素子と対と
なる欠陥データを記憶したＲＯＭを必要とすることな
く、欠陥画素を確実に補正できるようにすると共に静電
破壊や、ビデオカメラ搭載後の経時変化に伴う欠陥変化
にも対応できるようにすることを目的とする。In view of the above, the present invention makes it possible to reliably correct defective pixels without requiring a ROM storing defect data paired with a solid-state image pickup device, and to perform electrostatic destruction and video camera mounting. It is an object of the present invention to be able to cope with a defect change accompanying a later aging change.
【０００７】[0007]
【課題を解決するための手段】本発明固体撮像装置は、
例えば図１に示す如く、固体撮像素子１と、この固体撮
像素子１の出力信号が供給される欠陥補正回路２と、こ
の固体撮像素子１の出力信号に基づいて欠陥画素を検出
する欠陥検出回路３とを有し、この欠陥検出回路３の出
力信号に基づいてこの欠陥補正回路２でこの固体撮像素
子１の欠陥補正を行なうようにした固体撮像装置におい
て、この欠陥検出回路３は水平方向にｎ個の画素信号が
記憶できるメモリ３ａと、加算回路３ｂと、基準値と比
較する比較回路３ｃとを備え、奇数フィールドあるいは
偶数フィールドに対応する画素信号を水平方向にｎ個、
各フィールド毎に水平方向に１画素づつずらして選択
し、選択された画素信号とこのメモリ３ａに記憶されて
いる画素信号とを同じ画素位置からの画素信号同士を加
算し、加算した画素信号をフレーム毎に１画素づつ水平
方向にずらしてこのメモリ３ａに記憶することにより、
ずらす方向側の一番端に記憶されている（ｎ−１）回加
算された画素信号のレベルをこの比較回路３ｃで基準値
と比較して欠陥画素を検出するようにしたものである。
また、本発明固体撮像装置の欠陥検出補正方法は、固体
撮像素子１の出力信号を欠陥検出回路３に供給させ、こ
の欠陥検出回路３の出力信号に基づいて欠陥補正回路２
でこの固体撮像素子１の欠陥補正を行なうようにした固
体撮像装置の欠陥検出補正方法において、この欠陥検出
回路３は水平方向にｎ個の画素信号が記憶できるメモリ
３ａと、加算回路３ｂと、基準値と比較する比較回路３
ｃとを備え、奇数フィールドあるいは偶数フィールドに
対応する画素信号を水平方向にｎ個、各フィールド毎に
水平方向に１画素づつずらして選択し、選択された画素
信号とこのメモリ３ａに記憶されている画素信号とを同
じ画素位置からの画素信号同士を加算し、加算した画素
信号をフレーム毎に１画素づつ水平方向にずらしてこの
メモリ３ａに記憶することにより、ずらす方向側の一番
端に記憶されている（ｎ−１）回加算された画素信号の
レベルをこの比較回路３ｃで基準値と比較して欠陥画素
を検出するようにしたものである。According to the present invention, there is provided a solid-state imaging device comprising:
For example, as shown in FIG. 1, a solid-state imaging device 1, a defect correction circuit 2 to which an output signal of the solid-state imaging device 1 is supplied, and a defect detection circuit for detecting a defective pixel based on the output signal of the solid-state imaging device 1. In the solid-state imaging device, the defect correction circuit 2 corrects the defect of the solid-state imaging device 1 based on the output signal of the defect detection circuit 3. A memory 3a capable of storing n pixel signals, an adding circuit 3b, and a comparing circuit 3c for comparing with a reference value are provided, and n pixel signals corresponding to an odd field or an even field are arranged in the horizontal direction.
Each field is selected by shifting one pixel at a time in the horizontal direction, and the selected pixel signal and the pixel signal stored in the memory 3a are added together with pixel signals from the same pixel position, and the added pixel signal is output. By storing in this memory 3a by shifting in the horizontal direction one pixel at a time for each frame,
The level of the pixel signal added (n-1) times stored at the extreme end in the shifting direction is compared with a reference value by the comparison circuit 3c to detect a defective pixel.
Further, according to the defect detection and correction method of the solid-state imaging device of the present invention, an output signal of the solid-state imaging device 1 is supplied to a defect detection circuit 3, and a defect correction circuit 2 is provided based on the output signal of the defect detection circuit 3.
In the defect detection and correction method of the solid-state imaging device in which the defect correction of the solid-state imaging device 1 is performed, the defect detection circuit 3 includes a memory 3a capable of storing n pixel signals in a horizontal direction, an addition circuit 3b, Comparison circuit 3 for comparing with reference value
c, and selects n pixel signals corresponding to the odd field or the even field in the horizontal direction by shifting one pixel in the horizontal direction for each field, and stores the selected pixel signal and this memory signal in the memory 3a. The pixel signal from the same pixel position is added to the pixel signal that is present, and the added pixel signal is shifted in the horizontal direction one pixel at a time for each frame and stored in the memory 3a, so that the pixel signal at the extreme end in the shifting direction is stored. The comparator 3c compares the stored level of the pixel signal added (n-1) times with a reference value to detect a defective pixel.
【０００８】また、本発明固体撮像装置は例えば図１に
示す如く、上述において、加算回路３ｂの出力信号を平
均してこのメモリ３ａに記憶するようにしたものであ
る。Further, as shown in FIG. 1, for example, the solid-state imaging device of the present invention is such that the output signal of the addition circuit 3b is averaged and stored in the memory 3a.
【０００９】また、本発明固体撮像装置は、例えば図
１、図２に示す如く、メモリ３ａをｎ×ｍ個（ｎ及びｍ
は所定の正の整数）の画素信号が記憶できるものとし、
各フィールド毎に１画素信号づつずらした加算信号を順
次記憶するようにしたものである。In the solid-state imaging device according to the present invention, for example, as shown in FIGS. 1 and 2, n × m memories (n and m) are provided.
Is a predetermined positive integer).
An addition signal shifted by one pixel signal for each field is sequentially stored.
【００１０】[0010]
【作用】斯る本発明においては、固体撮像素子１よりの
出力信号より、欠陥画素を検出し、この検出された欠陥
画素に基づいて欠陥補正を行なっているので、固体撮像
素子１と対となる欠陥データを記憶したＲＯＭを必要と
することなく、欠陥画素を確実に補正できると共に静電
破壊や、ビデオカメラ搭載後の経時変化等に伴う欠陥変
化にも対応できる。In the present invention, a defective pixel is detected from an output signal from the solid-state imaging device 1 and defect correction is performed based on the detected defective pixel. It is possible to reliably correct defective pixels without requiring a ROM storing defective data, and to cope with electrostatic destruction and defect changes associated with aging after mounting a video camera.
【００１１】[0011]
【実施例】以下図面を参照して本発明固体撮像装置及び
固体撮像装置の欠陥検出補正方法の一実施例につき説明
する。図１において、１はＣＣＤ撮像素子を示し、被写
体からの入射光を撮像レンズ、光学フィルタを介して、
このＣＣＤ撮像素子１の撮像面に導く如くする。本例に
おいては説明を簡単にするため、このＣＣＤ撮像素子１
は白黒映像信号が得られるものとする。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a solid-state imaging device and a method for detecting and correcting defects in the solid-state imaging device according to the present invention. In FIG. 1, reference numeral 1 denotes a CCD image pickup device, which receives incident light from a subject through an image pickup lens and an optical filter.
The light is guided to the imaging surface of the CCD imaging device 1. In this example, for simplicity of explanation, this CCD image pickup device 1
Indicates that a monochrome video signal can be obtained.
【００１２】このＣＣＤ撮像素子１の電荷転送方式とし
て例えばインターライン転送方式とする。この場合はフ
ィールド毎に画素の加算する組み合わせが変わるので、
一つの画素に欠陥があっても、奇数フィールド及び偶数
フィールドの両フィールドに欠陥が現れるため、この両
フィールドで欠陥補正が必要である。The charge transfer system of the CCD 1 is, for example, an interline transfer system. In this case, the combination of pixel addition changes for each field,
Even if one pixel has a defect, a defect appears in both the odd field and the even field. Therefore, defect correction is necessary in both fields.
【００１３】このＣＣＤ撮像素子１の各画素の読出し
と、垂直及び水平転送の各駆動制御は、タイミング発生
回路４で発生される各種タイミング信号に基づいてドラ
イブ回路５によって行なわれる。このＣＣＤ撮像素子１
の撮像出力信号（ＣＣＤ出力信号）は、サンプルホール
ド回路６でサンプルホールドされ、かつＡ−Ｄ変換器７
でディジタル化された後、欠陥補正回路２及び欠陥検出
回路３に供給される。The reading of each pixel of the CCD image pickup device 1 and the driving control of vertical and horizontal transfer are performed by a drive circuit 5 based on various timing signals generated by a timing generation circuit 4. This CCD imaging device 1
The image pickup output signal (CCD output signal) is sampled and held by the sample and hold circuit 6 and the A / D converter 7
After that, it is supplied to the defect correction circuit 2 and the defect detection circuit 3.
【００１４】この欠陥補正回路２は欠陥検出回路３で検
出された欠陥画素について、リアルタイムで、その画素
信号を例えば前後の画素信号の平均値で置換するいわゆ
る平均値補間によって欠陥補正を行う。The defect correction circuit 2 performs defect correction on the defective pixel detected by the defect detection circuit 3 in real time by so-called average value interpolation in which the pixel signal is replaced with, for example, the average value of the preceding and succeeding pixel signals.
【００１５】次に本例の特徴とする欠陥検出回路３につ
き説明する。本例においてはＡ−Ｄ変換回路７の出力側
に得られるディジタル化された撮像出力信号をセレクタ
回路３ｄを介して加算回路３ｂ及びメモリ３ａに供給す
る如くする。Next, the defect detection circuit 3 which is a feature of the present embodiment will be described. In this example, the digitized image pickup output signal obtained at the output side of the A / D conversion circuit 7 is supplied to the addition circuit 3b and the memory 3a via the selector circuit 3d.
【００１６】このメモリ３ａとしては水平方向にｎ個及
び垂直方向にｍ個のｎ×ｍ個の画素信号を記憶できる如
くする。このｎを大きくすれば本例では加算平均するの
で、この加算平均する回数が増えるため、より検出精度
が向上し、このｍが大きくなれば一度に検査する領域が
増えるため、１画面をスキャン（検査）する時間を短く
することができる。しかしながら、このｎ，ｍの増大は
使用するメモリ３ａの容量を増加させるためあまり大き
くすることは好ましくない。本例においては、このメモ
リ３ａとして水平方向に５個の画素信号を記憶できる如
くすると共に垂直方向に３個の画素信号を記憶できる１
５個の記憶素子２０ａ，２０ｂ，‥‥２０ｅ、２１ａ，
‥‥２１ｅ、２２ａ，‥‥２２ｅより構成する。The memory 3a can store n × m pixel signals in the horizontal direction and m pixels in the vertical direction. If the value of n is increased, the averaging is performed in this example, so that the number of times of averaging is increased, so that the detection accuracy is further improved. If the value of m is increased, the area to be inspected at a time is increased. Inspection) can be shortened. However, it is not preferable to increase the values of n and m too much in order to increase the capacity of the memory 3a to be used. In the present embodiment, the memory 3a can store five pixel signals in the horizontal direction and can store three pixel signals in the vertical direction.
The five storage elements 20a, 20b, # 20e, 21a,
# 21e, 22a, and # 22e.
【００１７】この場合、本例においてはセレクタ３ｄは
フレーム毎に一方のフィールド例えば奇数フィールドの
画面における水平方向に５個、垂直方向に３個の計１５
個の画素信号をアドレスカウンタ３ｅの指示に従って通
過する如くする。この場合フレーム毎に水平方向に１画
素信号づつずらした１５個の画素信号を通過する如くす
る。In this case, in this example, the selector 3d has five fields in the horizontal direction and three fields in the vertical direction on a screen of one field, for example, an odd field every frame.
Pixel signals are passed according to the instruction of the address counter 3e. In this case, 15 pixel signals shifted by one pixel signal in the horizontal direction for each frame are passed.
【００１８】また本例においてはフレーム毎に、このセ
レクタ３ｄよりの１５個の画素信号とすでにメモリ３ａ
に記憶されている画素信号とを加算回路３ｂで加算し、
この加算回路３ｂよりの加算信号を平均回路３ｆで平均
して、メモリ３ａの所定の記憶素子に記憶する如くす
る。Also, in this embodiment, for each frame, 15 pixel signals from the selector 3d and the memory 3a
Is added by the addition circuit 3b to the pixel signal stored in
The addition signal from the addition circuit 3b is averaged by the averaging circuit 3f, and is stored in a predetermined storage element of the memory 3a.
【００１９】本例においては、セレクタ３ｇにより５回
加算した画素信号を選択し、選択された画素信号を時分
割で、基準レベルＶref 例えば平均画素レベルと比較す
る比較回路３ｃに順次供給する如くする。In the present embodiment, the selector 3g selects the pixel signal added five times, and sequentially supplies the selected pixel signal to the comparison circuit 3c which compares the selected pixel signal with a reference level Vref, for example, an average pixel level. I do.
【００２０】この比較回路３ｃにおいて欠陥画素を検出
したときには、その欠陥画素の位置をアドレスカウンタ
１０によりアドレス変換し、ＲＡＭ１１に格納し、補正
パルス発生回路より、このアドレスで補正パルスを欠陥
補正回路２に供給する如くする。この欠陥補正回路２で
欠陥補正された撮像出力信号は、信号処理回路８により
各種の信号処理が施されてビデオ信号としてビデオ出力
端子９に導出される。When a defective pixel is detected in the comparison circuit 3c, the address of the defective pixel is converted by the address counter 10 and stored in the RAM 11, and the correction pulse is supplied from the correction pulse generation circuit to the defect correction circuit 2 at this address. To be supplied. The imaging output signal corrected for defects by the defect correction circuit 2 is subjected to various kinds of signal processing by a signal processing circuit 8 and is derived to a video output terminal 9 as a video signal.
【００２１】ここでＣＣＤ撮像素子１から得られる画素
信号の空間的配列の一例は図４に示す如く、ｎ−１ライ
ンの画素信号がＡ11，Ａ12，Ａ13‥‥でｎラインの画素
信号がＡ21，Ａ22，Ａ23‥‥でｎ＋１ラインの画素信号
がＡ31，Ａ32，Ａ33‥‥であったとする。また、この図
４の空間的画素信号の配列においてｎラインの画素信号
Ａ25に対応する画素が欠陥であったとする。[0021] Here, one example of a spatial arrangement of the pixel signals obtained from the CCD image sensor 1 as shown in FIG. 4, n-1 line of pixel signals A 11, A 12, A 13 pixels n lines ‥‥ Assume that the signals are A 21 , A 22 , A 23 } and the pixel signals of the (n + 1) th line are A 31 , A 32 , A 33 }. Further, it is assumed that a pixel corresponding to the pixel signal A 25 on the n-th line in the spatial pixel signal array of FIG. 4 is defective.
【００２２】今、図２Ａに示す如くメモリ３ａの記憶素
子２０ａ，２０ｂ‥‥２０ｅに画素信号Ａ11，Ａ12‥‥
Ａ15、記憶素子２１ａ，２１ｂ‥‥２１ｅに画素信号Ａ
21，Ａ22‥‥Ａ25、記憶素子２２ａ，２２ｂ‥‥２２ｅ
に画素信号Ａ31，Ａ32‥‥Ａ35が記憶されていたとす
る。この場合セレクタ回路３ｄによる画素信号の選択は
フレーム毎に水平方向へ１画素づつずらして処理してい
るので、常にメモリ３ａの左端の列の記憶素子２０ａ，
２１ａ，２２ａに記憶されている画素信号が４回加算平
均された信号となっており、この左端の記憶素子２０
ａ，２１ａ，２２ａに記憶されている画素信号が検査信
号となる。Now, as shown in FIG. 2A, the pixel signals A 11 , A 12 } are stored in the storage elements 20a, 20b {20e} of the memory 3a.
A 15 , the pixel signal A is supplied to the storage elements 21a, 21b ‥‥ 21e.
21 , A 22 ‥‥ A 25 , storage elements 22a, 22b ‥‥ 22e
It is assumed that pixel signals A 31 and A 32 ‥‥ A 35 have been stored in the memory. In this case, the selection of the pixel signal by the selector circuit 3d is performed by shifting one pixel at a time in the horizontal direction for each frame, so that the storage elements 20a, 20a,
The pixel signals stored in the storage elements 21a and 22a are signals obtained by adding and averaging four times.
The pixel signals stored in a, 21a, and 22a are the inspection signals.
【００２３】この場合加算平均処理しているため、欠陥
画素に対応する画素信号は周囲の画素信号の平均画素レ
ベルよりも大きく（白点欠陥の場合）なり、ある基準レ
ベルＶref 例えばこの平均画素レベルよりも大きくな
り、欠陥画素を検出できる。In this case, since the averaging process is performed, the pixel signal corresponding to the defective pixel is larger than the average pixel level of the surrounding pixel signals (in the case of a white spot defect), and a certain reference level Vref, for example, this average pixel It becomes larger than the level, and a defective pixel can be detected.
【００２４】この画素信号Ａ25に対応する画素が欠陥で
あったときには図２Ａに示す如く右端の記憶素子２１ｅ
に記憶されており、次のフレームの奇数フィールドでは
図２Ｂに示す如くこの画素信号Ａ25は１回加算平均され
たものとなり、右端より２番目の記憶素子２１ｄに記憶
され、順次同様にして第４番目のフレームでは図２Ｃに
示す如く、この画素信号Ａ25は３回加算平均されたもの
となり、左端より２番目の記憶素子２１ｂに記憶され、
第５番目のフレームでは図２Ｄに示す如く、この画素信
号Ａ25は４回加算平均されたものとなり、左端の記憶素
子２１ａに記憶され、検査信号となる。その他の画素信
号も同様である。When the pixel corresponding to the pixel signal A 25 is defective, as shown in FIG. 2A, the rightmost storage element 21e
In the odd field of the next frame, as shown in FIG. 2B, the pixel signal A 25 is obtained by averaging once, and is stored in the second storage element 21d from the right end, and sequentially in the same manner. In the fourth frame, as shown in FIG. 2C, the pixel signal A 25 is obtained by averaging three times and stored in the second storage element 21b from the left end.
In the fifth frame, as shown in FIG. 2D, the pixel signal A 25 is obtained by averaging four times, stored in the leftmost storage element 21a, and becomes an inspection signal. The same applies to other pixel signals.
【００２５】この場合、記憶素子２０ａに記憶されてい
るｎ−１ライン目の画素信号Ａ15は欠陥画素に対応せ
ず、そのレベルは図３Ａに示す如く基準レベルＶref 以
下なので、比較回路３ｃでは欠陥画素とは判定されな
い。然しながら、記憶素子２１ａに記憶されているｎラ
イン目の画素信号Ａ25は欠陥画素に対応し、そのレベル
は図３Ｂに示す如く、基準レベルＶref 以上なので、比
較回路３ｃでは、欠陥画素と判定し、この欠陥画素の位
置をＲＡＭ１１に記憶する如くする。また記憶素子２２
ａに記憶されているｎ＋１ライン目の画素信号Ａ35は欠
陥画素に対応せず、そのレベルは図３Ｃに示す如く、基
準レベルＶref 以下なので、比較回路３ｃでは欠陥画素
とは判定されない。[0025] In this case, the pixel signal A 15 of n-1 th line stored in the storage device 20a does not correspond to the defective pixel, since the level is a following reference level V ref as shown in FIG. 3A, the comparison circuit 3c Is not determined to be a defective pixel. However, the pixel signal A 25 of the n-th line stored in the storage element 21a corresponds to the defective pixel, and its level is equal to or higher than the reference level Vref as shown in FIG. 3B. Then, the position of the defective pixel is stored in the RAM 11. The storage element 22
The pixel signal A 35 on the (n + 1) th line stored in “a” does not correspond to a defective pixel, and its level is equal to or lower than the reference level Vref, as shown in FIG. 3C. Therefore, the comparison circuit 3c does not determine that the pixel is defective.
【００２６】上述を奇数フィールド及び偶数フィールド
全域に亘って行い欠陥画素のアドレスをＲＡＭ１１に記
憶し、このＲＡＭ１１に記憶された欠陥画素のアドレス
に応じて補正パルスを欠陥補正回路２に送出して、欠陥
補正を行う如くする。The above operation is performed over the entire odd field and even field, the address of the defective pixel is stored in the RAM 11, and a correction pulse is sent to the defect correction circuit 2 in accordance with the address of the defective pixel stored in the RAM 11. Defect correction is performed.
【００２７】以上述べた如く、本例によれば固体撮像素
子１よりの撮像出力信号より欠陥画素を検出し、この検
出された欠陥画素に基づいて欠陥補正を行なうので、こ
の固体撮像素子１と対となる欠陥データを記憶したＲＯ
Ｍを必要とすることなく、欠陥画素を確実に補正できる
と共に静電破壊や、ビデオカメラ搭載後の経時変化等に
伴う欠陥変化にも対応できる利益がある。As described above, according to the present embodiment, a defective pixel is detected from an image output signal from the solid-state image sensor 1, and defect correction is performed based on the detected defective pixel. RO storing defect data to be paired
There is an advantage that the defective pixel can be surely corrected without requiring M, and that it can cope with a defect change due to an electrostatic destruction or a temporal change after mounting the video camera.
【００２８】また、本例においては欠陥検出回路３のメ
モリ３ａとして、ｎ×ｍ個例えば５×３個の画素信号を
記憶できる記憶素子より構成したものを使用する如くし
たので、このメモリ容量を非常に少なくでき、回路規
模、消費電力を小さくできる利益がある。In this embodiment, the memory 3a of the defect detection circuit 3 is constituted by a storage element capable of storing n × m pixel signals, for example, 5 × 3 pixel signals. There is an advantage that the circuit size and power consumption can be reduced very much.
【００２９】また本例においては欠陥検出回路３におい
て画素信号を所定フィールド例えば５フィールドに亘っ
て加算し、これにより欠陥画素を検出するので検出精度
が向上する利益がある。In this embodiment, the pixel signal is added over a predetermined field, for example, five fields in the defect detection circuit 3, and the defective pixel is detected by this.
【００３０】尚上述実施例においてはＣＣＤ撮像素子１
として白黒映像信号を得るものを使用した例につき述べ
たが、このＣＣＤ撮像素子としてカラーＣＣＤ撮像素子
を用いたときにおいても例えば現在の主流である補色市
松の色フィルタを用いた際にはインターライン転送方式
の読み出しにより各フィールドにおいて４種類の色加算
された出力信号が得られるが、同色信号のみを上述の同
様に処理すれば、上述と同様に欠陥画素を検出すること
ができ、上述同様の作用効果が得られることは容易に理
解できよう。この場合各フィールドの４色について平行
して同時処理するか、順番に処理するかはいずれも可能
である。このときの平行同時処理は総処理時間は短くな
るが、当然ながら回路規模が大きくなる。In the above embodiment, the CCD image pickup device 1
As described above, an example using a device that obtains a black-and-white video signal has been described. However, even when a color CCD image sensor is used as the CCD image sensor, for example, an interline Output signals obtained by adding four kinds of colors in each field are obtained by reading in the transfer method. If only the same color signals are processed in the same manner as described above, defective pixels can be detected in the same manner as described above, and the same as in the above-described manner. It can be easily understood that the effect is obtained. In this case, it is possible to simultaneously process the four colors of each field in parallel or to process them sequentially. At this time, the parallel simultaneous processing shortens the total processing time, but naturally increases the circuit scale.
【００３１】また上述実施例ではＣＣＤ撮像素子の白点
欠陥につき述べたが、黒点欠陥のときは図１実施例にお
ける比較回路３ｃにおいて、平均画素レベルに基づいて
決めた所定レベルに達しないときを欠陥と判定するよう
にすれば上述と同様に本例を適用できることは勿論であ
る。In the above-described embodiment, the white point defect of the CCD image pickup device has been described. However, in the case of a black point defect, the comparison circuit 3c in the embodiment of FIG. 1 determines when the predetermined level determined based on the average pixel level is not reached. If it is determined that a defect exists, the present embodiment can be applied similarly to the above.
【００３２】また本発明は上述実施例に限ることなく本
発明の要旨を逸脱することなくその他種々の構成が取り
得ることは勿論である。The present invention is not limited to the above-described embodiment, but may take various other configurations without departing from the gist of the present invention.
【００３３】[0033]
【発明の効果】以上述べた如く、本発明によれば固体撮
像素子１よりの撮像出力信号より欠陥画素を検出し、こ
の検出された欠陥画素に基づいて欠陥補正を行なうの
で、この固体撮像素子１と対となる欠陥データを記憶し
たＲＯＭを必要とすることなく、欠陥画素を確実に補正
できると共に静電破壊や、ビデオカメラ搭載後の経時変
化等に伴う欠陥変化にも対応できる利益がある。As described above, according to the present invention, a defective pixel is detected from an image output signal from the solid-state image sensor 1, and defect correction is performed based on the detected defective pixel. There is an advantage that the defective pixel can be surely corrected without the need of the ROM storing the defect data paired with 1, and also can cope with the electrostatic destruction and the defect change accompanying the aging change after mounting the video camera. .
【００３４】また本発明においては欠陥検出回路３のメ
モリ３ａとしてｎ×ｍ個例えば５×３個の画素信号を記
憶できる記憶素子より構成したものを使用する如くした
ので、このメモリ容量を非常に少なくでき、回路規模、
消費電力を小さくできる利益がある。In the present invention, the memory 3a of the defect detection circuit 3 is constituted by a memory element capable of storing n × m pixel signals, for example, 5 × 3 pixel signals. Circuit size,
There is an advantage that power consumption can be reduced.
【００３５】また本発明においては欠陥検出回路３にお
いて画素信号を所定フィールド例えば５フィールドに亘
って加算し、これにより欠陥画素を検出するので検出精
度が向上する利益がある。In the present invention, the pixel signal is added over a predetermined field, for example, 5 fields in the defect detection circuit 3, and the defective pixel is detected by this. Therefore, there is an advantage that the detection accuracy is improved.
【図１】本発明固体撮像装置の一実施例を示す構成図で
ある。FIG. 1 is a configuration diagram showing one embodiment of a solid-state imaging device of the present invention.
【図２】本発明の説明に供する線図である。FIG. 2 is a diagram for describing the present invention.
【図３】本発明の説明に供する線図である。FIG. 3 is a diagram for explanation of the present invention.
【図４】画素信号の空間的配列図である。FIG. 4 is a spatial arrangement diagram of pixel signals.
１ ＣＣＤ撮像素子 ２ 欠陥補正回路 ３ 欠陥検出回路 ３ａ メモリ ３ｂ 加算回路 ３ｃ 比較回路 ３ｄ，３ｇ セレクタ ３ｆ 平均回路 ８ 信号処理回路 １１ ＲＡＭ Reference Signs List 1 CCD image pickup device 2 Defect correction circuit 3 Defect detection circuit 3a Memory 3b Addition circuit 3c Comparison circuit 3d, 3g Selector 3f Average circuit 8 Signal processing circuit 11 RAM
Claims (3)
信号が供給される欠陥補正回路と、前記固体撮像素子の
出力信号に基づいて欠陥画素を検出する欠陥検出回路と
を有し、該欠陥検出回路の出力信号に基づいて前記欠陥
補正回路で前記固体撮像素子の欠陥補正を行なうように
した固体撮像装置において、 前記欠陥検出回路は水平方向にｎ個の画素信号が記憶で
きるメモリと、加算回路と、基準値と比較する比較回路
とを備え、奇数フィールドあるいは偶数フィールドに対
応する画素信号を水平方向にｎ個、各フィールド毎に水
平方向に１画素づつずらして選択し、選択された画素信
号と前記メモリに記憶されている画素信号とを同じ画素
位置からの画素信号同士を加算し、加算した画素信号を
フレーム毎に１画素づつ水平方向にずらして前記メモリ
に記憶することにより、ずらす方向側の一番端に記憶さ
れている（ｎ−１）回加算された画素信号のレベルを前
記比較回路で基準値と比較して欠陥画素を検出するよう
にしたことを特徴とする固体撮像装置。A solid-state imaging device, a defect correction circuit to which an output signal of the solid-state imaging device is supplied, and a defect detection circuit that detects a defective pixel based on an output signal of the solid-state imaging device. A solid-state imaging device configured to perform defect correction of the solid-state imaging device with the defect correction circuit based on an output signal of a defect detection circuit, wherein the defect detection circuit has a memory capable of storing n pixel signals in a horizontal direction; An adder circuit and a comparator circuit for comparing with a reference value are provided, and the pixel signals corresponding to the odd field or the even field are shifted by n pixels in the horizontal direction and by one pixel in the horizontal direction for each field, and are selected. A pixel signal and a pixel signal stored in the memory are added together with pixel signals from the same pixel position, and the added pixel signal is shifted horizontally by one pixel for each frame. By storing in the memory, the level of the pixel signal added (n-1) times stored at the extreme end on the shifting direction side is compared with a reference value by the comparison circuit to detect a defective pixel. A solid-state imaging device according to claim 1, wherein
るようにしたことを特徴とする固体撮像装置。2. The solid-state imaging device according to claim 1, wherein an output signal of said addition circuit is averaged and stored in said memory.
に供給させ、該欠陥検出回路の出力信号に基づいて欠陥
補正回路で前記固体撮像素子の欠陥補正を行なうように
した固体撮像装置の欠陥検出補正方法において、 前記欠陥検出回路は水平方向にｎ個の画素信号が記憶で
きるメモリと、加算回路と、基準値と比較する比較回路
とを備え、奇数フィールドあるいは偶数フィールドに対
応する画素信号を水平方向にｎ個、各フィールド毎に水
平方向に１画素づつずらして選択し、選択された画素信
号と前記メモリに記憶されている画素信号とを同じ画素
位置からの画素信号同士を加算し、加算した画素信号を
フレーム毎に１画素づつ水平方向にずらして前記メモリ
に記憶することにより、ずらす方向側の一番端に記憶さ
れている（ｎ−１）回加算された画素信号のレベルを前
記比較回路で基準値と比較して欠陥画素を検出するよう
にしたことを特徴とする固体撮像装置の欠陥検出補正方
法。3. A defect in a solid-state imaging device wherein an output signal of a solid-state imaging device is supplied to a defect detection circuit, and a defect correction circuit performs defect correction of the solid-state imaging device based on the output signal of the defect detection circuit. In the detection and correction method, the defect detection circuit includes a memory capable of storing n pixel signals in a horizontal direction, an addition circuit, and a comparison circuit for comparing with a reference value, and detects a pixel signal corresponding to an odd field or an even field. N pixels in the horizontal direction are selected by shifting one pixel in the horizontal direction for each field, and the selected pixel signal and the pixel signal stored in the memory are added with pixel signals from the same pixel position, By shifting the added pixel signal in the horizontal direction one pixel at a time for each frame and storing the shifted pixel signal in the memory, the (n-1) repetition stored at the extreme end in the shifting direction is stored. Defect detection and correction method of the solid-state imaging device is characterized in that to detect the defective pixel by comparing with the reference value level of the pixel signal in the comparator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07462893A JP3331666B2 (en) | 1993-03-31 | 1993-03-31 | Solid-state imaging device and defect detection and correction method for solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07462893A JP3331666B2 (en) | 1993-03-31 | 1993-03-31 | Solid-state imaging device and defect detection and correction method for solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06292088A JPH06292088A (en) | 1994-10-18 |
| JP3331666B2 true JP3331666B2 (en) | 2002-10-07 |
Family
ID=13552656
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07462893A Expired - Fee Related JP3331666B2 (en) | 1993-03-31 | 1993-03-31 | Solid-state imaging device and defect detection and correction method for solid-state imaging device |
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|---|---|---|---|---|
| US5854655A (en) * | 1995-08-29 | 1998-12-29 | Sanyo Electric Co., Ltd. | Defective pixel detecting circuit of a solid state image pick-up device capable of detecting defective pixels with low power consumption and high precision, and image pick-up device having such detecting circuit |
| US6002433A (en) * | 1995-08-29 | 1999-12-14 | Sanyo Electric Co., Ltd. | Defective pixel detecting circuit of a solid state image pick-up device capable of detecting defective pixels with low power consumption and high precision, and image pick-up device having such detecting circuit |
| KR100340052B1 (en) * | 1998-06-30 | 2002-07-18 | 박종섭 | Image sensor |
| JP5346781B2 (en) * | 2009-11-17 | 2013-11-20 | 能美防災株式会社 | Apparatus and method for identifying missing element position of infrared camera |
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1993
- 1993-03-31 JP JP07462893A patent/JP3331666B2/en not_active Expired - Fee Related
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