JP3313566B2 - Diode manufacturing method - Google Patents
Diode manufacturing methodInfo
- Publication number
- JP3313566B2 JP3313566B2 JP05578296A JP5578296A JP3313566B2 JP 3313566 B2 JP3313566 B2 JP 3313566B2 JP 05578296 A JP05578296 A JP 05578296A JP 5578296 A JP5578296 A JP 5578296A JP 3313566 B2 JP3313566 B2 JP 3313566B2
- Authority
- JP
- Japan
- Prior art keywords
- diode
- glass
- manufacturing
- glass film
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に係り、特に逆方向リーク電流が低減できるダイオ
ードの製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a diode capable of reducing a reverse leakage current.
【０００２】[0002]
【従来の技術】メサ型半導体装置（少なくとも１個のｐ
ｎ接合が主表面からエッチングによって溝が形成され、
溝の側壁にｐｎ接合が露出する半導体装置）を高耐圧化
するために従来から種々の技術が提案されている。2. Description of the Related Art A mesa type semiconductor device (at least one p
A groove is formed by etching the n-junction from the main surface,
Conventionally, various techniques have been proposed to increase the breakdown voltage of a semiconductor device in which a pn junction is exposed on the side wall of a groove.
【０００３】例えば、メサ型の半導体装置の高耐圧化に
関する従来技術として、特開昭60−186071号公報に記載
された技術が知られている。この従来技術は、メサ溝内
壁をガラスで被覆した半導体装置の製造方法において、
メサ溝を形成した後に熱処理等により、ｐｎ接合部を当
初の位置より移動させることにより、高耐圧が得られる
とされている。[0003] For example, a technique described in Japanese Patent Application Laid-Open No. 60-186071 is known as a conventional technique for increasing the breakdown voltage of a mesa type semiconductor device. This prior art relates to a method of manufacturing a semiconductor device in which a mesa groove inner wall is covered with glass,
It is said that a high breakdown voltage can be obtained by moving the pn junction from an initial position by heat treatment or the like after forming the mesa groove.
【０００４】さらに、メサ型の半導体装置の高耐圧化に
関する他の従来技術として、特開平7−221049 号公報に
記載された技術が知られている。この従来技術は、一定
の幅内に隣接する２つのメサ溝の中間に凸状の部分を設
け、この凸状の部分が半導体基板の表面よりも低くなる
ようにエッチングにより形成することにより、ダイシン
グ時にガラス内部にクラックが入らないようにでき、信
頼性と高耐圧化が図れるものとされている。Further, as another conventional technique for increasing the breakdown voltage of a mesa type semiconductor device, the technique described in Japanese Patent Application Laid-Open No. 7-221049 is known. In this prior art, dicing is performed by providing a convex portion in the middle of two adjacent mesa grooves within a certain width, and forming the convex portion by etching so as to be lower than the surface of the semiconductor substrate. At times, cracks can be prevented from entering the inside of the glass, and reliability and high withstand voltage can be achieved.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来技術では、ダイオードに逆バイアス電圧が印加される
阻止状態において、メサ部分の半導体表面に形成される
反転層によるチャネル電流によるリーク電流増大に関す
る問題については考慮されていなかった。However, in the above-mentioned prior art, there is a problem relating to an increase in leakage current due to a channel current due to an inversion layer formed on a semiconductor surface of a mesa in a blocking state in which a reverse bias voltage is applied to a diode. Was not taken into account.
【０００６】本発明の目的は、従来の製造方法の問題点
を解決した半導体装置の製造方法を提供することにあ
る。An object of the present invention is to provide a method of manufacturing a semiconductor device which solves the problems of the conventional manufacturing method.
【０００７】本発明の目的を具体的に言えば、高い逆方
向電圧が印加された阻止状態でのリーク電流を低減でき
るダイオードの製造方法を提供することにある。More specifically, an object of the present invention is to provide a method of manufacturing a diode which can reduce a leak current in a blocking state to which a high reverse voltage is applied.
【０００８】[0008]
【課題を解決するための手段】かかる目的を達成するた
めに本発明は、一対の主表面を有し、一方の主表面から
基板と反対導電型の不純物を拡散してｐｎ接合を形成し
た後に、一方の主表面から所定の領域にｐｎ接合が露出
するようメサ型に溝を設け、このメサ部にガラス被膜が
形成されているダイオードの製造方法において、鉛系ガ
ラス被膜を形成した後に水素あるいは水素を含むガス中
でアニールすることにより、上記ガラス膜中の電荷の極
性を等価的に正にするようにしたものである。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor device having a pair of main surfaces and forming a pn junction by diffusing impurities of the opposite conductivity type from the substrate from one of the main surfaces. In a diode manufacturing method in which a mesa-shaped groove is provided so that a pn junction is exposed in a predetermined region from one main surface, and a glass film is formed on the mesa portion, hydrogen or hydrogen is formed after forming a lead-based glass film. By annealing in a gas containing hydrogen, the polarity of the charge in the glass film is made equivalently positive.
【０００９】さらに、メサ部を形成した後に酸素を含む
ガス中で酸化し、その後鉛系ガラス被膜を形成した後に
水素あるいは水素を含むガス中でアニールすることによ
り、ガラス膜中の電荷の極性を一層正にするようにした
ものである。Further, after the mesa portion is formed, the film is oxidized in a gas containing oxygen, and thereafter, a lead-based glass film is formed and then annealed in hydrogen or a gas containing hydrogen, whereby the polarity of the charge in the glass film is reduced. It is intended to be more positive.
【００１０】さらに、上記の製造方法において、ダイオ
ードの逆方向電圧−電流波形の内、低電圧領域における
オーミック特性が０.１Ｖ 以下となるようにしたもので
ある。Further, in the above-mentioned manufacturing method, the ohmic characteristics in a low voltage region of the reverse voltage-current waveform of the diode are set to 0.1 V or less.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施例について説
明する。Embodiments of the present invention will be described below.
【００１２】（実施例１）本実施例では、シリコン基板
してＣＺ（１１１）のｎ型３５〜４５Ωcmを用い、一方
の主表面からＵ０１エッチャントで約６０μｍエッチン
グし表面を水洗し乾燥した後、スクリーン印刷法により
ペースト状の鉛系ガラス（主成分：ＰｂＯ，ＳｉＯ2，
Ａｌ2Ｏ3)を５０μｍ塗布した。次に、ガラス焼成とし
て酸素雰囲気中で８００〜８５０℃，４０分の熱処理を
した。その後、Ａｌをマスク蒸着して、ＭＩＳダイオー
ドを作製した。(Embodiment 1) In this embodiment, CZ (111) n-type 35-45Ωcm is used as a silicon substrate, and one main surface is etched by about 60 μm with a U01 etchant, and the surface is washed with water and dried. Lead-based paste glass (main component: PbO, SiO 2 ,
Al 2 O 3 ) was applied in a thickness of 50 μm. Next, heat treatment was performed at 800 to 850 ° C. for 40 minutes in an oxygen atmosphere as glass firing. Then, Al was vapor-deposited by a mask to produce a MIS diode.
【００１３】図１はガラス焼成後の水素アニール工程に
よる電荷密度の変化を示す。ここで言う電荷密度とは、
ガラス中のトラップ電荷，可動電荷，ガラスとシリコン
界面近傍の固定電荷，ガラスとシリコン界面の界面トラ
ップ電荷が半導体表面に実質的に影響するものと考え、
デルタ関数的にガラスとシリコン界面のガラス側に存在
しているとみなした単位面積当りの正味の電荷密度のこ
とを示す。図１から明らかなように、ガラス焼成後で
は、電荷密度Ｎは負の極性を示しその値は−８±２×１
０11／cm2であったのに対して、低温Ｈ2アニール（４１
０±１０℃，１０〜２０分)を１回行えば、、電荷密度
Ｎはやはり負の極性を示しその値は−６.２±１.８×１
０11／cm2と約１.８×１０11／cm2正方向にシフトし、
上記低温Ｈ2アニールを２回行うと、電荷密度Ｎはさら
に２.２×１０11／cm2正方向にシフトし、−３.８±１.
８×１０11／cm2の値を示した。ところが、高温Ｈ2アニ
ール（６２０±２０℃，１０〜２０分）を行うと、電荷
密度Ｎは正の極性を有し、その値は２.３±１.８×１０
11／cm2 の値を示した。このように、鉛系ガラスでシリ
コン表面を被覆した場合、ガラス中の電荷密度はガラス
焼成後で負の極性で絶対値が大きかったが、Ｈ2 アニー
ルを行うことにより、同じく負の極性を有しても絶対値
が小さくなったり、正の極性をもたらすことができるこ
とがわかった。さらに、この傾向は水素を含む、例え
ば、水素が１０〜５０％，窒素が５０〜９０％の混合ガ
ス中でアニールしても同様の効果があることを確認し
た。FIG. 1 shows the change in charge density due to the hydrogen annealing step after firing the glass. The charge density mentioned here is
Considering that the trapped charge in the glass, the mobile charge, the fixed charge near the glass-silicon interface, and the interface trap charge at the glass-silicon interface substantially affect the semiconductor surface.
It shows the net charge density per unit area that is considered to be present on the glass side of the glass-silicon interface in a delta function. As is clear from FIG. 1, after firing the glass, the charge density N shows a negative polarity, and the value is -8 ± 2 × 1.
0 11 / cm 2 , whereas low-temperature H 2 annealing (41
(0 ± 10 ° C., 10 to 20 minutes), the charge density N still shows a negative polarity, and the value is −6.2 ± 1.8 × 1.
0 11 / cm 2 and about 1.8 × 10 11 / cm 2 shift in the positive direction,
When the low-temperature H 2 annealing is performed twice, the charge density N further shifts in the positive direction of 2.2 × 10 11 / cm 2 to −3.8 ± 1.
The value was 8 × 10 11 / cm 2 . However, when high-temperature H 2 annealing (620 ± 20 ° C., 10 to 20 minutes) is performed, the charge density N has a positive polarity, and its value is 2.3 ± 1.8 × 10
The value of 11 / cm 2 was shown. Thus, when coated with a silicon surface with lead-based glass, the charge density in the glass was greater absolute value in the negative polarity after the glass firing, by performing of H 2 anneal, also have a negative polarity However, it was found that the absolute value could be reduced or a positive polarity could be provided. Further, it has been confirmed that this tendency has the same effect even when annealing is performed in a mixed gas containing hydrogen, for example, a mixed gas containing 10 to 50% of hydrogen and 50 to 90% of nitrogen.
【００１４】図２はガラス焼成後の水素アニール工程に
よるｐｎダイオードの逆方向印加電圧が４００Ｖでのリ
ーク電流の変化を示す。図２の横軸にはガラス焼成後の
リーク電流の値、縦軸にはＨ2 アニール後でのリーク電
流の値を示す。図２の線Ｉはガラス焼成後の値でばらつ
いているが、Ｈ2 アニール後の値との比較のために示し
たものであり、縦軸及び横軸での値は等しい。線IIは低
温Ｈ2アニール(４１０±１０℃，１０〜２０分）を１回
行った時のリーク電流の変化を示し、初期値すなわちガ
ラス焼成後では５００ｎＡ前後の値を示していたもの
が、２００ｎＡ程度に低減できている。線IIIは低温Ｈ2
アニール(４１０±１０℃，１０〜２０分)を２回行った
時のリーク電流の変化を示し、初期値すなわちガラス焼
成後では５００ｎＡ前後の値を示していたものが、１０
０ｎＡ程度に低減できており、低温Ｈ2 アニールでも回
数を増やせば、一層リーク電流を低減できることが判
る。さらに、線IVが示すように、高温Ｈ2 アニール（６
２０±２０℃，１０〜２０分）を行うと、リーク電流は
ガラス焼成後で６０〜６８０ｎＡとばらついていた値が
すべて２０ｎＡ以下と大幅に低減でき、高温アニールが
リーク電流低減に極めて有効であることが明らかであろ
う。FIG. 2 shows the change in the leakage current when the reverse applied voltage of the pn diode is 400 V in the hydrogen annealing step after firing the glass. The horizontal axis in FIG. 2 shows the value of the leak current after firing the glass, and the vertical axis shows the value of the leak current after H 2 annealing. The line I in FIG. 2 varies with the value after firing the glass, but is shown for comparison with the value after H 2 annealing, and the values on the vertical and horizontal axes are equal. Line II shows the change in leakage current when a single low-temperature H 2 anneal (410 ± 10 ° C., 10 to 20 minutes) was performed. The initial value, that is, the value around 500 nA after firing the glass, was shown. It can be reduced to about 200 nA. Line III is low temperature H 2
The change in the leakage current when annealing (410 ± 10 ° C., 10 to 20 minutes) was performed twice, and the initial value, that is, a value around 500 nA after firing the glass, was 10%.
It can be seen that the leakage current can be further reduced by increasing the number of times even in low-temperature H 2 annealing even when the annealing is performed at a low temperature of about 2 nA. Further, as indicated by line IV, the high temperature H 2 anneal (6
(20 ± 20 ° C., 10 to 20 minutes), the leakage current, which fluctuates from 60 to 680 nA after firing the glass, can be greatly reduced to 20 nA or less, and high-temperature annealing is extremely effective in reducing the leakage current. It will be clear.
【００１５】図３はガラス焼成後の水素アニール工程に
よるｐｎダイオードの逆方向電圧−電流波形の変化を示
す図である。図３において、特性Ｉ，II，III 及びIVは
それぞれガラス焼成後、低温Ｈ2アニールを１回実施
後、低温Ｈ2アニールを２回実施後及び高温Ｈ2 アニー
ル後での逆方向電圧−電流波形を示す。特性Ｉが示すよ
うにガラス焼成後において、逆方向印加電圧ＶR が４０
０Ｖでのリーク電流（図中■印で示す）が多いのは、逆
方向印加電圧ＶR が約２Ｖ以下の低電圧領域でリーク電
流が逆方向印加電圧に対してオーミック法則により流れ
ていることによることは明らかである。低温Ｈ2 アニー
ルを１回さらに２回実施すると、逆方向印加電圧ＶR が
４００Ｖでのリーク電流（図中●及び▲印で示す）の値
は、ガラス焼成後よりさらに低減でき、同時に低電圧領
域でオーミック法則からずれる電圧値は約１Ｖ，０.８
Ｖ と低下していることが判る。FIG. 3 is a diagram showing a change in the reverse voltage-current waveform of the pn diode due to the hydrogen annealing step after firing the glass. 3, characteristics I, II, after each III and IV glass firing, after performing once cold H 2 anneal, reverse voltage of cold H 2 anneal after performed twice and after the high temperature H 2 anneal - Current The waveform is shown. After the glass calcined as indicated characteristic I, the reverse applied voltage V R 40
The leakage current (indicated in the drawing ■ mark) often at 0V is a reverse applied voltage V R is flowing through ohmic law against leakage currents reverse applied voltage in a low voltage region of about 2V or less Obviously. When implemented once twice more cold H 2 anneal, the value of the reverse applied voltage V R is the leakage current at 400V (in the figure indicated by ● and ▲ marks) further be reduced than after the glass firing, at the same time a low voltage The voltage value deviating from the ohmic law in the region is about 1 V, 0.8
It can be seen that V has decreased.
【００１６】このことは、ガラス焼成後や低温Ｈ2 アニ
ールを１回さらに２回実施した場合は、図１で示したよ
うに電荷密度が負の極性を有しており、ｎ型半導体領域
表面にｐ型反転層が形成されることによるためである。
ところが、特性IVが示すように、高温Ｈ2 アニール後で
は逆方向印加電圧が４００Ｖでのリーク電流（図中○印
で示す）はガラス焼成後と比べて、約２桁も少なくなり
極めて高温Ｈ2 アニールがリーク電流の低減に効果があ
ることが理解できる。同時に低電圧領域でオーミック法
則からずれる電圧値は約０.０４Ｖ と極めて小さな値を
示していることから、低電圧領域からのオーミック伝導
を抑制することがリーク電流低減にもっとも効果的であ
ることが判った。このことは、ガラス焼成後に高温Ｈ2
アニールを実施した場合は、図１で示したように電荷密
度が正の極性を有しており、ｎ型半導体領域表面にはｐ
型反転層が形成されなく、蓄積層が存在していることを
示している。なお、発明者等は、低電圧領域でオーミッ
ク法則からずれる電圧値が約０.１Ｖ 以下となるよう高
温Ｈ2 アニール、あるいは窒素と水素の混合ガス中での
高温アニールを実施することにより、極めてリーク電流
の値を少なくでき、生産性を大幅に向上できることを確
認した。This means that the charge density has a negative polarity as shown in FIG. 1 when the glass is fired or when low-temperature H 2 annealing is performed once or twice, and the n-type semiconductor region surface This is because a p-type inversion layer is formed on the substrate.
However, as shown by the characteristic IV, the leakage current (indicated by a circle in the figure) at a reverse applied voltage of 400 V after the high-temperature H 2 annealing was reduced by about two orders of magnitude compared to that after the glass firing, and the extremely high-temperature H 2 It can be understood that annealing is effective in reducing the leak current. At the same time, the voltage value deviating from the ohmic law in the low-voltage region is as extremely small as about 0.04 V. Therefore, it is most effective to suppress the ohmic conduction from the low-voltage region to reduce the leak current. understood. This high temperature H 2 after glass baking
When the annealing is performed, the charge density has a positive polarity as shown in FIG.
This shows that the pattern inversion layer is not formed and the accumulation layer exists. Incidentally, the present inventors have performed extremely high-temperature H 2 annealing or high-temperature annealing in a mixed gas of nitrogen and hydrogen so that the voltage value deviating from the ohmic law in the low-voltage region is about 0.1 V or less. It has been confirmed that the value of the leak current can be reduced and the productivity can be greatly improved.
【００１７】（実施例２）次に、本発明を適用したダイ
オードの実施例について図４を用いて説明する。（ａ）
は本発明を適用したダイオードの実施例であり、ＣＺ
（１１１）のｎ型３５〜４５Ωcmのｎ型半導体領域１の
一方の主表面に高不純物濃度のｐ+ 型半導体領域２を形
成し、他方の主表面に高不純物濃度のｎ+ 型半導体領域
３を形成し、一方の主表面から所定の領域にｐｎ接合が
露出するようＵ０１エッチャントで約６０μｍエッチン
グしメサ溝を設け、このメサ部に鉛系ガラスをスクリー
ン印刷法によりペースト状の鉛系ガラス４(主成分：Ｐ
ｂＯ，ＳｉＯ2，Ａｌ2Ｏ3）を５０μｍ塗布した。次
に、ガラス焼成として酸素雰囲気中で８００〜８５０
℃，４０分の熱処理をした後、Ｃｒ−Ｎｉ−Ａｇ電極を
通常のホトリソグラフィと蒸着及びリフトオフにより、
アノード電極２０及びカソード電極３０を形成してダイ
オードを作製した。その後、本発明による低温Ｈ2アニ
ールや高温Ｈ2アニールを施し、電荷密度が正で低電圧
領域におけるオーミック伝導が０.１Ｖ 以下となるよう
にした。本実施例を用いたダイオードの耐圧は約８００
Ｖであり、リーク電流も逆方向印加電圧が４００Ｖで１
０ｎＡ以下となり、極めて阻止特性の優れた半導体装置
の製造方法であることを確認した。さらに、高温逆バイ
アス試験（ＤＣ４００Ｖ，接合温度１５０℃，時間１０
００ｈ）を実施したが、リーク電流は初期値の５０％増
加にとどまり、高信頼性を示すことを確認した。(Embodiment 2) Next, an embodiment of a diode to which the present invention is applied will be described with reference to FIG. (A)
Is an embodiment of a diode to which the present invention is applied.
A high impurity concentration p @ + type semiconductor region 2 is formed on one main surface of a (111) n type 35-45 .OMEGA.cm n-type semiconductor region 1, and a high impurity concentration n @ + type semiconductor region 3 is formed on the other main surface. Is formed by etching about 60 μm with a U01 etchant so that a pn junction is exposed in a predetermined region from one main surface, and a mesa groove is provided. (Main component: P
bO, SiO 2 , Al 2 O 3 ) was applied in a thickness of 50 μm. Next, 800 to 850 in an oxygen atmosphere as glass firing.
After performing a heat treatment at 40 ° C. for 40 minutes, the Cr—Ni—Ag electrode is subjected to ordinary photolithography, vapor deposition and lift-off.
A diode was fabricated by forming the anode electrode 20 and the cathode electrode 30. Then subjected to cold H 2 annealing or high temperature H 2 annealing according to the invention, the charge density ohmic conduction in the low voltage region a positive is set to be 0.1V or less. The withstand voltage of the diode using this embodiment is about 800
V, and the leak current is 1 at 400 V applied in the reverse direction.
It was 0 nA or less, and it was confirmed that this was a method for manufacturing a semiconductor device having extremely excellent blocking characteristics. Further, a high temperature reverse bias test (DC 400 V, junction temperature 150 ° C., time 10
00h), it was confirmed that the leak current was increased by only 50% of the initial value, indicating high reliability.
【００１８】（実施例３）（ｂ）は本発明を適用したダ
イオードの他の実施例であり、ＣＺ（１１１）のｎ型３
５〜４５Ωcmのｎ型半導体領域１の一方の主表面に高不
純物濃度のｐ+ 型半導体領域２を形成し、他方の主表面
に高不純物濃度のｎ+ 型半導体領域３を形成し、一方の
主表面から所定の領域にｐｎ接合が露出するようＵ０１
エッチャントで約６０μｍエッチングしメサ溝を設け、
その後、ドライ酸素雰囲気内あるいはウェット雰囲気
（水素と酸素からなる）内で熱処理をして５０ｎｍ〜２
μｍのＳｉＯ2膜を形成し、実質的に電荷密度をガラス
焼成後より約２×１０11／cm2正の方向にした。続い
て、このメサ部に鉛系ガラスをスクリーン印刷法により
ペースト状の鉛系ガラス４(主成分：ＰｂＯ，ＳｉＯ2，
Ａｌ2Ｏ3）を５０μｍ塗布した。次に、ガラス焼成とし
て酸素雰囲気中で８００〜８５０℃，４０分の熱処理を
した後、Ｃｒ−Ｎｉ−Ａｇ電極を通常のホトリソグラフ
ィと蒸着及びリフトオフにより、アノード電極２０及び
カソード電極３０を形成してダイオードを作製した。そ
の後、本発明による低温Ｈ2アニールや高温Ｈ2アニール
を施し、電荷密度が正で低電圧領域におけるオーミック
伝導が０.１Ｖ 以下となるようにした。本実施例を用い
たダイオードの耐圧は約７５０Ｖであり、リーク電流も
逆方向印加電圧が４００Ｖで５ｎＡ以下となり、極めて
阻止特性の優れた半導体装置の製造方法であることを確
認した。さらに、高温逆バイアス試験（ＤＣ４００Ｖ，
接合温度１５０℃，時間１０００ｈ）を実施したが、リ
ーク電流は初期値の３０％増加にとどまり、一層高信頼
性を示すことを確認した。(Embodiment 3) (b) is another embodiment of the diode to which the present invention is applied, and is an n-type 3 of CZ (111).
A high impurity concentration p + -type semiconductor region 2 is formed on one main surface of an n-type semiconductor region 1 of 5 to 45 Ωcm, and a high impurity concentration n + -type semiconductor region 3 is formed on the other main surface. U01 such that the pn junction is exposed in a predetermined region from the main surface.
Approximately 60 μm etched with an etchant to provide mesa grooves,
Thereafter, a heat treatment is performed in a dry oxygen atmosphere or a wet atmosphere (composed of hydrogen and oxygen) to a thickness of 50 nm to 2 nm.
A SiO 2 film having a thickness of μm was formed, and the charge density was substantially set to about 2 × 10 11 / cm 2 in the positive direction after firing the glass. Subsequently, a lead-based glass 4 (main component: PbO, SiO 2 ,
Al 2 O 3 ) was applied in a thickness of 50 μm. Next, after performing a heat treatment at 800 to 850 ° C. for 40 minutes in an oxygen atmosphere as glass firing, an anode electrode 20 and a cathode electrode 30 are formed on the Cr—Ni—Ag electrode by ordinary photolithography, vapor deposition, and lift-off. To produce a diode. Then subjected to cold H 2 annealing or high temperature H 2 annealing according to the invention, the charge density ohmic conduction in the low voltage region a positive is set to be 0.1V or less. The withstand voltage of the diode using this example was about 750 V, and the leak current was 5 nA or less at a reverse applied voltage of 400 V. It was confirmed that the method was a method of manufacturing a semiconductor device having extremely excellent blocking characteristics. Furthermore, a high temperature reverse bias test (DC400V,
A junction temperature of 150 ° C. and a time of 1000 h) were performed, but it was confirmed that the leak current was increased by only 30% from the initial value, indicating higher reliability.
【００１９】[0019]
【発明の効果】このようにして、本発明の製造方法によ
れば、鉛系ガラスで被覆されたメサ型ダイオードにおい
て、正味の電荷密度の極性を正にし、逆方向電圧−電流
波形においてオーミック法則により流れるリーク電流を
印加電圧の０.１Ｖ 以下の低電圧領域にすることによ
り、高耐圧でリーク電流の極めて少ないダイオードを製
造可能とすることができる。As described above, according to the manufacturing method of the present invention, in the mesa diode covered with the lead-based glass, the polarity of the net charge density is made positive, and the ohmic law in the reverse voltage-current waveform is obtained. , A diode having a high breakdown voltage and an extremely small leak current can be manufactured.
【図１】本発明による実施例における水素アニール工程
と安定化膜中の電荷密度の関係を示す図。FIG. 1 is a diagram showing a relationship between a hydrogen annealing step and a charge density in a stabilizing film in an example according to the present invention.
【図２】本発明による実施例における水素アニール前後
でのリーク電流の低減効果を示す図。FIG. 2 is a diagram showing the effect of reducing leakage current before and after hydrogen annealing in an example according to the present invention.
【図３】本発明による実施例における水素アニール前後
での逆方向電圧−電流波形の変化を示す図。FIG. 3 is a diagram showing a change in a reverse voltage-current waveform before and after hydrogen annealing in an example according to the present invention.
【図４】本発明による実施例を適用したダイオードの断
面図。FIG. 4 is a sectional view of a diode to which an embodiment according to the present invention is applied.
１…ｎ型半導体領域、２…ｐ+ 型半導体領域、３…ｎ+
型半導体領域、４…鉛系ガラス、５…二酸化珪素、２０
…アノード電極、３０…カソード電極。1 ... n-type semiconductor region, 2 ... p + -type semiconductor region, 3 ... n +
Semiconductor region, 4 lead glass, 5 silicon dioxide, 20
... Anode electrode, 30 ... Cathode electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佃 清 茨城県日立市幸町三丁目１番１号 株式 会社 日立製作所 日立工場内 (72)発明者 菅野 実 茨城県日立市弁天町三丁目10番２号 日 立原町電子工業株式会社内 (72)発明者 小林 五月 茨城県日立市弁天町三丁目10番２号 日 立原町電子工業株式会社内 (56)参考文献 特開 昭53−96765（ＪＰ，Ａ) 特開 昭61−226931（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 H01L 23/30 H01L 29/861 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoshi Tsukuda 3-1-1, Sachimachi, Hitachi-shi, Ibaraki Pref. Hitachi, Ltd. Hitachi Plant (72) Inventor Minoru Sugano 3-chome, Bentencho, Hitachi-shi, Ibaraki No. 2 Inside Tachihara-cho Electronics Co., Ltd. (72) Inventor May Kobayashi 3-10-2 Bentencho, Hitachi City, Ibaraki Prefecture Inside Tachihara-cho Electronics Co., Ltd. (56) References JP-A-53-96765 JP, A) JP-A-61-226931 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 H01L 23 / 30 H01L 29/861
Claims (3)
板と反対導電型の不純物を拡散してｐｎ接合を形成した
後に、一方の主表面から所定の領域にｐｎ接合が露出す
るようメサ型に溝を設け、このメサ部にガラス被膜が形
成されているダイオードの製造方法において、鉛系ガラ
ス被膜を形成した後に水素あるいは水素を含むガス中で
アニールすることにより、上記ガラス膜中の電荷の極性
を等価的に正にすることを特徴とするダイオードの製造
方法。An pn junction is formed in a predetermined region from one main surface after forming a pn junction by diffusing an impurity of a conductivity type opposite to that of a substrate from one main surface. In a method of manufacturing a diode in which a groove is formed in a mesa mold and a glass film is formed on the mesa portion, the lead-based glass film is formed and then annealed in hydrogen or a gas containing hydrogen to form a glass film. A method of manufacturing the diode, wherein the polarity of the electric charge of the diode is made equivalently positive.
板と反対導電型の不純物を拡散してｐｎ接合を形成した
後に、一方の主表面から所定の領域にｐｎ接合が露出す
るようメサ型に溝を設け、このメサ部にガラス被膜が形
成されているダイオードの製造方法において、メサ部を
形成した後に酸素を含むガス中で酸化し、その後鉛系ガ
ラス被膜を形成した後に水素あるいは水素を含むガス中
でアニールすることにより、ガラス膜中の電荷の極性を
等価的に正にすることを特徴とするダイオードの製造方
法。2. A semiconductor device comprising: a pair of main surfaces; a pn junction formed by diffusing impurities of the opposite conductivity type from the substrate from one main surface to form a pn junction; In a method of manufacturing a diode in which a groove is formed in a mesa mold and a glass film is formed on the mesa portion, the mesa portion is formed, then oxidized in a gas containing oxygen, and then a lead-based glass film is formed and then hydrogen is formed. Alternatively, a method for manufacturing a diode, wherein the polarity of the charge in the glass film is made equivalently positive by annealing in a gas containing hydrogen.
て、ダイオードの逆方向電圧−電流波形の内、低電圧領
域におけるオーミック特性が０.１Ｖ 以下であることを
特徴とするダイオードの製造方法。3. A diode according to claim 1, wherein the ohmic characteristic in a low voltage region of the reverse voltage-current waveform of the diode is 0.1 V or less. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05578296A JP3313566B2 (en) | 1996-03-13 | 1996-03-13 | Diode manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05578296A JP3313566B2 (en) | 1996-03-13 | 1996-03-13 | Diode manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09246571A JPH09246571A (en) | 1997-09-19 |
| JP3313566B2 true JP3313566B2 (en) | 2002-08-12 |
Family
ID=13008477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05578296A Expired - Lifetime JP3313566B2 (en) | 1996-03-13 | 1996-03-13 | Diode manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3313566B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3722326B2 (en) * | 1996-12-20 | 2005-11-30 | 三菱電機株式会社 | Manufacturing method of solar cell |
| DE19804580C2 (en) * | 1998-02-05 | 2002-03-14 | Infineon Technologies Ag | Power diode in semiconductor material |
| DE19837944A1 (en) | 1998-08-21 | 2000-02-24 | Asea Brown Boveri | Method of manufacturing a semiconductor device |
| JP5308595B1 (en) * | 2012-11-28 | 2013-10-09 | 新電元工業株式会社 | Manufacturing method of resin-encapsulated semiconductor device and resin-encapsulated semiconductor device |
-
1996
- 1996-03-13 JP JP05578296A patent/JP3313566B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09246571A (en) | 1997-09-19 |
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