JP3293349B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3293349B2 JP3293349B2 JP20195094A JP20195094A JP3293349B2 JP 3293349 B2 JP3293349 B2 JP 3293349B2 JP 20195094 A JP20195094 A JP 20195094A JP 20195094 A JP20195094 A JP 20195094A JP 3293349 B2 JP3293349 B2 JP 3293349B2
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- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor
- substrate
- conductive region
- silicon substrate
- Prior art date
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- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の構造及び
その製造方法に関するものであり、更に詳しくはＳＯＩ
基板を用いて横型ＭＯＳＦＥＴ等のデバイス（例えばス
イッチング素子）を集積した半導体装置及びその製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device.
The present invention relates to a semiconductor device in which a device such as a lateral MOSFET (for example, a switching element) is integrated using a substrate and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、複数のスイッチング素子と複数の
キャパシタンス素子とから構成されるスイッチドキャパ
シタ電力変換回路（ＳＣ回路）は複数の高電圧を扱うた
め、半導体上に集積化する場合、素子分離の自由度が高
く、且つ高耐圧分離が容易なＳＯＩ構造を用いることが
有効である。2. Description of the Related Art Conventionally, a switched capacitor power conversion circuit (SC circuit) composed of a plurality of switching elements and a plurality of capacitance elements handles a plurality of high voltages. It is effective to use an SOI structure that has a high degree of freedom and facilitates high-breakdown-voltage separation.
【０００３】図８は並列充電、直列放電型のＳＣ回路を
示すものであり、以下に動作を簡単に説明する。FIG. 8 shows an SC circuit of a parallel charging and series discharging type, and the operation will be briefly described below.
【０００４】先ず、スイッチング素子Ｓ2 をオフ、スイ
ッチング素子Ｓ1 をオンし、ＭＯＳＦＥＴ（Ｑ11）〜
（Ｑ41）をオン、ＭＯＳＦＥＴ（Ｑ12）〜（Ｑ42）をオ
フして、直流電源電圧ＥをキャパシタＣ1 〜Ｃ5 の並列
回路に印加する。この時、ＭＯＳＦＥＴ（Ｑ12）〜（Ｑ
42）のドレイン電圧Ｖ21〜Ｖ51は、ＭＯＳＦＥＴ
（Ｑ11）〜（Ｑ41）のオン抵抗が無視できるとすると直
流電源電圧Ｅとなり、ＭＯＳＦＥＴ（Ｑ12）〜（Ｑ42）
のソース電圧Ｖ10〜Ｖ40はダイオ−ドＤ1 〜Ｄ4 の電圧
降下がほぼ無視できるとするとゼロとなる。従ってキャ
パシタＣ1 〜Ｃ5 は直流電源電圧Ｅまで充電される。[0004] First, ON OFF, the switching element S 1 and switching element S 2, MOSFET (Q 11) ~
The (Q 41) ON, and turns off the MOSFET (Q 12) ~ (Q 42), applies a DC source voltage E to the parallel circuit of the capacitors C 1 -C 5. At this time, the MOSFETs (Q 12 ) to (Q
42 ) The drain voltages V 21 to V 51 are MOSFETs
(Q 11) ~ DC source voltage E becomes the ON resistance of the (Q 41) is to be ignored, MOSFET (Q 12) ~ ( Q 42)
Source voltage V 10 ~V 40 of diode - becomes the voltage drop of the de D 1 to D 4 is substantially negligible as zero. Thus capacitor C 1 -C 5 is charged to a DC power supply voltage E.
【０００５】次にスイッチング素子Ｓ1 をオフ、スイッ
チング素子Ｓ2 をオンして、ＭＯＳＦＥＴ（Ｑ11）〜
（Ｑ41）をオフ、ＭＯＳＦＥＴ（Ｑ12）〜（Ｑ42）をオ
ンすると、ダイオ−ドＤ1 〜Ｄ4 は逆バイアスされてオ
フとなり、負荷Ｚ→キャパシタＣ5 →ＭＯＳＦＥＴ（Ｑ
42）→キャパシタＣ4 →ＭＯＳＦＥＴ（Ｑ32）→キャパ
シタＣ3 →ＭＯＳＦＥＴ（Ｑ22）→キャパシタＣ2 →Ｍ
ＯＳＦＥＴ（Ｑ12）→キャパシタＣ1 →スイッチング素
子Ｓ2 →負荷Ｚというループで負荷Ｚには直流電源電圧
Ｅの５倍圧（５Ｅ）が印加される。この時、ダイオ−ド
Ｄ4 のカソ−ド電圧Ｖ50＝０を基準とすると、ＭＯＳＦ
ＥＴ（Ｑ11）のドレイン電圧Ｖ11＝５Ｅ，ＭＯＳＦＥＴ
（Ｑ21）のドレイン電圧Ｖ21＝４Ｅ，ＭＯＳＦＥＴ（Ｑ
31）のドレイン電圧Ｖ31＝３Ｅ，ＭＯＳＦＥＴ（Ｑ41）
のドレイン電圧Ｖ41＝２Ｅ，ＭＯＳＦＥＴ（Ｑ42）のド
レイン電圧Ｖ51＝Ｅ，ＭＯＳＦＥＴ（Ｑ12）のソース電
圧Ｖ 10＝４Ｅ，ＭＯＳＦＥＴ（Ｑ22）のソース電圧Ｖ20
＝３Ｅ，ＭＯＳＦＥＴ（Ｑ32）のソース電圧Ｖ30＝２
Ｅ，ＭＯＳＦＥＴ（Ｑ42）のソース電圧Ｖ40＝Ｅ，ダイ
オ−ドＤ4 のカソ−ド電圧Ｖ50＝０となる。Next, the switching element S1Off, switch
Ching element STwoAnd turn on the MOSFET (Q11) ~
(Q41) Off, MOSFET (Q12)-(Q42)
Then, diode D1~ DFourIs reverse biased
Load Z → capacitor CFive→ MOSFET (Q
42) → Capacitor CFour→ MOSFET (Q32) → Capacity
Sita CThree→ MOSFET (Qtwenty two) → Capacitor CTwo→ M
OSFET (Q12) → Capacitor C1→ Switching element
Child STwo→ Load Z is DC power supply voltage in load Z loop
A pressure five times E (5E) is applied. At this time, the diode
DFourCathode voltage V50= 0, the MOSF
ET (Q11) Drain voltage V11= 5E, MOSFET
(Qtwenty one) Drain voltage Vtwenty one= 4E, MOSFET (Q
31) Drain voltage V31= 3E, MOSFET (Q41)
Drain voltage V41= 2E, MOSFET (Q42)
Rain voltage V51= E, MOSFET (Q12) Source power
Pressure V Ten= 4E, MOSFET (Qtwenty two) Source voltage V20
= 3E, MOSFET (Q32) Source voltage V30= 2
E, MOSFET (Q42) Source voltage V40= E, die
Mode DFourCathode voltage V50= 0.
【０００６】この回路の一部であるＭＯＳＦＥＴ
（Ｑ12）〜ＭＯＳＦＥＴ（Ｑ42）をＳＯＩ構造に実現し
たもの（第１従来例）を図９に示す。本構造は、シリコ
ン基板１とシリコン活性層（ＳＯＩ層）３の間に一面絶
縁酸化膜層（絶縁膜）２があるＳＯＩ構造であり、ＳＯ
Ｉ層３の表面から絶縁膜２までトレンチ４を掘り、絶縁
酸化膜で埋めることにより個々のデバイス（ここではＭ
ＯＳＦＥＴ（Ｑ12）〜ＭＯＳＦＥＴ（Ｑ42））領域を分
離するものであり、各デバイス領域には横方向ＤＭＯＳ
ＦＥＴを形成し、基板表面より各端子を引き出してい
る。A MOSFET that is part of this circuit
FIG. 9 shows a structure in which (Q 12 ) to MOSFET (Q 42 ) are realized in an SOI structure (first conventional example). This structure is an SOI structure having a one-side insulating oxide film layer (insulating film) 2 between a silicon substrate 1 and a silicon active layer (SOI layer) 3.
A trench 4 is dug from the surface of the I layer 3 to the insulating film 2 and filled with an insulating oxide film to form an individual device (here, M
OSFET (Q 12 ) to MOSFET (Q 42 )) regions, and each device region has a lateral DMOS
An FET is formed and each terminal is drawn out from the substrate surface.
【０００７】ここで、図９の様な構成において、図８に
示す回路が例えば並列充電をする時は、ＭＯＳＦＥＴ
（Ｑ12）〜ＭＯＳＦＥＴ（Ｑ42）のドレインＤｎｉｈａ
それぞれ直流電源電圧Ｅの電圧が印加され、ソースＳに
はゼロの電圧が印加される。ここでシリコン基板１の基
準電位Ｖsubがゼロであれば、絶縁膜２に印加される電
圧は最大でも各デバイスの最大電圧（ここではドレイン
電圧）と基準電位Ｖsubの差であり、ＭＯＳＦＥＴ（Ｑ
12）のデバイス領域とシリコン基板１との間、つまり絶
縁膜２にかかる電圧Ｖ2Sは最大で、 Ｖ2S＝Ｖ21−Ｖsub＝Ｅ−０＝Ｅ ・・・・・・・・・・・・・・・（１） となる。同様に、ＭＯＳＦＥＴ（Ｑ22）〜ＭＯＳＦＥＴ
（Ｑ42）のデバイス領域とシリコン基板１との間、つま
り絶縁膜２にかかる電圧Ｖ3S〜Ｖ5Sは、電圧Ｖ31，
Ｖ41，Ｖ51が直流電源電圧Ｅであるため、 Ｖ3S＝Ｖ4S＝Ｖ5S＝Ｅ ・・・・・・・・・・・・・・・・・・・・（２） である。また、ＭＯＳＦＥＴ（Ｑ12）〜ＭＯＳＦＥＴ
（Ｑ42）に印加される電圧は直流電源電圧Ｅである。Here, in the configuration shown in FIG. 9, when the circuit shown in FIG.
(Q 12 ) -Drain Dniha of MOSFET (Q 42 )
A voltage of the DC power supply voltage E is applied, and a zero voltage is applied to the source S. If the reference potential Vsub of the silicon substrate 1 is zero, the voltage applied to the insulating film 2 is at most the difference between the maximum voltage (here, the drain voltage) of each device and the reference potential Vsub, and the MOSFET (Q
12 ) The voltage V 2S applied between the device region and the silicon substrate 1, that is, the voltage applied to the insulating film 2 is maximum, and V 2S = V 21 −Vsub = E−0 = E ... (1) Similarly, MOSFET (Q 22 ) to MOSFET
The voltages V 3S to V 5S applied between the device region of (Q 42 ) and the silicon substrate 1, that is, the insulating film 2 are applied to the voltages V 31 ,
Since V 41 and V 51 are the DC power supply voltage E, V 3S = V 4S = V 5S = E (2) Also, MOSFET (Q 12 ) to MOSFET
The voltage applied to (Q 42 ) is the DC power supply voltage E.
【０００８】一方、直列放電をする時は、ＭＯＳＦＥＴ
（Ｑ12）のデバイス領域とシリコン基板１との間、つま
り絶縁膜２にかかる電圧Ｖ2Sは最大で、 Ｖ2S＝Ｖ21−Ｖsub ＝４Ｅ−０＝４Ｅ ・・・・・・・・・・・・・（３） となり、絶縁膜２には最大で直流電源電圧Ｅの４倍圧
（４Ｅ）の電圧がかかり、同様にして、 Ｖ3S＝３Ｅ，Ｖ4S＝２Ｅ，Ｖ5S＝Ｅ ・・・・・・・・・・・・・・（４） となる。On the other hand, when performing series discharge, MOSFET
The voltage V 2S between the device region of (Q 12 ) and the silicon substrate 1, that is, the voltage applied to the insulating film 2 is the maximum, and V 2S = V 21 -Vsub = 4E-0 = 4E ... .. (3), and a voltage up to four times (4E) of the DC power supply voltage E is applied to the insulating film 2. Similarly, V 3S = 3E, V 4S = 2E, V 5S = E (4)
【０００９】以上のようにＳＯＩ基板上にデバイスを製
作し、それぞれのデバイスを絶縁分離することにより、
各デバイス間の電圧関係に制約を受けることなく１つの
基板上に素子を集積化できる。As described above, by fabricating devices on an SOI substrate and isolating and isolating each device,
The elements can be integrated on one substrate without being restricted by the voltage relationship between the devices.
【００１０】なお、本従来例に於いて、一般に知られて
いるようにシリコン活性層３の片面を所望の厚さまで酸
化して絶縁膜２とすると共に、シリコン基板１と貼り合
わせてシリコン活性層３を所望の厚さになるまで研磨す
る、貼り合わせＳＯＩ基板等を用いてもよく、また、Ｍ
ＯＳＦＥＴ（Ｑ12）〜ＭＯＳＦＥＴ（Ｑ42）として横方
向ＤＭＯＳＦＥＴの例を示してあるが、横方向ＭＯＳＦ
ＥＴやバイポーラトランジスタでも良い。In this conventional example, as is generally known, one surface of the silicon active layer 3 is oxidized to a desired thickness to form an insulating film 2 and is bonded to the silicon substrate 1 to form a silicon active layer. 3 may be polished to a desired thickness, a bonded SOI substrate or the like may be used.
It is shown an example of a lateral DMOSFET as OSFET (Q 12) ~MOSFET (Q 42) , but laterally MOSF
An ET or a bipolar transistor may be used.
【００１１】[0011]
【発明が解決しようとする課題】しかし、ＭＯＳＦＥＴ
（Ｑ12）〜ＭＯＳＦＥＴ（Ｑ42）においてデバイス自体
は直流電源電圧Ｅの耐圧を持てば良いにもかかわらず、
絶縁膜２には最大４Ｅの電圧が印加されるため、絶縁膜
２はそれに耐えるだけの膜厚をもつ必要がある。その為
に、基板を介しての放熱が悪くなるという問題があっ
た。また、各デバイスはオン/ オフ時に大きな電圧差を
持つ絶縁膜２の容量の電荷を充放電する必要がある為
に、各デバイスのスイッチングスピードが遅くなると共
に、基板間の電圧差はそれぞれ異なるためにスイッチン
グスピードが異なり、回路動作が不安定になるという問
題があった。However, MOSFETs
In (Q 12 ) to MOSFET (Q 42 ), although the device itself only needs to have the withstand voltage of the DC power supply voltage E,
Since a voltage of a maximum of 4E is applied to the insulating film 2, the insulating film 2 needs to have a thickness enough to withstand the voltage. Therefore, there is a problem that heat radiation through the substrate is deteriorated. In addition, since each device needs to charge and discharge the charge of the capacitance of the insulating film 2 having a large voltage difference at the time of ON / OFF, the switching speed of each device becomes slow, and the voltage difference between the substrates is different. However, there is a problem that the switching speed is different and the circuit operation becomes unstable.
【００１２】上記問題点を解決し、さらにデバイス中の
等電位線を均等にしてデバイス自体の耐圧を向上する為
に、図１０の符号５に示すようにデバイスの最高電位点
（Ｖ21）をシリコン基板１と接続することによりシリコ
ン基板１を最高電位に固定するフィールドプレートを用
いる手段（第２従来例）がある。この様に構成すれば、
最高電位にあるデバイス（ＭＯＳＦＥＴ（Ｑ12））とシ
リコン基板１との間、つまり絶縁膜２にかかる電圧Ｖ2S
は低減されるが、逆に最低電位にあるデバイス（ここで
はＭＯＳＦＥＴ（Ｑ42））とシリコン基板１との間、つ
まり絶縁膜２にかかる電圧Ｖ5Sは−３Ｅ〜−４Ｅと大き
くなるという問題が生じる。In order to solve the above problem and further improve the breakdown voltage of the device itself by equalizing the equipotential lines in the device, the highest potential point (V 21 ) of the device as shown by reference numeral 5 in FIG. There is a means (second conventional example) using a field plate for fixing the silicon substrate 1 to the highest potential by connecting to the silicon substrate 1. With this configuration,
The voltage V 2S between the device (MOSFET (Q 12 )) at the highest potential and the silicon substrate 1, that is, the voltage applied to the insulating film 2
Is being reduced, the device (MOSFET (Q 42 in this case)) in the lowest potential in the opposite and between the silicon substrate 1, that is a problem that the voltage V 5S according to the insulating film 2 becomes large as -3E~-4E Occurs.
【００１３】本発明は上記問題点に鑑みてなされたもの
で、その目的とするところは、素子の高耐圧化に影響を
与えることなく高速動作が可能となると共に、ＳＯＩ構
造の埋め込み酸化膜厚が素子に印加される電位によらず
任意に設定可能となり、また、デバイスの電位が固定さ
れることにより安定動作も可能となる半導体装置及びそ
の製造方法を提供する。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. It is an object of the present invention to enable a high-speed operation without affecting a high withstand voltage of an element and to obtain a buried oxide film of an SOI structure. A semiconductor device and a method of manufacturing the same, which can be set arbitrarily irrespective of the potential applied to the element, and can perform stable operation by fixing the potential of the device.
【００１４】[0014]
【発明を解決するための手段】上記課題を解決する為
に、請求項１記載の発明によれば、支持基板となる第１
の半導体基板と、該第１の半導体基板とは反対導電型を
有し、複数のデバイスが互いに絶縁されて形成されてい
る第２の半導体基板と、前記第１及び第２の半導体基板
とを互いに電気的に絶縁させる第１の絶縁層とから構成
される、ＳＯＩ構造を有する半導体装置において、前記
第１の半導体基板中に形成されると共に、前記第１の半
導体基板とは反対導電型を有し前記複数のデバイスの少
なくとも２つと電気的に接続される第１の導電性領域
と、前記デバイスと前記第１の導電性領域とを電気的に
接続する為の、前記第１の絶縁層に形成された開口部と
を有し、前記第１の導電性領域は、前記デバイスの同じ
導電型の領域に電気的に接続されることを特徴とするも
のである。請求項２記載の発明によれば、支持基板とな
る第１の半導体基板と、該第１の半導体基板とは反対導
電型を有し、複数のデバイスが互いに絶縁されて形成さ
れている第２の半導体基板と、前記第１及び第２の半導
体基板とを互いに電気的に絶縁させる第１の絶縁層とか
ら構成される、ＳＯＩ構造を有する半導体装置におい
て、前記第１の絶縁層中に形成されると共に、前記複数
のデバイスの少なくとも２つと電気的に接続される第１
の導電性領域と、前記デバイスと前記第１の導電性領域
とを電気的に接続する為の、前記第１の絶縁層に形成さ
れた開口部とを有し、前記第１の導電性領域は、前記デ
バイスの同じ導電型の領域に電気的に接続されることを
特徴とするものである。請求項３記載の発明によれば、
請求項１または請求項２記載の半導体装置において、前
記第１の導電性領域が複数形成されることを特徴とする
ものである。請求項４記載の発明によれば、請求項１乃
至請求項３のいずれかに記載の半導体装置において、前
記第２の半導体基板の前記第１の絶縁層が配置された面
と異なる面側に、第２の絶縁層を介して、前記第１の半
導体基板とは反対導電型を有し、前記複数のデバイスの
少なくとも２つと電気的に接続される第２の導電性領域
と、前記デバイスと前記第２の導電性領域とを電気的に
接続する為の、前記第２の絶縁層に形成された開口部と
を有し、前記第２の導電性領域は、前記デバイ スの同じ
導電型の領域に電気的に接続されることを特徴とするも
のである。請求項５記載の発明によれば、請求項１乃至
請求項４のいずれかに記載のＳＯＩ構造を、前記第２の
半導体基板の一面側をエッチングすることにより凹部を
形成し、該凹部が形成された前記第２の半導体基板の一
面側に前記第１の絶縁膜となる酸化膜を形成し、凸部が
露出して、かつ、表面が平坦になるまで研磨を行い、前
記第２の半導体基板の研磨を行った面に前記第１の半導
体基板を貼り合わせ工程により貼り合わせた後、前記第
２の半導体基板の二面側を、前記第２の半導体基板が所
望の厚さになるまで研磨することにより形成することを
特徴とするものである。 In order to solve the above problems, according to the first aspect of the present invention, the first substrate serving as a support substrate is provided.
And a semiconductor substrate having a conductivity type opposite to that of the first semiconductor substrate.
Multiple devices are formed insulated from each other
A second semiconductor substrate, and the first and second semiconductor substrates
And a first insulating layer for electrically insulating each other from each other
A semiconductor device having an SOI structure,
A first semiconductor substrate formed in a first semiconductor substrate;
Having a conductivity type opposite to that of the conductive substrate and having a small number of the plurality of devices;
First conductive region electrically connected to at least two
Electrically connecting the device and the first conductive region
An opening formed in the first insulating layer for connection;
Wherein the first conductive region is the same as the device
Characterized by being electrically connected to the conductive type region.
It is. According to the invention described in claim 2, the support substrate
A first semiconductor substrate, and a first semiconductor substrate opposite to the first semiconductor substrate.
Multiple devices are formed insulated from each other
A second semiconductor substrate, and the first and second semiconductors.
A first insulating layer that electrically insulates the substrate from each other
Semiconductor device having an SOI structure
And forming the plurality of layers in the first insulating layer.
A first device electrically connected to at least two of the devices
Conductive region, the device and the first conductive region
Formed on the first insulating layer for electrically connecting
And the first conductive region has an opening formed therein.
Electrically connected to the same conductivity type area of the device.
It is a feature. According to the invention described in claim 3,
The semiconductor device according to claim 1 or 2, wherein
A plurality of first conductive regions are formed.
Things. According to the invention described in claim 4, claim 1 is
4. The semiconductor device according to claim 3, wherein
The surface of the second semiconductor substrate on which the first insulating layer is disposed
On the side different from the first half via the second insulating layer.
The conductive substrate has an opposite conductivity type to the plurality of devices.
Second conductive region electrically connected to at least two
Electrically connecting the device and the second conductive region
An opening formed in the second insulating layer for connection.
It has the second conductive region, the same of the device
Characterized by being electrically connected to the conductive type region.
It is. According to the invention described in claim 5, claims 1 to
The SOI structure according to claim 4,
The recess is formed by etching one surface of the semiconductor substrate.
Forming one of the second semiconductor substrates on which the concave portions are formed.
An oxide film to be the first insulating film is formed on the surface side,
Polish until exposed and the surface is flat.
The polished surface of the second semiconductor substrate is provided on the first semiconductor substrate.
After bonding the body substrate by the bonding process,
The second semiconductor substrate is located on two sides of the second semiconductor substrate.
To form by polishing to the desired thickness.
It is a feature.
【００１５】[0015]
【作用】請求項１乃至請求項４記載の発明によれば、Ｓ
ＯＩ層３とシリコン基板１との間に存在する絶縁膜２に
よって形成される寄生容量を充放電することは必要な
く、シリコン基板１は接地電位ゼロに接続され、導電性
領域６１は常に正電位となる為に、シリコン基板１に対
して導電性領域６１は常に逆バイアス条件となり、ＰＮ
接合の整流特性により導電性領域６１とシリコン基板１
とは電気的に分離される。According to the first to fourth aspects of the present invention, S
It is not necessary to charge and discharge the parasitic capacitance formed by the insulating film 2 existing between the OI layer 3 and the silicon substrate 1, the silicon substrate 1 is connected to the ground potential zero, and the conductive region 61 is always at the positive potential. Therefore, the conductive region 61 is always in a reverse bias condition with respect to the silicon substrate 1 and PN
The conductive region 61 and the silicon substrate 1
And is electrically separated from.
【００１６】請求項５記載の発明によれば、Ｎ型シリコ
ン基板３の一面側の所定の領域にシリコンエッチングを
行い、Ｎ型シリコン基板３の一面側に凹凸部を形成した
後、一面側の熱酸化を行うことにより絶縁膜となる酸化
膜を形成し、その後で凸部が露出して、かつ、表面が平
坦化されるまで研磨する。ここでＰ型シリコン基板１と
Ｎ型シリコン基板３との貼り合わせを行い、ＳＯＩ構造
の基板が形成される。この後、Ｎ型シリコン基板３の二
面側を所望の厚みまで研磨することにより、結晶性を維
持してＳＯＩ構造の絶縁膜に開口部を備えた半導体装置
を形成することができる。According to the fifth aspect of the present invention, a predetermined region on one surface of the N-type silicon substrate 3 is subjected to silicon etching to form a concavo-convex portion on one surface of the N-type silicon substrate 3. An oxide film to be an insulating film is formed by performing thermal oxidation, and thereafter, polishing is performed until the convex portions are exposed and the surface is flattened. Here, the P-type silicon substrate 1 and the N-type silicon substrate 3 are bonded to each other to form a substrate having an SOI structure. Thereafter, by polishing the two surfaces of the N-type silicon substrate 3 to a desired thickness, a semiconductor device having an opening in an SOI structure insulating film while maintaining crystallinity can be formed.
【００１７】[0017]
（実施例１）本発明に係る第１実施例を図１に示し、そ
の製造方法を図２に示す。(Embodiment 1) A first embodiment according to the present invention is shown in FIG. 1 and a manufacturing method thereof is shown in FIG.
【００１８】図１０に示した第２従来例と異なる点は、
絶縁膜２を介してＳＯＩ層３と相対する比較的高抵抗な
導電性領域６１をシリコン基板１中に新たに設けて、横
型ＭＯＳＦＥＴ（Ｑ12）が形勢されているＳＯＩ層３
と、横型ＭＯＳＦＥＴ（Ｑ42）が形成されているＳＯＩ
層３とを電気的に接続した構造であることであり、その
他の第２従来例と同一構成には同一符号を付すことによ
り説明を省略する。The difference from the second conventional example shown in FIG.
A relatively high-resistance conductive region 61 facing the SOI layer 3 via the insulating film 2 is newly provided in the silicon substrate 1 so that the lateral MOSFET (Q 12 ) is activated.
And an SOI in which a lateral MOSFET (Q 42 ) is formed
This is a structure in which the layer 3 is electrically connected. The same reference numerals are given to the same components as those of the second conventional example, and the description is omitted.
【００１９】次に、製造方法を図２を用いて説明する。
図２（ａ）に示す様にＰ型シリコン基板１の表面の酸化
膜２上に拡散窓７を開口した後、図２（ｂ）に示す様に
開口された拡散窓７よりリン等のＮ型不純物を導入し熱
拡散を行いＮ型不純物領域６１を形成する。一方、図２
（ｃ）に示す様にＮ型シリコン基板３表面の適当な領域
にシリコンエッチングを行い、Ｎ型シリコン基板３表面
に凹凸部を形成した後、図２（ｄ）に示す様にＮ型シリ
コン基板３表面の熱酸化を行う。引続き図２（ｅ）に示
す様にＮ型シリコン基板３表面が平坦化されるまで研磨
する。ここで、図２（ｂ）に示すＰ型シリコン基板１の
ウエハと、図２（ｅ）に示すＮ型シリコン基板３のウエ
ハとの貼り合わせを行う。この貼り合わせ工程におい
て、図２（ｅ）に示したＮ型シリコン基板３のウエハの
表裏を反転し貼り合わせ工程は実施し、ＳＯＩ構造の基
板が形成される。この後ＳＯＩ基板の表面シリコン層を
所望の厚みまで研磨して、図２（ｆ）に示す構造が形成
される。この後、図２（ｇ）に示す様にＳＯＩ基板の表
面シリコン基板のシリコンエッチングを行った後、エッ
チングされたシリコン溝８に絶縁膜２を堆積することに
より、ＳＯＩ基板が完成される。そして、ＳＯＩ層３に
横型ＭＯＳＦＥＴを形成することにより図１に示した半
導体装置が完成する。Next, the manufacturing method will be described with reference to FIG.
After the diffusion window 7 is opened on the oxide film 2 on the surface of the P-type silicon substrate 1 as shown in FIG. 2A, N such as phosphorus is diffused from the diffusion window 7 opened as shown in FIG. An N-type impurity region 61 is formed by introducing a type impurity and performing thermal diffusion. On the other hand, FIG.
As shown in FIG. 2C, an appropriate region on the surface of the N-type silicon substrate 3 is subjected to silicon etching to form irregularities on the surface of the N-type silicon substrate 3, and then, as shown in FIG. 3. Thermal oxidation of the surface is performed. Subsequently, as shown in FIG. 2E, polishing is performed until the surface of the N-type silicon substrate 3 is flattened. Here, the wafer of the P-type silicon substrate 1 shown in FIG. 2B and the wafer of the N-type silicon substrate 3 shown in FIG. In this bonding step, the wafer is turned upside down on the N-type silicon substrate 3 shown in FIG. 2E, and the bonding step is performed to form a substrate having an SOI structure. Thereafter, the surface silicon layer of the SOI substrate is polished to a desired thickness to form a structure shown in FIG. Thereafter, as shown in FIG. 2G, silicon etching is performed on the surface silicon substrate of the SOI substrate, and then the insulating film 2 is deposited in the etched silicon grooves 8, thereby completing the SOI substrate. Then, by forming a lateral MOSFET on the SOI layer 3, the semiconductor device shown in FIG. 1 is completed.
【００２０】ここで、各々の横型ＭＯＳＦＥＴのドレイ
ン電圧は横型ＭＯＳＦＥＴ（Ｑ12）とＭＯＳＦＥＴ（Ｑ
42）が形成されているＳＯＩ層３と電気的に接続され
る。また、高抵抗な導電性領域６１の導電型はＳＯＩ層
３と同一導電型で、シリコン基板１とは反対導電型であ
る。そして、シリコン基板１は接地電位に電気的に接続
されている。そして、導電性領域６１の両端の電位はそ
れぞれＶ21とＶ51と等しくなり導電性領域６１間では電
位はＶ21からＶ51へと連続的に変化する。従って、図１
に示す回路における並列充電、直列放電時のＳＯＩ層３
とシリコン基板１との間の電圧は常にほぼゼロとなる。Here, the drain voltage of each lateral MOSFET is determined by the lateral MOSFET (Q 12 ) and the MOSFET (Q
42 ) is electrically connected to the SOI layer 3 where the SOI layer 3 is formed. The conductivity type of the high-resistance conductive region 61 is the same conductivity type as that of the SOI layer 3, and is the opposite conductivity type to that of the silicon substrate 1. The silicon substrate 1 is electrically connected to the ground potential. The potentials at both ends of the conductive region 61 are equal to V 21 and V 51 , respectively, and the potential between the conductive regions 61 continuously changes from V 21 to V 51 . Therefore, FIG.
SOI layer 3 during parallel charging and series discharging in the circuit shown in FIG.
The voltage between the substrate and the silicon substrate 1 is almost always zero.
【００２１】この為、ＳＯＩ層３とシリコン基板１との
間に存在する絶縁膜２によって形成される寄生容量を充
放電することは必要なく、スイッチング素子は高周波動
作が可能となる。また、シリコン基板１は接地電位ゼロ
に接続され、導電性領域６１は常に正電位となる為に、
シリコン基板１に対して導電性領域６１は常に逆バイア
ス条件となり、ＰＮ接合の整流特性により導電性領域６
１とシリコン基板１とは電気的に分離される。そして、
ＭＯＳＦＥＴ（Ｑ12）〜ＭＯＳＦＥＴ（Ｑ42）のドレイ
ン電位は絶縁膜２の容量で導電性領域６１の電位に結合
される為、ノイズ等で基準電位がふらつくことが低減さ
れ、安定動作も可能となる。更に、導電性領域６１はフ
ィールドプレート効果も有している為、デバイスの耐圧
に悪影響を与えることはは何等ないことは明らかであ
る。Therefore, it is not necessary to charge and discharge the parasitic capacitance formed by the insulating film 2 existing between the SOI layer 3 and the silicon substrate 1, and the switching element can operate at a high frequency. Further, since the silicon substrate 1 is connected to the ground potential zero and the conductive region 61 is always at the positive potential,
The conductive region 61 is always in a reverse bias condition with respect to the silicon substrate 1, and the conductive region 6
1 and the silicon substrate 1 are electrically separated. And
MOSFET (Q 12) the drain potential of ~MOSFET (Q 42) is for being coupled to the potential of the conductive region 61 in a volume of the insulating film 2, is reduced to the reference potential fluctuates due to noise, stable operation can also be a Become. Further, since the conductive region 61 also has a field plate effect, it is clear that it has no adverse effect on the breakdown voltage of the device.
【００２２】（実施例２）本発明に係る第２実施例を図
３に示し、その製造方法を図４に示す。(Embodiment 2) FIG. 3 shows a second embodiment according to the present invention, and FIG. 4 shows a manufacturing method thereof.
【００２３】図１に示した第１実施例と異なる点は、導
電性領域６１がＳＯＩ基板のＳＯＩ層３とシリコン基板
１との間の絶縁膜２１及び絶縁膜２２中に埋め込まれた
構造にして、導電性領域６１とシリコン基板１との分離
を、絶縁膜２１及び絶縁膜２２で電気的に行うものであ
り、第１実施例と同一構成には同一符号を付すことによ
り説明を省略する。The difference from the first embodiment shown in FIG. 1 is that the conductive region 61 is embedded in the insulating films 21 and 22 between the SOI layer 3 of the SOI substrate and the silicon substrate 1. The conductive region 61 and the silicon substrate 1 are electrically separated from each other by the insulating films 21 and 22. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. .
【００２４】次に、図４を用いて製造方法を簡単に示
す。図４（ａ）に示す様にＮ型シリコン基板３表面の適
当な領域のシリコンエッチングを行い、Ｎ型シリコン基
板３表面に凹凸部を形成した後、図４（ｂ）に示す様に
Ｎ型シリコン基板３表面の熱酸化を行う。そして、図４
（ｃ）に示す様にＮ型シリコン基板３表面が平坦化され
るまで研磨する。一方、図４（ｄ）に示す様にＰ型シリ
コン基板１に高加速エネルギにより酸素イオンをイオン
注入するＳＩＭＯＸ法によりＰ型シリコン基板１中に酸
化膜２２とＰ型シリコン基板１表面にシリコン層６１を
形成する。ここで、図４（ｃ）に示すＮ型シリコン基板
３中に酸化膜２１が埋め込まれたウエハと、図４（ｄ）
に示すＰ型シリコン基板１のウエハとの両者の貼り合わ
せを行う。この貼り合わせ工程において、図４（ｃ）に
示すＮ型シリコン基板３のウエハの表裏を反転して貼り
合わせ工程を行い、ＳＯＩ構造の基板が形成され、ＳＯ
Ｉ基板のＳＯＩ層３を所望の厚みまで研磨し、図４
（ｅ）に示す構造が形成される。図４（ｆ）に示す様に
ＳＯＩ基板のＳＯＩ層３のシリコンエッチングを行った
後、図４（ｇ）に示す様にエッチングされたシリコン溝
８に絶縁膜２１を堆積することにより、ＳＯＩ基板が完
成される。ＳＯＩ層３に横型ＭＯＳＦＥＴを形成するこ
とにより図３に示す半導体装置が完成する。Next, a manufacturing method will be briefly described with reference to FIG. As shown in FIG. 4A, an appropriate region of the surface of the N-type silicon substrate 3 is subjected to silicon etching to form irregularities on the surface of the N-type silicon substrate 3, and then, as shown in FIG. Thermal oxidation of the surface of the silicon substrate 3 is performed. And FIG.
Polishing is performed until the surface of the N-type silicon substrate 3 is flattened as shown in FIG. On the other hand, as shown in FIG. 4D, an oxide film 22 is formed in the P-type silicon substrate 1 and a silicon layer is formed on the surface of the P-type silicon substrate 1 by a SIMOX method in which oxygen ions are implanted into the P-type silicon substrate 1 with high acceleration energy. 61 is formed. Here, a wafer in which the oxide film 21 is embedded in the N-type silicon substrate 3 shown in FIG.
Are bonded together with the wafer of the P-type silicon substrate 1 shown in FIG. In this bonding step, the bonding step is performed by reversing the front and back of the wafer of the N-type silicon substrate 3 shown in FIG. 4C, and a substrate having an SOI structure is formed.
The SOI layer 3 of the I substrate is polished to a desired thickness, and FIG.
The structure shown in (e) is formed. After silicon etching of the SOI layer 3 of the SOI substrate is performed as shown in FIG. 4F, an insulating film 21 is deposited in the etched silicon groove 8 as shown in FIG. Is completed. By forming a lateral MOSFET on the SOI layer 3, the semiconductor device shown in FIG. 3 is completed.
【００２５】ここで、図４（ｇ）に示すＳＯＩ構造を得
る為に、図４（ｄ）の工程においてＰ型シリコン基板１
の表面に酸化膜２２を形成した後、ＳＩＰＯＳ等の導電
性膜を形成しても良い。Here, in order to obtain the SOI structure shown in FIG. 4G, in the step of FIG.
After the oxide film 22 is formed on the surface, a conductive film such as SIPOS may be formed.
【００２６】なお、上記実施例１及び実施例２に示した
製造方法は、いずれも２枚のウエハを貼り合わせてＳＯ
Ｉウエハを作成する場合に、一方のシリコン基板のウエ
ハ表面を予めエッチングし凹凸部を形成しておいた後に
酸化を施して表面の凹凸部を無くする様に平坦化する。
この酸化膜はＳＯＩウエハの埋め込み酸化膜として機能
する。又、埋め込み酸化膜が形成された一方のシリコン
基板のウエハは貼り合わせ時に反転し、他方のシリコン
基板のウエハと貼り合わせた後、所望の厚みになるまで
研磨する為、得られたＳＯＩウエハの表面半導体層の結
晶性は従来の貼り合わせ法による表面半導体層と同様の
良好な結晶性が維持されている。In each of the manufacturing methods shown in the first and second embodiments, the two wafers are bonded together and the SO
When forming an I-wafer, the wafer surface of one silicon substrate is etched in advance to form an uneven portion, and then oxidized to flatten the surface so as to eliminate the uneven portion.
This oxide film functions as a buried oxide film of the SOI wafer. Further, the wafer of one silicon substrate on which the buried oxide film is formed is inverted at the time of bonding, is bonded to the wafer of the other silicon substrate, and is polished to a desired thickness. Regarding the crystallinity of the surface semiconductor layer, the same good crystallinity as that of the surface semiconductor layer obtained by the conventional bonding method is maintained.
【００２７】（実施例３）本発明に係る第３実施例を図
５に示す。(Embodiment 3) FIG. 5 shows a third embodiment according to the present invention.
【００２８】図１に示す第１実施例と異なる点は、個別
に形成された導電性領域６１が絶縁膜２を間に挟んでＳ
ＯＩ層３に形成された横型ＭＯＳＦＥＴの各々と個別に
電気的接続されていることであり、その他の第１実施例
と同一構成には同一符号を付すことにより説明を省略す
る。The difference from the first embodiment shown in FIG. 1 is that the separately formed conductive regions 61 are formed with the insulating film 2 interposed therebetween.
That is, they are individually electrically connected to each of the lateral MOSFETs formed in the OI layer 3. The same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
【００２９】（実施例４）本発明に係る第４実施例を図
６に示す。(Embodiment 4) FIG. 6 shows a fourth embodiment according to the present invention.
【００３０】図５に示す第３実施例と異なる点は、個別
に形成された導電性領域６１がＳＯＩ基板のＳＯＩ層３
とシリコン基板１の間の絶縁膜２１及び絶縁膜２２の中
に埋め込まれた構造になっていることであり、その他の
第３実施例と同一構成には同一符号を付すことにより説
明を省略する。The difference from the third embodiment shown in FIG. 5 is that the separately formed conductive regions 61 are formed on the SOI layer 3 of the SOI substrate.
The structure is buried in the insulating film 21 and the insulating film 22 between the semiconductor substrate 1 and the silicon substrate 1. The same components as those in the third embodiment are denoted by the same reference numerals, and description thereof is omitted. .
【００３１】なお、実施例３及び実施例４に於ける導電
性領域６１は比較的高抵抗でなくても良い。The conductive region 61 in the third and fourth embodiments does not need to have a relatively high resistance.
【００３２】（実施例５）本発明に係る第５実施例を図
７に示す。(Embodiment 5) FIG. 7 shows a fifth embodiment according to the present invention.
【００３３】図１に示す第１実施例と異なる点は、新た
に高抵抗導電性領域６２を絶縁膜２３を介してＳＯＩ層
３の表面に形成し、高抵抗導電性領域６２とＳＯＩ層３
とを電気的に接続したことであり、その他の第１実施例
と同一構成には同一符号を付すことにより説明を省略す
る。The difference from the first embodiment shown in FIG. 1 is that a high-resistance conductive region 62 is newly formed on the surface of the SOI layer 3 via the insulating film 23, and the high-resistance conductive region 62 and the SOI layer 3
Are electrically connected to each other, and the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
【００３４】なお、上記実施例３から実施例５に示した
構造の製造方法は、上記実施例１，実施例２に示した製
造方法を適用して、更に導電性領域６１とＳＯＩ層３と
の電気的接続を形成する為に、適当なシリコンエッチン
グを施すことは容易に推察される。The manufacturing method of the structure shown in the third embodiment to the fifth embodiment is the same as the manufacturing method shown in the first embodiment and the second embodiment. It is easily assumed that appropriate silicon etching is performed in order to form an electrical connection.
【００３５】また、上記実施例１から実施例５のいずれ
を組み合わせてもよく、上記実施例１から実施例５に示
す導電性領域６１は、シリコン基板１の内部に形成して
も、絶縁膜２の内部に形成してもよく、導電性領域６１
とシリコン基板１との電気的接続を行う箇所を任意に設
定してもよい。Further, any of the first to fifth embodiments may be combined. The conductive region 61 shown in the first to fifth embodiments may be formed inside the silicon substrate 1, 2 may be formed inside the conductive region 61.
May be set arbitrarily at a location where electrical connection is made between the silicon substrate 1.
【００３６】[0036]
【発明の効果】請求項１乃至請求項４記載の発明によれ
ば、素子の高耐圧化に影響を与えることなく高速動作が
可能となると共に、ＳＯＩ構造の埋め込み酸化膜厚が素
子に印加される電位によらず任意に設定可能となり、ま
た、デバイスの電位が固定されることにより安定動作も
可能となる半導体装置を提供できる。According to the first to fourth aspects of the present invention, high-speed operation can be performed without affecting the high breakdown voltage of the element, and the buried oxide film thickness of the SOI structure is applied to the element. It is possible to provide a semiconductor device which can be set arbitrarily irrespective of the potential, and which can perform stable operation by fixing the potential of the device.
【００３７】請求項５記載の発明によれば、結晶性を維
持したまま、請求項１乃至請求項４のいずれかに記載の
半導体装置を容易に得る製造方法を提供できる。According to the fifth aspect of the present invention, it is possible to provide a manufacturing method for easily obtaining the semiconductor device according to any one of the first to fourth aspects while maintaining the crystallinity.
【図１】本発明に係る第１実施例を示す構造の断面図で
ある。FIG. 1 is a sectional view of a structure showing a first embodiment according to the present invention.
【図２】上記実施例に用いる半導体基板の製造工程を示
す断面図である。FIG. 2 is a sectional view showing a manufacturing process of a semiconductor substrate used in the above embodiment.
【図３】本発明に係る第２実施例を示す構造の断面図で
ある。FIG. 3 is a sectional view of a structure showing a second embodiment according to the present invention.
【図４】上記実施例に用いる半導体基板の製造工程を示
す断面図である。FIG. 4 is a sectional view showing a manufacturing process of the semiconductor substrate used in the above embodiment.
【図５】本発明に係る第３実施例を示す構造の断面図で
ある。FIG. 5 is a sectional view of a structure showing a third embodiment according to the present invention.
【図６】本発明に係る第４実施例を示す構造の断面図で
ある。FIG. 6 is a sectional view of a structure showing a fourth embodiment according to the present invention.
【図７】本発明に係る第５実施例を示す構造の断面図で
ある。FIG. 7 is a sectional view of a structure showing a fifth embodiment according to the present invention.
【図８】本発明に係る並列充電、直列放電型のＳＣ回路
の回路図である。FIG. 8 is a circuit diagram of a parallel charging and series discharging SC circuit according to the present invention.
【図９】本発明に係る第１従来例を示す構造の断面図で
ある。FIG. 9 is a sectional view of a structure showing a first conventional example according to the present invention.
【図１０】本発明に係る第２従来例を示す構造の断面図
である。FIG. 10 is a sectional view of a structure showing a second conventional example according to the present invention.
１ シリコン基板 ２ 酸化膜 ３ ＳＯＩ層 ６ 導電性領域 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Oxide film 3 SOI layer 6 Conductive area
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大西 雅人 大阪府門真市大字門真1048番地松下電工 株式会社内 (72)発明者 早崎 嘉城 大阪府門真市大字門真1048番地松下電工 株式会社内 (56)参考文献 特開 平３−93265（ＪＰ，Ａ) 特開 昭61−85853（ＪＰ，Ａ) 特開 昭58−93282（ＪＰ，Ａ) 特開 昭61−67253（ＪＰ，Ａ) 特開 平４−275450（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/8234 H01L 21/762 H01L 27/088 H01L 29/786 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masato Onishi 1048 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. References JP-A-3-93265 (JP, A) JP-A-61-85853 (JP, A) JP-A-58-93282 (JP, A) JP-A-61-67253 (JP, A) 4-275450 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/8234 H01L 21/762 H01L 27/088 H01L 29/786
Claims (5)
第１の半導体基板とは反対導電型を有し、複数のデバイ
スが互いに絶縁されて形成されている第２の半導体基板
と、前記第１及び第２の半導体基板とを互いに電気的に
絶縁させる第１の絶縁層とから構成される、ＳＯＩ構造
を有する半導体装置において、前記第１の半導体基板中
に形成されると共に、前記第１の半導体基板とは反対導
電型を有し前記複数のデバイスの少なくとも２つと電気
的に接続される第１の導電性領域と、前記デバイスと前
記第１の導電性領域とを電気的に接続する為の、前記第
１の絶縁層に形成された開口部とを有し、前記第１の導
電性領域は、前記デバイスの同じ導電型の領域に電気的
に接続されることを特徴とする半導体装置。A first semiconductor substrate serving as a support substrate; a second semiconductor substrate having a conductivity type opposite to the first semiconductor substrate and having a plurality of devices formed insulated from each other; A semiconductor device having an SOI structure, comprising: a first insulating layer that electrically insulates the first and second semiconductor substrates from each other; wherein the semiconductor device is formed in the first semiconductor substrate; A first conductive region having a conductivity type opposite to that of the first semiconductor substrate and electrically connected to at least two of the plurality of devices; and electrically connecting the device and the first conductive region. An opening formed in the first insulating layer for connection, wherein the first conductive region is electrically connected to a region of the same conductivity type of the device. Semiconductor device.
第１の半導体基板とは反対導電型を有し、複数のデバイ
スが互いに絶縁されて形成されている第２の半導体基板
と、前記第１及び第２の半導体基板とを互いに電気的に
絶縁させる第１の絶縁層とから構成される、ＳＯＩ構造
を有する半導体装置において、前記第１の絶縁層中に形
成されると共に、前記複数のデバイスの少なくとも２つ
と電気的に接続される第１の導電性領域と、前記デバイ
スと前記第１の導電性領域とを電気的に接続する為の、
前記第１の絶縁層に形成された開口部とを有し、前記第
１の導電性領域は、前記デバイスの同じ導電型の領域に
電気的に接続されることを特徴とする半導体装置。2. A first semiconductor substrate serving as a support substrate, a second semiconductor substrate having a conductivity type opposite to that of the first semiconductor substrate and having a plurality of devices formed insulated from each other; A first insulating layer for electrically insulating the first and second semiconductor substrates from each other; a semiconductor device having an SOI structure, wherein the semiconductor device is formed in the first insulating layer, A first conductive region electrically connected to at least two of the plurality of devices; and a device for electrically connecting the device and the first conductive region.
A semiconductor device having an opening formed in the first insulating layer, wherein the first conductive region is electrically connected to a region of the same conductivity type of the device.
ことを特徴とする請求項１または請求項２記載の半導体
装置。3. The semiconductor device according to claim 1, wherein a plurality of said first conductive regions are formed.
層が配置された面と異なる面側に、第２の絶縁層を介し
て、前記第１の半導体基板とは反対導電型を有し、前記
複数のデバイスの少なくとも２つと電気的に接続される
第２の導電性領域と、前記デバイスと前記第２の導電性
領域とを電気的に接続する為の、前記第２の絶縁層に形
成された開口部とを有し、前記第２の導電性領域は、前
記デバイスの同じ導電型の領域に電気的に接続されるこ
とを特徴とする請求項１乃至請求項３のいずれかに記載
の半導体装置。4. On the surface of the second semiconductor substrate, which is different from the surface on which the first insulating layer is arranged, a conductive type opposite to that of the first semiconductor substrate is provided via a second insulating layer. A second conductive region electrically connected to at least two of the plurality of devices; and a second insulating region for electrically connecting the device and the second conductive region. 4. The device according to claim 1, further comprising an opening formed in a layer, wherein the second conductive region is electrically connected to a region of the same conductivity type of the device. 13. A semiconductor device according to claim 1.
のＳＯＩ構造を、前記第２の半導体基板の一面側をエッ
チングすることにより凹凸部を形成し、該凹凸部が形成
された前記第２の半導体基板の一面側に前記第１の絶縁
膜となる酸化膜を形成し、凸部が露出して、かつ、表面
が平坦になるまで研磨を行い、前記第２の半導体基板の
研磨を行った面に前記第１の半導体基板を貼り合わせ工
程により貼り合わせた後、前記第２の半導体基板の二面
側を、前記第２の半導体基板が所望の厚さになるまで研
磨することにより形成することを特徴とする半導体装置
の製造方法。5. The SOI structure according to claim 1, wherein an uneven portion is formed by etching one surface side of the second semiconductor substrate, and wherein the uneven portion is formed. Forming an oxide film serving as the first insulating film on one surface side of the second semiconductor substrate, and polishing the surface until the projections are exposed and the surface becomes flat; After bonding the first semiconductor substrate to the surface on which the second semiconductor substrate has been subjected to the bonding step, the two surfaces of the second semiconductor substrate are polished until the second semiconductor substrate has a desired thickness. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20195094A JP3293349B2 (en) | 1994-08-26 | 1994-08-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20195094A JP3293349B2 (en) | 1994-08-26 | 1994-08-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0864687A JPH0864687A (en) | 1996-03-08 |
| JP3293349B2 true JP3293349B2 (en) | 2002-06-17 |
Family
ID=16449469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20195094A Expired - Fee Related JP3293349B2 (en) | 1994-08-26 | 1994-08-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3293349B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3061020B2 (en) | 1997-11-12 | 2000-07-10 | 日本電気株式会社 | Dielectric separated type semiconductor device |
| JP5055813B2 (en) | 2006-04-10 | 2012-10-24 | 富士電機株式会社 | SOI lateral semiconductor device |
-
1994
- 1994-08-26 JP JP20195094A patent/JP3293349B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0864687A (en) | 1996-03-08 |
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