JP3264190B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3264190B2 JP3264190B2 JP27592196A JP27592196A JP3264190B2 JP 3264190 B2 JP3264190 B2 JP 3264190B2 JP 27592196 A JP27592196 A JP 27592196A JP 27592196 A JP27592196 A JP 27592196A JP 3264190 B2 JP3264190 B2 JP 3264190B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- positioning guide
- semiconductor device
- semiconductor chip
- terminal body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】この発明は、複数個の絶縁ゲ
ート型バイポーラトランジスタ（ＩＧＢＴ）などを同一
の平型パッケージ内に組み込んだ半導体装置に関する。The present invention relates to a semiconductor device in which a plurality of insulated gate bipolar transistors (IGBTs) and the like are incorporated in the same flat package.
【０００２】[0002]
【従来の技術】ＩＧＢＴはパワースイッチングデバイス
としてモータＰＷＭ制御インバータの応用などに幅広く
使われている。また、このＩＧＢＴは電圧駆動型で扱い
易い点などから、市場の要求は大容量化へと向かってい
る。このような中で、容量の増加を図るために、ＩＧＢ
Ｔチップを複数個、同一パッケージ内に集積したモジュ
ール構造が採用されている。2. Description of the Related Art IGBTs are widely used as power switching devices for applications such as motor PWM control inverters. In addition, since the IGBT is a voltage-driven type and is easy to handle, the demands on the market are increasing toward higher capacities. Under such circumstances, in order to increase the capacity, IGB
A module structure in which a plurality of T chips are integrated in the same package is employed.
【０００３】ところで、ＩＧＢＴのようなＭＯＳ制御型
のデバイスでは、半導体チップの主面上にエミッタ電極
とゲート電極とが並んで作られている。このため、ＩＧ
ＢＴをパッケージ容器に組み込む場合に、下面側に作ら
れたコレクタ電極は、放熱体兼用の金属ベースである支
持板上にはんだ等でマウントして、この支持板を外部導
出端子とすることができるが、エミッタ電極とゲート電
極は別々にボンディングワイヤなどで外部導出端子に接
続する必要がある。このボンディングワイヤの線径は３
００μｍ程度のアルミ導線であるため、エミッタ電極側
からの放熱は極めて悪く、コレクタ電極側からの片面放
熱となる。また内部配線インダクタンスも大きい。In a MOS control type device such as an IGBT, an emitter electrode and a gate electrode are formed side by side on a main surface of a semiconductor chip. For this reason, IG
When the BT is incorporated in a package container, the collector electrode formed on the lower surface side can be mounted on a support plate, which is a metal base also used as a heat radiator, with solder or the like, and this support plate can be used as an external lead terminal. However, the emitter electrode and the gate electrode need to be separately connected to an external lead-out terminal by a bonding wire or the like. The wire diameter of this bonding wire is 3
Since it is an aluminum conductive wire of about 00 μm, heat radiation from the emitter electrode side is extremely poor, and one-side heat radiation from the collector electrode side. Also, the internal wiring inductance is large.
【０００４】これらの解決のために、従来のサイリスタ
やＧＴＯサイリスタと同様に、セラミックの絶縁外筒を
有する平型パッケージに実装した加圧接触型のＩＧＢＴ
が提案されているが、ＧＴＯサイリスタと違って、ＩＧ
ＢＴのエミッタ電極側はＭＯＳ構造をしており、電気的
特性と長期信頼性を確保するために、このＭＯＳ構造部
以外の領域に集電電極を設けて加圧する必要がある。In order to solve these problems, similarly to a conventional thyristor or a GTO thyristor, a pressure contact type IGBT mounted on a flat package having a ceramic insulating outer cylinder is used.
Has been proposed, but unlike the GTO thyristor, the IG
The emitter electrode side of the BT has a MOS structure, and in order to secure electrical characteristics and long-term reliability, it is necessary to provide a current collecting electrode in a region other than the MOS structure and apply pressure.
【０００５】図３は従来の平型ＩＧＢＴの要部断面構造
を示す図である。図示されていない前記の集電電極と接
触するコンタクト端子体２は半導体チップ１の外周部に
設けたガードリング部６と接触しないように、半導体チ
ップ１のガードリング部６に対応するコンタクト端子体
２の面に凹部１４（切り欠き部）を設けている。また位
置決めガイド５をコレクタ基板３の二段の溝１５（円
内）の深い溝１２に挿入し、この位置決めガイド５をガ
イドにして半導体チップ１およびコンタクト端子体２と
を位置決めする。また浅い方の溝ははんだ逃げ代８とし
て利用する。尚、図３では平型パッケージを構成するセ
ラミックの絶縁外筒および上下の共通電極板は省略され
ており、平型パッケージに収納される内容物についての
み説明されている。また図では複数個の半導体チップ１
の内２個に相当した部分のみ詳細に示した。FIG. 3 is a diagram showing a cross-sectional structure of a main part of a conventional flat IGBT. A contact terminal body corresponding to the guard ring portion 6 of the semiconductor chip 1 so that the contact terminal body 2 that contacts the current collecting electrode (not shown) does not contact the guard ring portion 6 provided on the outer peripheral portion of the semiconductor chip 1. A concave portion 14 (a cutout portion) is provided on the second surface. Further, the positioning guide 5 is inserted into the deep groove 12 of the two-step groove 15 (in the circle) of the collector substrate 3, and the semiconductor chip 1 and the contact terminal body 2 are positioned using the positioning guide 5 as a guide. The shallower groove is used as a solder escape margin 8. FIG. 3 does not show the ceramic insulating outer cylinder and the upper and lower common electrode plates that constitute the flat package, and only the contents housed in the flat package are described. In the figure, a plurality of semiconductor chips 1
Only portions corresponding to two of them are shown in detail.
【０００６】[0006]
【発明が解決しようとする課題】従来のワイヤボンディ
ングを利用する組立構造ではコレクタ側から放熱はでき
るが、エミッタ側からの放熱は殆ど行われないために素
子の電流容量が大幅に制限される。また大電流容量の素
子ではエミッタ電極に接続したボンディングワイヤの本
数も多くなり、特に複数個のＩＧＢＴを同一パッケージ
に組み込んでモジュール化した構成ではワイヤ本数が数
百本にも及ぶため、内部配線インダクタンスが増大し、
これが基でＩＧＢＴのスイッチング動作時に大きなサー
ジが発生するといった問題や、信頼性的な問題なども派
生する。In a conventional assembly structure using wire bonding, heat can be dissipated from the collector side, but heat is hardly dissipated from the emitter side, so that the current capacity of the element is greatly limited. In the case of a device having a large current capacity, the number of bonding wires connected to the emitter electrode also increases. Particularly, in the case where a plurality of IGBTs are incorporated in the same package to form a module, the number of wires increases to several hundreds. Increases,
This leads to problems such as a large surge occurring during the switching operation of the IGBT and reliability problems.
【０００７】一方、前記の組立構造による放熱性、内部
配線インダクタンスなどの問題を解消することを狙い
に、ＧＴＯサイリスタなどの平型の半導体装置と同様に
ＩＧＢＴを平型パッケージに組み込み、その主面に形成
されたエミッタ電極、コレクタ電極をそれぞれ平型パッ
ケージの上下面に露出する共通電極板に面接触させて引
き出すようにすることが考えられる。しかしながら、Ｉ
ＧＢＴはゲート電極を覆う絶縁層の上にエミッタ電極が
延長して作られるために、半導体チップのエミッタ電極
に平型パッケージ側の共通電極板を加圧接触させると、
ＭＯＳ構造に加圧力が加わって応力の生じるおそれがあ
り、このままでは実用に供し得ない。このため、ＩＧＢ
Ｔのエミッタ電極側にＭＯＳ構造を持たない、電流通路
と放熱を目的とした集電電極と呼ばれる構造を設け、そ
の集電電極部にコンタクト端子体を位置決めガイドを用
い正確に位置決めして接触させ、加圧による応力がＭＯ
Ｓ構造部に及ばないようにしている。このように横方向
のずれがないように位置決めガイドで半導体チップおよ
びコンタクト端子体が正確に位置決めされる構造となっ
ている。On the other hand, in order to solve problems such as heat dissipation and internal wiring inductance due to the above-mentioned assembly structure, an IGBT is incorporated in a flat package like a flat semiconductor device such as a GTO thyristor, and the main surface thereof is formed. It is conceivable that the emitter electrode and the collector electrode formed in this manner are brought into surface contact with the common electrode plates exposed on the upper and lower surfaces of the flat package, respectively, and are drawn out. However, I
Since the GBT is formed by extending the emitter electrode on an insulating layer covering the gate electrode, when the common electrode plate on the flat package side is brought into pressure contact with the emitter electrode of the semiconductor chip,
There is a possibility that a stress is generated due to a pressing force applied to the MOS structure, so that it cannot be put to practical use as it is. For this reason, IGB
On the emitter electrode side of T, there is provided a structure called a collector electrode for the purpose of current flow and heat dissipation without a MOS structure, and the contact terminal body is accurately positioned and contacted with the collector electrode portion using a positioning guide. , The stress due to pressure is MO
It does not reach the S structure. In this manner, the semiconductor chip and the contact terminal body are accurately positioned by the positioning guide so that there is no lateral displacement.
【０００８】このように、横方向には位置決めガイドと
半導体チップおよびコンタクト端子体が正確に位置決め
される構造となっているが、半導体チップの耐圧を確保
するために設けられたガードリング部と接触しないよう
にコンタクト端子体に凹部を設けている。ガードリング
部上に金属で形成されたコンタクト端子体が来ると電界
強度が強くなり、この凹部で放電が起こり、ＩＧＢＴが
耐圧劣化を引き起こす。As described above, the positioning guide, the semiconductor chip, and the contact terminal body are configured to be accurately positioned in the lateral direction, but contact with the guard ring portion provided to ensure the withstand voltage of the semiconductor chip. A concave portion is provided in the contact terminal body so as not to prevent it. When the contact terminal body made of metal comes on the guard ring portion, the electric field strength increases, and a discharge occurs in this concave portion, causing the IGBT to deteriorate in withstand voltage.
【０００９】この発明の目的は、前記の課題を解決し、
ガードリング部で放電の発生がない高耐圧を確実に確保
できる半導体装置を提供することにある。An object of the present invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a semiconductor device that can reliably ensure a high withstand voltage in which no discharge occurs in a guard ring portion.
【００１０】[0010]
【課題を解決するための手段】前記の目的を達成するた
めに、例えばＩＧＢＴの場合、第１主面に第１主電極と
制御電極、第２主面に第２主電極を有する半導体チップ
を複数個並設して平型パッケージに組み込んだ半導体装
置で、両面に露出する一対の共通電極板と、両共通電極
板の間に挟まれる絶縁外筒とからなる平型パッケージ
に、半導体チップの第２主電極が一方の共通電極板に固
着され、且つ、半導体チップが位置決めガイドで位置決
めされて、固着され、他方の共通電極板と第１主電極と
の間に、前記の位置決めガイドで位置決めされた加圧、
導電および放熱を兼ねる個別のコンタクト端子体を具備
する半導体装置において、半導体チップの外周部に配置
されるガードリング部の上部を、隙間をもって覆うよう
に、位置決めガイドに凸部を設け、該凸部でコンタクト
端子体を位置決めする構成とする。To achieve the above object, for example, in the case of an IGBT, a semiconductor chip having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is used. A semiconductor device in which a plurality of semiconductor chips are juxtaposed and incorporated in a flat package. A flat package including a pair of common electrode plates exposed on both sides and an insulating outer cylinder sandwiched between the two common electrode plates is provided with a second semiconductor chip. The main electrode is fixed to one common electrode plate, and the semiconductor chip is positioned and fixed by a positioning guide, and is positioned between the other common electrode plate and the first main electrode by the positioning guide. Pressurization,
In a semiconductor device having individual contact terminals that also serve as conduction and heat dissipation, a projection is provided on a positioning guide so as to cover an upper part of a guard ring portion arranged on an outer peripheral portion of a semiconductor chip with a gap, and Is used to position the contact terminal body.
【００１１】前記の凸部が位置決めガイドの上部に設け
た上部蓋で形成されるとよい。またこの凸部が位置決め
ガイドと一体に形成されてもよい。また第１主面に第１
主電極と制御電極、第２主面に第２主電極を有する半導
体チップが絶縁ゲート型バイポーラトランジスタ、ＭＯ
Ｓ制御サイリスタもしくはＭＯＳトランジスタのいずれ
かであり、同一の平型パッケージ内に複数個の前記の半
導体チップと並置してフライホイールダイオードが組み
込まれ、他方の共通電極とフライホイールダイオードの
アノード電極との間に加圧、導電および放熱を兼ねたコ
ンタクト端子体を備えた構成とする。It is preferable that the projection is formed by an upper lid provided above the positioning guide. Further, the projection may be formed integrally with the positioning guide. Also, the first main surface has the first
A semiconductor chip having a main electrode and a control electrode and a second main electrode on a second main surface is an insulated gate bipolar transistor, MO
An S-control thyristor or a MOS transistor, in which a flywheel diode is incorporated side by side with a plurality of the semiconductor chips in the same flat package, and the other common electrode is connected to the anode electrode of the flywheel diode. A configuration is provided in which a contact terminal body having both pressure, conductivity, and heat radiation is provided therebetween.
【００１２】この構成とすると、ガードリング部の上方
に金属板が存在しなく、絶縁物がくるため、放電が発生
せず、また、コンタクト端子体はシリコンと熱膨張係数
が近いＭｏやＷで形成されているが、機械加工が極めて
困難で、凹部をこのＭｏ板やＷ板に設けると、製造コス
トがアップしてしまうが、この構成では、コンタクト端
子体には凹部を設ける必要がないため、製造コストを低
減できる。With this configuration, no metal plate exists above the guard ring portion, and an insulator is formed, so that no discharge occurs. Further, the contact terminal body is made of Mo or W having a thermal expansion coefficient close to that of silicon. Although it is formed, machining is extremely difficult, and providing a concave portion on this Mo plate or W plate increases the manufacturing cost. However, with this configuration, it is not necessary to provide a concave portion on the contact terminal body. The manufacturing cost can be reduced.
【００１３】[0013]
【発明の実施の形態】以下に説明する構成図では平型パ
ッケージを構成するセラミックの絶縁外筒および上下の
共通電極板は省略されており、平型パッケージに収納さ
れる内容物についてのみ説明されている。図１はこの発
明の第１実施例の要部構成図である。第１位置決めガイ
ド５ａをコレクタ基板３（ＩＧＢＴのコレクタ側がはん
だ付けされるＣｕなどでできた基板のこと）の溝１１に
挿入し、この第１位置決めガイド５ａをガイドとして、
はんだシート（図でははんだシートが溶けて半導体チッ
プ１とコレクタ基板３とがはんだ４で固着した状態を示
す）と半導体チップ１とを挿入し、第２位置決めガイド
５ｂ（上部枠のこと）を第１位置決めガイド５ａにセッ
トする。セットの仕方は第２位置決めガイド５ｂの外周
部に切り欠き部１０を設け第１位置決めガイドにその切
り欠き部１０をガイドにして載せる。第２位置決めガイ
ド５ｂにはコンタクト端子体２を位置決めする四角形の
孔（上部枠の内側のこと）が開いており、その孔にコン
タクト端子体２を挿入して位置決めする。その後でリフ
ロー炉などのはんだ付け炉を通して、半導体チップ１と
コレクタ基板３とをはんだ４で固着する。第１および第
２位置決めガイド５ａ、５ｂは耐熱性プラスチックで形
成され、はんだ付け工程での半導体チップ１の位置決め
に利用すると同時に高温工程での形状および材質の変化
がないため、最終製品での位置決めガイドとしても利用
している。従来のようにガードリング部６の上をコンタ
クト端子体２で覆うことがなく、絶縁物で形成された第
２位置決めガイド５ｂで覆うために、ガードリング部６
とコンタクト端子体２との放電はなくなる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the configuration diagrams described below, a ceramic insulating outer cylinder and upper and lower common electrode plates constituting a flat package are omitted, and only the contents housed in the flat package are described. ing. FIG. 1 is a configuration diagram of a main part of a first embodiment of the present invention. The first positioning guide 5a is inserted into the groove 11 of the collector substrate 3 (a substrate made of Cu or the like on which the collector side of the IGBT is soldered), and the first positioning guide 5a is used as a guide.
A solder sheet (in the figure, a state where the solder sheet is melted and the semiconductor chip 1 and the collector substrate 3 are fixed by the solder 4) and the semiconductor chip 1 are inserted, and the second positioning guide 5b (the upper frame) is inserted. 1 Set on the positioning guide 5a. In setting, a notch 10 is provided on the outer peripheral portion of the second positioning guide 5b, and the notch 10 is used as a guide on the first positioning guide. The second positioning guide 5b has a rectangular hole (inside the upper frame) for positioning the contact terminal body 2, and the contact terminal body 2 is inserted and positioned in the hole. After that, the semiconductor chip 1 and the collector substrate 3 are fixed with solder 4 through a soldering furnace such as a reflow furnace. The first and second positioning guides 5a and 5b are formed of heat-resistant plastic, and are used for positioning the semiconductor chip 1 in the soldering process, and at the same time there is no change in shape and material in the high-temperature process. I also use it as a guide. In order to cover the guard ring portion 6 with the second positioning guide 5b made of an insulating material without covering the guard ring portion 6 with the contact terminal body 2 unlike the related art,
And the contact terminal body 2 is no longer discharged.
【００１４】またこの構造にすることで、機械加工が困
難なＭｏやＷなどのコンタクト端子体２の外周部を従来
構造のように凹部に機械加工する必要もなくなり、また
第１位置決めガイド５ａにプラスチック（ポリイミドな
どの高温耐熱性樹脂）の成形でＬ字型９とすることで、
従来構造のようにコレクタ基板３にはんだ逃げ代用の溝
と位置決めガイド用の溝の二段の溝１５（図３参照）を
付ける必要もなくなり、製造コストを低減できる。With this structure, it is not necessary to machine the outer peripheral portion of the contact terminal body 2 such as Mo or W, which is difficult to machine, into a concave portion as in the conventional structure. By forming L-shaped 9 by molding plastic (high temperature heat resistant resin such as polyimide),
Unlike the conventional structure, there is no need to provide the collector substrate 3 with a two-step groove 15 (see FIG. 3) of a groove for a solder escape and a groove for a positioning guide, so that the manufacturing cost can be reduced.
【００１５】図２はこの発明の第２実施例の要部構成図
である。図１との大きな違いは第２位置決めガイドを第
１位置決めガイトと一体に形成している点である。コレ
クタ基板３にはんだシートと半導体チップ１を載せ、被
せるように位置決めガイド５をコレクタ基板３の深い溝
１２に挿入し、位置決めガイド５の内壁に付いている凸
部１３を位置決めとして利用してコンタクト端子体２を
挿入し、コンタクト端子体２と半導体チップ１とを位置
決めする。その後ではんだ付け炉を通してはんだ接合を
する。ガードリング部６の上には絶縁物の位置決めガイ
ド５の凸部１３がくるため、コンタクト端子体２とガー
ドリング部６との放電は起こらない。また従来構造のよ
うにコンタクト端子体２の外周部を凹型に加工する必要
がないため、製造コストは低減できる。FIG. 2 is a block diagram of a main part of a second embodiment of the present invention. The major difference from FIG. 1 is that the second positioning guide is formed integrally with the first positioning guide. The soldering sheet and the semiconductor chip 1 are placed on the collector substrate 3, and the positioning guide 5 is inserted into the deep groove 12 of the collector substrate 3 so as to cover the solder sheet and the semiconductor chip 1, and the projection 13 provided on the inner wall of the positioning guide 5 is used as a positioning contact. The terminal body 2 is inserted, and the contact terminal body 2 and the semiconductor chip 1 are positioned. After that, soldering is performed through a soldering furnace. Since the convex portion 13 of the insulator positioning guide 5 comes on the guard ring portion 6, no discharge occurs between the contact terminal body 2 and the guard ring portion 6. Further, since it is not necessary to process the outer peripheral portion of the contact terminal body 2 into a concave shape unlike the conventional structure, the manufacturing cost can be reduced.
【００１６】[0016]
【発明の効果】この発明によれば、半導体チップのＭＯ
Ｓ制御電極構造に異常な加圧力を加えることなしに、複
数個の半導体チップを平型パッケージに組み込んで面接
触による均一な加圧接触が達成できるとともに、各半導
体チップの両面からの放熱が可能となり、電流容量の大
幅な増加が図れるほか、主電極からの電流の引出しにボ
ンディングワイヤを使用しないので、内部配線インダク
タンスも小さくなる。またハーメチッックシールの平型
パッケージとボンディングワイヤを無くすることにより
大幅な信頼性の向上を図ることができる。さらにＩＧＢ
Ｔおよびダイオードなどの半導体チップのガードリング
部とコンタクト端子体との間の放電を防止することがで
き、且つ、機械加工が困難なＭｏやＷなどでできたコン
タクト端子体に従来必要とされた外周部に凹部を付ける
という機械加工が不要となり、製造コストが低減でき
る。According to the present invention, the MO of a semiconductor chip can be reduced.
Without applying abnormal pressure to the S control electrode structure, it is possible to achieve uniform pressure contact by surface contact by incorporating multiple semiconductor chips into a flat package and to radiate heat from both sides of each semiconductor chip. As a result, the current capacity can be greatly increased, and since the bonding wire is not used for extracting the current from the main electrode, the internal wiring inductance is also reduced. Also, by eliminating the flat package of the hermetic seal and the bonding wire, it is possible to significantly improve the reliability. Further IGB
Conventionally, a contact terminal body made of Mo, W, or the like, which can prevent discharge between a guard ring portion of a semiconductor chip such as T and a diode and a contact terminal body, and is difficult to machine. There is no need for machining to form a concave portion on the outer peripheral portion, and the manufacturing cost can be reduced.
【図１】この発明の第１実施例の要部構成図FIG. 1 is a configuration diagram of a main part of a first embodiment of the present invention.
【図２】この発明の第２実施例の要部構成図FIG. 2 is a configuration diagram of a main part of a second embodiment of the present invention.
【図３】従来の平型ＩＧＢＴの断面構造を示す図FIG. 3 is a diagram showing a cross-sectional structure of a conventional flat IGBT.
１ 半導体チップ ２ コンタクト端子体 ３ コレクタ基板 ４ はんだ ５ 位置決めガイド ５ａ 第１位置決めガイド ５ｂ 第２位置決めガイド ６ ガードリング部 ７ 隙間 ８ はんだ逃げ代 ９ Ｌ字型 １０ 切り欠き部 １１ 溝 １２ 深い溝 １３ 凸部 １４ 凹部 １５ 二段の溝 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Contact terminal body 3 Collector board 4 Solder 5 Positioning guide 5a 1st positioning guide 5b 2nd positioning guide 6 Guard ring part 7 Gap 8 Solder allowance 9 L shape 10 Notch part 11 Groove 12 Deep groove 13 Convex Part 14 Recess 15 Double groove
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 29/74 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/52 H01L 29/74 H01L 29/78
Claims (4)
面に第２主電極を有する半導体チップを複数個並設して
平型パッケージに組み込んだ半導体装置で、両面に露出
する一対の共通電極板と、両共通電極板の間に挟まれる
絶縁外筒とからなる平型パッケージに、半導体チップの
第２主電極が一方の共通電極板に固着され、且つ、半導
体チップが位置決めガイドで位置決めされて、固着さ
れ、他方の共通電極板と第１主電極との間に、前記の位
置決めガイドで位置決めされた加圧、導電および放熱を
兼ねる個別のコンタクト端子体を具備する半導体装置に
おいて、半導体チップの外周部に配置されるガードリン
グ部の上部を、隙間をもって覆うように、位置決めガイ
ドに凸部を設け、該凸部でコンタクト端子体を位置決め
することを特徴とする半導体装置。1. A semiconductor device comprising a plurality of semiconductor chips having a first main electrode and a control electrode on a first main surface and a plurality of semiconductor chips having a second main electrode on a second main surface, which are incorporated in a flat package. A second main electrode of a semiconductor chip is fixed to one common electrode plate in a flat package including a pair of exposed common electrode plates and an insulating outer cylinder sandwiched between the two common electrode plates, and the semiconductor chip is positioned. A semiconductor device including a separate contact terminal body which is positioned and fixed by a guide, and which also serves as a pressurizing, conductive, and heat dissipating position, which is positioned by the positioning guide, between the other common electrode plate and the first main electrode. Wherein a convex portion is provided on a positioning guide so as to cover a guard ring portion disposed on an outer peripheral portion of the semiconductor chip with a gap, and the contact terminal body is positioned by the convex portion. Semiconductor device.
枠で形成されることを特徴とする請求項１記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the projection is formed by an upper frame provided above the positioning guide.
ことを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the projection is formed integrally with the positioning guide.
面に第２主電極を有する半導体チップが絶縁ゲート型バ
イポーラトランジスタ、ＭＯＳ制御サイリスタもしくは
ＭＯＳトランジスタのいずれかであり、同一の平型パッ
ケージ内に複数個の前記の半導体チップと並置してフラ
イホイールダイオードが組み込まれ、他方の共通電極と
フライホイールダイオードのアノード電極との間に加
圧、導電および放熱を兼ねたコンタクト端子体を具備す
ることを特徴とする請求項１記載の半導体装置。4. A semiconductor chip having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is one of an insulated gate bipolar transistor, a MOS control thyristor and a MOS transistor, A flywheel diode is built in juxtaposition with a plurality of the above semiconductor chips in the same flat package, and a contact which combines pressure, conduction and heat dissipation between the other common electrode and the anode electrode of the flywheel diode The semiconductor device according to claim 1, further comprising a terminal body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27592196A JP3264190B2 (en) | 1996-10-18 | 1996-10-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27592196A JP3264190B2 (en) | 1996-10-18 | 1996-10-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10125701A JPH10125701A (en) | 1998-05-15 |
| JP3264190B2 true JP3264190B2 (en) | 2002-03-11 |
Family
ID=17562288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27592196A Expired - Fee Related JP3264190B2 (en) | 1996-10-18 | 1996-10-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3264190B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915350A (en) * | 2012-12-28 | 2014-07-09 | 西安永电电气有限责任公司 | IGBT-module installation method |
| CN115020252B (en) * | 2022-08-10 | 2022-11-08 | 合肥芯谷微电子有限公司 | Manufacturing method of TR component |
-
1996
- 1996-10-18 JP JP27592196A patent/JP3264190B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10125701A (en) | 1998-05-15 |
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