JP3262086B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3262086B2 JP3262086B2 JP31140098A JP31140098A JP3262086B2 JP 3262086 B2 JP3262086 B2 JP 3262086B2 JP 31140098 A JP31140098 A JP 31140098A JP 31140098 A JP31140098 A JP 31140098A JP 3262086 B2 JP3262086 B2 JP 3262086B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- metal film
- solder
- package
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体とパッケー
ジがはんだを使用して接合される半導体装置に関し、特
に半導体基板が薄膜化され、段差部が形成された半導体
とパッケージとをはんだを使用して接合される半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor and a package are joined by using solder. More particularly, the present invention relates to a semiconductor device in which a semiconductor substrate is thinned and a stepped portion is formed and the package is used by using solder. And a semiconductor device to be joined.
【０００２】[0002]
【従来の技術】近時、半導体装置おいて、放熱性を上げ
るために熱伝導率の低い半導体基板の薄膜化を行い、放
熱性の高いパッケージにマウントする方法が採用されて
いる。2. Description of the Related Art In recent years, in a semiconductor device, a method has been adopted in which a semiconductor substrate having a low thermal conductivity is thinned in order to enhance heat dissipation, and the semiconductor substrate is mounted on a package having high heat dissipation.
【０００３】しかし、この半導体基板の薄膜化は、半導
体基板の強度を低下させ、半導体基板の割れ、欠けを発
生しやすくし、パッケージへの組立時の半導体基板の取
り扱いを困難にしている。このため、薄膜化した半導体
基板の裏面及び側面を熱伝導率の良い金属膜で被覆し、
放熱性を上げて半導体基板の強度を確保する方法が用い
られている。[0003] However, the thinning of the semiconductor substrate reduces the strength of the semiconductor substrate, makes it easy for the semiconductor substrate to crack or chip, and makes it difficult to handle the semiconductor substrate during assembly into a package. For this reason, the back and side surfaces of the thinned semiconductor substrate are covered with a metal film having good thermal conductivity,
A method of increasing the heat dissipation and ensuring the strength of the semiconductor substrate has been used.
【０００４】図６は従来の方法でパッケージにマウント
された半導体装置を示す断面図である。従来の半導体基
板１００は、金属膜１０１を介してパッケージ１０８の
凹部１０８ｂにはんだ１０２により接合される。また、
半導体基板１００の上面１００ａには電極パッド１０３
が形成され、パッケージ１０８の上面１０８ａには配線
１０７が形成されている。この電極パッド１０３と配線
１０７とはボンディングワイヤ１０６により電気的に接
続されている。[0004] FIG. 6 is a sectional view showing a semiconductor device that is mounted in a package in a conventional manner. A conventional semiconductor substrate 100 is joined to a concave portion 108b of a package 108 by a solder 102 via a metal film 101. Also,
An electrode pad 103 is provided on the upper surface 100a of the semiconductor substrate 100.
Are formed, and a wiring 107 is formed on an upper surface 108a of the package 108. The electrode pad 103 and the wiring 107 are electrically connected by a bonding wire 106.
【０００５】裏面及び側面を金属膜１０１で被覆した半
導体基板１００をパッケージ１０８へマウントする場合
には、半導体基板１００とパッケージ１０８を加熱し、
両者の間に溶融させたはんだ１０２を流し込んで接合す
る。そして、全体を冷却して固定している。この半導体
基板１００を固定する場合に、半導体基板１００とパッ
ケージ１０８との密着性を上げるため、冶具で半導体基
板１００をパッケージ１０８に押しつける。この場合に
は、はんだ１０２が半導体基板１００の半導体基板側面
１０４を被覆した金属膜１０１表面を伝い、半導体基板
１００の上面１００ａにまで這い上がることがある。こ
のため半導体基板１００の上面１００ａの縁を覆ってい
る金属膜１０１上にはんだ１０２が広がり、表面張力に
より金属膜１０１上で***した形状で凝集し、突出部１
０５が形成される。When the semiconductor substrate 100 whose back and side surfaces are covered with the metal film 101 is mounted on the package 108, the semiconductor substrate 100 and the package 108 are heated,
The molten solder 102 is poured between the two to join them. And the whole is cooled and fixed. When the semiconductor substrate 100 is fixed, the semiconductor substrate 100 is pressed against the package 108 with a jig in order to increase the adhesion between the semiconductor substrate 100 and the package 108. In this case, the solder 102 may travel along the surface of the metal film 101 covering the side surface 104 of the semiconductor substrate 100 of the semiconductor substrate 100 and climb up to the upper surface 100 a of the semiconductor substrate 100. Therefore, the solder 102 spreads on the metal film 101 covering the edge of the upper surface 100a of the semiconductor substrate 100, and aggregates in a shape protruding on the metal film 101 due to surface tension.
05 is formed.
【０００６】[0006]
【発明が解決しようとする課題】しかし、半導体基板１
００の上面１００ａの縁の***したはんだ１０２の突出
部１０５は、半導体装置１００の外観不良を引き起こす
と共に、半導体基板１００の電極パッド１０３と、パッ
ケージ１０８の配線１０７とを接合するボンディングワ
イヤ１０６の障害となる。However, the semiconductor substrate 1
The protruding portion 105 of the solder 102 at the edge of the upper surface 100a of the semiconductor device 100 causes poor appearance of the semiconductor device 100, and also causes a failure of the bonding wire 106 joining the electrode pad 103 of the semiconductor substrate 100 and the wiring 107 of the package 108. Becomes
【０００７】また、この***した突出部１０５を介した
半導体基板１００との短絡を回避するため、ボンディン
グワイヤ１０６を山なりに長く打つ必要があり、これに
よりボンディングワイヤ１０６のインピーダンスの増加
・半導体装置１００との不整合を招くということが問題
点になっている。Further, in order to avoid a short circuit with the semiconductor substrate 100 via the raised protrusion 105, it is necessary to hit the bonding wire 106 long in a hill, thereby increasing the impedance of the bonding wire 106. There is a problem that inconsistency with 100 is caused.
【０００８】更に、ミリ波等の高周波で用いる半導体装
置の場合、ボンディングワイヤ１０６のインピーダンス
の増加・不整合は信号の損失となり、半導体装置の特性
を劣化させるということが問題点になっている。Further, in the case of a semiconductor device used at a high frequency such as a millimeter wave, an increase or mismatch of the impedance of the bonding wire 106 results in a loss of a signal, thereby deteriorating the characteristics of the semiconductor device.
【０００９】本発明はかかる問題点に鑑みてなされたも
のであって、薄膜化された半導体基板の縁部にＬ字型の
段差部を設け、この段差部に金属膜を成膜することによ
り半導体基板を割れ又は欠け等から守り、半導体基板を
パッケージに取り付ける場合、半導体基板の上面へのは
んだの這い上がりによる凝集・突出の防止を可能するこ
とができる半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is provided by providing an L-shaped step at an edge of a thinned semiconductor substrate and forming a metal film on the step. It is an object of the present invention to provide a semiconductor device capable of protecting a semiconductor substrate from cracking or chipping or the like and, when mounting the semiconductor substrate in a package, capable of preventing aggregation and protrusion due to solder creeping up on the upper surface of the semiconductor substrate. .
【００１０】[0010]
【課題を解決するための手段】本願第１発明に係る半導
体装置は、回路が形成され底面及び側面が金属膜により
覆われた半導体基板と、前記半導体基板がはんだにより
接合されて収納されるパッケージと、を有し、前記半導
体基板の上面縁部には金属膜により覆われて前記はんだ
が溜まる段差部が形成されていることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device in which a circuit is formed and a bottom surface and side surfaces are formed of a metal film.
The covered semiconductor substrate and the semiconductor substrate are soldered
Has a package are joined Ru is accommodated, wherein the solder above the upper surface edge portion of the semiconductor substrate is covered with a metal film
Wherein the step portion accumulated is formed.
【００１１】本願第２発明に係る半導体装置は、回路が
形成され底面及び側面が金属膜により覆われた半導体基
板と、前記半導体基板がはんだにより接合されて収納さ
れるパッケージと、前記半導体基板及びパッケージの上
面に夫々設けられた電極パッド及び配線と、前記電極パ
ッドと配線とを接続するボンディングワイヤと、を有
し、前記半導体基板の上面における前記電極パッドより
も端縁側の部分に局部的に金属膜により覆われて前記は
んだが溜まる段差部が形成されていることを特徴とす
る。[0011] The semiconductor device according to the present second invention, housing and the semiconductor substrate bottom surface and side circuit is formed is covered with a metal film, wherein the semiconductor substrate is bonded by solder
A package that Re, the includes a semiconductor substrate and a top surface of the package respectively provided with electrode pads and wiring, and a bonding wire for connecting the wiring and the electrode pad than the electrode pads on the upper surface of the semiconductor substrate
Is also partially covered with a metal film on the edge side.
I I wherein the Tei Rukoto stepped portion is formed accumulated but.
【００１２】本発明においては、前記半導体基板は、金
属膜で覆われていることが好ましい。In the present invention, it is preferable that the semiconductor substrate is covered with a metal film.
【００１３】また、本発明においては、前記段差部は、
前記半導体基板の縦断面においてＬ字形に形成すること
ができ、この場合に、前記段差部の深さは、前記はんだ
の盛り上がり高さと実質的に同一か又はそれより深いこ
とが好ましい。[0013] In the present invention, the step portion may include:
Forming an L-shaped in longitudinal section of the semiconductor substrate
In this case, the depth of the step is
It is preferable that the height is substantially the same as or higher than the swelling height .
【００１４】本願第３発明に係る半導体装置の製造方法
は、半導体基板の上面に回路と電極パッドとを形成する
工程と、前記半導体基板の上面縁部に段差部を形成する
工程と、前記段差部に金属膜を形成する工程と、前記半
導体基板の底面及び側面に金属膜を形成する工程と、前
記半導体基板の裏面とパッケージとの間にはんだを介し
て両者を接合する工程と、を有することを特徴とする。[0014] manufacturing method of the present semiconductor device according to the third invention includes the steps of forming a circuit and electrode pads on the upper surface of the semiconductor substrate, forming a stepped portion to the top edge portions of the semiconductor substrate, the step forming a metal film on the parts, forming a metal film on the bottom and side surfaces of the semiconductor substrate, prior to
Insert solder between the back of the semiconductor substrate and the package.
And joining the two together.
【００１５】本願第４発明に係る半導体装置の製造方法
は、半導体基板の上面に回路と電極パッドとを形成する
工程と、前記半導体基板の上面における前記電極パッド
よりも端部側の部分に局所的に段差部を形成する工程
と、前記段差部に金属膜を形成する工程と、前記半導体
基板の底面及び側面に金属膜を形成する工程と、前記半
導体基板の裏面とパッケージとの間にはんだを介して両
者を接合する工程と、を有することを特徴とする。A method of manufacturing a semiconductor device according to a fourth aspect of the present invention includes the steps of forming a circuit and an electrode pad on an upper surface of a semiconductor substrate, and forming the electrode pad on the upper surface of the semiconductor substrate.
Forming a locally stepped portion on a portion of the end portion than the step of forming a metal film on the step portion, forming a metal film on the bottom and side surfaces of said semiconductor substrate, said half
Solder between the back of the conductive board and the package
Joining the persons .
【００１６】本発明においては、前記段差部の深さは、
前記半導体基板と前記パッケージとの接合後にはんだが
溜まる高さと実質的に同一か又はそれより深いことが好
ましい。In the present invention, the depth of the step portion is
After joining the semiconductor substrate and the package, the solder
Preferably, it is substantially equal to or deeper than the pool height .
【００１７】本発明においては、半導体基板の上面縁部
にはんだが溜まる段差部を設けることにより、半導体基
板とパッケージとの接合する場合に、はんだが半導体基
板の上面上まで這い上がることを防止することができ
る。In the present invention, by providing a step portion on the upper surface edge of the semiconductor substrate where the solder accumulates , when the semiconductor substrate and the package are joined, the solder is applied to the semiconductor substrate.
Crawling up to the upper surface of the plate can be prevented .
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施例に係る半導
体装置について、添付の図面を参照して具体的に説明す
る。図１は、本発明の実施例に係るパッケージに取り付
けられた半導体装置のボンディング部を示す断面図であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a sectional view showing a bonding portion of a semiconductor device mounted on a package according to an embodiment of the present invention.
【００１９】本発明の実施例に係る半導体装置におい
て、半導体基板１は薄膜化され、半導体基板１の外周部
領域の全てに亘り半導体基板の縦断面において、Ｌ字形
の段差部５が形成されている。この半導体基板１の外周
面及び底面１ｂには、金属膜２が形成されている。即
ち、半導体基板１には、上面縁部に段差部５が形成さ
れ、上面を除く全ての面に金属膜２が形成されている。In the semiconductor device according to the embodiment of the present invention, the semiconductor substrate 1 is thinned, and an L-shaped stepped portion 5 is formed in the vertical section of the semiconductor substrate over the entire outer peripheral region of the semiconductor substrate 1. I have. A metal film 2 is formed on the outer peripheral surface and the bottom surface 1b of the semiconductor substrate 1. That is, the semiconductor substrate 1 has the step portion 5 formed on the upper surface edge, and the metal film 2 formed on all surfaces except the upper surface.
【００２０】半導体基板１は、この金属膜２を介してパ
ッケージ９の凹部９ｂにはんだ３により接合されてい
る。また、半導体基板１の上面１ａには回路（図示せ
ず）と電極パッド４とが形成され、パッケージ９の上面
９ａには配線８が形成されている。この電極パッド４と
配線８とはボンディングワイヤ７により電気的に接続さ
れている。The semiconductor substrate 1 is joined to the recess 9b of the package 9 by the solder 3 via the metal film 2. Further, the upper surface 1a of the semiconductor substrate 1 circuitry (not shown) and the electrode pad 4 is formed, the wiring 8 is formed on the upper surface 9a of the package 9. The electrode pad 4 and the wiring 8 are electrically connected by a bonding wire 7.
【００２１】上述の構成とすることにより、パッケージ
９に半導体基板１をマウントする場合に、半導体基板１
の側面部から這い上がったはんだ３はＬ字型の段差部５
に凝集して、突出部６を形成する。この這い上がったは
んだ３の突出部６の高さは、Ｌ字型の段差部５で濡れる
ために突出することがなく半導体基板１及びパッケージ
９の夫々の上面１ａ、９ａの略同一の高さに抑えること
ができる。また、はんだ３の這い上がりによる半導体装
置の外観不良を防ぐことができる。更に、はんだ３の突
出部６の高さを抑えることができるために、半導体基板
１の電極パッド４と、パッケージ９の上面９ａに形成さ
れた配線８とを接合する場合にボンディングワイヤ７を
短縮でき、半導体装置の特性を低下させるボンディング
ワイヤ７のインピーダンス増加を低減させることができ
る。With the above configuration, when the semiconductor substrate 1 is mounted on the package 9, the semiconductor substrate 1
The step portion 5 is a side section or al crept up solder third L-shaped
To form the protrusion 6. The height of the protruding portion 6 of the crawled solder 3 is substantially the same as the height of the upper surfaces 1a and 9a of the semiconductor substrate 1 and the package 9, respectively, without protruding because of being wet by the L-shaped step portion 5. Can be suppressed. Further, it is possible to prevent the appearance of the semiconductor device from being defective due to the creeping of the solder 3. Furthermore, since the height of the protruding portion 6 of the solder 3 can be suppressed, the bonding wire 7 is shortened when the electrode pad 4 of the semiconductor substrate 1 is bonded to the wiring 8 formed on the upper surface 9a of the package 9. As a result, an increase in the impedance of the bonding wire 7 that degrades the characteristics of the semiconductor device can be reduced.
【００２２】本実施例においては、半導体基板１の上面
縁部に設けたＬ字型の段差部５に凝集するはんだ３が、
段差部５を包み込むことにより半導体基板１の外周部の
欠け等に対する保護材の役割を果たす。In the present embodiment, the solder 3 agglomerated on the L-shaped step 5 provided on the edge of the upper surface of the semiconductor substrate 1
Enclosing the step 5 serves as a protective material against chipping of the outer peripheral portion of the semiconductor substrate 1 and the like.
【００２３】次に、本発明の実施例に係る半導体装置の
製造方法について説明する。図２及び図３は、本実施例
の製造方法を工程順に示す断面図である。Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. 2 and 3 are cross-sectional views showing the manufacturing method of this embodiment in the order of steps.
【００２４】先ず、図２（ａ）に示すように半導体基板
１に回路１０及び電極パッド４を形成する。次に、図２
（ｂ）に示すように、この半導体基板１をＬ字型の段差
部５となる部分以外をレジスト１１で覆う。次に、図２
（ｃ）に示すように、例えばドライエッチングにより半
導体基板１を上面１ａ側から垂直方向に、例えば５０μ
ｍ彫り込み、Ｌ字型の段差部５を形成する。First, a circuit 10 and an electrode pad 4 are formed on a semiconductor substrate 1 as shown in FIG. Next, FIG.
As shown in FIG. 1B, the semiconductor substrate 1 is covered with a resist 11 except for the portion that becomes the L-shaped step portion 5. Next, FIG.
(C), the vertical semiconductor substrate 1 by de dry etching from the top surface 1a side For example, for example 50μ
An m-carved portion is formed to form an L-shaped step portion 5.
【００２５】更に、図２（ｄ）に示すようにレジスト１
１を残した状態で、Ｌ字型の段差部５に、例えばスパッ
タリング法又はメッキ法で、例えば金等の金属膜２を、
例えば膜厚を３μｍに形成する。そして、レジスト１１
とレジスト１１上の金属膜２を、例えばリフトオフ法等
で除去し、Ｌ字型の段差部５にのみ金属膜２が残るよう
に形成し、Ｌ字型の段差部５に金属膜２を形成した後、
半導体基板１を裏面１ｂ側より、例えば研磨又はエッチ
ングによる方法で、半導体基板１の厚さが、例えば１０
０μｍまで薄膜化する。Further, as shown in FIG.
While leaving one, the stepped portion 5 of the L-shaped, with scan pad <br/> Taringu method or plating For example, the metal film 2 such as gold For example,
For example to form a film thickness 3 [mu] m. And resist 11
And a metal film 2 on the resist 11 is removed by re Futoofu method For example, as the metal film 2 remains only in the step portion 5 of the L-shaped
After formed, forming a metal film 2 on the stepped portion 5 of the L-shape,
From the semiconductor substrate 1 back surface 1b side, in the process according to the Invite Migaku Ken or etching for example, the thickness of the semiconductor substrate 1 is 1 For example 0
The thickness is reduced to 0 μm.
【００２６】次に、図３（ａ）に示すように、回路１０
部分を個別に分離し、半導体基板１の裏面１ｂ及び側面
１ｃに金属膜２を形成するため、半導体基板１の裏面１
ｂ側よりレジスト１１でパターニングする。この場合に
は、Ｌ字型の段差部５の水平部の長さを、例えば４０μ
ｍに形成するため、パターニングによる開口部１２は上
面１ａでエッチングを行った領域よりも狭いことが必要
である。Next, as shown in FIG.
In order to form the metal film 2 on the back surface 1b and the side surface 1c of the semiconductor substrate 1,
Patterning is performed with the resist 11 from the b side. In this case, the length of the horizontal portion of the L-shaped step portion 5, for example if 4 0Myu
m, the opening 12 by patterning needs to be narrower than the region etched on the upper surface 1a.
【００２７】次に、図３（ｂ）に示すように、半導体基
板１の裏面１ｂ側からレジスト１１の開口部１２を、例
えば、ドライエッチング等の異方性の高いエッチング方
法を使用してＬ字型の段差部５上に形成した金属膜２に
達するまで半導体基板１をエッチングする。更に、レジ
スト１１の開口部１２の金属膜２を例えば、イオンミリ
ング法やエッチング法等により除去し、回路１０部分毎
に半導体基板１を分離する。そして、レジスト１１を除
去する。Next, as shown in FIG. 3B, the opening 12 of the resist 11 is cut from the back surface 1b side of the semiconductor substrate 1 by using an etching method having high anisotropy such as dry etching. The semiconductor substrate 1 is etched until it reaches the metal film 2 formed on the V-shaped step portion 5. Further, the metal film 2 in the opening 12 of the resist 11 is removed by, for example, an ion milling method or an etching method, and the semiconductor substrate 1 is separated for each circuit 10 portion. Then, the resist 11 is removed.
【００２８】次に、図３（ｃ）に示すように半導体基板
１の裏面１ｂ及び側面１ｃに例えば、スパッタリング法
又はメッキ法により、例えば、膜厚が２０μｍの金の金
属膜２を形成する。Next, as shown in FIG. 3C, a gold metal film 2 having a thickness of, for example, 20 μm is formed on the back surface 1b and the side surface 1c of the semiconductor substrate 1 by, for example, a sputtering method or a plating method.
【００２９】次に、図３（ｄ）に示すように、この半導
体基板１の側面に形成した金属膜２は上面１ａに形成し
た金属膜２とがつながる。Next, as shown in FIG. 3D, the metal film 2 formed on the side surface of the semiconductor substrate 1 is connected to the metal film 2 formed on the upper surface 1a.
【００３０】これにより、半導体基板１の外周面にＬ字
型の段差部５が形成され、更に金属膜２が半導体基板１
の裏面１ｂ及び側面１ｃに形成される。また、半導体基
板１をパッケージ９に取り付ける場合に、はんだ３が半
導体基板１の側面１ｃ側を這い上がっても、Ｌ字型の段
差部５にはんだ３が凝集して突出部６が形成される。溶
融したはんだ３の接触面積が増えるために突出部６の隆
起が抑えられてしまうために、半導体基板１及びパッケ
ージ９の夫々の上面１ａ、９ａよりも高く形成されるこ
とがない。As a result, an L-shaped step 5 is formed on the outer peripheral surface of the semiconductor substrate 1 and the metal film 2 is further formed on the semiconductor substrate 1.
Are formed on the back surface 1b and the side surface 1c. Further, when the semiconductor substrate 1 is mounted on the package 9, even when the solder 3 crawls on the side surface 1 c side of the semiconductor substrate 1, the solder 3 aggregates on the L-shaped step portion 5 to form the protruding portion 6. . Since the protrusion of the protruding portion 6 is suppressed because the contact area of the molten solder 3 is increased, the protrusion is not formed higher than the upper surfaces 1a and 9a of the semiconductor substrate 1 and the package 9, respectively.
【００３１】本実施例においては、金属膜２に金を使用
したが、特にこれに限定されるものではなく、半導体基
板１に反りが生じにくく、はんだ３に対して濡れ性の良
い金属であればよい。また、金属膜２の膜厚に関して
も、Ｌ字型の段差部５で形成される突出部６にはんだ３
が付いた状態で半導体基板１及びパッケージ９の上面１
ａ、９ａよりも突出することのない膜厚であればよく、
特に３μｍに限定されるものではなく、半導体基板１の
大小等により適宜変更可能である。In the present embodiment, gold is used for the metal film 2. However, the present invention is not limited to this. Any metal that does not easily warp the semiconductor substrate 1 and has good wettability to the solder 3 is used. I just need. Regarding the thickness of the metal film 2, the protrusions 6 formed by the L-shaped step portions 5 have the solder 3.
With the semiconductor substrate 1 and the upper surface 1 of the package 9
a, any film thickness that does not protrude beyond 9a,
The thickness is not particularly limited to 3 μm, and can be changed as appropriate according to the size of the semiconductor substrate 1 or the like.
【００３２】次に、本発明の他の実施例について説明す
る。図４及び図５は、本発明の他の実施例に係る半導体
装置の製造方法を工程順に示す断面図である。なお、本
発明の実施例を示す図１乃至図３と同一構成には、同一
符号を付してその詳細な説明は省略する。Next, another embodiment of the present invention will be described. 4 and 5 are sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps. 1 to 3 showing the embodiment of the present invention are denoted by the same reference numerals, and a detailed description thereof will be omitted.
【００３３】本願出願人は、実施例においては図３
（ｄ）に示すように半導体基板１の回路１０の全周囲に
亘りＬ字型の段差部５を設ける構成としたが、ボンディ
ングワイヤ７の短絡の問題が発生するのは、半導体基板
１からパッケージ９へボンディングワイヤ７を引き出す
引出部分である。このため、ボンディングワイヤ７の引
出部分にのみＬ字型の段差部６に設ける構成とすると共
に、はんだ３の突出部６が生じないようにすればよいこ
とを見出した。The applicant of the present invention has shown in FIG.
As shown in (d), the L-shaped stepped portion 5 is provided over the entire periphery of the circuit 10 of the semiconductor substrate 1. However, the problem of short-circuiting of the bonding wires 7 occurs because 9 is a drawing portion for drawing out the bonding wire 7 to 9. Therefore, it has been found that the L-shaped stepped portion 6 should be provided only at the portion where the bonding wire 7 is drawn out, and that the projecting portion 6 of the solder 3 should not be formed.
【００３４】本実施例は、実施例と比較して、電極パッ
ド４部からボンディングワイヤ７を引き出す引出部のみ
Ｌ字型の段差部５を設ける構成とした点で異なり、それ
以外は同一である。The present embodiment is different from the embodiment in that an L-shaped step portion 5 is provided only in a lead portion for pulling out a bonding wire 7 from an electrode pad 4 portion, and the other portions are the same. .
【００３５】上述の構成にすることにより、ボンディン
グワイヤ７の引出部分にのみＬ字型の段差部５が設けら
れ、半導体基板１とパッケージ９とを金属膜２を介して
はんだ３により組立てした場合、突出部６は半導体基板
１の上面１ａよりも突出することがない。With the above-described structure, the L-shaped step portion 5 is provided only at the portion where the bonding wire 7 is drawn out, and the semiconductor substrate 1 and the package 9 are assembled with the solder 3 via the metal film 2. The protrusion 6 does not protrude from the upper surface 1a of the semiconductor substrate 1.
【００３６】次に、本発明の実施例に係る半導体装置の
製造方法について説明する。図４及び図５は、本実施例
の製造方法を工程順に示す断面図である。Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. 4 and 5 are cross-sectional views showing the manufacturing method of this embodiment in the order of steps.
【００３７】先ず、図４（ａ）に示すように、半導体基
板１に電極パッド４、金属膜２及び回路１０を形成す
る。この場合には、Ｌ字型の段差部５となる部分以外は
半導体基板１の周囲を保護するための金属膜２を形成す
る。First, as shown in FIG. 4A, an electrode pad 4, a metal film 2, and a circuit 10 are formed on a semiconductor substrate 1. In this case , a metal film 2 is formed to protect the periphery of the semiconductor substrate 1 except for the portion that becomes the L-shaped step portion 5.
【００３８】次に、図４（ｂ）に示すように、Ｌ字型の
段差部５を形成する部分のみ開口するようにパターニン
グしたレジスト１１で半導体基板１の上面１ａを覆う。Next, as shown in FIG. 4B, the upper surface 1a of the semiconductor substrate 1 is covered with a resist 11 patterned so as to open only a portion where the L-shaped step 5 is formed.
【００３９】次に、図４(ｃ)に示すように、例えばドラ
イエッチングにより半導体基板１を、例えば５０μｍ彫
り込み、Ｌ字型の段差部５を形成する。Next, as shown in FIG. 4 (c), for example, a semiconductor substrate 1 by dry etching, engraving 5 0 .mu.m For example, to form the stepped portion 5 of the L-shape.
【００４０】次に、図４（ｄ）に示すように、レジスト
１１を残した状態で、半導体基板１の上面１ａ側からＬ
字型の段差部５に、例えばスパッタリング法又はメッキ
法を使用して金等の金属膜２を、例えば膜厚を３μｍに
形成する。この場合には、Ｌ字型の段差部５の底面１ｂ
及び側面１ｃに金属膜２が形成される。レジスト１１と
レジスト１１上の金属膜２を、例えばリフトオフ法等で
除去し、Ｌ字型の段差部５にのみ金属膜２を残す。更
に、半導体基板１を裏面１ｂ側から、例えば研磨又はエ
ッチングを使用して、半導体基板１の厚さを、例えば１
００μｍまで薄膜化する。Next, as shown in FIG. 4D, while the resist 11 is left, the upper surface 1a of the semiconductor substrate 1 is
The stepped portion 5 of the shaped, a metal film 2 such as gold using a scan sputtering method or plating For example, a film thickness when compared to a 3 [mu] m. In this case, the bottom surface 1b of the L-shaped step portion 5
The metal film 2 is formed on the side surface 1c. The metal film 2 on the resist 11 and the resist 11 is removed by re Futoofu method For example, leaving the metal layer 2 only in the stepped portion 5 of the L-shape. Further, the semiconductor substrate 1 from the back surface 1b side, for example using a grinding or etching, the thickness of the semiconductor substrate 1, for example 1
The thickness is reduced to 00 μm.
【００４１】そして、図５（ａ）に示すように、回路１
０部分を個別に分離し、半導体基板１の裏面１ｂ及び側
面１ｃに金属膜２を形成するため、半導体基板１の裏面
１ｂ側よりレジスト１１で開口部１２を設けてパターニ
ングする。Then, as shown in FIG.
In order to form the metal film 2 on the back surface 1b and the side surface 1c of the semiconductor substrate 1, an opening 12 is formed with a resist 11 from the back surface 1b side of the semiconductor substrate 1 and patterned.
【００４２】次に、図５（ｂ）に示すように、半導体基
板１の裏面１ｂ側からレジスト１１の開口部１２を、例
えばドライエッチング等の異方性の高いエッチング方法
を使用してＬ字型の段差部５上に形成した金属膜２に達
するまで半導体基板１をエッチングする。更に、レジス
ト１１の開口部１２の金属膜２を、例えばイオンミリン
グ法又はエッチング法等により除去し、回路１０を部分
毎に半導体基板１を分離する。そして、レジスト１１を
除去する。Next, as shown in FIG. 5 (b), the opening 12 of the resist 11 from the back surface 1b side of the semiconductor substrate 1, a high anisotropy of de dry etching or the like For example <br/> example etching Using the method, the semiconductor substrate 1 is etched until the metal film 2 formed on the L-shaped step portion 5 is reached. Further, a metal film 2 of the opening 12 of the Regis <br/> DOO 11 was removed by Lee Onmiringu method or etching method, etc. For example, to separate the semiconductor substrate 1 to the circuit 10 for each partial. Then, the resist 11 is removed.
【００４３】次に、図５（ｃ）に示すように半導体基板
１の裏面１ｂ及びその側面１ｃに、例えばスパッタリン
グ法又はメッキ法により、例えば金で膜厚が２０μｍの
金属膜２を形成する。Next, the back surface 1b and the side surface 1c of the semiconductor substrate 1 as shown in FIG. 5 (c), by, for example, a sputtering method or a plating method, the film thickness of gold For example to form the metal film 2 of 20μm .
【００４４】次に、図５（ｄ）に示すように、この半導
体基板１の側面に形成した金属膜２は上面１ａに形成し
たＬ字型の段差部５の金属膜２とつながる。Next, as shown in FIG. 5 (d), a metal film 2 formed on the side surface of the semiconductor substrate 1 is want metal film 2 convex L-shaped step portion 5 formed on the upper surface 1a .
【００４５】これにより、半導体基板１の外周面にＬ字
型の段差部５が形成され、更に金属膜２が半導体基板１
の裏面１ｂ及び側面１ｃに形成される。また、半導体基
板１をパッケージ９に取り付ける場合に、はんだ３が半
導体基板１の側面１ｃ側を這い上がっても、Ｌ字型の段
差部５にはんだ３が凝集して突出部６が形成される。溶
融したはんだ３の接触面積が増えるために突出部６の隆
起が抑えられてしまい、半導体基板１及びパッケージ９
の夫々の上面１ａ、９ａよりも高く形成されることがな
い。As a result, an L-shaped step 5 is formed on the outer peripheral surface of the semiconductor substrate 1, and the metal film 2 is further formed on the semiconductor substrate 1.
Are formed on the back surface 1b and the side surface 1c. Further, when the semiconductor substrate 1 is mounted on the package 9, even when the solder 3 crawls on the side surface 1 c side of the semiconductor substrate 1, the solder 3 aggregates on the L-shaped step portion 5 to form the protruding portion 6. . Melted with raised protrusions 6 is suppressed because the contact area of the solder 3 is increased have striped semiconductor substrate 1 and the package 9
Are not formed higher than the respective upper surfaces 1a and 9a.
【００４６】上述のいずれの実施例において、Ｌ字型の
段差部５のコーナー部は必ずしも垂直である必要はな
く、台形状又は円錐状とすることができる。In any of the above embodiments, the corners of the L-shaped step 5 do not necessarily have to be vertical, but may be trapezoidal or conical.
【００４７】また、上述のいずれの実施例において、半
導体基板１を金属膜２で覆う構成としたが、この金属膜
２は、半導体基板１の裏面１ｂ、段差部５及び段差部５
から裏面１ｂに続く側面に形成されていればよい。In each of the above embodiments, the semiconductor substrate 1 is covered with the metal film 2. However, the metal film 2 is formed on the back surface 1 b of the semiconductor substrate 1, the step 5, and the step 5.
It is only necessary to be formed on the side surface following the back surface 1b.
【００４８】[0048]
【発明の効果】以上詳述したように本発明によれば、薄
膜化された半導体基板の上面縁部にはんだが溜まる段差
部を設け、この段差部に金属膜を成膜することにより半
導体基板を割れ・欠けから守り、半導体基板をパッケー
ジに取り付ける場合の半導体基板の上面へのはんだの這
い上がりによる突出部の形成を防止することができる。As described above in detail, according to the present invention, a step portion in which solder accumulates is provided at an upper edge of a thinned semiconductor substrate, and a metal film is formed on the step portion to form a semiconductor substrate. From cracking or chipping, and the formation of a protruding portion due to solder creeping up on the upper surface of the semiconductor substrate when the semiconductor substrate is mounted on a package can be prevented.
【００４９】また、はんだの突出部が半導体基板上面よ
り突出しないことにより、ボンディングワイヤの長さを
最適化することができるためにインピーダンスの増加・
半導体装置との不整合を回避することができる。更に、
半導体装置の外観不良となることがない。Further, since the protruding portion of the solder does not protrude from the upper surface of the semiconductor substrate, the length of the bonding wire can be optimized, thereby increasing the impedance.
Mismatch with the semiconductor device can be avoided. Furthermore,
The appearance of the semiconductor device does not deteriorate.
【図１】本発明の実施例に係るパッケージに取り付けら
れた半導体装置のボンディング部を示す断面図である。FIG. 1 is a sectional view showing a bonding portion of a semiconductor device attached to a package according to an embodiment of the present invention.
【図２】（ａ）乃至（ｄ）は、本発明の実施例に係る半
導体装置の製造方法を工程順に示す断面図である。FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【図３】（ａ）乃至（ｄ）は、図２の次の工程を示す断
面図である。FIGS. 3A to 3D are cross-sectional views showing the next step of FIG.
【図４】（ａ）乃至（ｄ）は、本発明の他の実施例に係
る半導体装置の製造方法を工程順に示す断面図である。4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.
【図５】（ａ）乃至（ｄ）は、図４の次の工程を示す断
面図である。FIGS. 5A to 5D are cross-sectional views showing the next step of FIG.
【図６】従来の半導体装置を示す断面図である。FIG. 6 is a sectional view showing a conventional semiconductor device.
１、１００；半導体基板 １ａ、１００ａ、９ａ、１０８ａ；上面 １ｂ；裏面 １ｃ；側面 ２、１０１；金属膜 ３、１０２；はんだ ４、１０３；電極パッド ５；段差部 ６、１０５；突出部 ７、１０６；ボンディングワイヤ ８、１０７；配線 ９、１０８；パッケージ ９ｂ、１０８ｂ；凹部 １０；回路 １１；レジスト １２；開口部 １０４；半導体基板側面 1,100; semiconductor substrate 1a, 100a, 9a, 108a; top 1b; backside 1c; side 2,101; metal film 3,102; solder 4,103; electrode pads 5; step portion 6,105; protrusion 7, 106; bonding wire 8,107; wiring 9,108; package 9b, 108b; recess 10; circuit 11; resist 12; opening 104; the semiconductor substrate side
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−145739（ＪＰ，Ａ) 特開 平６−112249（ＪＰ，Ａ) 特開 平５−182997（ＪＰ，Ａ) 特開 昭63−241937（ＪＰ，Ａ) 特開 昭58−158935（ＪＰ，Ａ) 特開 昭64−12541（ＪＰ，Ａ) 特開 昭61−115332（ＪＰ，Ａ) 特開 昭55−148434（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-145739 (JP, A) JP-A-6-112249 (JP, A) JP-A-5-182997 (JP, A) JP-A-63- 241937 (JP, A) JP-A-58-158935 (JP, A) JP-A-64-12541 (JP, A) JP-A-61-115332 (JP, A) JP-A-55-148434 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/52 H01L 21/60
Claims (7)
より覆われた半導体基板と、前記半導体基板がはんだに
より接合されて収納されるパッケージと、を有し、前記
半導体基板の上面縁部には金属膜により覆われて前記は
んだが溜まる段差部が形成されていることを特徴とする
半導体装置。1. A circuit is formed and a bottom surface and side surfaces are formed on a metal film.
And more covered semiconductor substrate, the semiconductor substrate is a solder
It has a package that will be accommodated is more joined, wherein the the top edge portions of the semiconductor substrate is covered with a metal film
And wherein a step portion that do it but accumulated is formed.
より覆われた半導体基板と、前記半導体基板がはんだに
より接合されて収納されるパッケージと、前記半導体基
板及びパッケージの上面に夫々設けられた電極パッド及
び配線と、前記電極パッドと配線とを接続するボンディ
ングワイヤと、を有し、前記半導体基板の上面における
前記電極パッドよりも端縁側の部分に局部的に金属膜に
より覆われて前記はんだが溜まる段差部が形成されてい
ることを特徴とする半導体装置。2. A circuit is formed and the bottom and side surfaces are formed on a metal film.
And more covered semiconductor substrate, the semiconductor substrate is a solder
It has a package that will be accommodated is more joined, and the semiconductor substrate and the top surface of the package respectively provided with electrode pads and wiring, and a bonding wire for connecting the wiring to the electrode pad, an upper surface of said semiconductor substrate A metal film is locally formed on a portion closer to the edge than the electrode pad.
Wherein a more covered the stepped portion of the solder accumulation are formed by Tei <br/> Rukoto.
においてＬ字形に形成されていることを特徴とする請求
項１又は２に記載の半導体装置。Wherein the step portion, the semiconductor device according to claim 1 or 2, characterized in that it is formed in an L-shaped in longitudinal section of the semiconductor substrate.
るはんだの盛り上がり高さと実質的に同一か又はそれよ
り深いことを特徴とする請求項３に記載の半導体装置。 4. The depth of the step portion is set at the step portion.
Is substantially equal to or
The semiconductor device according to claim 3, wherein the semiconductor device is deep.
を形成する工程と、前記半導体基板の上面縁部に段差部
を形成する工程と、前記段差部に金属膜を形成する工程
と、前記半導体基板の底面及び側面に金属膜を形成する
工程と、前記半導体基板の底面とパッケージとの間には
んだを介して両者を接合する工程と、を有することを特
徴とする半導体装置の製造方法。Circuit and the electrode pads on the upper surface of 5. The semiconductor substrate and forming a step of forming a stepped portion to the top edge portions of the semiconductor substrate, forming a metal film on the step portion, the Forming a metal film on the bottom and side surfaces of the semiconductor substrate; and between the bottom surface of the semiconductor substrate and the package.
And a step of joining the two via a solder.
を形成する工程と、前記半導体基板の上面における前記
電極パッドよりも端部側の部分に局所的に段差部を形成
する工程と、前記段差部に金属膜を形成する工程と、前
記半導体基板の底面及び側面に金属膜を形成する工程
と、前記半導体基板の底面とパッケージとの間にはんだ
を介して両者を接合する工程と、を有することを特徴と
する半導体装置の製造方法。6. A step of forming a circuit and an electrode pad on an upper surface of a semiconductor substrate, and a step portion is locally formed on a portion of the upper surface of the semiconductor substrate closer to an end portion than the electrode pad. Forming a metal film on the step portion , forming a metal film on the bottom surface and side surfaces of the semiconductor substrate, and soldering between the bottom surface of the semiconductor substrate and the package.
And a step of joining the two via the method.
前記パッケージとの 接合後にはんだが溜まる高さと実質
的に同一か又はそれより深いことを特徴とする請求項５
又は６に記載の半導体装置の製造方法。7. The semiconductor device according to claim 1, wherein a depth of the step portion is equal to a depth of the semiconductor substrate.
The height and substance where the solder collects after joining with the package
6. The method as claimed in claim 5, wherein the distance is substantially the same or deeper.
Or a method of manufacturing a semiconductor device according to item 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31140098A JP3262086B2 (en) | 1998-10-30 | 1998-10-30 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31140098A JP3262086B2 (en) | 1998-10-30 | 1998-10-30 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000138238A JP2000138238A (en) | 2000-05-16 |
| JP3262086B2 true JP3262086B2 (en) | 2002-03-04 |
Family
ID=18016749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31140098A Expired - Fee Related JP3262086B2 (en) | 1998-10-30 | 1998-10-30 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3262086B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010238889A (en) * | 2009-03-31 | 2010-10-21 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| WO2014128796A1 (en) | 2013-02-25 | 2014-08-28 | パナソニック株式会社 | Semiconductor device |
-
1998
- 1998-10-30 JP JP31140098A patent/JP3262086B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000138238A (en) | 2000-05-16 |
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