JP3260573B2 - YC separation circuit - Google Patents
YC separation circuitInfo
- Publication number
- JP3260573B2 JP3260573B2 JP00983095A JP983095A JP3260573B2 JP 3260573 B2 JP3260573 B2 JP 3260573B2 JP 00983095 A JP00983095 A JP 00983095A JP 983095 A JP983095 A JP 983095A JP 3260573 B2 JP3260573 B2 JP 3260573B2
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- JP
- Japan
- Prior art keywords
- signal
- circuit
- vertical synchronization
- supply
- period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Processing Of Color Television Signals (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はYC分離回路に関し、特
にくし型フィルタを用いてカラー映像信号の輝度信号と
色信号とを分離するYC分離回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a YC separation circuit, and more particularly to a YC separation circuit for separating a luminance signal and a color signal of a color video signal using a comb filter.
【0002】[0002]
【従来の技術】従来この種のYC分離回路は、1水平走
査期間に相当する遅延(1H遅延)で相関をとるくし型
フィルタ構成を用いるため、この1H遅延信号の出力振
幅、相関用演算器入力レベル、色信号分離の遅延時間の
調整の少なくとも3箇所の調整を必要としていた。2. Description of the Related Art Conventionally, this type of YC separation circuit uses a comb-type filter configuration which takes a correlation with a delay (1H delay) corresponding to one horizontal scanning period. At least three adjustments of the input level and the delay time of the color signal separation are required.
【0003】一般的なテレビジョン受像機やVTRなど
に用いられている従来のYC分離回路をブロックで示す
図2を参照すると、この従来のYC分離回路は、入力映
像信号Iの不要高周波成分を除去し信号IFを出力する
ローパスフィルタ(LPF)4と、信号IFを1水平走
査期間分遅延させ1H遅延信号Hを生成する1H遅延素
子6と、1H遅延信号の出力レベルを調整し信号VHを
生成する可変抵抗器20と、信号VH中の不要クロック
成分を除去し信号LHを生成するLPF7と、信号LH
を増幅し信号AHを出力する増幅器21と、信号AHの
レベルを調整し信号HFを出力する可変抵抗器22と、
信号IFと信号HFとを加算し輝度信号Yを発生する加
算器15と、信号IFと信号HFとを相互に減算し色信
号Cを発生する加算器16とを備える。Referring to FIG. 2, which shows a block diagram of a conventional YC separation circuit used in a general television receiver or VTR, the conventional YC separation circuit removes unnecessary high frequency components of an input video signal I. A low-pass filter (LPF) 4 that removes and outputs a signal IF, a 1H delay element 6 that delays the signal IF by one horizontal scanning period to generate a 1H delay signal H, and adjusts an output level of the 1H delay signal to generate a signal VH. A variable resistor 20 for generating a signal LH; an LPF 7 for removing an unnecessary clock component from the signal VH to generate a signal LH;
An amplifier 21 for amplifying the signal AH and outputting a signal AH; a variable resistor 22 for adjusting the level of the signal AH and outputting a signal HF;
An adder 15 that adds the signal IF and the signal HF to generate a luminance signal Y and an adder 16 that subtracts the signal IF and the signal HF from each other to generate a color signal C are provided.
【0004】次に、図2を参照して、従来のYC分離回
路の動作について説明すると、この回路は周知の隣接走
査線間にライン相関があることを利用した2ライン型の
YC分離回路であり、まず、入力端子T1より入力され
た映像信号Iは、LPF4に供給され、LPF4は映像
信号Iの不要高周波成分を除去して信号IFを出力す
る。信号IFは1H遅延素子6と加算器15,16にそ
れぞれ供給される。1H遅延素子6は公知のクロック信
号駆動のCCD等で構成され、信号IFを1H分遅延し
その出力信号Hを可変抵抗器20に供給する。可変抵抗
器20は信号Hを適切なレベルに調整し、出力信号VH
をLPF7に供給する。LPF7はカットオフ周波数が
約5.5MHZであり、1H遅延された信号VHに含ま
れる上記クロック信号成分を除去し出力信号LHを増幅
器21に供給する。増幅器21は供給された信号LHを
増幅し、出力信号AHを可変抵抗器22に供給する。可
変抵抗器22は信号AHをレベル調整し、出力の相関信
号HFを加算器15,16の各々に供給する。加算器1
5,16は、NTSC方式の信号の特徴である1H期間
の前後の色信号の位相の反転と、色信号の類似性を利用
して信号IF,HFの相関演算を行う。加算器15は信
号IF,HFの加算の結果色信号Cを減衰させて輝度信
号Yを抽出し出力端子TYに出力する。加算器16は信
号IF,HFの相互減算の結果輝度信号Yを減衰させて
色信号Cを抽出し出力端子TCより出力する。Next, the operation of a conventional YC separation circuit will be described with reference to FIG. 2. This circuit is a two-line YC separation circuit utilizing the well-known fact that there is a line correlation between adjacent scanning lines. First, the video signal I input from the input terminal T1 is supplied to the LPF 4, and the LPF 4 removes unnecessary high frequency components of the video signal I and outputs the signal IF. The signal IF is supplied to the 1H delay element 6 and the adders 15 and 16, respectively. The 1H delay element 6 is composed of a known clock signal driven CCD or the like, delays the signal IF by 1H, and supplies the output signal H to the variable resistor 20. The variable resistor 20 adjusts the signal H to an appropriate level, and the output signal VH
Is supplied to the LPF 7. The LPF 7 has a cutoff frequency of about 5.5 MHZ, removes the clock signal component included in the signal VH delayed by 1 H, and supplies the output signal LH to the amplifier 21. Amplifier 2 1 amplifies the supplied signal LH, and supplies an output signal AH to the variable resistor 22. The variable resistor 22 adjusts the level of the signal AH and supplies an output correlation signal HF to each of the adders 15 and 16. Adder 1
Reference numerals 5 and 16 perform the inversion of the phase of the color signal before and after the 1H period, which is a feature of the signal of the NTSC system, and the correlation operation of the signals IF and HF using the similarity of the color signals. The adder 15 extracts the luminance signal Y by attenuating the color signal C as a result of the addition of the signals IF and HF, and outputs the luminance signal Y to the output terminal TY. The adder 16 extracts the chrominance signal C by attenuating the luminance signal Y as a result of the mutual subtraction of the signals IF and HF, and outputs it from the output terminal TC.
【0005】次に従来のYC分離回路の調整方法につい
てさらに説明を追加すると、1H遅延素子6の出力信号
Hは可変抵抗器20へ入力される。この可変抵抗器20
の調整目的は1H遅延素子のゲインのばらつきを吸収し
LPF7に供給する信号VHのレベルを適切に設定する
ことである。次に、可変抵抗器22は、LPF7と増幅
器21のゲインのばらつきを吸収し加算器15,16に
供給する相関信号HFのレベルを他の一方の入力信号I
Fのレベルと一致させることを目的としてレベル調整す
る。Next, a further description will be given of the conventional method of adjusting the YC separation circuit. The output signal H of the 1H delay element 6 is input to the variable resistor 20. This variable resistor 20
The purpose of the adjustment is to set the level of the signal VH to be supplied to the LPF 7 by absorbing the variation in the gain of the 1H delay element. Next, the variable resistor 22 absorbs a variation in gain between the LPF 7 and the amplifier 21 and supplies the level of the correlation signal HF to be supplied to the adders 15 and 16 to the other input signal I.
The level is adjusted to match the level of F.
【0006】最後にLPF7の遅延時間の増減により加
算器15,16の各々に供給される信号IF,HFの相
互間の時間誤差を調整する。この遅延時間の調整結果、
加算器15,16には相関演算対象の信号IFとこの信
号IFを丁度1H分遅延した相関信号HFすなわち1H
前の信号IFとが入力される。Finally, the time error between the signals IF and HF supplied to the adders 15 and 16 is adjusted by increasing or decreasing the delay time of the LPF 7. As a result of this delay time adjustment,
The adders 15 and 16 provide a signal IF to be subjected to a correlation operation and a correlation signal HF obtained by delaying the signal IF by exactly 1H, that is, 1H.
The previous signal IF is input.
【0007】上述したようにこの従来のYC分離回路
は、1H遅延素子6の出力信号VHのレベル調整と、加
算器15,16に供給する相関信号HFのレベルの調整
と、相関信号HFの1H遅延の遅延時間の調整との計3
ケ所の調整を必要とする。As described above, this conventional YC separation circuit adjusts the level of the output signal VH of the 1H delay element 6, adjusts the level of the correlation signal HF supplied to the adders 15 and 16, and adjusts the 1H of the correlation signal HF. Adjustment of delay time and total 3
It needs to be adjusted in several places.
【0008】上記調整が不完全であると、輝度信号の色
信号への漏込により生じるクロスカラーや色信号の輝度
信号への漏込により生じるドット妨害などの不具合発生
により鮮明な画像が得られないためこれらの調整は不可
欠とされていた。[0008] If the above adjustment is incomplete, a clear image can be obtained due to the occurrence of problems such as cross color caused by leakage of the luminance signal to the color signal and dot interference caused by leakage of the color signal to the luminance signal. These adjustments were considered essential.
【0009】[0009]
【発明が解決しようとする課題】上述した従来のYC分
離回路は、1H遅延素子の出力信号のレベル調整と、輝
度信号,色信号分離用の各加算器に供給する相関信号の
レベルの調整と、相関信号の1H遅延時間の調整との3
ケ所の調整を必要とし、これを用いたテレビジョン受像
機等の製造工程において、工数およびコストの増大要因
となるという欠点があった。The conventional YC separation circuit described above adjusts the level of the output signal of the 1H delay element, and adjusts the level of the correlation signal supplied to each adder for separating the luminance signal and the chrominance signal. And adjustment of the 1H delay time of the correlation signal.
There is a drawback in that it requires adjustment of the locations, and in the manufacturing process of a television receiver or the like using the same, it causes an increase in man-hours and costs.
【0010】また、可変抵抗器等の調整要素の経時変化
により上記調整ずれを発生し、長期間の安定動作が困難
であるという欠点があった。Further, there has been a drawback that the above-described adjustment deviation occurs due to a change over time of an adjustment element such as a variable resistor, and stable operation for a long period of time is difficult.
【0011】[0011]
【課題を解決するための手段】本発明のYC分離回路
は、入力カラー映像信号を1水平走査期間分遅延させ1
H遅延信号を発生する1H遅延素子と、前記1H遅延信
号の不要高周波成分を除去しフィルタ通過1H遅延信号
を発生する低域通過フィルタと、前記フィルタ通過1H
遅延信号対応の相関信号と前記入力カラー映像信号との
相互加算および相互減算により相関をとりそれぞれ輝度
信号および色信号を発生する第1および第2の加算器と
を備えくし形フィルタ特性を有するYC分離回路におい
て、前記低域通過フィルタが周波数制御信号の供給に応
答して遮断周波数を可変する周波数調整手段を備え、前
記入力カラー映像信号から垂直同期信号を抽出する垂直
同期信号分離回路と、色副搬送波信号を90度移相した
直角位相副搬送波信号を発生する直角位相副搬送波発生
回路と、前記垂直同期信号の供給に応答して垂直同期信
号期間に前記入力カラー映像信号をこの垂直同期信号期
間以外の期間に前記直角位相副搬送波信号をそれぞれ通
過させる第1のスイッチ回路と、利得制御信号に応答し
て利得が制御され前記フィルタ通過1H遅延信号を増幅
し前記相関信号を発生する利得可変増幅回路と、前記直
角位相副搬送波信号と前記相関信号との供給に応答して
前記周波数制御信号を発生する周波数制御信号発生回路
と、前記直角位相副搬送波信号と前記輝度信号との供給
に応答して前記利得制御信号を発生する利得制御信号発
生回路とを備えて構成されている。The YC separation circuit of the present invention delays an input color video signal by one horizontal scanning period.
A 1H delay element that generates an H delay signal, a low-pass filter that removes unnecessary high frequency components of the 1H delay signal and generates a filtered 1H delay signal,
A YC having a comb filter characteristic comprising first and second adders for correlating a correlation signal corresponding to a delayed signal and the input color video signal by mutual addition and subtraction to generate a luminance signal and a color signal, respectively; In the separation circuit, the low-pass filter includes frequency adjustment means for varying a cutoff frequency in response to supply of a frequency control signal, a vertical synchronization signal separation circuit for extracting a vertical synchronization signal from the input color video signal, A quadrature subcarrier generating circuit for generating a quadrature subcarrier signal obtained by shifting the subcarrier signal by 90 degrees; and supplying the input color video signal to the vertical synchronizing signal during a vertical synchronizing signal period in response to the supply of the vertical synchronizing signal. A first switch circuit for passing the quadrature subcarrier signal during a period other than a period, and a gain controlled in response to a gain control signal. A variable gain amplifier circuit for amplifying the 1H delay signal passing through the filter to generate the correlation signal, and a frequency control signal generating circuit for generating the frequency control signal in response to the supply of the quadrature subcarrier signal and the correlation signal And a gain control signal generating circuit for generating the gain control signal in response to the supply of the quadrature subcarrier signal and the luminance signal.
【0012】[0012]
【実施例】次に、本発明の実施例を図2と共通の構成要
素には共通の参照文字/数字を付して同様にブロックで
示す図1を参照すると、この図に示す本実施例のYC分
離回路は、従来と共通のLPF4と、1H遅延素子6
と、従来のLPF7と同様の機能に加えて制御信号IM
の供給に応答してカットオフ周波数fcが制御されるL
PF7Aと、加算器15,16とに加えて、入力映像信
号Iから水平・垂直同期信号Sを分離する同期信号分離
回路1と、同期信号Sから垂直同期信号Vのみを抽出す
る垂直分離回路2と、垂直同期信号Vの供給に応答して
信号IF,fを選択的に切替るスイッチ5と、信号Gに
より利得制御され信号LHを増幅し信号VHFを出力す
る電圧制御増幅(VCA)回路8と、副搬送波信号fs
cの位相を90°移相し信号f,fAを出力する位相器
9と、供給を受けた信号VHF,fAとから制御信号I
Mを発生する周波数制御回路10と、信号fと信号Yと
の乗算を行い信号Gを発生する掛算器17と、垂直同期
信号Vの供給に応答してスイッチ18と、データ保持用
コンデンサ19とを備える。FIG. 1 is a block diagram showing an embodiment of the present invention, in which components common to those in FIG. 2 are denoted by common reference characters / numerals, and FIG. The YC separation circuit of FIG.
And the control signal IM in addition to the same function as the conventional LPF 7
L whose cutoff frequency fc is controlled in response to the supply of
In addition to the PF 7A and the adders 15 and 16, a synchronization signal separation circuit 1 for separating the horizontal / vertical synchronization signal S from the input video signal I, and a vertical separation circuit 2 for extracting only the vertical synchronization signal V from the synchronization signal S A switch 5 for selectively switching between the signals IF and f in response to the supply of the vertical synchronizing signal V, and a voltage-controlled amplification (VCA) circuit 8 for gain-controlled by the signal G to amplify the signal LH and output the signal VHF. And the subcarrier signal fs
The phase shifter 9 outputs the signals f and fA by shifting the phase of c by 90 °, and the control signal I from the supplied signals VHF and fA.
A frequency control circuit 10 for generating M, a multiplier 17 for multiplying the signal f by the signal Y to generate a signal G, a switch 18 in response to the supply of the vertical synchronization signal V, and a data holding capacitor 19 Is provided.
【0013】周波数制御回路10は、供給を受けた信号
VHFと信号fAとの乗算を行い信号Mを発生する掛算
器11と、電圧値の信号Mを電流値信号である制御信号
IMに変換する電圧電流(VI)変換器12と、垂直同
期信号Vの供給に応答して垂直同期信号期間だけ掛算器
11の位相比較動作させるスイッチ13と、データ保持
用コンデンサ14とから成る周波数制御回路10とを備
える。The frequency control circuit 10 multiplies the supplied signal VHF by the signal fA to generate a signal M, and converts the voltage signal M into a control signal IM which is a current signal. A frequency control circuit 10 including a voltage-current (VI) converter 12, a switch 13 for performing a phase comparison operation of a multiplier 11 for a vertical synchronization signal period in response to supply of a vertical synchronization signal V, and a data holding capacitor 14. Is provided.
【0014】次に、図1を参照して本実施例の動作につ
いて説明すると、まず、入力端子T1より入力された映
像信号Iは、LPF4と同期分離回路1とに供給され、
従来と同様、LPF4は映像信号Iの不要高周波成分を
除去して信号IFを出力し、スイッチ5に供給する。同
期分離回路1は映像信号Iから水平・垂直同期信号Sを
抽出する。垂直分離回路2は同期信号Sから垂直同期信
号Vを抽出する。この垂直同期信号Vはスイッチ5を制
御する。Next, the operation of the present embodiment will be described with reference to FIG. 1. First, a video signal I inputted from an input terminal T1 is supplied to an LPF 4 and a sync separation circuit 1,
As in the conventional case, the LPF 4 removes unnecessary high frequency components of the video signal I, outputs a signal IF, and supplies the signal IF to the switch 5. The sync separation circuit 1 extracts a horizontal / vertical sync signal S from the video signal I. The vertical separation circuit 2 extracts a vertical synchronization signal V from the synchronization signal S. This vertical synchronization signal V controls the switch 5.
【0015】一方、位相器9は端子Tfを経由して供給
を受けた副搬送波信号fscの位相をそれぞれ90°移
相した直角位相副搬送波信号fをスイッチ5に直角位相
副搬送波信号fAを掛算器11にそれぞれ供給する。ス
イッチ5の2つの接点の各々には、上記のように、信号
IFと信号fとが供給されるが垂直同期信号Vの制御に
応答して垂直同期信号期間以外は信号IFを、垂直同期
信号期間中は信号fを選択的に通過させた信号SFを出
力する。On the other hand, the phase shifter 9 multiplies the quadrature subcarrier signal f obtained by shifting the phase of the subcarrier signal fsc supplied via the terminal Tf by 90 ° with the switch 5 by the quadrature subcarrier signal fA. To the vessel 11 respectively. Each of the two contacts of the switch 5 is supplied with the signal IF and the signal f as described above. In response to the control of the vertical synchronizing signal V, the signal IF and the vertical synchronizing signal are output except during the vertical synchronizing signal period. During the period, the signal SF that selectively passes the signal f is output.
【0016】信号SFは従来と同様に1H遅延素子6に
供給され、その出力HはLPF7Aでクロック成分が除
去され、その出力信号LHがVCA回路8に供給され
る。VCA回路8は信号LH対応の出力信号VHFを掛
算器11および加算器15,16の各々にそれぞれ供給
する。The signal SF is supplied to the 1H delay element 6 as in the prior art. The output H of the signal SF is removed from the clock component by the LPF 7A, and the output signal LH is supplied to the VCA circuit 8. The VCA circuit 8 supplies an output signal VHF corresponding to the signal LH to each of the multiplier 11 and the adders 15 and 16.
【0017】周波数制御回路10の掛算器11は供給を
受けた信号VHF,fAを乗算し、信号Mを発生する。
ここで、LPF7Aのカットオフ周波数fcすなわち信
号VHFの周波数fcが所定値からずれていない場合は
信号VFA,fA間の位相差は丁度90°すなわち直角
位相であり、したがって信号Mは0となる。この信号M
の供給に応答してVI変換器12はカットオフ周波数f
cを変化させない所定の中央値の制御信号IM0をLP
F7Aに供給する。したがって、LPF7Aはこの状態
のカットオフ周波数fcをそのまま保持する。LPF7
Aのカットオフ周波数fcが所定値より低い場合は信号
VHFの位相が信号fAより90°より遅れ、信号Mは
正極性となる。この正極性の信号Mの供給に応答してV
I変換器12はカットオフ周波数fcを増加させる制御
信号IMlをLPF7Aに供給する。この結果、LPF
7Aはカットオフ周波数fcを増加させる。また、LP
F7Aのカットオフ周波数fcが所定値より高い場合は
逆に信号VHFの位相が信号fAより90°より進み、
信号Mは負極性となる。この負極性の信号Mの供給に応
答してVI変換器12はカットオフ周波数fcを低下さ
せる制御信号IMhをLPF7Aに供給する。この結
果、LPF7Aはカットオフ周波数fcを低下させる。The multiplier 11 of the frequency control circuit 10 multiplies the supplied signals VHF and fA to generate a signal M.
Here, when the cutoff frequency fc of the LPF 7A, that is, the frequency fc of the signal VHF does not deviate from a predetermined value, the phase difference between the signals VFA and fA is exactly 90 °, that is, the quadrature phase, and therefore the signal M becomes zero. This signal M
The VI converter 12 responds to the supply of
control signal IM0 having a predetermined median value which does not change c
Supply to F7A. Therefore, the LPF 7A holds the cutoff frequency fc in this state as it is. LPF7
When the cutoff frequency fc of A is lower than a predetermined value, the phase of the signal VHF is delayed by more than 90 ° from the signal fA, and the signal M has a positive polarity. In response to the supply of the positive polarity signal M, V
The I converter 12 supplies a control signal IMl for increasing the cutoff frequency fc to the LPF 7A. As a result, LPF
7A increases the cutoff frequency fc. Also, LP
If the cut-off frequency fc of F7A is higher than a predetermined value, the phase of the signal VHF is more advanced than the signal fA by 90 °,
The signal M has a negative polarity. In response to the supply of the signal M having the negative polarity, the VI converter 12 supplies a control signal IMh for lowering the cutoff frequency fc to the LPF 7A. As a result, the LPF 7A lowers the cutoff frequency fc.
【0018】スイッチ13は、隣接走査線間に相関がな
い場合や映像信号に色信号が含まれていない場合等にV
I変換器12の誤動作を避けるため、掛算器11が垂直
同期信号期間だけ位相比較を行い、垂直同期信号期間以
外の期間はそのときの値を保持するように制御する。こ
のように、掛算器11,VI変換器12,スイッチ13
の一連の動作により1H期間の遅延時間調整を自動化で
きる。When there is no correlation between adjacent scanning lines or when a video signal does not include a color signal, the switch 13
In order to avoid a malfunction of the I-converter 12, the multiplier 11 performs a phase comparison only during the vertical synchronizing signal period, and controls so as to hold the value at that time during periods other than the vertical synchronizing signal period. Thus, the multiplier 11, the VI converter 12, the switch 13
, The delay time adjustment for the 1H period can be automated.
【0019】次に、掛算器17は信号fと加算器15の
出力信号Yとの供給に応答して信号Gを出力する。加算
器15,16の各々に供給される信号SFと信号VHF
とのレベルが等しい場合、信号Yには残留色信号成分が
含まれないためこの掛算器17には信号fのみが入力さ
れ、出力信号Gの電圧は0となりVCA回路8のゲイン
は変化せず信号VHFのレベルをそのまま保持する。Next, the multiplier 17 outputs a signal G in response to the supply of the signal f and the output signal Y of the adder 15. Signal S F and the signal VHF supplied to each of the adders 15 and 16
Are equal, the signal Y does not include a residual color signal component, so only the signal f is input to the multiplier 17, the voltage of the output signal G becomes 0, and the gain of the VCA circuit 8 does not change. The level of the signal VHF is kept as it is.
【0020】次に、信号VHFのレベルが信号SFより
小さい場合には、信号Yには残留色信号成分が含まれる
ため、掛算器17はこの信号Yと信号fとを位相比較
し、出力信号Gの電圧によりVCA回路8のゲインを増
加させ信号VHF,SF両者のレベルが同一となるまで
信号VHFのレベルを増大させる。逆に、信号VHFの
レベルが信号Sより大きい場合には、信号Yには逆極性
の残留色信号成分が含まれるため、掛算器17は信号Y
と信号fとの位相比較結果の逆極性の出力信号Gの電圧
によりVCA回路8のゲインを低減させ信号VHF,S
F両者のレベルが同一となるまで信号VHFのレベルを
低下させる。Next, when the level of the signal VHF signal S F smaller than, since the signal Y contains residual color signal components, the multiplier 17 and the signal Y and the signal f to the phase comparator, the output signal G gain signal increase VHF the VCA circuit 8 by a voltage of the level of S F both increase the level of the signal VHF until the same. Conversely, when the level of the signal VHF is higher than the signal S, the signal Y includes a residual color signal component of the opposite polarity, and the multiplier 17 outputs the signal Y.
The gain of the VCA circuit 8 is reduced by the voltage of the output signal G having the opposite polarity as a result of the phase comparison between the signals VHF and S.
F. The level of the signal VHF is reduced until both levels become the same.
【0021】スイッチ18は、前述の掛算器11,スイ
ッチ13の場合と同様に、垂直同期信号の期間の期間の
み掛算器17の位相比較動作を行わせそれ以外の期間は
コンデンサ19に信号Gの電圧をホールドする。The switch 18 performs the phase comparison operation of the multiplier 17 only during the period of the vertical synchronizing signal, similarly to the case of the multiplier 11 and the switch 13 described above. Hold the voltage.
【0022】以上の動作により加算器15,16には信
号SFと同一レベルで丁度1H期間遅延した信号VHF
が供給される。The above operation by the adder 15 and 16 of the signal S F just the same level as 1H period delayed signal VHF
Is supplied.
【0023】[0023]
【発明の効果】以上説明したように、本発明のYC分離
回路は、垂直同期信号分離回路と、直角位相副搬送波発
生回路と、垂直同期信号期間に入力カラー映像信号を垂
直同期信号期間以外の期間に上記直角位相副搬送波信号
をそれぞれ通過させるスイッチ回路と、利得可変増幅回
路と、上記直角位相副搬送波信号と相関信号との供給に
応答して周波数制御信号を発生する周波数制御信号発生
回路と、上記直角位相副搬送波信号と輝度信号との供給
に応答して利得制御信号を発生する利得制御信号発生回
路とを備えるので、LPFのカットオフ周波数のずれす
なわち1H遅延信号(相関信号)の遅延時間およびレベ
ルを自動的に修正することにより、製造工程におけるこ
れら調整を不要とし、工数および製造コストの削減がで
きるという効果がある。As described above, the YC separation circuit according to the present invention comprises a vertical synchronization signal separation circuit, a quadrature subcarrier generation circuit, and an input color video signal during a vertical synchronization signal period. A switch circuit that passes the quadrature subcarrier signal during the period, a variable gain amplifier circuit, and a frequency control signal generation circuit that generates a frequency control signal in response to the supply of the quadrature subcarrier signal and the correlation signal. And a gain control signal generating circuit for generating a gain control signal in response to the supply of the quadrature subcarrier signal and the luminance signal, so that the shift of the cutoff frequency of the LPF, that is, the delay of the 1H delay signal (correlation signal). By automatically correcting the time and level, these adjustments in the manufacturing process are not required, which has the effect of reducing man-hours and manufacturing costs. That.
【0024】また、経時変化要因となる可変抵抗器等の
調整素子が不要であることと、クローズドループシステ
ムを構成することとにより経時変化による特性劣化を防
止できるという効果がある。In addition, there is an effect that an adjustment element such as a variable resistor which causes a change with time is not required, and that a characteristic deterioration due to a change with time can be prevented by forming a closed loop system.
【図1】本発明のYC分離回路の一実施例を示すブロッ
ク図である。FIG. 1 is a block diagram showing one embodiment of a YC separation circuit of the present invention.
【図2】従来のYC分離回路の一例を示すブロック図で
ある。FIG. 2 is a block diagram illustrating an example of a conventional YC separation circuit.
1 同期分離回路 2 垂直分離回路 4,7,7A LPF 5,13,18 スイッチ 6 1H遅延素子 8 VCA回路 9 位相器 10 周波数制御回路 11,17 掛算器 12 VI変換器 14,19 コンデンサ 15,16 加算器 20,22 可変抵抗器 21 増幅器 DESCRIPTION OF SYMBOLS 1 Synchronization separation circuit 2 Vertical separation circuit 4,7,7A LPF 5,13,18 Switch 6 1H delay element 8 VCA circuit 9 Phase shifter 10 Frequency control circuit 11,17 Multiplier 12 VI converter 14,19 Capacitor 15,16 Adder 20,22 Variable resistor 21 Amplifier
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−67989(JP,A) 特開 平6−335020(JP,A) 特開 平6−276545(JP,A) 特開 平1−181212(JP,A) 特開 昭61−228705(JP,A) 特開 昭61−73412(JP,A) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-67989 (JP, A) JP-A-6-335020 (JP, A) JP-A-6-276545 (JP, A) JP-A-1- 181212 (JP, A) JP-A-61-228705 (JP, A) JP-A-61-73412 (JP, A)
Claims (2)
遅延させ1H遅延信号を発生する1H遅延素子と、前記
1H遅延信号の不要高周波成分を除去した遅延映像信号
対応の相関信号と前記入力カラー映像信号との相互加算
および相互減算により相関をとりそれぞれ輝度信号およ
び色信号を発生する第1および第2の加算器とを備えく
し形フィルタ特性を有するYC分離回路において、 周波数制御信号の供給に応答して遮断周波数を可変する
周波数調整手段を備え前記1H遅延信号の不要高周波成
分を除去し前記遅延映像信号を発生する低域通過フィル
タと、 前記入力カラー映像信号から垂直同期信号を抽出する垂
直同期信号分離回路と、 副搬送波信号を90度移相した直角位相副搬送波信号を
発生する直角位相副搬送波発生回路と、 前記垂直同期信号の供給に応答して垂直同期信号期間以
外に前記入力カラー映像信号を通過させ、垂直同期信号
期間に前記直角位相副搬送波信号を通過させる第1のス
イッチ回路と、 利得制御信号に応答して利得が制御され前記遅延映像信
号を増幅し前記相関信号を発生する利得可変増幅回路
と、 前記直角位相副搬送波信号と前記相関信号とを乗算し第
1の乗算信号を発生する第1の掛算器と、前記第1の乗
算信号の電圧値を電流値に変換して前記周波数制御信号
を発生する電圧電流変換回路と、前記垂直同期信号の供
給に応答して前記垂直同期信号期間に前記第1の掛算器
を動作させる第2のスイッチ回路とを有し、前記直角位
相副搬送波信号と前記相関信号との供給に応答して前記
周波数制御信号を発生する周波数制御信号発生回路と、 前記直角位相副搬送波信号と前記第1の加算器の出力信
号との供給に応答して前記利得制御信号を発生する利得
制御信号発生回路とを備えることを特徴とするYC分離
回路。1. A 1H delay element for delaying an input color video signal by one horizontal scanning period to generate a 1H delay signal, a correlation signal corresponding to a delayed video signal from which unnecessary high frequency components of the 1H delay signal have been removed, and the input color A YC separation circuit having a comb filter characteristic comprising first and second adders for generating a luminance signal and a chrominance signal by correlating by mutual addition and mutual subtraction with a video signal; A low-pass filter that removes unnecessary high-frequency components of the 1H delay signal and generates the delayed video signal; and a vertical filter that extracts a vertical synchronization signal from the input color video signal. A synchronization signal separation circuit; a quadrature subcarrier generation circuit that generates a quadrature subcarrier signal obtained by shifting the subcarrier signal by 90 degrees; A first switch circuit that allows the input color video signal to pass during periods other than the vertical synchronization signal period in response to the supply of the vertical synchronization signal, and passes the quadrature subcarrier signal during the vertical synchronization signal period; A gain variable amplifier circuit whose gain is controlled to amplify the delayed video signal to generate the correlation signal; and a first multiplication circuit that multiplies the quadrature subcarrier signal by the correlation signal to generate a first multiplied signal. A multiplier, a voltage-current conversion circuit for converting the voltage value of the first multiplication signal into a current value to generate the frequency control signal, and the voltage-current conversion circuit responding to the supply of the vertical synchronization signal during the vertical synchronization signal period. A second switch circuit for operating a first multiplier, and a frequency control signal generation circuit for generating the frequency control signal in response to the supply of the quadrature subcarrier signal and the correlation signal; A quadrature subcarrier signal and an output signal of the first adder.
YC separation circuit comprising: a gain control signal generating circuit in response to the supply of the No. generates the gain control signal.
位相副搬送波信号と前記輝度信号とを乗算し前記利得制
御信号を発生する第2の掛算器と、前記垂直同期信号の
供給に応答して前記垂直同期信号期間に前記第2の掛算
器を動作させる第3のスイッチ回路とを備えることを特
徴とする請求項1記載のYC分離回路。And a second multiplier for multiplying the quadrature subcarrier signal by the luminance signal to generate the gain control signal, and responsive to the supply of the vertical synchronization signal. 2. The YC separation circuit according to claim 1, further comprising: a third switch circuit for operating the second multiplier during the vertical synchronization signal period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP00983095A JP3260573B2 (en) | 1995-01-25 | 1995-01-25 | YC separation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP00983095A JP3260573B2 (en) | 1995-01-25 | 1995-01-25 | YC separation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08205184A JPH08205184A (en) | 1996-08-09 |
JP3260573B2 true JP3260573B2 (en) | 2002-02-25 |
Family
ID=11731058
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP00983095A Expired - Fee Related JP3260573B2 (en) | 1995-01-25 | 1995-01-25 | YC separation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3260573B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69839112T2 (en) * | 1997-12-19 | 2008-05-21 | Matsushita Electric Industrial Co., Ltd., Kadoma | Comb filter and control method thereto |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3128423B2 (en) * | 1993-03-23 | 2001-01-29 | 株式会社東芝 | YC signal separation automatic adjustment circuit |
-
1995
- 1995-01-25 JP JP00983095A patent/JP3260573B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH08205184A (en) | 1996-08-09 |
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