JP3257907B2 - Conductive tray for storing semiconductor integrated circuit devices - Google Patents

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置等
を収納するための導電性トレ−に関する。さらに具体的
には、その部分収縮率が一定で、反りが低減され、かつ
トレーの軽量化が可能な導電性トレ−に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive tray for housing a semiconductor integrated circuit device and the like. More specifically, the present invention relates to a conductive tray whose partial shrinkage is constant, warpage is reduced, and the weight of the tray is reduced.

【０００２】[0002]

【従来の技術】現在、半導体集積回路装置等を収納する
導電性トレ−としては、実公平３ー３３６７０に記載さ
れる形状の導電性トレ−が、一般的に多数使用されてい
る。前記公報の導電性トレ−の形状は、一例として図４
及び図５に示されるとおり、ポケットが形成され、ポケ
ットの面上に半導体集積回路装置の外周面を嵌着、保持
するための微小リブに囲まれた凹部（この中に空隙が設
けられてる事が多い）が設けられ、トレ−外枠とポケッ
トをつなぐトレ−支持平面板の上面の高さがトレ−全体
高さと同一である形状が一般的である。2. Description of the Related Art At present, a large number of conductive trays having the shape described in Japanese Utility Model Publication No. 3-33670 are generally used as conductive trays for housing semiconductor integrated circuit devices and the like. The shape of the conductive tray disclosed in the above publication is shown in FIG.
As shown in FIG. 5, a pocket is formed, and a recess surrounded by minute ribs for fitting and holding the outer peripheral surface of the semiconductor integrated circuit device on the surface of the pocket (an air gap is provided in the recess). Are generally provided, and the height of the upper surface of the tray-supporting flat plate connecting the tray outer frame and the pocket is the same as the overall height of the tray.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、従来使
用されている導電性トレ−の場合、トレ−面内の各方向
（長尺あるいは短尺方向）において、例えば短尺方向の
トレ−外枠部とこれに対向する外枠部間の長さ（以下短
尺寸法と略記する）と任意の隣接するポケットの中心間
の長さ（以下ピッチ寸法と略記する）において、寸法
（長さ）中での樹脂材料部と空隙部の占有割合が一定で
ないために、一定方向であっても、ピッチ寸法と短尺寸
法との間に、トレ−成形時あるいは加熱時の収縮率に差
が発生し、このため、ポケット形状の寸法精度が悪化
し、かつ、金型作成を著しく困難にする。However, in the case of a conventionally used conductive tray, in each direction (long or short direction) in the plane of the tray, for example, a short outer frame portion and a short outer frame portion are formed. In the length (hereinafter abbreviated as a short dimension) between the outer frame portions facing each other and the length between the centers of any adjacent pockets (hereinafter abbreviated as a pitch dimension), the resin within the dimension (length) Since the occupation ratio of the material portion and the void portion is not constant, even in a fixed direction, a difference occurs in the shrinkage rate during the tray forming or the heating between the pitch dimension and the short dimension, and therefore, In addition, the dimensional accuracy of the pocket shape deteriorates, and the production of the mold becomes extremely difficult.

【０００４】又、従来の導電性トレ−の場合、トレ−外
枠とポケットをつなぐトレ−支持平面板は、その上面の
高さがトレ−の高さと同等程度のため、トレ−上面付近
に樹脂材料が多く存在し、このためトレ−上面付近がト
レー下面付近に比較し収縮が大きく、結果としてトレ−
の反りが大きくなるなどの欠点があり、繊維状充填材を
混入した材料においては特に顕著な欠点であった。即
ち、本発明は、前記の欠点を改良したものであり、金型
設計上、必要なピッチ寸法や短尺寸法等の各部分の収縮
率が一定で、反りが低減され、かつトレーの軽量化が可
能な導電性トレ−を提供するものである。In the case of a conventional conductive tray, the upper surface of the tray supporting plate for connecting the outer frame of the tray and the pocket is approximately the same as the height of the tray. Because there are many resin materials, the upper part of the tray shrinks more than the lower part of the tray as compared to the lower part of the tray.
However, there is a defect such as an increase in warpage of the material, and this is a particularly remarkable defect in a material mixed with a fibrous filler. That is, the present invention is an improvement of the above-mentioned disadvantages. In the design of the mold, the shrinkage of each part such as the pitch dimension and the short dimension required is constant, the warpage is reduced, and the weight of the tray is reduced. The present invention provides a conductive tray that can be used.

【０００５】[0005]

【課題を解決するための手段】すなわち、本発明は、フ
ラットタイプの半導体集積回路装置を収納する導電性ト
レ−であって、前記導電性トレ−には、半導体集積回路
装置を単数、又は複数収納するための、格子状の壁によ
り同じ形状に区画された凹部からなるポケットが形成さ
れ、このポケットの内側部分には、前記半導体集積回路
装置の外周面を嵌着、保持するための微小リブで囲まれ
た凹部が設けられ、（１）（イ）任意の隣接するポケッ
ト間の格子状の壁を挟み、最も近く位置する微小リブ間
に空隙を設け、及び／又は（ロ）トレ−外枠とそれと平
行に隣接する微小リブに挟まれた部分に空隙を設け、及
び／又は（２）ポケットとトレ−外枠をつなぐ支持平面
板上面の高さがトレ−全体高さの中間に位置することを
特徴とする半導体集積回路装置の収納用導電性トレ−で
ある。That is, the present invention relates to a conductive tray for housing a flat type semiconductor integrated circuit device, wherein the conductive tray includes one or more semiconductor integrated circuit devices. A pocket formed of a concave section defined by a lattice-shaped wall for storage is formed in the same shape, and minute ribs for fitting and holding the outer peripheral surface of the semiconductor integrated circuit device are formed inside the pocket. (1) (a) sandwich a grid-like wall between any adjacent pockets, provide a gap between the nearest minute ribs, and / or (b) outside the tray A space is provided between the frame and a portion adjacent to the micro ribs adjacent to the frame, and / or (2) the height of the upper surface of the supporting flat plate connecting the pocket and the outer frame is located in the middle of the entire height of the tray. Semiconductor characterized by the following Accommodating conductive Torre product circuit device - a.

【０００６】以下、本発明を詳細に説明する。本発明の
導電性トレ−は、半導体集積回路装置を単数、又は複数
収納するための、格子状の壁により同じ形状に区画され
た凹部からなるポケットを有する。図３に、本発明の導
電性トレ−の概略的平面図を示す。本発明の導電性トレ
−は、図１及び図２に例示するとおり、フラットタイプ
の半導体集積回路装置を収納する導電性トレ−であっ
て、前記導電性トレ−には、半導体集積回路装置を単
数、又は複数収納するための、格子状の壁により同じ形
状に区画された凹部からなるポケットが形成され、この
ポケットの内側部分には、前記半導体集積回路装置の外
周面を嵌着、保持するための微小リブで囲まれた凹部が
設けられ、（１）（イ）任意の隣接するポケット間の格
子状の壁を挟み、最も近く平行に位置する微小リブ間に
空隙を設け、及び／又は（ロ）トレ−外枠とそれと平行
に隣接する微小リブに挟まれた部分に空隙を設け、及び
／又は（２）ポケットとトレ−外枠をつなぐ支持平面板
上面の高さがトレ−全体高さの中間に位置する導電性ト
レ−である。Hereinafter, the present invention will be described in detail. The conductive tray according to the present invention has a pocket formed of a recessed portion having the same shape defined by a lattice-shaped wall for accommodating one or more semiconductor integrated circuit devices. FIG. 3 shows a schematic plan view of the conductive tray of the present invention. As shown in FIGS. 1 and 2, the conductive tray of the present invention is a conductive tray for housing a flat type semiconductor integrated circuit device, and the conductive tray includes a semiconductor integrated circuit device. A pocket formed of a recessed section of the same shape defined by a lattice-like wall for accommodating a single or a plurality of pockets is formed, and an outer peripheral surface of the semiconductor integrated circuit device is fitted and held in an inner portion of the pocket. (1) (a) a gap is provided between the closest parallel ribs sandwiching a lattice-like wall between any adjacent pockets, and / or (B) A space is provided in a portion sandwiched between the outer frame of the tray and the minute rib adjacent to the outer frame, and / or (2) the height of the upper surface of the supporting flat plate connecting the pocket and the outer frame of the tray is equal to the entire height of the tray. Conductive tray located in the middle of height It is.

【０００７】本発明の格子状の壁を挟み、最も近く平行
に位置する微小リブ間の空隙５は、基本的には、形状、
大きさ、位置、数量等は、特に制限される物ではない
が、好ましくは、幅が格子状の壁と微小リブに挟まれた
間隔の約半分、長さは平行に存在する微小リブの長さと
同等以上であり、形状は、空隙の角に丸みをもたせた長
方形類似の形状の物である。本発明のトレ−外枠とそれ
と平行に隣接する微小リブ間の空隙６は、基本的には、
形状、大きさ、位置、数量等は、特に制限される物では
ない。[0007] The gap 5 between the minute ribs located closest and parallel to each other with the grid-like wall of the present invention interposed therebetween has basically a shape,
The size, position, quantity, etc. are not particularly limited, but preferably, the width is about half of the interval between the grid-like wall and the microrib, and the length is the length of the microrib that exists in parallel. And the shape is similar to a rectangle with rounded corners of the void. The gap 6 between the tray outer frame of the present invention and the micro rib adjacent to the tray outer frame is basically
The shape, size, position, quantity and the like are not particularly limited.

【０００８】また、ポケット間の格子状の壁を挟み、最
も近く平行に位置する微小リブ間の空隙５、トレ−外枠
とそれと平行に隣接する微小リブ間の空隙６及び微小リ
ブに囲まれたポケット中央の空隙５ａは、必要に応じ
て、それぞれが連結することが可能である。本発明にお
いて、ポケットとトレ−外枠をつなぐ支持平面板上面の
高さがトレ−全体高さの中間に位置されたものが好まし
い。これらの支持平面板の厚み、高さについては、トレ
−全体高さの中間に位置すれば、特に制限されるもので
はないが、トレ−高さの約半分の高さが特に好ましい。
また必要に応じて、これらの支持平面板に空隙を設ける
事も可能である。さらに、本発明においては、従来の導
電性トレ−と同様に、各ポケット表面の位置は、トレ−
全体高さの中間に位置されたものが好ましい。Further, a gap 5 between minute ribs located closest and parallel to each other with a grid-like wall between pockets therebetween, a gap 6 between a tray outer frame and a minute rib adjacent to the outer frame in parallel with the rib, and a small rib. The gap 5a at the center of the pocket can be connected to each other as necessary. In the present invention, it is preferable that the height of the upper surface of the supporting flat plate connecting the pocket and the outer frame of the tray is located in the middle of the entire height of the tray. The thickness and height of these supporting flat plates are not particularly limited as long as they are located in the middle of the entire height of the tray, but a height of about half the height of the tray is particularly preferable.
If necessary, it is also possible to provide a gap in these supporting flat plates. Furthermore, in the present invention, the position of each pocket surface is determined by the tray, as in the conventional conductive tray.
Those located in the middle of the overall height are preferred.

【０００９】本発明の導電性トレ−を製造するために使
用される材料は、熱可塑性樹脂と導電性充填材を含有す
る樹脂組成物が好ましい。使用される熱可塑性樹脂は、
（ａ）スチレン系樹脂、例えば、耐衝撃ポリスチレン樹
脂、ＡＢＳ樹脂、スチレン−ブタジエン共重合体樹脂な
ど、（ｂ）塩化ビニル系樹脂、例えば、塩化ビニル樹
脂、塩化ビニル−酢酸ビニル共重合体樹脂など、（ｃ）
オレフィン系樹脂、例えば、ポリエチレン樹脂、ポリプ
ロピレン樹脂、エチレン−プロピレン共重合体樹脂な
ど、さらに、ポリカ−ボネ−ト樹脂、ポリアミド樹脂、
ポリフェニレンエ−テル樹脂等といった樹脂から選ばれ
た少なくとも一種類が用いられる。導電性充填材として
は、カ−ボンファイバ−、カ−ボンブラック、または
銅、アルミニウム等の金属の粉末、繊維、フレ−クある
いは、その他の導電性充填材が用いられる。前記樹脂組
成物は、必要に応じて、帯電防止剤、着色剤、一般的な
充填材、及び加工助剤等を含有するものであってもよ
い。The material used for producing the conductive tray of the present invention is preferably a resin composition containing a thermoplastic resin and a conductive filler. The thermoplastic resin used is
(A) Styrene resin, for example, impact-resistant polystyrene resin, ABS resin, styrene-butadiene copolymer resin, etc., and (b) Vinyl chloride resin, for example, vinyl chloride resin, vinyl chloride-vinyl acetate copolymer resin, etc. , (C)
Olefin-based resins, for example, polyethylene resin, polypropylene resin, ethylene-propylene copolymer resin, etc., further, polycarbonate resin, polyamide resin,
At least one selected from resins such as polyphenylene ether resin is used. As the conductive filler, carbon fiber, carbon black, metal powder such as copper or aluminum, fiber, flake or other conductive filler is used. The resin composition may contain an antistatic agent, a coloring agent, a general filler, a processing aid, and the like, if necessary.

【００１０】[0010]

【実施例】以下、実施例により本発明を詳細に説明す
る。The present invention will be described below in detail with reference to examples.

【００１１】実施例１ ＡＢＳ樹脂（電気化学工業（株）社製、商品名「デンカ
ＡＢＳ、ＧＲ−３０００」、ＡＢＳと略記する）８５重
量部にカ−ボンファイバ−（東邦レーヨン（株）社製、
商品名「ＨＴＡ−Ｃ６−ＳＲ」、ＣＦと略記する）１５
重量部を混入した樹脂組成物を用い、射出成形により、
フラットタイプの半導体集積回路装置１１を収納する導
電性トレ−１であって、前記導電性トレ−１には、半導
体集積回路装置１１を複数収納するための、格子状の壁
２により同じ形状に区画された凹部からなるポケット３
が形成され、このポケット３の内側部分には、前記半導
体集積回路装置１１の外周面を嵌着、保持するための微
小リブ４で囲まれた凹部が設けられ、（１）（イ）任意
の隣接するポケット間の格子状の壁を挟み、最も近く平
行に位置する微小リブ間に空隙５を設け、及び（ロ）ト
レ−外枠７とそれと平行に隣接する微小リブ４間に空隙
を設け、かつ、（２）ポケット３とトレ−外枠７をつな
ぐ支持平面板上面９の高さがトレ−全体高さ10の２分の
１である半導体集積回路装置の収納用導電性トレ−を得
た。得られた導電性トレ−の形状を図１及び図２に示
す。導電性トレ−の評価結果を表１に示す。この導電性
トレ−は、成形後収縮率において、短尺寸法及びピッチ
寸法の数値の差が小さく、かつ、ソリが小さく、実用的
であった。Example 1 Carbon fiber (Toho Rayon Co., Ltd.) was used in 85 parts by weight of ABS resin (trade name "DENKA ABS, GR-3000", manufactured by Denki Kagaku Kogyo KK). Made,
Product name "HTA-C6-SR", abbreviated as CF) 15
Using a resin composition mixed with parts by weight, by injection molding,
A conductive tray for housing a flat-type semiconductor integrated circuit device, wherein the conductive tray has the same shape by a lattice-shaped wall for housing a plurality of semiconductor integrated circuit devices. Pocket 3 consisting of partitioned recesses
A recess is provided in the inside of the pocket 3 and is surrounded by microribs 4 for fitting and holding the outer peripheral surface of the semiconductor integrated circuit device 11. An air gap 5 is provided between the minute ribs located closest and parallel to each other with a grid-like wall between adjacent pockets therebetween, and an air gap is provided between the (b) tray outer frame 7 and the minute ribs 4 adjacent thereto in parallel. And (2) a conductive tray for accommodating a semiconductor integrated circuit device in which the height of the upper surface 9 of the supporting flat plate connecting the pocket 3 and the tray outer frame 7 is one half of the total height 10 of the tray. Obtained. The shape of the obtained conductive tray is shown in FIGS. Table 1 shows the results of the evaluation of the conductive tray. This conductive tray was practical because the difference between the numerical values of the short dimension and the pitch dimension in the shrinkage after molding was small and the warpage was small.

【００１２】評価方法については、トレ−各部の寸法
は、三次元測定機（XYZAX S-400A TOKYOSEIMITU社
製）、反りについては、成形品を定盤の上に置き、ハイトケ
゛-シ゛（NO.192-653 MITUTOYO社製）を使用し、９箇所の
定盤からの高さを測定し、最大値ー最小値で示した。Regarding the evaluation method, the dimensions of each part of the tray were measured with a three-dimensional measuring machine (XYZAX S-400A manufactured by TOKYOSEIMITU). -653 MITUTOYO Co., Ltd.), and measured the height from the surface plate at 9 places, and showed the maximum value-minimum value.

【００１３】実施例２ 実施例１において、同じ材料を使用して（イ）任意の隣
接するポケット間の格子状の壁を挟み、最も近く平行に
位置する微小リブ間に空隙５を設けず、かつ（ロ）トレ
−外枠７とそれと平行に隣接する微小リブ４間に空隙を
設けず、ポケット３とトレ−外枠７をつなぐ支持平面板
上面９の高さをトレ−全体高さ10の２分の１とした以外
は同様に行い、半導体集積回路装置の収納用導電性トレ
−を得た。結果を表１に示す。この導電性トレ−は、成
形後収縮率において、短尺寸法及びピッチ寸法の数値の
差が小さく、かつ、ソリが小さく、実用的であった。Embodiment 2 In Embodiment 1, the same material is used, and (a) a grid-like wall between arbitrary adjacent pockets is sandwiched, and no gap 5 is provided between the minute parallel ribs closest to each other. (B) No space is provided between the tray outer frame 7 and the micro ribs 4 adjacent to the tray outer frame 7, and the height of the upper surface 9 of the supporting flat plate connecting the pocket 3 and the tray outer frame 7 is set to the total height of the tray 10. The same procedure as above was carried out except that the half was reduced to obtain a conductive tray for housing a semiconductor integrated circuit device. Table 1 shows the results. This conductive tray was practical because the difference between the numerical values of the short dimension and the pitch dimension in the shrinkage after molding was small and the warpage was small.

【００１４】実施例３ 実施例１において、同じ材料を使用して（イ）任意の隣
接するポケット間の格子状の壁を挟み、最も近く平行に
位置する微小リブ間に空隙５を設け、（ロ）トレ−外枠
７とそれと平行に隣接する微小リブ４間に空隙を設け
ず、ポケット３とトレ−外枠７をつなぐ支持平面板上面
９の高さがトレ−全体高さ10と同じであること以外は同
様に行い、半導体集積回路装置の収納用導電性トレ−を
得た。結果を表１に示す。この導電性トレ−は、成形後
収縮率において、短尺寸法及びピッチ寸法の数値の差が
小さく、かつ、ソリが小さく、実用的であった。Embodiment 3 In the embodiment 1, the same material is used, (a) a lattice-shaped wall between arbitrary adjacent pockets is sandwiched, and a gap 5 is provided between minute parallel ribs which are closest to and parallel to each other. B) No space is provided between the tray outer frame 7 and the minute ribs 4 adjacent to the tray outer frame 7, and the height of the upper surface 9 of the supporting flat plate connecting the pocket 3 and the tray outer frame 7 is the same as the overall height 10 of the tray. A conductive tray for housing a semiconductor integrated circuit device was obtained. Table 1 shows the results. This conductive tray was practical because the difference between the numerical values of the short dimension and the pitch dimension in the shrinkage after molding was small and the warpage was small.

【００１５】実施例４ 実施例１において、同じ材料を使用して（イ）任意の隣
接するポケット間の格子状の壁を挟み、最も近く平行に
位置する微小リブ間に空隙５を設けず、（ロ）トレ−外
枠７とそれと平行に隣接する微小リブ４間に空隙を設
け、ポケット３とトレ−外枠７をつなぐ支持平面板上面
９の高さがトレ−全体高さ10と同じであること以外は同
様に行い、半導体集積回路装置の収納用導電性トレ−を
得た。結果を表１に示す。この導電性トレ−は、成形後
収縮率において、短尺寸法及びピッチ寸法の数値の差が
小さく、かつ、ソリが小さく、実用的であった。 比較例１ 実施例１において、同じ材料を使用して（イ）任意の隣
接するポケット間の格子状の壁を挟み、最も近く平行に
位置する微小リブに空隙を設けず、かつ（ロ）トレ−外
枠とそれと平行に隣接する微小リブ間に空隙を設けず、
かつ、ポケットとトレ−外周をつなぐ支持平面板の高さ
がトレ−全体高さと同じである半導体集積回路装置の収
納用導電性トレ−を得た。結果を表１に示す。この導電
性トレ−は、成形後収縮率において、短尺寸法及びピッ
チ寸法の数値の差が大きく、かつ、ソリが大きく、実用
的でなかった。Embodiment 4 In Embodiment 1, the same material is used, and (a) a grid-like wall between arbitrary adjacent pockets is sandwiched, and no gap 5 is provided between minute ribs located closest and parallel to each other. (B) A space is provided between the tray outer frame 7 and the micro ribs 4 adjacent to the tray outer frame 7, and the height of the upper surface 9 of the supporting flat plate connecting the pocket 3 and the tray outer frame 7 is the same as the overall height 10 of the tray. A conductive tray for housing a semiconductor integrated circuit device was obtained. Table 1 shows the results. This conductive tray was practical because the difference between the numerical values of the short dimension and the pitch dimension in the shrinkage after molding was small and the warpage was small. Comparative Example 1 In Example 1, the same material was used and (a) a lattice-like wall between arbitrary adjacent pockets was sandwiched. -No gap is provided between the outer frame and the micro ribs adjacent to the outer frame,
Further, a conductive tray for accommodating a semiconductor integrated circuit device in which the height of the supporting flat plate connecting the pocket and the outer periphery of the tray is the same as the entire height of the tray is obtained. Table 1 shows the results. This conductive tray was not practical because of a large difference between the numerical values of the short dimension and the pitch dimension in the shrinkage ratio after molding, and a large warp.

【００１６】[0016]

【表１】 （注１）短尺寸法及びピッチ寸法について、樹脂材料部分と空隙部分の占有割合 を示す。[Table 1] (Note 1) Regarding the short dimension and pitch dimension, the occupation ratio of the resin material portion and the void portion is shown.

【００１７】[0017]

【発明の効果】以上の通り本発明の導電性トレ−は、ト
レ−一定方向における部分収縮率の一定化、反りの低
減、あわせてトレ−軽量化効果等を有する半導体集積回
路装置の収納用導電性トレ−を提供するものである。As described above, the conductive tray of the present invention is used for accommodating a semiconductor integrated circuit device having a constant partial shrinkage in a fixed direction of the tray, a reduction in warpage, and an effect of reducing the weight of the tray. A conductive tray is provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の導電性トレ−の部分的平面図である。FIG. 1 is a partial plan view of a conductive tray of the present invention.

【図２】図１のＡ−Ａ’断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.

【図３】本発明の導電性トレ−の概略的平面図である。FIG. 3 is a schematic plan view of the conductive tray of the present invention.

【図４】従来の導電性トレ−の部分的平面図である。FIG. 4 is a partial plan view of a conventional conductive tray.

【図５】図４のＢ−Ｂ’断面図である。FIG. 5 is a sectional view taken along line B-B 'of FIG.

【符号の説明】[Explanation of symbols]

１ 導電性トレ− ２ 格子状の壁 ３ ポケット ４ 微小リブ ５ 格子状の壁を挟み、最も近く平行に位置する微小リ
ブ間の空隙 ５ａ 微小リブに囲まれたポケット中央の空隙 ６ トレ−外枠とそれと平行に隣接する微小リブ間の空
隙 ７ トレー外枠 ８ ポケットとトレ−外枠をつなぐ支持平面板 ９ ポケットとトレ−外枠をつなぐ支持平面板上面 １０ トレ−全体高さ １１ 半導体集積回路装置 １２ 短尺寸法 １３ ピッチ寸法 １４ ポケット表面DESCRIPTION OF SYMBOLS 1 Conductive tray 2 Lattice wall 3 Pocket 4 Micro rib 5 Space between micro ribs located closest and parallel to the lattice wall 5a Void at the center of pocket surrounded by micro ribs 6 Train outer frame And a gap between the micro ribs adjacent thereto in parallel with the tray 7 tray outer frame 8 supporting flat plate connecting the pocket and the tray outer frame 9 upper surface of the supporting flat plate connecting the pocket and the tray outer frame 10 tray overall height 11 semiconductor integrated circuit Equipment 12 Short dimension 13 Pitch dimension 14 Pocket surface

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−201888（ＪＰ，Ａ) 特開 平６−127582（ＪＰ，Ａ) 実開 平６−12392（ＪＰ，Ｕ) 実公 平３−33670（ＪＰ，Ｙ２) (58)調査した分野(Int.Cl.⁷，ＤＢ名) B65D 85/38 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-201888 (JP, A) JP-A-6-127582 (JP, A) JP-A-6-12392 (JP, U) 33670 (JP, Y2) (58) Field surveyed (Int. Cl. ⁷ , DB name) B65D 85/38

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】フラットタイプの半導体集積回路装置を収
納する導電性トレーであって、前記導電性トレーには、
半導体集積回路装置を単数、又は複数収納するための、
格子状の壁により同じ形状に区画された凹部からなるポ
ケットが形成され、このポケットの内側部分には、前記
半導体集積回路装置の外周面を嵌着、保持するための微
小リブで囲まれた凹部が設けられ、（１）（イ）任意の
隣接するポケット間の格子状の壁を挟み、最も近く平行
に位置する微小リブ間に空隙を設け、及び／又は（ロ）
トレー外枠とそれと平行に隣接する微小リブ間に空隙を
設けたことを特徴とする半導体集積回路装置の収納用導
電性トレー。1. A conductive tray for storing a flat type semiconductor integrated circuit device, wherein the conductive tray includes:
For housing a single or a plurality of semiconductor integrated circuit devices,
A pocket consisting of a recess partitioned into the same shape by the lattice-like wall is formed, and a recess surrounded by microribs for fitting and holding the outer peripheral surface of the semiconductor integrated circuit device is formed inside the pocket. (1) (a) a gap is provided between micro ribs located closest and parallel to each other with a grid-like wall between any adjacent pockets, and / or (b)
Create a gap between the tray outer frame and the minute ribs
A conductive tray for storing a semiconductor integrated circuit device, wherein the conductive tray is provided. 【請求項２】フラットタイプの半導体集積回路装置を収2. A flat type semiconductor integrated circuit device.
納する導電性トレーであって、前記導電性トレーには、A conductive tray to be stored, wherein the conductive tray includes:
半導体集積回路装置を単数、又は複数収納するための、For housing a single or a plurality of semiconductor integrated circuit devices,
格子状の壁により同じ形状に区画された凹部からなるポPos, consisting of concave portions divided into the same shape by latticed walls
ケットが形成され、このポケットの内側部分には、前記A pocket is formed, and the inside of the pocket is
半導体集積回路装置の外周面を嵌着、保持するための微A fine fitting for holding the outer peripheral surface of the semiconductor integrated circuit device.
小リブで囲まれた凹部が設けられ、（１）（イ）任意のA recess surrounded by small ribs is provided.
隣接するポケット間の格子状の壁を挟み、最も近く平行Nearest parallel, sandwiching grid-like walls between adjacent pockets
に位置する微小リブ間に空隙を設け、及び／又は（ロ）Providing a gap between the micro ribs located at
トレー外枠とそれと平行に隣接する微小リブ間に空隙をCreate a gap between the tray outer frame and the minute ribs
設け、（２）ポケットとトレー外枠をつなぐ支持平面板(2) A supporting flat plate that connects the pocket and the outer frame of the tray
上面の高さがトレー全体高さの中間に位置することを特The height of the upper surface is located in the middle of the height of the entire tray.
徴とする半導体集積回路装置の収納用導電性トレー。A conductive tray for storing a semiconductor integrated circuit device.