JP3252432B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置及びその製
造方法に係わり、特に電気的に絶縁されたウェルの構造
及びその形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of an electrically insulated well and a method of forming the same.

【０００２】[0002]

【従来の技術】近年、半導体素子の微細化に伴い、半導
体装置内の一部のみに基板バイアスを与えること、少数
キャリアの注入に伴うソフトエラー防止を行なうこと等
を目的として、電気的に絶縁されたウェル構造が用いら
れてきている。2. Description of the Related Art In recent years, with the miniaturization of semiconductor elements, electrical insulation has been made for the purpose of applying a substrate bias to only a part of a semiconductor device and preventing soft errors due to minority carrier injection. Well structures have been used.

【０００３】従来のウェル構造及びその形成方法の例１
について図面を参照しながら説明する。図５は従来のウ
ェルの構造及びその形成方法を示す工程断面図である。
図５において、1はｐ型半導体基板、3は電気的に基板と
絶縁された第１のｐウェル、9は第１のｐウェル3を絶縁
させるためのｎ型ウェル、4は電気的に基板に接続した
第２のｐウェル、5は第３のｎウェルを示す。また一般
的な製造方法として、先ず絶縁用ｎウェル９をフォトレ
ジストマスク91を用い選択的に基板１表面にＰイオン注
入92を行い（工程ａ）、その後熱処理により不純物の拡
散を行い、所望の深さに不純物拡散領域を広げる（工程
ｂ）。さらに第１のｐウェル形成のためのフォトレジス
トマスク31を絶縁用ｎウェル９領域内に形成し、Ｂイオ
ン注入32を行うことで電気的に基板1と絶縁された第１
のｐウェル３が形成される（工程ｃ）。また、絶縁用ｎ
ウェル９領域外に第２のｐウェル形成のためのフォトレ
ジストマスク41を形成し、Ｂイオン注入42を行なうこと
で基板１と電気的に接続された第２のｐウェル４が形成
される（工程ｄ）。さらに絶縁用ｎウェル９，第２のｐ
ウェル４領域外に第３のｎウェル形成のためのフォトレ
ジストマスク51を形成し、Ｐイオン注入52を行なうこと
で、第３のｎウェル５が形成される（工程ｅ）。その
後、熱処理を行い不純物拡散並びに活性化を行なうこと
で、電気的に基板１と絶縁された第１のｐウェル３，電
気的に基板１に接触している第２のｐウェル４,第３の
ｎウェル５がそれぞれ形成される（工程ｆ）。Example 1 of conventional well structure and method of forming the same
Will be described with reference to the drawings. FIG. 5 is a process sectional view showing a conventional well structure and a method for forming the same.
In FIG. 5, 1 is a p-type semiconductor substrate, 3 is a first p-well electrically insulated from the substrate, 9 is an n-type well for insulating the first p-well 3, and 4 is an electrical substrate. Indicates a second p-well, and 5 indicates a third n-well. Further, as a general manufacturing method, first, P ions are implanted 92 in the insulating n-well 9 selectively on the surface of the substrate 1 using a photoresist mask 91 (step a), and then impurities are diffused by heat treatment to obtain a desired impurity. The impurity diffusion region is expanded to the depth (step b). Further, a photoresist mask 31 for forming a first p-well is formed in the region of the insulating n-well 9 and B ion implantation 32 is performed to thereby electrically insulate the first substrate 1 from the substrate 1.
Is formed (step c). Also, for insulation n
A photoresist mask 41 for forming a second p-well is formed outside the well 9 region, and B ion implantation 42 is performed to form a second p-well 4 electrically connected to the substrate 1 ( Step d). Further, the insulating n-well 9 and the second p
A third n-well 5 is formed by forming a photoresist mask 51 for forming a third n-well outside the region of the well 4 and performing P ion implantation 52 (step e). Thereafter, the first p-well 3, electrically insulated from the substrate 1, the second p-well 4, electrically in contact with the substrate 1, the third Are formed respectively (step f).

【０００４】絶縁用ウェル形成において１ＭｅＶ程度の
高エネルギー領域でのイオン注入を用いて形成した場合
の、従来のウェル構造及びその形成方法の例２について
図面を参照しながら説明する。図６は従来のウェルの構
造及びその形成方法を示す工程断面図である。図６にお
いて、1はｐ型半導体基板、3は電気的に基板と絶縁され
た第１のｐウェル、31は電気的に絶縁された第１のｐウ
ェル形成のためのフォトレジストマスク、4は第２のｐ
ウェル、41は第２のｐウェル形成のためのフォトレジス
トマスク、5は第３のｎウェル、51は第３のｎウェル形
成のためのフォトレジストマスク、2は埋め込み領域、2
1は埋め込み領域形成のためのフォトレジストマスク、6
はウォール領域、61はウォール領域形成のためのフォト
レジストマスクである。イオン注入22,32,42,52,62を用
いた各ウェル形成において高エネルギー領域でのイオン
注入を用いた場合、不純物の拡散を行なう必要が無く熱
処理は不純物の活性化程度で良い。以上のように構成さ
れた半導体装置については例えば、電子情報通信学会技
術研究報告ＳＤＭ８９−３３,８７ページ〜９２ページ,
１９８９年に記されている。A conventional well structure and an example 2 of a method of forming the same in the case where the insulating well is formed by ion implantation in a high energy region of about 1 MeV will be described with reference to the drawings. FIG. 6 is a process sectional view showing a conventional well structure and a method of forming the same. In FIG. 6, 1 is a p-type semiconductor substrate, 3 is a first p-well electrically insulated from the substrate, 31 is a photoresist mask for forming an electrically insulated first p-well, 4 is The second p
Well, 41 is a photoresist mask for forming a second p-well, 5 is a third n-well, 51 is a photoresist mask for forming a third n-well, 2 is a buried region, 2
1 is a photoresist mask for forming a buried region, 6
Is a wall region, and 61 is a photoresist mask for forming the wall region. When ion implantation in a high energy region is used in the formation of each well using the ion implantations 22, 32, 42, 52, and 62, diffusion of impurities does not need to be performed, and heat treatment may be performed only to activate the impurities. For the semiconductor device configured as described above, for example, IEICE Technical Report SDM89-33, pp. 87-92,
It was written in 1989.

【０００５】まず半導体記憶装置（ＤＲＡＭ）ではメモ
リセル部を基板と電気的に絶縁されたｐウェル内に形成
し、ｐウェル内に負の基板バイアスを与える。さらに絶
縁用ｎウェルには正のバイアスを与えることで周辺回路
において発生した少数キャリア（電子）はセルを形成し
たウェル内に入り込むことができない。その結果ソフト
エラー耐性並びに周辺回路のｎＭＯＳトランジスタから
発生する少数キャリアーによるセルデータ破壊の問題が
解消する。以上述べてきたように電気的に絶縁されたウ
ェル内に半導体記憶素子を形成することで少数キャリア
ーの侵入に伴うソフトエラーを防ぐことが可能となる。First, in a semiconductor memory device (DRAM), a memory cell portion is formed in a p-well electrically insulated from a substrate, and a negative substrate bias is applied to the p-well. Further, by applying a positive bias to the insulating n-well, minority carriers (electrons) generated in the peripheral circuit cannot enter the well in which the cell is formed. As a result, problems of soft error resistance and cell data destruction due to minority carriers generated from the nMOS transistor of the peripheral circuit are solved. As described above, by forming a semiconductor memory element in an electrically insulated well, it becomes possible to prevent a soft error due to intrusion of minority carriers.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら例１に示
した構成では、熱処理による拡散法を用いて不純物を深
く拡散させることにより、絶縁用ｎウェル9 の形成を行
っていたため、不純物は横方向にも拡散し、電気的に基
板１と絶縁された第１のｐウェル３と電気的に基板１に
接続している第２のｐウェル４の間の領域において不純
物濃度が緩い勾配を示し、かつ不純物濃度がウェルの中
央部に比べて低くなるので、絶縁された第１のｐウェル
３の端部から基板に接続している第２のｐウェル４端部
までの距離を小さくする事ができず、素子の微細化に不
向きであるという問題を有していた。However, in the structure shown in Example 1, the impurity is diffused deeply by the diffusion method by heat treatment to form the insulating n-well 9, so that the impurity is laterally diffused. Is also diffused, and the impurity concentration shows a gentle gradient in a region between the first p well 3 electrically insulated from the substrate 1 and the second p well 4 electrically connected to the substrate 1, and Since the impurity concentration is lower than the central part of the well, the distance from the end of the insulated first p well 3 to the end of the second p well 4 connected to the substrate can be reduced. However, it is not suitable for miniaturization of devices.

【０００７】さらに、例２の構造においては、電気的に
基板１から絶縁された第１のｐウェル３底面に埋め込み
領域２を形成する場合、高エネルギー領域でのイオン注
入により深い位置に不純物導入が行えるため、熱処理に
よる拡散が原因の緩い不純物濃度勾配はない。しかしな
がら高いエネルギーでのイオン注入においては不純物分
布がガウス分布を示すため、基板表面付近のｎ型不純物
濃度が低くなり、絶縁された第１のｐウェル3端部から
基板に接続している第２のｐウェル4端部との間にパン
チスル−を防止するために基板表面付近のｎ型不純物濃
度を高くする必要がある。そのため、ｎ型不純物濃度の
高いウォール領域6形成のためにフォトレジストマスク6
1を形成し、追加のＰイオン注入62を行なわなければな
らない。このウォール領域形成のためのフォトレジスト
マスク61を形成する場合においても例１の場合と同様マ
スク合わせ精度を高くしないと素子の微細化に不向きで
ある。さらに製造工程が増加するという問題を有してい
た。Furthermore, in the structure of Example 2, when the buried region 2 is formed on the bottom surface of the first p-well 3 which is electrically insulated from the substrate 1, impurities are introduced into deep positions by ion implantation in a high energy region. Therefore, there is no gentle impurity concentration gradient caused by the diffusion due to the heat treatment. However, in the ion implantation with high energy, the impurity distribution shows a Gaussian distribution, so that the n-type impurity concentration near the substrate surface decreases, and the second insulated first p-well 3 is connected to the substrate from the end. It is necessary to increase the n-type impurity concentration near the surface of the substrate in order to prevent punch through between the p-well 4 and the end of the p-well. Therefore, the photoresist mask 6 is formed to form the wall region 6 having a high n-type impurity concentration.
A 1 must be formed and an additional P ion implant 62 must be performed. Even in the case of forming the photoresist mask 61 for forming the wall region, as in the case of Example 1, unless the mask alignment accuracy is increased, it is not suitable for miniaturization of elements. Further, there is a problem that the number of manufacturing steps increases.

【０００８】本発明は上記問題点に鑑み、素子の微細化
に適しかつ工程数の増加を伴うことなく少数キャリアー
によるソフトエラーを防ぐことが可能な半導体装置及び
その製造方法を提供するものである。In view of the above problems, the present invention provides a semiconductor device suitable for miniaturization of elements and capable of preventing a soft error due to minority carriers without increasing the number of steps, and a method of manufacturing the same. .

【０００９】[0009]

【課題を解決するための手段】本発明の請求項１に係わ
る半導体装置は、上記問題を同時に解決するため、半導
体基板内部に前記半導体基板全面にわたり形成され、前
記基板と反対の導電型を有する埋め込み層と、前記基板
表面から内部に至り、前記基板と同じ導電型を有する、
メモリーセルが搭載された第１のウェルと、前記第１の
ウェル周辺を取り囲み、前記埋め込み層から前記基板表
面まで連続して形成され、前記基板と反対の導電型を有
するウォール領域と、前記基板表面から内部に至り、前
記基板と同じ導電型を有する第２のウェルと、前記基板
表面から内部に至り、前記基板と反対の導電型を有する
第３のウェルを有し、前記第３のウェルを前記埋め込み
層と接触させたことを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device which is formed inside a semiconductor substrate over the entire surface of the semiconductor substrate and has a conductivity type opposite to that of the substrate in order to simultaneously solve the above problems. A buried layer, extending from the substrate surface to the inside, having the same conductivity type as the substrate ,
A first well in which a memory cell is mounted , a wall region surrounding the first well, formed continuously from the buried layer to the substrate surface, and having a conductivity type opposite to that of the substrate; A third well extending from the surface to the inside and having the same conductivity type as the substrate; and a third well extending from the substrate surface to the inside and having a conductivity type opposite to the substrate, wherein the third well is provided. Is brought into contact with the buried layer.

【００１０】本発明の請求項２に係わる半導体装置は、
半導体基板内部に前記半導体基板全面にわたり形成さ
れ、前記基板と反対の導電型を有する埋め込み層と、前
記基板と同じ導電型を有し前記埋め込み層より高い不純
物濃度を有する補償領域と、前記基板表面から内部に至
り、前記基板と同じ導電型を有する第１のウェルと、前
記第１のウェル周辺を取り囲み、前記埋め込み層から前
記基板表面まで連続して形成され、前記基板と反対の導
電型を有するウォール領域と、前記基板表面から内部に
至り、前記基板と同じ導電型を有する第２のウェル及び
第４のウェルと、前記基板表面から内部に至り、前記基
板と反対の導電型を有する第３のウェル及び第５のウェ
ルを有し、前記補償領域を前記埋め込み層と同じ深さに
設けて前記埋め込み層と第３,第５のウェルとの接続を
遮断することを特徴とする。A semiconductor device according to a second aspect of the present invention comprises:
A buried layer formed inside the semiconductor substrate over the entire surface of the semiconductor substrate and having a conductivity type opposite to the substrate; a compensation region having the same conductivity type as the substrate and having a higher impurity concentration than the buried layer; To the inside, a first well having the same conductivity type as the substrate, and surrounding the first well, formed continuously from the buried layer to the substrate surface, and having a conductivity type opposite to the substrate. A second well and a fourth well extending from the surface of the substrate and having the same conductivity type as the substrate, and a second region having a conductivity type opposite to the substrate and extending from the surface of the substrate to the inside. A third well and a fifth well, wherein the compensation region is provided at the same depth as the buried layer to cut off connection between the buried layer and the third and fifth wells. I do.

【００１１】本発明の請求項３に係わる半導体装置は、
半導体基板内部に前記半導体基板全面にわたり形成さ
れ、前記基板と反対の導電型を有する埋め込み層と、前
記基板表面に前記基板と同じ導電型を有する第１のウェ
ルと、前記第１のウェル周辺を取り囲み、前記埋め込み
層から前記基板表面まで連続して形成され、前記基板と
反対の導電型を有するウォール領域と、前記基板と同じ
導電型を有する第２のウェル及び第４のウェルと、前記
基板と反対の導電型を有する第３のウェル及び第５のウ
ェルを有し、前記第３のウェル及び前記第５のウェルが
前記埋め込み層より浅い位置に形成され、前記第３のウ
ェル及び前記第５のウェルと前記埋め込み層が離間して
いることを特徴とする。[0011] The semiconductor device according to claim 3 of the present invention comprises:
A buried layer formed over the entire surface of the semiconductor substrate inside the semiconductor substrate and having a conductivity type opposite to the substrate, a first well having the same conductivity type as the substrate on the surface of the substrate, and a periphery of the first well. A surrounding wall region formed continuously from the buried layer to the substrate surface and having a conductivity type opposite to the substrate, a second well and a fourth well having the same conductivity type as the substrate, A third well and a fifth well having a conductivity type opposite to that of the third well and the fifth well are formed at a position shallower than the buried layer. 5 is separated from the buried layer.

【００１２】また本発明の請求項４に係わる半導体装置
は、請求項２記載の第２のウェル及び第４のウェル底部
の、埋め込み層と同じ深さに基板と同じ導電型の補償領
域を有し、前記基板と第２のウェル及び第４のウェル底
部が前記補償領域を介して接続されることを特徴とす
る。A semiconductor device according to a fourth aspect of the present invention has a compensation region of the same conductivity type as the substrate at the same depth as the buried layer at the bottom of the second well and the fourth well according to the second aspect. The substrate is connected to the second well and the bottom of the fourth well via the compensation region.

【００１３】本発明の請求項５に係わる半導体装置の製
造方法は、マスクを用い選択的に半導体基板表面から不
純物を導入し前記基板と同じ導電型の第１のウェルを形
成する工程と、マスクを用い選択的に前記基板表面から
不純物を導入し前記基板と同じ導電型の第２のウェルを
形成する工程と、マスクを用い選択的に前記基板表面か
ら不純物を導入し前記基板と反対の導電型の第３のウェ
ルを形成する工程と、マスクを用い選択的に不純物を導
入し前記基板と反対導電型のウォール領域を形成する工
程と、前記半導体基板の全面にわたり不純物を導入し前
記基板と反対の導電型を有する埋め込み層を形成する工
程とを備え、前記ウォール領域は前記第１のウェル周辺
を取り囲み、前記埋め込み層は前記第３のウェル及び前
記ウォール領域に接触する所定の深さに形成されること
を特徴とする。According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of selectively introducing impurities from the surface of a semiconductor substrate by using a mask to form a first well of the same conductivity type as the substrate; Forming a second well of the same conductivity type as that of the substrate by selectively introducing impurities from the surface of the substrate using a mask; and selectively introducing impurities from the surface of the substrate by using a mask to form a second well. Forming a third well of a mold, selectively introducing an impurity using a mask to form a wall region of a conductivity type opposite to that of the substrate, and introducing an impurity over the entire surface of the semiconductor substrate to form a third region. Forming a buried layer having an opposite conductivity type, wherein the wall region surrounds the periphery of the first well, and the buried layer is formed in the third well and the wall region. Characterized in that it is formed to a predetermined depth to touch.

【００１４】本発明の請求項６に係わる半導体装置の製
造方法は、マスクを用い選択的に半導体基板表面から不
純物を導入し前記基板と同じ導電型の第１のウェルを形
成する工程と、マスクを用い選択的に半導体基板表面か
ら不純物を導入し前記基板と同じ導電型の第２のウェル
及び第４のウェルを形成する工程と、マスクを用い選択
的に半導体基板表面から不純物を導入し前記基板と反対
の導電型の第３のウェル及び第５のウェルを形成する工
程と、前記第２のウェル及び第４のウェル形成時に用い
たマスクを用い自己整合的に不純物を導入し、前記基板
と同じ導電型の第１の補償領域を形成する工程と、前記
第３のウェル及び第５のウェル形成時に用いたマスクを
用い自己整合的に不純物を導入し、前記基板と同じ導電
型の第２の補償領域を形成する工程と、マスクを用い選
択的に不純物を導入し前記基板と反対導電型のウォール
領域を形成する工程と、前記半導体基板の全面にわたり
不純物を導入し前記基板と反対の導電型を有する埋め込
み層を形成する工程とを備え、前記第１の補償領域は前
記埋め込み層と同じ深さにかつ前記埋め込み層よりも高
い濃度となるように形成され、前記第２の補償領域は前
記埋め込み層と同じ深さにかつ前記埋め込み層よりも高
い濃度となるように形成され、前記ウォール領域は前記
第１のウェルを取り囲み、前記埋め込み層は前記ウォー
ル領域に接触する所定の深さに形成されることを特徴と
する。According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of selectively introducing impurities from the surface of a semiconductor substrate by using a mask to form a first well of the same conductivity type as the substrate; Selectively introducing impurities from the surface of the semiconductor substrate using a mask to form second and fourth wells of the same conductivity type as the substrate, and selectively introducing impurities from the surface of the semiconductor substrate using a mask. Forming a third well and a fifth well of a conductivity type opposite to that of the substrate, and introducing impurities in a self-alignment manner using a mask used in forming the second well and the fourth well; Forming a first compensation region of the same conductivity type as the first step, and introducing a self-aligned impurity using a mask used in forming the third well and the fifth well to form a first compensation region of the same conductivity type as the substrate. 2 Compensation territory A step of selectively introducing impurities using a mask to form a wall region of the opposite conductivity type to the substrate; and introducing an impurity over the entire surface of the semiconductor substrate to have a conductivity type opposite to that of the substrate. Forming a buried layer, wherein the first compensation region is formed at the same depth as the buried layer and at a higher concentration than the buried layer, and wherein the second compensation region is And the wall region surrounds the first well, and the buried layer is formed at a predetermined depth in contact with the wall region. It is characterized by the following.

【００１５】本発明の請求項７に係わる半導体装置の製
造方法は、マスクを用い選択的に半導体基板表面から不
純物を導入し前記基板と同じ導電型の第１のウェルを形
成する工程と、マスクを用い選択的に半導体基板表面か
ら不純物を導入し前記基板と同じ導電型の第２のウェル
及び第４のウェルを形成する工程と、マスクを用い選択
的に半導体基板表面から不純物を導入し前記基板と反対
の導電型の第３のウェル及び第５のウェルを形成する工
程と、マスクを用い選択的に不純物を導入し前記基板と
反対導電型のウォール領域を形成する工程と、前記半導
体基板の全面にわたり不純物を導入し前記基板と反対の
導電型を有する埋め込み層を形成する工程とを備え、前
記ウォール領域は前記第１のウェルを取り囲み、前記埋
め込み層は前記第３のウェルと前記第５のウェルと離間
しかつ前記ウォール領域に接触する所定の深さに形成さ
れることを特徴とする。According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of selectively introducing impurities from the surface of a semiconductor substrate using a mask to form a first well of the same conductivity type as the substrate; Selectively introducing impurities from the surface of the semiconductor substrate using a mask to form second and fourth wells of the same conductivity type as the substrate, and selectively introducing impurities from the surface of the semiconductor substrate using a mask. Forming a third well and a fifth well of a conductivity type opposite to the substrate, selectively introducing impurities using a mask to form a wall region of a conductivity type opposite to the substrate, Forming an embedded layer having a conductivity type opposite to that of the substrate by introducing an impurity over the entire surface of the substrate, wherein the wall region surrounds the first well, and the embedded layer is Spaced wells and the fifth well and characterized in that it is formed to a predetermined depth in contact with the wall region.

【００１６】[0016]

【作用】請求項１および請求項５に係わる半導体装置及
びその製造方法により、基板と同じ導電型を有する第１
のウェルと基板と同じ導電形を有する第２のウェルは、
電気的に半導体基板全面に形成された基板と反対の導電
型を有する埋め込み領域により底面絶縁され、また第１
のウェルと第２のウェルが、第１のウェル側面周辺を取
り囲み埋め込み領域から基板表面まで連続した基板と反
対の導電型を有するウォール領域により側面絶縁され、
かつウォール領域を形成することで横方向の不純物濃度
勾配を急峻にすることができるので、第１のウェル端部
からウォール領域を経て第２のウェル端部に至る距離を
小さくすることが可能となる。さらに、第１のウェル底
面を絶縁する埋め込み領域はマスク工程を経る事なく半
導体基板全面に形成するので工程を増加する事なく電気
的に絶縁されたウェルの形成が可能となる。According to the semiconductor device and the method of manufacturing the same according to the first and fifth aspects, the first device having the same conductivity type as the substrate is provided.
And a second well having the same conductivity type as the substrate,
The bottom surface is electrically insulated by a buried region having a conductivity type opposite to that of the substrate formed electrically over the entire surface of the semiconductor substrate.
And the second well are side-insulated by a wall region surrounding the periphery of the first well side surface and having a conductivity type opposite to that of the substrate continuous from the buried region to the substrate surface,
Moreover, since the impurity concentration gradient in the lateral direction can be made steep by forming the wall region, the distance from the end of the first well to the end of the second well via the wall region can be reduced. Become. Further, since the buried region for insulating the bottom of the first well is formed on the entire surface of the semiconductor substrate without going through a masking step, it is possible to form an electrically insulated well without increasing the number of steps.

【００１７】請求項２および請求項６に係わる半導体装
置及びその製造方法により、基板と同じ導電型を有する
第１のウェルと、基板と同じ導電形を有する第２のウェ
ル及び第４のウェルは、電気的に半導体基板全面に形成
された基板と反対の導電型を有する埋め込み領域により
底面絶縁され、また第１のウェルと第２のウェル及び第
４のウェルが、第１のウェル側面周辺を取り囲み埋め込
み領域から基板表面まで連続した基板と反対の導電型を
有するウォール領域により側面絶縁され、かつウォール
領域を形成することで横方向の不純物濃度勾配を急峻に
することができるので、第１のウェル端部からウォール
領域を経て第２のウェル端部に至る距離を小さくするこ
とが可能となる。さらに、第１のウェル底面の埋め込み
領域はマスク工程を経る事なく半導体基板全面に形成す
るので、工程を増加する事なく電気的に絶縁されたウェ
ルの形成が可能となる。さらに、基板と反対の導電型を
有する第３のウェル及び第５のウェル底部の埋め込み領
域と同じ深さに埋め込み領域より高い不純物濃度で自己
整合的に基板と同じ導電型の補償領域を形成すること
で、第３のウェルとウォール領域及び埋め込み領域との
電気的絶縁が可能となる。According to the second and sixth aspects of the semiconductor device and the method of manufacturing the same, the first well having the same conductivity type as the substrate and the second well and the fourth well having the same conductivity type as the substrate are provided. The bottom surface is electrically insulated by a buried region having a conductivity type opposite to that of the substrate formed electrically over the entire surface of the semiconductor substrate, and the first well, the second well, and the fourth well are formed around the side of the first well. The side surface is insulated by a wall region having a conductivity type opposite to that of the substrate, which is continuous from the surrounding buried region to the substrate surface, and the formation of the wall region enables a steep impurity concentration gradient in the lateral direction. The distance from the well end to the second well end via the wall region can be reduced. Furthermore, since the buried region on the bottom surface of the first well is formed on the entire surface of the semiconductor substrate without going through a masking step, it is possible to form an electrically insulated well without increasing the number of steps. Further, a compensation region having the same conductivity type as that of the substrate is formed in a self-aligned manner at the same depth as the buried region at the bottom of the third well and the bottom of the fifth well having the conductivity type opposite to that of the substrate at a higher impurity concentration than the buried region. This enables electrical insulation between the third well and the wall region and the buried region.

【００１８】請求項４および請求項６に係わる半導体装
置およびその製造方法により、第２のウェル及び第４の
ウェル底部の埋め込み領域と同じ深さに埋め込み領域よ
り高い不純物濃度で自己整合的に基板と同じ導電型の補
償領域を形成することで、第２のウェル及び第４のウェ
ルと基板との電気的接続を得ることが可能となり、基板
裏面よりの電気的接続、及び第２のウェルと第４のウェ
ル間の電気的接続が可能となる。According to the semiconductor device and the method of manufacturing the same according to the fourth and sixth aspects, the substrate is self-aligned at the same depth as the buried region at the bottom of the second well and the fourth well at a higher impurity concentration than the buried region. By forming a compensation region of the same conductivity type as that described above, it is possible to obtain electrical connection between the second well and the fourth well and the substrate, electrical connection from the back surface of the substrate, and the second well. Electrical connection between the fourth wells becomes possible.

【００１９】請求項３および請求項７に係わる半導体装
置およびその製造方法により、基板と同じ導電型を有す
る第１のウェルと、基板と同じ導電形を有する第２のウ
ェル及び第４のウェルは、半導体基板全面に形成された
基板と反対の導電型を有する埋め込み領域により電気的
に底面絶縁され、また第１のウェルと第２のウェル及び
第４のウェルが、第１のウェル側面周辺を取り囲み埋め
込み領域から基板表面まで連続した基板と反対の導電型
を有するウォール領域により側面絶縁され、かつ第１の
ウェルを囲うようにマスクを用い基板と反対導電型のウ
ォール領域を形成することで横方向の不純物濃度勾配を
急峻にすることができるので、第１のウェル端部からウ
ォール領域を経て第２のウェル端部に至る距離を小さく
することが可能となる。さらに、第１のウェル底面を絶
縁する埋め込み領域はマスク工程を経る事なく半導体基
板全面に形成するので、工程を増加する事なく電気的に
絶縁されたウェルの形成が可能となる。さらに、基板と
反対の導電型を有する第３のウェル及び第５のウェルと
埋め込み領域との間に距離を設けることで、第３のウェ
ル及び第５のウェルとウォール領域及び埋め込み領域と
の電気的絶縁が可能となる。According to the semiconductor device and the method of manufacturing the same according to the third and seventh aspects, the first well having the same conductivity type as the substrate, and the second well and the fourth well having the same conductivity type as the substrate are formed. The bottom surface is electrically insulated by a buried region having a conductivity type opposite to that of the substrate formed on the entire surface of the semiconductor substrate, and the first well, the second well, and the fourth well are formed around the side surface of the first well. The side surface is insulated by a wall region having a conductivity type opposite to that of the substrate from the surrounding buried region to the substrate surface, and a wall region of the opposite conductivity type to the substrate is formed using a mask so as to surround the first well. The impurity concentration gradient in the direction can be made steeper, so that the distance from the first well end to the second well end via the wall region can be reduced. That. Further, since the buried region for insulating the bottom of the first well is formed on the entire surface of the semiconductor substrate without going through a mask process, it is possible to form an electrically insulated well without increasing the number of processes. Further, by providing a distance between the third well and the fifth well having a conductivity type opposite to that of the substrate and the buried region, an electric connection between the third well and the fifth well and the wall region and the buried region is provided. Insulation is possible.

【００２０】[0020]

【実施例】以下本発明の半導体装置およびその製造方法
について図面を用い説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG.

【００２１】（実施例１）図１（ａ）は本発明の実施例
１として請求項１に示した半導体装置の断面図である。
図１（ａ）において1は比抵抗が１０〜２０Ωｃｍ程度
のｐ型シリコン基板、2は基板1と反対の導電型を有する
ｎ型埋め込み領域、3は基板1と同じ導電型を有する第１
のｐウェル、4は基板1と同じ導電型を有する第２のｐウ
ェル、5は基板1と反対の導電型を有する第３のｎウェ
ル、6は基板1と反対の導電型を有するｎ型ウォール領域
である。また図７において、(a)〜(e)は埋め込み領域
2、第１のｐウェル3、第２のｐウェル4、第３のｎウェ
ル5、ウォール領域6の各々のドーピングされた不純物濃
度分布を示している。また、破線Ｓは基準となる基板1
中の初期不純物濃度を示している。(Embodiment 1) FIG. 1A is a sectional view of a semiconductor device according to a first embodiment of the present invention.
In FIG. 1A, 1 is a p-type silicon substrate having a specific resistance of about 10 to 20 Ωcm, 2 is an n-type buried region having a conductivity type opposite to that of the substrate 1, and 3 is a first buried region having the same conductivity type as the substrate 1.
4 is a second p-well having the same conductivity type as the substrate 1, 5 is a third n-well having a conductivity type opposite to the substrate 1, and 6 is an n-type having a conductivity type opposite to the substrate 1. This is a wall area. Also, in FIG. 7, (a) to (e) show embedded regions.
2, the respective doped impurity concentration distributions of the first p-well 3, the second p-well 4, the third n-well 5, and the wall region 6 are shown. The broken line S indicates the reference substrate 1
The figure shows the initial impurity concentration in the inside.

【００２２】埋め込み領域２は平面的には基板1全面に
形成されており、その不純物濃度分布は図７(a)に示す
ように、基板１表面（上面）からの接合面の深さＪ_Bは
約１.５μｍである。ウォール領域６は、平面的には第
１のｐウェル3の周囲を取り囲み、埋め込み領域２上面
に完全に接する構造であり、その不純物濃度分布は図７
(e)に示すように、ドーピングされた不純物が基板１表
面まで到達し、底面の接合面の深さＪ_Wは約２.０μｍで
ある。The buried region 2 is formed over the entire surface of the substrate 1 in plan view, and its impurity concentration distribution is, as shown in FIG. 7 (a), the depth J _B of the bonding surface from the surface (upper surface) of the substrate 1. Is about 1.5 μm. The wall region 6 has a structure that surrounds the periphery of the first p-well 3 in a plan view and is completely in contact with the upper surface of the buried region 2.
As shown in (e), the doped impurity reaches the surface of the substrate 1, and the depth _JW of the bonding surface on the bottom surface is about 2.0 μm.

【００２３】第１のｐウェル３は、平面的には側面がウ
ォール領域6に囲まれる構造で、その不純物濃度分布は
図７(b)に示すように、上面が基板1の表面に露呈し、底
面の接合面の深さＪ_PW1は約１.５μｍであり、底面が埋
め込み領域２上面に接する構造となる。さらに、上面を
除いてｎ型の領域に完全に囲まれている。The first p-well 3 has a structure in which the side surface is surrounded by a wall region 6 in plan view, and its impurity concentration distribution is such that its upper surface is exposed to the surface of the substrate 1 as shown in FIG. The depth J _PW1 of the bonding surface of the bottom surface is about 1.5 μm, and the bottom surface is in contact with the upper surface of the buried region 2. Furthermore, it is completely surrounded by an n-type region except for the upper surface.

【００２４】第２のｐウェル４は、不純物濃度分布が図
７(c)に示されるように底面の接合面の深さＪ_PW2は約
１.５μｍであり、底面が埋め込み領域２上面に接する
構造となる。さらに、第２のｐウェル４は上面が基板1
の表面に露呈し、底面が埋め込み領域２上面に接してい
るので、基板１及び第１のｐウェル３とは電気的に絶縁
可能な構造である。しかし、必ずしも周囲を完全にｎ型
領域で囲まれることはないので、電位を独立して設定で
きない場合もある。As shown in FIG. 7 (c), the depth J _PW2 of the bottom junction surface of the second p well 4 is approximately 1.5 μm, and the bottom surface is in contact with the upper surface of the buried region 2. Structure. Further, the upper surface of the second p-well 4 is
And the bottom surface is in contact with the upper surface of the buried region 2, so that the substrate 1 and the first p-well 3 can be electrically insulated. However, since the periphery is not always completely surrounded by the n-type region, the potential may not be set independently.

【００２５】第３のｎウェル５は、不純物濃度分布が図
７(d)に示されるように底面の接合面の深さＪ_NW3は約
１.５μｍであり、底面が埋め込み領域２上面に接する
構造となる。さらに、第３のｎウェル５は上面が基板１
の表面に露呈し、底面が埋め込み領域２上面に接してい
るので、ウォール領域６と電気的に接続されている。As shown in FIG. 7 (d), the third n-well 5 has a junction surface depth J _NW3 of about 1.5 μm as shown in FIG. 7D, and the bottom surface is in contact with the upper surface of the buried region 2. Structure. Further, the third n-well 5 has an upper surface
And is electrically connected to the wall region 6 because the bottom surface is in contact with the upper surface of the embedded region 2.

【００２６】本実施例に示した構造によれば、第１のｐ
ウェル３のみを電気的に独立させる必要があり、第２の
ｐウェル４は基板１と同じ電位に固定する必要がなく、
また第３のｎウェル５はウォール領域６と電気的に接続
させたい場合に有効である。According to the structure shown in this embodiment, the first p
Only the well 3 needs to be electrically independent, and the second p-well 4 does not need to be fixed at the same potential as the substrate 1,
Further, the third n-well 5 is effective when it is desired to electrically connect to the wall region 6.

【００２７】一例として、ＤＲＡＭにおけるソフトエラ
ー対策に本実施例を適用した場合について述べる。ソフ
トエラー対策のために第１のｐウェル３内部にメモリー
セルを設け、第１のｐウェル３は負に電位（例えば−２
Ｖ）をもたせる。一方、ウォール領域６には正の電位
（例えば＋３.３Ｖ）をもたせ、第１のｐウェル３周辺
をウォール領域６により取り囲むことで、少数キャリア
ーの侵入を防ぐことが可能となる。この少数キャリアー
の侵入防止のためには、第１のｐウェル３，ウォール領
域６はそれぞれ負，正に電位を与えることが必要であ
る。さらに、第１のｐウェル３をＤＲＡＭのメモリーセ
ル領域とし、電位を負にすることでトランジスタの見か
け上のしきい値電圧を高くすることが可能となる。その
結果、メモリーセル内のトランジスタのみしきい値電圧
が高くオフ動作時のソース〜ドレイン間リーク電流の減
少を図ることが可能となり、メモリーセルの電荷保持特
性を改善できる。本構造において複数のｎウェルを形成
した場合、埋め込み領域を介し全てのｎウェルは同じ電
位になる。そのため、電位供給に必要な電極の数を削減
でき素子の微細化に有利である。例えばＤＲＡＭデバイ
スに本構造を採用した場合、内部回路において昇圧され
ている回路部分、例えばワード線ドライバー回路等がｎ
ＭＯＳ構造を採用して第２のｐウエル４のみに設けられ
ると、複数のｎウェル間が全て同じウェル電位でよいこ
とになり、この場合は有効である。As an example, a case where the present embodiment is applied to a soft error countermeasure in a DRAM will be described. A memory cell is provided inside the first p-well 3 as a countermeasure against soft errors, and the first p-well 3 has a negative potential (for example, −2).
V). On the other hand, by applying a positive potential (for example, +3.3 V) to the wall region 6 and surrounding the first p-well 3 with the wall region 6, it is possible to prevent minority carriers from invading. In order to prevent the invasion of minority carriers, it is necessary to apply a negative and positive potential to the first p-well 3 and the wall region 6, respectively. Furthermore, by setting the first p-well 3 as a memory cell region of the DRAM and making the potential negative, it becomes possible to increase the apparent threshold voltage of the transistor. As a result, only the transistor in the memory cell has a high threshold voltage, and it is possible to reduce the leak current between the source and the drain at the time of the off operation, so that the charge retention characteristics of the memory cell can be improved. When a plurality of n-wells are formed in this structure, all the n-wells have the same potential via the buried region. Therefore, the number of electrodes required for potential supply can be reduced, which is advantageous for miniaturization of elements. For example, when this structure is adopted in a DRAM device, a boosted circuit portion in an internal circuit, for example, a word line driver circuit, etc.
If the MOS structure is adopted and provided only in the second p-well 4, all of the plurality of n-wells need to have the same well potential, which is effective in this case.

【００２８】本発明の実施例１に示した半導体装置の製
造方法の１例を、工程断面図（図２）を用いて説明す
る。比抵抗が１０〜２０Ω程度のｐ型シリコン基板１上
に、基板１と同じ導電型を有する第１のｐウェル３を形
成するために、例えばフォトレジストマスク31を形成し
てＢイオン注入32を、例えば注入エネルギー４００Ｋｅ
Ｖ，注入ドーズ量２×１０¹³ｃｍ^-2で注入を行なう（工
程ａ）。次に、基板１と同じ導電型を有する第２のｐウ
ェル４を形成するために、基板１上第１のｐウェル３領
域外の所定の場所に、フォトレジストマスク41を形成し
てＢイオン42を例えば注入エネルギー４００ＫｅＶ，注
入ドーズ量３×１０¹³ｃｍ^-2で注入を行なう（工程
ｂ）。さらに基板１と反対の導電型を有する第３のｎウ
ェル５を形成するために、シリコン基板１上第１のｐウ
ェル３及び第２のｐウェル４領域外の所定の場所に、フ
ォトレジストマスク51を形成してＰイオン52を例えば注
入エネルギー７００ＫｅＶ，注入ドーズ量１×１０¹³ｃ
ｍ^-2で注入を行なう（工程ｃ）。One example of the method for manufacturing the semiconductor device shown in the first embodiment of the present invention will be described with reference to a process sectional view (FIG. 2). In order to form a first p-well 3 having the same conductivity type as the substrate 1 on a p-type silicon substrate 1 having a specific resistance of about 10 to 20 Ω, for example, a photoresist mask 31 is formed and B ion implantation 32 is performed. , For example, an injection energy of 400 Ke
V, implantation is performed at an implantation dose of 2 × 10 ¹³ cm ⁻² (step a). Next, in order to form a second p-well 4 having the same conductivity type as the substrate 1, a photoresist mask 41 is formed at a predetermined location on the substrate 1 outside the region of the first p-well 3 to form a B ion 42 is implanted, for example, at an implantation energy of 400 KeV and an implantation dose of 3 × 10 ¹³ cm ⁻² (step b). Further, in order to form a third n-well 5 having a conductivity type opposite to that of the substrate 1, a photoresist mask is formed on a predetermined position outside the region of the first p-well 3 and the second p-well 4 on the silicon substrate 1. 51 are formed and P ions 52 are implanted, for example, at an implantation energy of 700 KeV and an implantation dose of 1 × 10 ¹³ c.
Injection is performed at m ^-2 (step c).

【００２９】その後、基板１と反対の導電型を有するｎ
型ウォール領域６を形成するために、第１のｐウェル３
の周囲にフォトレジストマスク61を形成し２段階のＰイ
オン注入62を、例えば注入エネルギー１.２ＭｅＶ，注
入ドーズ量５×１０¹²ｃｍ^-2および注入エネルギー４０
０ＫｅＶ，注入ドーズ量３×１０¹²ｃｍ^-2で行なう（工
程ｄ）。さらに基板１と反対の導電型を有する埋め込み
領域２を形成するために、マスクを形成する事なく基板
１全面にＰイオン22を注入エネルギー２ＭｅＶ，注入ド
ーズ量１×１０¹³ｃｍ^-2でイオン注入を行なう。最後に
不純物活性化のための熱処理を例えば１０５０℃,２時
間行なうことにより、第１のｐウェル３が第２のｐウェ
ル４および基板１と電気的に絶縁されたウェル構造（図
１(a)）を形成する事が可能となる。ここで、埋め込み
領域２、第１のｐウェル３、第２のｐウェル４、第３の
ｎウェル５を形成するためのイオン注入の順序に制限は
ない。更に第２のｐウェル４の底部が、必ずしも埋め込
み領域２に接続される必要はない。Thereafter, n having the opposite conductivity type to the substrate 1 is used.
The first p-well 3 is formed to form the mold wall region 6.
A photoresist mask 61 is formed around the substrate and a two-stage P ion implantation 62 is performed, for example, with an implantation energy of 1.2 MeV, an implantation dose of 5 × 10 ¹² cm ⁻² and an implantation energy of 40
This is performed at 0 KeV and an implantation dose of 3 × 10 ¹² cm ⁻² (step d). Further, in order to form a buried region 2 having a conductivity type opposite to that of the substrate 1, P ions 22 are implanted into the entire surface of the substrate 1 at an implantation energy of 2 MeV and an implantation dose of 1 × 10 ¹³ cm ⁻² without forming a mask. Perform Finally, a heat treatment for activating the impurities is performed, for example, at 1050 ° C. for 2 hours, so that the first p-well 3 is electrically insulated from the second p-well 4 and the substrate 1 (FIG. 1A )) Can be formed. Here, there is no limitation on the order of ion implantation for forming the buried region 2, the first p-well 3, the second p-well 4, and the third n-well 5. Furthermore, the bottom of the second p-well 4 does not necessarily need to be connected to the buried region 2.

【００３０】本実施例によれば、ウォール領域６及び第
１のｐウェル３、第２のｐウェル４、第３のｎウェル５
はそれぞれ高温長時間の熱処理を用いることなく所望の
形状を形成することが可能であるため、不純物濃度勾配
が急峻となり、第１のｐウェル３端部からウォール領域
６を経て第２のｐウェル４端部に至る距離を縮小させる
ことが可能となる。同時に、埋め込み領域２はマスク形
成する事なく全面にイオン注入して形成されるので、マ
スク合わせ精度に依存する縮小限界に制限される事な
く、さらにマスク工程の増加や工程数の増加に伴う製造
コストの増加を防ぐことが可能となる。According to the present embodiment, the wall region 6, the first p-well 3, the second p-well 4, and the third n-well 5
Can form a desired shape without using a heat treatment for a long time at high temperature, the impurity concentration gradient becomes steep, and the second p-well is formed from the end of the first p-well 3 through the wall region 6. The distance to the four ends can be reduced. At the same time, since the buried region 2 is formed by ion implantation over the entire surface without forming a mask, the buried region 2 is not limited to a reduction limit depending on mask alignment accuracy, and is further manufactured with an increase in the number of mask steps and the number of steps. It is possible to prevent an increase in cost.

【００３１】（実施例２）本発明の実施例２として請求
項２に示した半導体装置の断面図である図１（ｂ）と、
不純物濃度分布図である図８を用いて説明する。図１
（ｂ）において、1は比抵抗が１０〜２０Ωｃｍ程度の
ｐ型シリコン基板、2は基板1と反対の導電型を有するｎ
型埋め込み領域、3は基板1と同じ導電型を有する第１の
ｐウェル、4は基板1と同じ導電型を有する第２のｐウェ
ル、5は基板1と反対の導電型を有する第３のｎウェル、
6は基板1と反対の導電型を有するｎ型ウォール領域であ
る。7は基板1と同じ導電型を有する補償領域、8は基板1
と同じ導電型を有する第４のウェルである。10は基板1
と反対の導電型を有する第５のｎウェルである。また図
８において、(a)〜(f)は埋め込み領域2、第１のｐウェ
ル3、第２,第４のｐウェル4,8、第３,第５のｎウェル5,
10、ウォール領域6、補償領域7の各々のドーピングされ
た不純物濃度分布を示している。また、破線Ｓは基準と
なる基板1中の初期不純物濃度を示している。(Embodiment 2) FIG. 1B is a sectional view of a semiconductor device according to a second embodiment of the present invention,
This will be described with reference to FIG. 8 which is an impurity concentration distribution diagram. FIG.
In (b), 1 is a p-type silicon substrate having a specific resistance of about 10 to 20 Ωcm, and 2 is an n-type semiconductor having a conductivity type opposite to that of the substrate 1.
A mold buried region, 3 is a first p-well having the same conductivity type as the substrate 1, 4 is a second p-well having the same conductivity type as the substrate 1, and 5 is a third p-well having the opposite conductivity type to the substrate 1. n-well,
Reference numeral 6 denotes an n-type wall region having a conductivity type opposite to that of the substrate 1. 7 is a compensation region having the same conductivity type as the substrate 1 and 8 is a substrate 1
This is a fourth well having the same conductivity type as that of FIG. 10 is substrate 1
And a fifth n-well having the opposite conductivity type. 8A to 8F, the buried region 2, the first p-well 3, the second and fourth p-wells 4, 8 and the third and fifth n-wells 5,
10 shows a doped impurity concentration distribution of each of the 10, the wall region 6, and the compensation region 7. A broken line S indicates an initial impurity concentration in the substrate 1 serving as a reference.

【００３２】埋め込み領域２は平面的には第２のｐウェ
ル4、第３のｎウェル5、第４のｐウェル8、第５のｎウ
ェル10を除く基板1全面に形成されており、その不純物
濃度分布は図８(a)に示すように、基板1表面（上面）か
らの接合面の深さＪ_Bは約１.５μｍである。ウォール領
域６は、平面的には第１のｐウェル３の周囲を取り囲
み、不純物濃度分布は図８(e)に示すように、ドーピン
グされた不純物が基板1表面まで到達し、底面の接合面
の深さＪ_Wは約２.０μｍであり、ウォール領域６は埋め
込み領域２上面に完全に接する構造となる。The buried region 2 is formed on the entire surface of the substrate 1 except for the second p-well 4, the third n-well 5, the fourth p-well 8, and the fifth n-well 10 in plan view. impurity concentration distribution as shown in FIG. 8 (a), the depth J _B of the bonding surface of the substrate 1 surface (upper surface) is about 1.5 [mu] m. The wall region 6 planarly surrounds the periphery of the first p-well 3, and the impurity concentration distribution is such that the doped impurity reaches the surface of the substrate 1 as shown in FIG. the depth J _W about 2.0 .mu.m, wall region 6 becomes a structure in contact with the completely buried region 2 top.

【００３３】第１ｐウェル３は、平面的には側面がウォ
ール領域６に囲まれる構造で、その不純物濃度分布は図
８(b)に示されるように、上面が基板１の表面に露呈
し、底面の接合面の深さＪ_PW1は約１.５μｍであり、底
面が埋め込み領域２上面に接する構造となる。さらに、
上面を除いてｎ型の領域に完全に囲まれている。第２,
第４のｐウェル4,8は、不純物濃度分布が図８(c)に示さ
れるように底面の接合面の深さＪ_PW2は約１.５μｍであ
り、上面が基板１の表面に露呈し、底面が補償領域７上
面に接続された構造となる。その結果、第２,第４のｐ
ウェル4,8の実質的な接合面の深さは図８(f)に示される
ように補償領域底面の接合深さＪ_CBであり約２.７μｍ
となる。The first p-well 3 has a structure in which the side surface is surrounded by the wall region 6 in plan view, and its impurity concentration distribution is such that the upper surface is exposed to the surface of the substrate 1 as shown in FIG. The depth J _PW1 of the bonding surface on the bottom surface is about 1.5 μm, and the bottom surface is in contact with the upper surface of the buried region 2. further,
Except for the top surface, it is completely surrounded by an n-type region. Second,
As shown in FIG. 8C, the fourth p-wells 4 and 8 have an impurity concentration distribution in which the depth J _PW2 of the bottom junction surface is about 1.5 μm and the upper surface is exposed to the surface of the substrate 1. , The bottom surface is connected to the top surface of the compensation region 7. As a result, the second and fourth p
The actual junction depth of the wells 4 and 8 is approximately 2.7 μm, which is the junction depth J _CB at the bottom of the compensation region as shown in FIG.
Becomes

【００３４】第３,第５のｎウェル５,10は、不純物濃度
分布が図８(d)に示されるように底面の接合面の深さＪ
_NW3は約１.５μｍであり、上面が基板1の表面に露呈
し、底面が補償領域７上面に接触した構造となる。その
結果、第３,第５のｎウェル５,10の実質的な接合面の深
さは図８(f)に示されるように補償領域上面の接合深さ
Ｊ_CT（約１.３μｍ）と第３,第５のｎウェル５,10底面
の接合深さＪ_NW3（約１.５μｍ）の間の深さとなる。補
償領域７は、埋め込み領域２にドーピングされたＰより
も高濃度のＢがドーピングされた領域で、平面的には上
記第２,第４のｐウェル4,8、第３,第５のｎウェル5,10
と重なる領域にのみ形成されている。本実施例に示した
構造によれば、第１のｐウェル３は上面が基板１表面に
露呈し、底面が埋め込み領域２上面に接し、側面がウォ
ール領域６に囲まれる構造で、上面を除いてｎ型の領域
に完全に囲まれるので、独立した電位を与えることがで
きる。第２のｐウェル４，第４のｐウェル８は、上面が
基板１の表面に露呈し、底面が補償領域７の上面に接し
ているので、電気的に同一電位を与えることができる。As shown in FIG. 8D, the third and fifth n-wells 5 and 10 have a depth J of the junction surface on the bottom surface as shown in FIG.
_NW3 is about 1.5 μm, and has a structure in which the upper surface is exposed on the surface of the substrate 1 and the bottom surface is in contact with the upper surface of the compensation region 7. As a result, the substantial junction depth of the third and fifth n-wells 5 and 10 is equal to the junction depth J _CT (about 1.3 μm) on the upper surface of the compensation region as shown in FIG. The third and fifth n-wells 5 and 10 have a depth between the junction depths J _NW3 (about 1.5 μm). The compensation region 7 is a region in which B is doped at a higher concentration than P doped in the buried region 2, and the second and fourth p wells 4 and 8 and the third and fifth n wells are planarly viewed. Well 5,10
Is formed only in the region overlapping with According to the structure shown in the present embodiment, the first p-well 3 has a structure in which the upper surface is exposed to the surface of the substrate 1, the bottom surface is in contact with the upper surface of the buried region 2, and the side surface is surrounded by the wall region 6. As a result, the semiconductor device is completely surrounded by the n-type region, so that an independent potential can be given. Since the second p-well 4 and the fourth p-well 8 have their upper surfaces exposed to the surface of the substrate 1 and their bottom surfaces in contact with the upper surface of the compensation region 7, they can be given the same electrical potential.

【００３５】本実施例に示した構造によれば、第１のｐ
ウェル３のみを電気的に独立させる必要があり、第２の
ｐウェル４、第４のｐウェル８を同電位に固定する必要
がある場合有効であ。さらに、第２のｐウェル4、第４
のｐウェル8の電位を固定させるために基板１裏面に電
極を設け第２のｐウェル4、第４のｐウェル8の電位を取
る場合に有効となる。また第３,第５のｎウェル５,10は
ウォール領域６と電気的に分離させたい場合有効であ
る。According to the structure shown in this embodiment, the first p
This is effective when only the well 3 needs to be electrically independent and the second p-well 4 and the fourth p-well 8 need to be fixed at the same potential. Further, the second p-well 4 and the fourth
This is effective when an electrode is provided on the back surface of the substrate 1 in order to fix the potential of the p-well 8, and the potentials of the second p-well 4 and the fourth p-well 8 are taken. The third and fifth n-wells 5 and 10 are effective when it is desired to electrically separate them from the wall region 6.

【００３６】本構造においても本発明の実施例１の場合
と同様、ＤＡＲＭデバイスのソフトエラー、電荷保持特
性の向上に有効となる。さらに本構造を採用した場合、
ＤＲＡＭのメモリーセル部以外の領域のトランジスタ、
例えば第２のｐウェル4，第４のｐウェル8は基板1裏面
からも電位の固定が可能となり、コンタクト領域の縮小
に伴い素子の微細化に有効となる。さらに、第３,第５
のｎウェル５,10内に形成されたトランジスタは、素子
の微細化に伴いウェル電位をウォール領域６とは異なる
値（例えば、ウォール領域６を＋５Ｖ,第３,第５のｎウ
ェル５,10を＋3.3Ｖ）に固定する事でトランジスタのオ
ン動作時のドレイン電流を増加させることが可能とな
り、速度性能が向上する等、設計上の自由度が大きくな
るという利点を有している。さらに、ＤＲＡＭにおいて
は、内部回路において昇圧されている回路部分、例えば
ワード線ドライバー回路等においてＣＭＯＳ構造を採用
して周辺回路部に設ける場合は、複数のｎウェル間（例
えば、第３のｎウェルと第５のｎウェルとの間）におい
てそれぞれ異なるウェル電位を与える必要があり、この
場合は本実施例の構造において可能となる。This structure is also effective in improving the soft error and charge retention characteristics of the DARM device, as in the first embodiment of the present invention. If this structure is adopted,
Transistors in regions other than the memory cell portion of the DRAM,
For example, the potential of the second p-well 4 and the fourth p-well 8 can be fixed from the back surface of the substrate 1, which is effective for miniaturization of the element as the contact area is reduced. Furthermore, the third and fifth
The transistors formed in the n-wells 5 and 10 have a well potential different from that of the wall region 6 (for example, the wall region 6 is set to +5 V, the third and fifth n-wells 5 and 10 Is fixed at +3.3 V), it is possible to increase the drain current at the time of the ON operation of the transistor, and there is an advantage that the degree of freedom in design is increased, for example, the speed performance is improved. Further, in the case of a DRAM, when a CMOS circuit is employed in a circuit portion boosted in an internal circuit such as a word line driver circuit and provided in a peripheral circuit portion, a plurality of n wells (for example, a third n well) are provided. And the fifth n-well), it is necessary to apply different well potentials, and this case is possible in the structure of this embodiment.

【００３７】本発明の実施例２における半導体装置の製
造方法の１例を工程断面図（図３）を用いて説明する。
比抵抗が１０〜２０Ωｃｍ程度のｐ型シリコン基板１上
に、基板１と同じ導電型を有する第１のｐウェル３を形
成するために、フォトレジストマスク31を形成したＢイ
オン32を例えば注入エネルギー４００ＫｅＶ，注入ドー
ズ量２×１０¹³ｃｍ^-2で注入を行なう（工程ａ）。さら
に基板１と同じ導電型を有する第２のｐウェル4及び第
４のｐウェル8を形成するために、基板１上の第１のｐ
ウェル３領域外の所定の場所に、フォトレジストマスク
41を形成してＢイオン42を、例えば注入エネルギー４０
０ＫｅＶ，注入ドーズ量３×１０¹³ｃｍ^-2で注入を行な
う（工程ｂ）。引続き基板１と同じ導電型を有する補償
領域７を形成するために、フォトレジストマスク41を用
いて第２のｐウェル4,第４のｐウェル8と自己整合的
に、第２のｐウェル4，第４のｐウェル8下部にＢイオン
72を注入エネルギー１.３ＭｅＶ，注入ドーズ量３×１
０¹³ｃｍ^-2で注入を行う（工程ｃ）。An example of a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to a process sectional view (FIG. 3).
In order to form a first p-well 3 having the same conductivity type as the substrate 1 on a p-type silicon substrate 1 having a specific resistance of about 10 to 20 Ωcm, B ions 32 having a photoresist mask 31 formed thereon are implanted with, for example, an implantation energy. Implantation is performed at 400 KeV and an implantation dose of 2 × 10 ¹³ cm ⁻² (step a). Further, to form a second p-well 4 and a fourth p-well 8 having the same conductivity type as the substrate 1, the first p-well 4 on the substrate 1 is formed.
A photoresist mask is formed at a predetermined place outside the well 3 region.
41 to form B ions 42, for example, at an implantation energy 40
Implantation is performed at 0 KeV and an implantation dose of 3 × 10 ¹³ cm ⁻² (step b). Subsequently, in order to form the compensation region 7 having the same conductivity type as the substrate 1, the second p-well 4 and the fourth p-well 8 are self-aligned with the second p-well 4 using a photoresist mask 41. , B ion below the fourth p-well 8
72 at an implantation energy of 1.3 MeV and an implantation dose of 3 × 1
Implantation is performed at 0 ¹³ cm ^-2 (step c).

【００３８】さらに、基板１と反対の導電型を有する第
３,第５のｎウェル５,10を形成するために、基板１上の
第１のｐウェル3，第２のｐウェル4及び第４のｐウェル
8領域外の所定の場所に、フォトレジストマスク51を形
成して、Ｐイオン52を例えば注入エネルギー７００Ｋｅ
Ｖ，注入ドーズ量１×１０¹³ｃｍ^-2で注入を行なう（工
程ｄ）。引続き基板１と同じ導電型を有する補償領域７
を形成するために、フォトレジストマスク51を用いて第
３,第５のｎウェル５,10と自己整合的に、第３,第５の
ｎウェル５,10下部にＢイオン72を、例えば注入エネル
ギー１.３ＭｅＶ，注入ドーズ量３×１０¹³ｃｍ^-2でイ
オン注入を行う（工程ｅ）。Further, in order to form third and fifth n-wells 5 and 10 having a conductivity type opposite to that of the substrate 1, a first p-well 3, a second p-well 4 and a 4 p-wells
A photoresist mask 51 is formed at a predetermined location outside the region 8, and P ions 52 are implanted at an implantation energy of, for example, 700 Ke.
V, implantation is performed at an implantation dose of 1 × 10 ¹³ cm ⁻² (step d). Subsequently, a compensation region 7 having the same conductivity type as the substrate 1
B ions 72 are implanted below the third and fifth n-wells 5 and 10 in a self-aligned manner with the third and fifth n-wells 5 and 10 using a photoresist mask 51, for example. Ion implantation is performed at an energy of 1.3 MeV and an implantation dose of 3 × 10 ¹³ cm ⁻² (step e).

【００３９】その後、基板１と反対の導電型を有するウ
ォール領域６を形成するために、第１のｐウェル３周辺
を取り囲むようにフォトレジストマスク61を形成し、２
段階のＰイオン注入62 を、例えば注入エネルギー１.２
ＭｅＶ，注入ドーズ量５×１０¹²ｃｍ^-2および注入エネ
ルギー４００ＫｅＶ，注入ドーズ量３×１０¹²ｃｍ^-2で
行なう（工程ｆ）。さらに、基板１と反対の導電型を有
する埋め込み領域２を形成するために、マスクを形成す
る事なく基板１全面に、第２, 第４のｐウェル4，8下部
及び第３,第５のｎウェル5,10 下部の補償領域7と同じ
深さになるように、例えばＰイオン22を注入エネルギー
２ＭｅＶ，注入ドーズ量１×１０¹³ｃｍ ^-2 で注入を行
なう（工程ｇ）。最後に不純物活性化のための熱処理を
１０５０℃，２時間行なうことにより、図１（ｂ）に示
した、第１のｐウェル3 が、第２のｐウェル4、第４の
ｐウェル8及び基板1 と電気的に絶縁されたウェル構造
を形成する事が可能となる。また、第３,第５のｎウェ
ル５,10が、埋め込み領域２及びウォール領域６と電気
的に絶縁されたウェル構造を形成する事が可能となる。
ここで、埋め込み領域2、第１のｐウェル3、第２のｐウ
ェル4、第３のｎウェル5、第４のｐウェル8 、第５のｎ
ウェル10を形成するためのイオン注入の順序に制限はな
い。Thereafter, a c-type substrate having a conductivity type opposite to that of the substrate 1 is formed.
Around the first p-well 3 to form the
A photoresist mask 61 is formed so as to surround
Step P ion implantation 62 is performed, for example, with an implantation energy of 1.2.
MeV, implantation dose 5 × 10¹²cm^-2And injection energy
Lugie 400 KeV, implantation dose 3 × 10¹²cm^-2so
(Step f). Furthermore, a conductive type opposite to that of the substrate 1 is provided.
A mask is formed to form the buried region 2 to be formed.
2nd and 4th p-wells 4 and 8 below
And the same as the compensation region 7 below the third and fifth n-wells 5,10
For example, implant energy of P ions 22 so that the depth becomes
2 MeV, implantation dose 1 × 10¹³cm ^-2 Line with injection
Now (step g). Finally, heat treatment to activate impurities
By conducting the test at 1050 ° C. for 2 hours, as shown in FIG.
Then, the first p well 3 is connected to the second p well 4 and the fourth p well 4.
Well structure electrically insulated from p-well 8 and substrate 1
Can be formed. In addition, the third and fifth n-way
Are connected to the buried area 2 and the wall area 6
It is possible to form a well structure that is electrically insulated.
Here, the buried region 2, the first p-well 3, the second p-well
Well 4, third n-well 5, fourth p-well 8, fifth n-well
There is no restriction on the order of ion implantation for forming the well 10.
No.

【００４０】本実施例により形成されたウェル構造によ
れば、ウォール領域6、第１のｐウェル3、第２,第４の
ｐウェル4,8、第３,第５のｎウェル5,10はそれぞれ高温
長時間の熱処理を用いることなく所望の形状を形成する
ことが可能であるため、不純物濃度勾配が急峻となり、
第１のｐウェル３端部からウォール領域６を経て第２の
ｐウェル４端部に至る距離を縮小させることが可能とな
る。さらに、埋め込み領域２をマスク形成する事なく全
面にイオン注入し、形成することでマスク合わせ精度に
依存する縮小限界に制限される事なく、さらにマスク工
程の増加や工程数の増加に伴う製造コストの増加を防ぐ
ことが可能となる。また、第２のｐウェル4，第４のｐ
ウェル8はウェル下部にｐ型補償領域７を有するため、
基板１裏面からウェル電位を固定すること、ならびに第
２のｐウェル4と第４のｐウェル8間の電気的接続を得る
ことが可能となる。一方、第３,第５のｎウェル5,１０
は下部にｐ型補償領域7を有するため、第３,第５のｎウ
ェル5,10と埋め込み領域2及びウォール領域6との電気的
絶縁が可能となる。According to the well structure formed in this embodiment, the wall region 6, the first p-well 3, the second and fourth p-wells 4, 8 and the third and fifth n-wells 5, 10 Can form a desired shape without using high-temperature and long-time heat treatment, so that the impurity concentration gradient becomes steep,
The distance from the end of the first p-well 3 to the end of the second p-well 4 via the wall region 6 can be reduced. Further, the ion implantation is performed on the entire surface without forming a mask in the buried region 2 to form the buried region 2 without being limited to a reduction limit depending on mask alignment accuracy. Can be prevented from increasing. Also, the second p well 4 and the fourth p well
Since the well 8 has the p-type compensation region 7 below the well,
It is possible to fix the well potential from the back surface of the substrate 1 and to obtain an electrical connection between the second p-well 4 and the fourth p-well 8. On the other hand, the third and fifth n-wells 5, 10
Has a p-type compensation region 7 below, so that the third and fifth n-wells 5 and 10 can be electrically insulated from the buried region 2 and the wall region 6.

【００４１】（実施例３）本発明の実施例３として請求
項３に示した半導体装置の断面図である図１（ｃ）と、
不純物濃度分布図である図９を用いて説明する。図１
（ｃ）において、1は比抵抗が１０〜２０Ωｃｍ程度の
ｐ型シリコン基板、2は基板1と反対の導電型を有するｎ
型埋め込み領域、3は基板1と同じ導電型を有する第１の
ｐウェル、4は基板1と同じ導電型を有する第２のｐウェ
ル、5は基板1と反対の導電型を有する第３のｎウェル、
6は基板1と反対の導電型を有するｎ型ウォール領域であ
る。8は基板1と同じ導電型を有する第４のウェルであ
る。10は基板1と反対の導電型を有する第５のｎウェル
である。また図９において、(a)〜(e)は埋め込み領域
2、第１のｐウェル3、第２,第４のｐウェル4,8、第３,
第５のｎウェル5,10、ウォール領域6各々の不純物濃度
分布を示している。また、破線Ｓは基準となる基板1中
の初期不純物濃度を示している。(Embodiment 3) FIG. 1 (c) is a sectional view of a semiconductor device according to a third embodiment of the present invention,
This will be described with reference to FIG. 9 which is an impurity concentration distribution diagram. FIG.
In (c), 1 is a p-type silicon substrate having a specific resistance of about 10 to 20 Ωcm, and 2 is an n-type semiconductor having an opposite conductivity type to the substrate 1.
A mold buried region, 3 is a first p-well having the same conductivity type as the substrate 1, 4 is a second p-well having the same conductivity type as the substrate 1, and 5 is a third p-well having the opposite conductivity type to the substrate 1. n-well,
Reference numeral 6 denotes an n-type wall region having a conductivity type opposite to that of the substrate 1. Reference numeral 8 denotes a fourth well having the same conductivity type as the substrate 1. Reference numeral 10 denotes a fifth n-well having a conductivity type opposite to that of the substrate 1. In FIG. 9, (a) to (e) denote embedded regions.
2, the first p-well 3, the second and fourth p-wells 4, 8, the third,
The impurity concentration distribution of each of the fifth n-wells 5 and 10 and the wall region 6 is shown. A broken line S indicates an initial impurity concentration in the substrate 1 serving as a reference.

【００４２】埋め込み領域２は平面的には基板１全面に
形成されており、その不純物濃度分布は図９(a)に示す
ように、基板1表面（上面）からの接合面の深さＪ_Bは約
２μｍである。ウォール領域６は、平面的には第１のｐ
ウェル３の周囲を取り囲み、不純物濃度分布は図９(e)
に示すように、上面は基板１表面までドーピングされた
不純物が到達し、底面の接合面の深さＪ_Wは約２.７μｍ
であり、ウォール領域６は埋め込み領域２上面に完全に
接する構造となる。第１のｐウェル３は、平面的には側
面がウォール領域６に囲まれる構造で、その不純物濃度
分布は図９(b)に示されるように、上面が基板１の表面
に露呈し、底面が埋め込み領域２上部に位置し、底面の
接合面の深さＪ_PW1は約１.５μｍである。一方、埋め込
み領域２の接合面の深さＪ_Bは前述したように約２μｍ
となり実質的に第１のｐウェル３の接合面の深さは約２
μｍである。また、第１のｐウェル３は上面を除いてｎ
型の領域に完全に囲まれている。The buried region 2 is formed over the entire surface of the substrate 1 in plan view, and its impurity concentration distribution is, as shown in FIG. 9A, the depth J _B of the bonding surface from the surface (upper surface) of the substrate 1. Is about 2 μm. The wall region 6 has a first p
Surrounding the periphery of the well 3, the impurity concentration distribution is shown in FIG.
As shown in the figure, the doped impurity reaches the upper surface of the substrate 1 and the depth _JW of the bonding surface on the bottom surface is about 2.7 μm.
Thus, the wall region 6 has a structure completely in contact with the upper surface of the buried region 2. The first p-well 3 has a structure in which the side surface is surrounded by a wall region 6 in plan view, and its impurity concentration distribution is such that the upper surface is exposed to the surface of the substrate 1 and the bottom surface is as shown in FIG. Are located above the buried region 2, and the depth J _PW1 of the bonding surface on the bottom surface is about 1.5 μm. On the other hand, the depth J _B of the bonding surface of the buried region 2 is about 2 μm as described above.
And the depth of the junction surface of the first p-well 3 is substantially 2
μm. The first p-well 3 has n
It is completely surrounded by the type area.

【００４３】第２，第４のｐウェル4,8は、上面が基板
１の表面に露呈し、底面が埋め込み領域２上部に位置す
る構造である。その不純物濃度分布は図９(c)に示され
るように、上面が基板１の表面に露呈し、底面が埋め込
み領域２上部に埋め込み領域２に接触しないように位置
し、底面の接合面の深さＪ_PW2は約１.５μｍである。基
板１及び第１のｐウェル３とは電気的に絶縁可能な構造
である。しかし、必ずしも周囲を完全にｎ型領域で囲ま
れることはないので電位を独立して設定できない場合も
ある。第３,第５のｎウェル５,10は、上面が基板１の表
面に露呈し、底面が埋め込み領域２上面に位置する構造
である。その不純物濃度分布は図９(d)に示されるよう
に、上面が基板１の表面に露呈し、底面が埋め込み領域
２上部に埋め込み領域２に接触しないように位置し、底
面の接合面の深さＪ_NW3は約１.５μｍである。埋め込み
領域２とは電気的に絶縁可能な構造である。The second and fourth p-wells 4 and 8 have a structure in which the upper surface is exposed on the surface of the substrate 1 and the lower surface is located above the buried region 2. As shown in FIG. 9C, the impurity concentration distribution is such that the upper surface is exposed on the surface of the substrate 1 and the bottom surface is located above the buried region 2 so as not to contact the buried region 2. J _PW2 is about 1.5 μm. The substrate 1 and the first p-well 3 have a structure that can be electrically insulated. However, since the periphery is not always completely surrounded by the n-type region, the potential may not be set independently. The third and fifth n-wells 5 and 10 have a structure in which the upper surface is exposed on the surface of the substrate 1 and the bottom surface is located on the upper surface of the buried region 2. As shown in FIG. 9D, the impurity concentration distribution is such that the upper surface is exposed on the surface of the substrate 1 and the bottom surface is located above the buried region 2 so as not to contact the buried region 2. J _NW3 is about 1.5 μm. The buried region 2 has a structure that can be electrically insulated.

【００４４】本実施例に示した構造によれば、第１のｐ
ウェル３のみを電気的に独立させる必要があり、第２の
ｐウェル4及び第４のｐウェル8は相互に電気的な接続が
必要な場合、また第３,第５のｎウェル５,10はウォール
領域６と電気的に分離させたい場合有効である。According to the structure shown in this embodiment, the first p
Only the well 3 needs to be electrically independent, the second p-well 4 and the fourth p-well 8 need to be electrically connected to each other, and the third and fifth n-wells 5, 10 Is effective when it is desired to electrically separate from the wall region 6.

【００４５】本構造においても本発明の実施例１,２の
場合と同様ＤＲＡＭデバイスにおけるソフトエラー、電
荷保持特性の向上に有効となる。さらに、本構造におい
ては本発明の実施例２の場合と同様、第３,第５のｎウ
ェル５,10のウェル電位をウォール領域とは異なる値に
固定する事が可能となる。また複数のｎウェル間（例え
ば、第３のｎウェルと第５のｎウェルとの間）において
それぞれ異なるウェル電位を与えることが可能となる
等、本実施例の構造において有効である。This structure is also effective in improving the soft error and charge retention characteristics of the DRAM device as in the first and second embodiments of the present invention. Further, in this structure, similarly to the second embodiment of the present invention, the well potentials of the third and fifth n-wells 5 and 10 can be fixed to values different from those of the wall region. Further, it is effective in the structure of the present embodiment such that different well potentials can be given between a plurality of n-wells (for example, between a third n-well and a fifth n-well).

【００４６】本発明の実施例３における半導体装置の製
造方法の１例を、工程断面図である図４を用いて説明す
る。比抵抗が１０〜２０Ω程度のｐ型シリコン基板１上
に基板１と同じ導電型を有する第１のｐウェル３を形成
するために、例えばフォトレジストマスク31を形成して
Ｂイオン注入32を例えば注入エネルギー４００ＫｅＶ，
注入ドーズ量２×１０¹³ｃｍ^-2で注入を行なう（工程
ａ）。次に、基板１と同じ導電型を有する第２のｐウェ
ル4及び第４のｐウェル8を形成するために、基板１上第
１のｐウェル３領域外の所定の場所に、フォトレジスト
マスク41を形成してＢイオン42を例えば注入エネルギー
４００ＫｅＶ，注入ドーズ量３×１０¹³ｃｍ^-2で注入を
行なう（工程ｂ）。さらに基板１と反対の導電型を有す
る第３,第５のｎウェル５,10を形成するために、シリコ
ン基板１上の第１のｐウェル3及び第２のｐウェル4領域
外の所定の場所に、フォトレジストマスク51を形成し、
Ｐイオン52を例えば注入エネルギー７００ＫｅＶ，注入
ドーズ量１×１０¹³ｃｍ^-2で注入を行なう（工程ｃ）。An example of a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. In order to form a first p-well 3 having the same conductivity type as the substrate 1 on a p-type silicon substrate 1 having a specific resistance of about 10 to 20 Ω, for example, a photoresist mask 31 is formed and B ion implantation 32 is performed, for example. 400 KeV implantation energy,
An implantation is performed at an implantation dose of 2 × 10 ¹³ cm ⁻² (step a). Next, in order to form a second p-well 4 and a fourth p-well 8 having the same conductivity type as the substrate 1, a photoresist mask is formed on a predetermined position outside the region of the first p-well 3 on the substrate 1. 41 are formed and B ions 42 are implanted at an implantation energy of 400 KeV and an implantation dose of 3 × 10 ¹³ cm ⁻² (step b). Further, in order to form third and fifth n-wells 5 and 10 having a conductivity type opposite to that of the substrate 1, predetermined outside of the first p-well 3 and the second p-well 4 on the silicon substrate 1 In a location, a photoresist mask 51 is formed,
P ions 52 are implanted, for example, at an implantation energy of 700 KeV and an implantation dose of 1 × 10 ¹³ cm ⁻² (step c).

【００４７】その後、基板１と反対の導電型を有するｎ
型ウォール領域６を形成するために、第１のｐウェル３
の周囲にフォトレジストマスク61を形成し３段階のＰイ
オン62を、例えば注入エネルギー２ＭｅＶ，注入ドーズ
量５×１０¹²ｃｍ^-2；注入エネルギー１．２ＭｅＶ，注
入ドーズ量５×１０¹²ｃｍ^-2および注入エネルギー４０
０ＫｅＶ，注入ドーズ量３×１０¹²ｃｍ^-2でイオン注入
を行なう（工程ｄ）。Thereafter, n having the opposite conductivity type to the substrate 1 is used.
The first p-well 3 is formed to form the mold wall region 6.
A photoresist mask 61 is formed around the substrate and P ions 62 in three stages are implanted, for example, at an implantation energy of 2 MeV and an implantation dose of 5 × 10 ¹² cm ⁻² ; an implantation energy of 1.2 MeV, and an implantation dose of 5 × 10 ¹² cm ^−2. And injection energy 40
Ion implantation is performed at 0 KeV and an implantation dose of 3 × 10 ¹² cm ⁻² (step d).

【００４８】さらに基板１と反対の導電型を有する埋め
込み領域２を形成するために、マスクを形成する事なく
基板1全面にＰイオン22を注入エネルギー２.７ＭｅＶ，
注入ドーズ量１×１０¹³ｃｍ^-2でイオン注入を行なう
（工程ｅ）。最後に不純物活性化のための熱処理を、例
えば１０５０℃，２時間行なうことにより、図１（ｃ）
に示した、第１のｐウェル３が、第２のｐウェル4、第
４のｐウェル8及び基板1と電気的に絶縁されたウェル構
造を形成する事が可能となる。また、第３,第５のｎウ
ェル５,10が、埋め込み領域2及びウォール領域6と電気
的に絶縁されたウェル構造を形成する事が可能となる。
ここで、埋め込み領域2、第１のｐウェル3、第２,第４
のｐウェル4,8、第３,第５のｎウェル5,10を形成するた
めのイオン注入の順序に制限はない。Further, in order to form a buried region 2 having a conductivity type opposite to that of the substrate 1, P ions 22 are implanted over the entire surface of the substrate 1 without forming a mask, at an energy of 2.7 MeV,
Ion implantation is performed at an implantation dose of 1 × 10 ¹³ cm ⁻² (step e). Finally, a heat treatment for activating the impurities is performed, for example, at 1050 ° C. for 2 hours, so that the structure shown in FIG.
1 can form a well structure in which the first p-well 3 is electrically insulated from the second p-well 4, the fourth p-well 8, and the substrate 1. In addition, the third and fifth n-wells 5 and 10 can form a well structure that is electrically insulated from the buried region 2 and the wall region 6.
Here, the buried region 2, the first p-well 3, the second and fourth
The order of ion implantation for forming the p wells 4 and 8 and the third and fifth n wells 5 and 10 is not limited.

【００４９】本実施例によれば、ウォール領域6、第１
のｐウェル3、第２,第４のｐウェル4,8、第３,第５のｎ
ウェル5,10はそれぞれ高温長時間の熱処理を用いること
なく所望の形状を形成することが可能であるため、不純
物濃度勾配が急峻となり、第１のｐウェル3端部からウ
ォール領域6を経て第２のｐウェル4端部に至る距離を縮
小させることが可能となる。同時に、埋め込み領域２は
マスク形成する事なく全面にイオン注入して形成される
ので、マスク合わせ精度に依存する縮小限界に制限され
る事なく、さらにマスク工程の増加や工程数の増加に伴
う製造コストの増加を防ぐことが可能となる。また、第
２のｐウェル4，第４のｐウェル8はウェル下端の接合深
さが埋め込み領域２の上面の接合深さよりも浅いため相
互に電気的接続を得る事が可能となる。一方、第３,第
５のｎウェル５,10はウェル下端の接合深さが埋め込み
領域２上面の接合深さよりも浅いため、第３,第５のｎ
ウェル５,10と埋め込み領域2及びウォール領域6との電
気的絶縁が可能となる。更に第２〜第５ウェル形成のた
めのイオン注入条件を、埋め込み領域２と接続されない
ように設定することにより、第２の実施例で必要とする
補償領域７を形成する必要がなくなる。According to the present embodiment, the wall region 6, the first region
P well 3, second and fourth p wells 4, 8 and third and fifth n wells
Since the wells 5 and 10 can each have a desired shape without using a high-temperature and long-time heat treatment, the impurity concentration gradient becomes steep, and the wells 5 and 10 pass through the wall region 6 from the end of the first p-well 3 and pass through the wall region 6. It is possible to reduce the distance to the end of the second p-well 4. At the same time, since the buried region 2 is formed by ion implantation over the entire surface without forming a mask, the buried region 2 is not limited to a reduction limit depending on mask alignment accuracy, and is further manufactured with an increase in the number of mask steps and the number of steps. It is possible to prevent an increase in cost. Further, since the junction depth of the second p-well 4 and the fourth p-well 8 is shallower than the junction depth of the upper surface of the buried region 2, electrical connection can be obtained. On the other hand, in the third and fifth n-wells 5 and 10, since the junction depth at the lower end of the well is smaller than the junction depth at the upper surface of the buried region 2, the third and fifth n-wells 5 and 10 are formed.
The wells 5 and 10 can be electrically insulated from the buried region 2 and the wall region 6. Further, by setting the ion implantation conditions for forming the second to fifth wells so as not to be connected to the buried region 2, it is not necessary to form the compensation region 7 required in the second embodiment.

【００５０】なお、実施例１〜３においてはｐ型シリコ
ン基板を用い説明したが、ｎ型シリコン基板を用い、埋
め込み領域及びウォール領域をｐ型とし、ｎウェルを電
気的に絶縁しても同様の効果が得られる。Although Embodiments 1 to 3 have been described using a p-type silicon substrate, the same applies when an n-type silicon substrate is used, the buried region and the wall region are p-type, and the n-well is electrically insulated. The effect of is obtained.

【００５１】また、実施例１〜３においてはウェル形成
のイオン注入に高エネルギー領域でのイオン注入を用い
たが、第１のｐウェル端部からウォール領域を経て第２
のｐウェル端部の間の不純物濃度勾配が急峻であれば、
第１のｐウェル端部からウォール領域を経て第２のｐウ
ェル端部の間の距離は小さくすることが可能である。従
って、第１のｐウェル，第２,第４のｐウェル，第３,第
５のｎウェルは熱処理による拡散を用い領域形成を行な
い、しかる後ウォール領域を形成し、ウォール領域の形
成後の熱処理時間を短くもしくは熱処理温度を低くする
ことで、ウォール領域の横方向不純物濃度勾配が急峻に
なるようにすれば、第１のｐウェル端部からウォール領
域を経て第２のｐウェル端部の間の距離は小さくするこ
とが可能となる。In the first to third embodiments, the ion implantation in the high energy region is used for the ion implantation for forming the well. However, the ion implantation is performed from the end of the first p well to the second through the wall region.
If the impurity concentration gradient between the ends of the p-well is steep,
The distance between the end of the first p-well and the end of the second p-well through the wall region can be reduced. Therefore, the first p-well, the second and fourth p-wells, and the third and fifth n-wells are formed using diffusion by heat treatment, and then a wall region is formed. If the lateral impurity concentration gradient in the wall region is made steeper by shortening the heat treatment time or lowering the heat treatment temperature, the end of the second p well from the end of the first p well through the wall region is formed. The distance between them can be reduced.

【００５２】さらに、実施例１〜３においてはウォール
領域を第１のｐウェルの電気的分離用としてのみ用いた
が、ウォール領域内にトランジスターなどのデバイスを
作製し、ウォール領域をｎ型ウェルとして用いることも
可能である。Further, in the first to third embodiments, the wall region is used only for electrical isolation of the first p-well. However, a device such as a transistor is formed in the wall region, and the wall region is formed as an n-type well. It is also possible to use.

【００５３】[0053]

【発明の効果】以上のように、本発明は半導体基板全面
に基板不純物濃度より高い基板と反対の導電型の埋め込
み領域を有し、基板と同じ導電型を有する第１のウェル
周辺を基板と反対の導電型を有するウォール領域が側面
を取り囲みかつ埋め込み領域が底面でウォール領域と接
続されているので、基板と同じ導電型を有する第２のウ
ェル及び基板と反対の導電型を有する第３のウェルを埋
め込み領域より浅い位置に形成することで、第１のウェ
ルと第２のウェル間が電気的に絶縁され、かつ第１のウ
ェル周辺を囲うようにマスクを用い基板と反対の導電型
を有するウォール領域を形成することで、不純物濃度勾
配が急峻で、第１のウェル端部からウォール領域を経て
第２のウェル端部に至る距離を小さくすることが可能と
なる。さらに、埋め込み領域を半導体基板全面にマスク
工程を経る事なく形成する事で、工程数を増加する事な
く電気的に絶縁されたウェルの形成が可能となる。その
結果、ＤＲＡＭデバイスにおけるソフトエラー、電荷保
持特性の向上に有効となる。As described above, the present invention has a buried region of a conductivity type opposite to that of a substrate having a higher impurity concentration on the entire surface of a semiconductor substrate, and the periphery of a first well having the same conductivity type as the substrate is formed as a substrate. A second well having the same conductivity type as the substrate and a third well having the opposite conductivity type as the wall region having the opposite conductivity type surrounds the side surface and the buried region is connected to the wall region at the bottom surface. By forming the well at a position shallower than the buried region, the first well and the second well are electrically insulated from each other, and a conductive type opposite to the substrate is formed using a mask so as to surround the periphery of the first well. By forming the wall region, the impurity concentration gradient is steep, and the distance from the end of the first well to the end of the second well via the wall region can be reduced. Furthermore, by forming the buried region on the entire surface of the semiconductor substrate without going through a masking step, it is possible to form an electrically insulated well without increasing the number of steps. As a result, it is effective in improving the soft error and charge retention characteristics of the DRAM device.

【００５４】また、基板と同じ導電型を有する第２,第
４のウェルおよび基板と反対の導電型を有する第３,第
５のウェル底部の埋め込み領域と同じ深さに、埋め込み
領域より高い不純物濃度で自己整合的に基板と同じ導電
型の不純物層を形成することで、第２のウェル及び第４
のウェルと基板との電気的接続を得ることが可能とな
り、基板裏面よりの電気的接続が可能となる。また第
３,第５のウェルと、第１のウェル周辺を囲む基板と反
対の導電型を有するウォール領域及び半導体基板全面に
形成された基板と反対の導電型を有する埋め込み領域と
の電気的絶縁が可能となる。その結果、ＤＲＡＭデバイ
スにおいて、複数のｎウェル間においてそれぞれ異なる
ウェル電位を与えることが可能となる。Further, the second and fourth wells having the same conductivity type as the substrate and the third and fifth wells having the opposite conductivity type to the substrate have the same impurity as the buried region at the bottom of the buried region. By forming an impurity layer of the same conductivity type as that of the substrate in a self-aligning manner with the concentration, the second well and the fourth well are formed.
Electrical connection between the well and the substrate can be obtained, and electrical connection from the back surface of the substrate becomes possible. Electrical insulation between the third and fifth wells and a wall region having the opposite conductivity type to the substrate surrounding the periphery of the first well and a buried region having the opposite conductivity type to the substrate formed on the entire surface of the semiconductor substrate. Becomes possible. As a result, in the DRAM device, different well potentials can be respectively applied to the plurality of n-wells.

【００５５】また、基板と同じ導電型を有する第２,第
４のウェル及び基板と反対の導電型を有する第３,第５
のウェルと埋め込み領域との間に距離を設けることで、
第２のウェルと第４のウェル間の電気的接続、第３のウ
ェルと、ウォール領域及び半導体基板全面に形成された
基板と反対の導電型を有する埋め込み領域との電気的絶
縁が可能となり、例えば、埋め込み領域と第３のウェル
に独立した電位を取ることが可能となりその実用的効果
は大きい。The second and fourth wells having the same conductivity type as the substrate and the third and fifth wells having the conductivity type opposite to the substrate are provided.
By providing a distance between the well and the buried region,
Electrical connection between the second well and the fourth well, and electrical insulation between the third well and the buried region having the opposite conductivity type to the substrate formed on the wall region and the entire surface of the semiconductor substrate, For example, it is possible to take independent potentials for the buried region and the third well, and the practical effect is large.

【図面の簡単な説明】[Brief description of the drawings]

【図１】(a)は本発明１における半導体装置の構造の断
面図 (b)は本発明２における半導体装置の構造の断面図 (c)は本発明３における半導体装置の構造の断面図1A is a cross-sectional view of a structure of a semiconductor device according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view of a structure of a semiconductor device according to a second embodiment of the present invention, and FIG.

【図２】本発明１の実施例における半導体装置の製造工
程断面図FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

【図３】本発明２の実施例における半導体装置の製造工
程断面図FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図４】本発明３の実施例における半導体装置の製造工
程断面図FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention;

【図５】従来技術における半導体装置の製造工程断面図FIG. 5 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

【図６】従来技術における半導体装置の製造工程断面図FIG. 6 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

【図７】本発明１の実施例における不純物濃度分布図FIG. 7 is an impurity concentration distribution chart according to the embodiment of the present invention 1.

【図８】本発明２の実施例における不純物濃度分布図FIG. 8 is an impurity concentration distribution diagram according to the embodiment of the present invention 2.

【図９】本発明３の実施例における不純物濃度分布図FIG. 9 is an impurity concentration distribution diagram according to the third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ ｐ型シリコン基板 ２ ｎ型埋め込み領域 ３ 第１のｐウェル ４ 第２のｐウェル ５ 第３のｎウェル ６ ｎ型ウォール領域 ７ 補償領域 ８ 第４のｐウェル １０ 第５のｎウェル Reference Signs List 1 p-type silicon substrate 2 n-type buried region 3 first p-well 4 second p-well 5 third n-well 6 n-type wall region 7 compensation region 8 fourth p-well 10 fifth n-well

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.⁷ 識別記号 ＦＩ Ｈ０１Ｌ 27/108 (56)参考文献 特開 平４−241451（ＪＰ，Ａ) 特開 平３−296260（ＪＰ，Ａ) 特開 昭60−10771（ＪＰ，Ａ) 特開 昭63−102371（ＪＰ，Ａ) (58)調査した分野(Int.Cl.⁷，ＤＢ名) H01L 27/092 H01L 21/8238 H01L 27/108 H01L 21/8242 H01L 21/761 H01L 21/265 ────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/108 (56) References JP-A-4-241451 (JP, A) JP-A-3-296260 (JP, A) JP-A-60-10771 (JP, A) JP-A-63-102371 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 27/108 H01L 21/8242 H01L 21/761 H01L 21/265

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体基板内部に前記半導体基板全面に
わたり形成され、前記基板と反対の導電型を有する埋め
込み層と、前記基板表面から内部に至り、前記基板と同
じ導電型を有する、メモリーセルが搭載された第１のウ
ェルと、前記第１のウェル周辺を取り囲み、前記埋め込
み層から前記基板表面まで連続して形成され、前記基板
と反対の導電型を有するウォール領域と、前記基板表面
から内部に至り、前記基板と同じ導電型を有する第２の
ウェルと、前記基板表面から内部に至り、前記基板と反
対の導電型を有する第３のウェルを有し、前記第３のウ
ェルを前記埋め込み層と接触させたことを特徴とする半
導体装置。A buried layer formed inside the semiconductor substrate over the entire surface of the semiconductor substrate and having a conductivity type opposite to the substrate; and a memory cell extending from the substrate surface to the inside and having the same conductivity type as the substrate. A first well mounted thereon, a wall region surrounding the first well, formed continuously from the buried layer to the substrate surface, and having a conductivity type opposite to the substrate; And a second well having the same conductivity type as the substrate and a third well extending from the surface of the substrate to the inside and having a conductivity type opposite to that of the substrate, wherein the third well is embedded with the third well. A semiconductor device which is brought into contact with a layer. 【請求項２】半導体基板内部に前記半導体基板全面にわ
たり形成され、前記基板と反対の導電型を有する埋め込
み層と、前記基板と同じ導電型を有し前記埋め込み層よ
り高い不純物濃度を有する補償領域と、前記基板表面か
ら内部に至り、前記基板と同じ導電型を有する第１のウ
ェルと、前記第１のウェル周辺を取り囲み、前記埋め込
み層から前記基板表面まで連続して形成され、前記基板
と反対の導電型を有するウォール領域と、前記基板表面
から内部に至り、前記基板と同じ導電型を有する第２の
ウェル及び第４のウェルと、前記基板表面から内部に至
り、前記基板と反対の導電型を有する第３のウェル及び
第５のウェルを有し、前記補償領域を前記埋め込み層と
同じ深さに設けて前記埋め込み層と第３,第５のウェル
との接続を遮断することを特徴とする半導体装置。2. A buried layer formed inside the semiconductor substrate over the entire surface of the semiconductor substrate and having a conductivity type opposite to the substrate, and a compensation region having the same conductivity type as the substrate and having a higher impurity concentration than the buried layer. A first well extending from the surface of the substrate to the inside and having the same conductivity type as the substrate, and surrounding the periphery of the first well, being continuously formed from the buried layer to the surface of the substrate, A wall region having an opposite conductivity type, a second well and a fourth well having the same conductivity type as the substrate, reaching the inside from the substrate surface, and reaching the inside from the substrate surface, and opposing the substrate. A third well and a fifth well having a conductivity type, wherein the compensation region is provided at the same depth as the buried layer to cut off connection between the buried layer and the third and fifth wells; A semiconductor device characterized by the above-mentioned. 【請求項３】半導体基板内部に前記半導体基板全面にわ
たり形成され、前記基板と反対の導電型を有する埋め込
み層と、前記基板表面に前記基板と同じ導電型を有する
第１のウェルと、前記第１のウェル周辺を取り囲み、前
記埋め込み層から前記基板表面まで連続して形成され、
前記基板と反対の導電型を有するウォール領域と、前記
基板と同じ導電型を有する第２のウェル及び第４のウェ
ルと、前記基板と反対の導電型を有する第３のウェル及
び第５のウェルを有し、前記第３のウェル及び前記第５
のウェルが前記埋め込み層より浅い位置に形成され、前
記第３のウェル及び前記第５のウェルと前記埋め込み層
が離間していることを特徴とする半導体装置。3. A buried layer formed inside the semiconductor substrate over the entire surface of the semiconductor substrate and having a conductivity type opposite to that of the substrate, a first well having the same conductivity type as the substrate on the surface of the substrate, Surrounding the periphery of one well, and being formed continuously from the buried layer to the substrate surface;
A wall region having a conductivity type opposite to the substrate, a second well and a fourth well having the same conductivity type as the substrate, and a third well and a fifth well having a conductivity type opposite to the substrate The third well and the fifth well
Wherein the well is formed at a position shallower than the buried layer, and the third well and the fifth well are separated from the buried layer. 【請求項４】請求項２記載の第２のウェル及び第４のウ
ェル底部の、埋め込み層と同じ深さに基板と同じ導電型
の補償領域を有し、前記基板と第２のウェル及び第４の
ウェル底部が前記補償領域を介して接続されることを特
徴とする半導体装置。4. A compensation region of the same conductivity type as that of a substrate at the same depth as a buried layer at the bottom of the second well and the fourth well according to claim 2, wherein the substrate, the second well and the fourth well are formed. 4. The semiconductor device according to claim 4, wherein the bottom of the well is connected through the compensation region. 【請求項５】マスクを用い選択的に半導体基板表面から
不純物を導入し前記基板と同じ導電型の第１のウェルを
形成する工程と、マスクを用い選択的に前記基板表面か
ら不純物を導入し前記基板と同じ導電型の第２のウェル
を形成する工程と、マスクを用い選択的に前記基板表面
から不純物を導入し前記基板と反対の導電型の第３のウ
ェルを形成する工程と、マスクを用い選択的に不純物を
導入し前記基板と反対導電型のウォール領域を形成する
工程と、前記半導体基板の全面にわたり不純物を導入し
前記基板と反対の導電型を有する埋め込み層を形成する
工程とを備え、前記ウォール領域は前記第１のウェル周
辺を取り囲み、前記埋め込み層は前記第３のウェル及び
前記ウォール領域に接触する所定の深さに形成されるこ
とを特徴とする半導体装置の製造方法。5. A step of selectively introducing impurities from the surface of the semiconductor substrate by using a mask to form a first well of the same conductivity type as that of the substrate, and selectively introducing impurities from the surface of the substrate by using a mask. Forming a second well of the same conductivity type as the substrate, selectively introducing impurities from the surface of the substrate using a mask to form a third well of a conductivity type opposite to the substrate, Forming a wall region of a conductivity type opposite to that of the substrate by selectively introducing impurities using a method of forming a buried layer having a conductivity type opposite to that of the substrate by introducing impurities over the entire surface of the semiconductor substrate; Wherein the wall region surrounds the periphery of the first well, and the buried layer is formed at a predetermined depth in contact with the third well and the wall region. Method of manufacturing a body apparatus. 【請求項６】マスクを用い選択的に半導体基板表面から
不純物を導入し前記基板と同じ導電型の第１のウェルを
形成する工程と、マスクを用い選択的に半導体基板表面
から不純物を導入し前記基板と同じ導電型の第２のウェ
ル及び第４のウェルを形成する工程と、マスクを用い選
択的に半導体基板表面から不純物を導入し前記基板と反
対の導電型の第３のウェル及び第５のウェルを形成する
工程と、前記第２のウェル及び第４のウェル形成時に用
いたマスクを用い自己整合的に不純物を導入し、前記基
板と同じ導電型の第１の補償領域を形成する工程と、前
記第３のウェル及び第５のウェル形成時に用いたマスク
を用い自己整合的に不純物を導入し、前記基板と同じ導
電型の第２の補償領域を形成する工程と、マスクを用い
選択的に不純物を導入し前記基板と反対導電型のウォー
ル領域を形成する工程と、前記半導体基板の全面にわた
り不純物を導入し前記基板と反対の導電型を有する埋め
込み層を形成する工程とを備え、前記第１の補償領域は
前記埋め込み層と同じ深さにかつ前記埋め込み層よりも
高い濃度となるように形成され、前記第２の補償領域は
前記埋め込み層と同じ深さにかつ前記埋め込み層よりも
高い濃度となるように形成され、前記ウォール領域は前
記第１のウェルを取り囲み、前記埋め込み層は前記ウォ
ール領域に接触する所定の深さに形成されることを特徴
とする半導体装置の製造方法。6. A step of selectively introducing impurities from the surface of the semiconductor substrate by using a mask to form a first well of the same conductivity type as that of the substrate, and a step of selectively introducing impurities from the surface of the semiconductor substrate by using a mask. Forming a second well and a fourth well of the same conductivity type as the substrate, and selectively introducing impurities from the surface of the semiconductor substrate using a mask to form a third well and a fourth well of a conductivity type opposite to the substrate; Forming a fifth well, and introducing impurities in a self-aligned manner using a mask used in forming the second well and the fourth well to form a first compensation region of the same conductivity type as the substrate. Forming a second compensation region of the same conductivity type as that of the substrate by introducing impurities in a self-aligned manner using a mask used for forming the third well and the fifth well; Selective impurities Forming a wall region of a conductivity type opposite to that of the substrate, and forming a buried layer having a conductivity type opposite to that of the substrate by introducing an impurity over the entire surface of the semiconductor substrate; The compensation region is formed at the same depth as the buried layer and at a higher concentration than the buried layer, and the second compensation region is formed at the same depth as the buried layer and at a higher concentration than the buried layer. Wherein the wall region surrounds the first well, and the buried layer is formed at a predetermined depth in contact with the wall region. 【請求項７】マスクを用い選択的に半導体基板表面から
不純物を導入し前記基板と同じ導電型の第１のウェルを
形成する工程と、マスクを用い選択的に半導体基板表面
から不純物を導入し前記基板と同じ導電型の第２のウェ
ル及び第４のウェルを形成する工程と、マスクを用い選
択的に半導体基板表面から不純物を導入し前記基板と反
対の導電型の第３のウェル及び第５のウェルを形成する
工程と、マスクを用い選択的に不純物を導入し前記基板
と反対導電型のウォール領域を形成する工程と、前記半
導体基板の全面にわたり不純物を導入し前記基板と反対
の導電型を有する埋め込み層を形成する工程とを備え、
前記ウォール領域は前記第１のウェルを取り囲み、前記
埋め込み層は前記第３のウェルと前記第５のウェルと離
間しかつ前記ウォール領域に接触する所定の深さに形成
されることを特徴とする半導体装置の製造方法。7. A step of selectively introducing impurities from the surface of the semiconductor substrate by using a mask to form a first well of the same conductivity type as that of the substrate, and selectively introducing impurities from the surface of the semiconductor substrate by using a mask. Forming a second well and a fourth well of the same conductivity type as the substrate, and selectively introducing impurities from the surface of the semiconductor substrate using a mask to form a third well and a fourth well of a conductivity type opposite to the substrate; 5, a step of selectively introducing impurities using a mask to form a wall region of the opposite conductivity type to the substrate, and a step of introducing impurities over the entire surface of the semiconductor substrate to form a conductive region opposite to the substrate. Forming a buried layer having a mold,
The wall region surrounds the first well, and the buried layer is formed at a predetermined depth that is separated from the third well and the fifth well and is in contact with the wall region. A method for manufacturing a semiconductor device.