JP3243956B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3243956B2 JP3243956B2 JP01683195A JP1683195A JP3243956B2 JP 3243956 B2 JP3243956 B2 JP 3243956B2 JP 01683195 A JP01683195 A JP 01683195A JP 1683195 A JP1683195 A JP 1683195A JP 3243956 B2 JP3243956 B2 JP 3243956B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- electrode
- stage
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップと配線回
路基板とのバンプ（突起電極）接続構造の半導体装置お
よびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump (protruding electrode) connection structure between a semiconductor chip and a printed circuit board, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体素子の高密度実装傾向が著
しく、プリント配線板上に半導体素子を直接接合するＣ
ＯＢ（Chip On Board）法が多用されるようになってき
ている。また、ＭＰＵ・ロジック用素子では接続端子数
が超多ピン化の傾向にあり、２００ピンを超える超多ピ
ン半導体素子では、従来一般的に使用されていたＱＦＰ
等のパッケージに組み立てた場合、実装が容易なアウタ
ーリードピッチ０.６５ｍｍ以上では外形寸法が非常に
大型化し、またアウターリードピッチ０.５ｍｍ以下で
は実装が非常に困難となるため、ＣＯＢ技術の応用とし
て半導体素子を中間基板上に接合してグリッド状のアウ
ターリードで基板に実装するＣＳＰ（ChipSize Packag
e）等のパッケージが提案されている。これらの工程で
は、従来のワイヤボンディング法による接続に加えてバ
ンプにより基板に直接に実装するフリップチップ工法が
採用される場合があり、本発明は新しいフリップチップ
工法の提案に関するものである。2. Description of the Related Art In recent years, the tendency of high-density mounting of semiconductor elements has been remarkable.
The OB (Chip On Board) method has been used frequently. In addition, the number of connection terminals in MPU / logic elements tends to be very large, and in the case of semiconductor devices having more than 200 pins, QFPs conventionally used in general have been used.
If the outer lead pitch is 0.65 mm or more, the outer dimensions become extremely large, and if the outer lead pitch is 0.5 mm or less, mounting becomes extremely difficult. CSP (ChipSize Packag) in which a semiconductor element is bonded to an intermediate substrate and mounted on the substrate with grid-like outer leads
Packages such as e) have been proposed. In these steps, in addition to the connection by the conventional wire bonding method, a flip chip method of mounting directly on a substrate by bumps may be adopted, and the present invention relates to a proposal of a new flip chip method.
【０００３】従来のバンプ接続による半導体装置の実装
構造の例を図５を参照しながら説明する。図５におい
て、従来の実装構造は、半導体チップ１の電極パッド２
上に形成された金・はんだ等のバンプ３を介して、導電
性接着剤４により配線回路基板５上の基板配線６に接合
されているものである。そして半導体チップ１と配線回
路基板５との間隙および周囲に封止樹脂７を塗布し、実
装構造として完成するものであった。An example of a conventional mounting structure of a semiconductor device by bump connection will be described with reference to FIG. In FIG. 5, the conventional mounting structure is the same as the electrode pad 2 of the semiconductor chip 1.
It is joined to a board wiring 6 on a printed circuit board 5 by a conductive adhesive 4 via a bump 3 made of gold, solder or the like formed thereon. Then, a sealing resin 7 is applied to the gap between the semiconductor chip 1 and the printed circuit board 5 and the periphery thereof, thereby completing the mounting structure.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上述の従
来の構成では、バンプと基板配線との接合に導電性接着
剤を用いており、これをすべてのバンプ頭頂部に均等に
塗布する工程が必要であり、スキージ等を用いて接着剤
を薄い膜状にして転写する方法による場合など、接着剤
が硬化しやすくなるため、連続生産を行うために常時接
着剤膜を除去して再び形成する手法等によりオープンタ
イムを長くする必要があった。また同様の理由により接
着剤の特性が変動しやすく、接着強度がばらつくという
信頼性上の課題もあった。However, in the above-described conventional structure, a conductive adhesive is used for bonding the bump and the substrate wiring, and a step of uniformly applying the conductive adhesive to the tops of all the bumps is required. Yes, the adhesive is easily cured, such as when transferring the adhesive into a thin film using a squeegee or the like.Therefore, the method of removing the adhesive film and forming it again for continuous production, etc. It was necessary to lengthen the open time. Further, for the same reason, the characteristics of the adhesive tend to fluctuate, and there is a problem in reliability that the adhesive strength varies.
【０００５】[0005]
【課題を解決するための手段】上述の課題を解決するた
めに、本発明の半導体装置は、第１の２段突起電極がそ
の電極パッド上に設けられた半導体素子と、半導体素子
上の第１の２段突起電極に接合した第２の２段突起電極
がその基板配線上に設けられた配線回路基板と、半導体
素子と配線回路基板との間隙を充填した封止樹脂とより
なる半導体装置であって、半導体素子と配線回路基板と
の間には第１の２段突起電極と第２の２段突起電極とが
互いに当接して接合して中央部が括れた略鼓形状の高背
バンプが設けられていることを特徴とする。In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a semiconductor element having a first two-stage projecting electrode provided on its electrode pad, A semiconductor device comprising: a wiring circuit board having a second two-step projection electrode joined to the first two-step projection electrode provided on the substrate wiring; and a sealing resin filling a gap between the semiconductor element and the wiring circuit board. The first two-stage protruding electrode and the second two-stage protruding electrode are in contact with and joined to each other between the semiconductor element and the printed circuit board, and have a substantially drum-shaped high height with a central portion constricted. It is characterized in that a bump is provided.
【０００６】製造方法においては、半導体素子上の電極
パッドに第１の２段金突起電極を形成する工程と、配線
回路基板上の基板配線上であって、半導体素子上に形成
された第１の２段金突起電極に対向する位置に第２の２
段金突起電極を形成する工程と、半導体素子および配線
回路基板の温度を低く保ったままで加圧し、半導体素子
上の第１の２段金突起電極と配線回路基板上の第２の２
段金突起電極とを圧接接合し、半導体素子と配線回路基
板との間を接続する中央部が括れた略鼓状形状の高背突
起電極を形成する工程と、半導体素子と配線回路基板と
の間隙に封止樹脂を流し込み、充填する工程とを有する
ことを特徴とする。[0006] In the manufacturing method, a step of forming a first 2 Dunkin protruding electrodes to the electrode pads on the semiconductor element, the wiring circuit a substrate wiring on the substrate, first formed on the semiconductor element The second 2
A step of forming a stepped protruding electrode, and applying pressure while keeping the temperature of the semiconductor element and the wiring circuit board low;
A step of forming a substantially tall-shaped high-height protruding electrode in which a central portion for connecting the semiconductor element and the wiring circuit board is joined by press-welding the corrugated metal protruding electrode to the semiconductor element and the wiring circuit board; Pouring and filling the sealing resin into the gap.
【０００７】[0007]
【作用】上述の構成により接合のための導電性接着剤が
不要となるので、従来の接着剤均等塗布機構が不要とな
り、設備を簡略化することができる。また導電性接着剤
の管理も不要になり、量産工場での配慮が少なくても安
定した生産が可能である。この場合、両方のバンプを塑
性変形機能に優れた金（Ａｕ）で形成することにより、
接合温度を低く保った状態で圧接接合することが可能に
なる。さらに、この金バンプを金ワイヤのボールボンデ
ィング法を応用した方法で２段形状に形成し、それぞれ
を接合させることにより、温度変動時の接合部への応力
発生を緩和するのに有利な鼓状に近い形状の接続部を得
ることができ、接合部分の信頼性を向上させることがで
きる。According to the above construction, a conductive adhesive for bonding is not required, so that a conventional adhesive uniform application mechanism is not required and the equipment can be simplified. In addition, there is no need to manage the conductive adhesive, and stable production is possible even with little consideration in a mass production factory. In this case, by forming both bumps with gold (Au) having excellent plastic deformation function,
It becomes possible to perform pressure welding while keeping the joining temperature low. Furthermore, the gold bumps are formed in a two-stage shape by applying a gold wire ball bonding method, and the two are joined to form a drum-like shape which is advantageous for reducing the generation of stress at the joint when the temperature fluctuates. Thus, it is possible to obtain a connection portion having a shape close to that of the first embodiment, and to improve the reliability of the joint portion.
【０００８】[0008]
【実施例】本発明の一実施例について図面を参照しなが
ら説明する。本実施例においては、プロセス的に構造、
製造方法について説明する。An embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the structure,
The manufacturing method will be described.
【０００９】図１，図２は本発明の第１の実施例を示す
断面図である。図１に示すように、半導体チップ１の電
極パッド２上に第１バンプ８が形成され、また配線回路
基板５上の基板配線６上に第２バンプ９が形成されてい
る。これら第１バンプ８，第２バンプ９の材質は、金、
銅、半田、またはアルミニウム等であり、第１バンプ８
と第２バンプ９との材質は同じであっても、あるいは互
いに異なっていてもよい。さらに第１バンプ８，第２バ
ンプ９上に適宜メッキを施し、共晶形成による接合性の
向上を図ることもできる。第１バンプ８や第２バンプ９
の形成方法としては、バンプの組成によりメッキ法や、
ワイヤーボンディング時に用いるボールボンダーによ
り、金属細線を使用したボールボンディング法により形
成する。FIG. 1 and FIG. 2 are sectional views showing a first embodiment of the present invention. As shown in FIG. 1, a first bump 8 is formed on an electrode pad 2 of a semiconductor chip 1, and a second bump 9 is formed on a substrate wiring 6 on a printed circuit board 5. The material of the first bump 8 and the second bump 9 is gold,
The first bump 8 is made of copper, solder, aluminum, or the like.
The material of the second bump 9 and the material of the second bump 9 may be the same or different from each other. Further, the first bumps 8 and the second bumps 9 may be appropriately plated to improve the bonding property by eutectic formation. First bump 8 and second bump 9
As a method of forming, depending on the composition of the bump, a plating method,
It is formed by a ball bonding method using a thin metal wire by a ball bonder used at the time of wire bonding.
【００１０】次に、図２に示すように、配線回路基板５
を適当なステージ上に載せ、半導体チップ１をツールに
より真空吸着し、半導体チップ１上の第１バンプ８と配
線回路基板５上の第２バンプ９とをそれぞれ当接させて
電気的導通を得る。これによって、半導体チップ１と配
線回路基板５との間には、第１バンプ８と第２バンプ９
とによりハイバンプ１０が形成される。この後、半導体
チップ１と配線回路基板５との間隙および周囲に封止樹
脂７を塗布して実装構造を完成する。Next, as shown in FIG.
Is placed on an appropriate stage, the semiconductor chip 1 is vacuum-sucked by a tool, and the first bumps 8 on the semiconductor chip 1 and the second bumps 9 on the printed circuit board 5 are brought into contact with each other to obtain electrical continuity. . Thereby, the first bump 8 and the second bump 9 are provided between the semiconductor chip 1 and the printed circuit board 5.
Thus, the high bump 10 is formed. Thereafter, a sealing resin 7 is applied to the gap between the semiconductor chip 1 and the printed circuit board 5 and the periphery thereof to complete the mounting structure.
【００１１】図２に示す本実施例の実装構造は、第１の
バンプ８がその電極パッド２上に設けられた半導体チッ
プ１と、半導体チップ１上の第１のバンプ８に接合した
第２のバンプ９がその基板配線６上に設けられた配線回
路基板５と、半導体チップ１と配線回路基板５との間隙
を充填した封止樹脂７とよりなるもので、半導体チップ
１と配線回路基板５との間には第１のバンプ８と第２の
バンプ９とが互いに当接して接合してハイバンプ１０が
設けられているものである。The mounting structure of this embodiment shown in FIG. 2 has a structure in which the first bump 8 is bonded to the semiconductor chip 1 provided on the electrode pad 2 and the second bump 8 bonded to the first bump 8 on the semiconductor chip 1. The semiconductor chip 1 and the printed circuit board are formed of a printed circuit board 5 provided on the board wiring 6 and a sealing resin 7 filling a gap between the semiconductor chip 1 and the printed circuit board 5. The first bump 8 and the second bump 9 are in contact with each other and joined to each other to provide a high bump 10.
【００１２】なお、第１バンプ８と第２バンプ９を塑性
変形機能に優れた金同士として、配線回路基板５、半導
体チップ１の温度を低く保ったままで、押圧ツールによ
り加圧することにより、容易に第１バンプ８と第２バン
プ９とを圧接構造とすることができる。また、この際押
圧ツールを加熱すれば熱圧着構造とすることができ、第
１バンプ８、第２バンプ９を半田等の低融点金属、また
は金と錫等の共晶形成組成の金属を選ぶことで、溶融接
構造の接合部（ハイバンプ）を得ることもできる。The first bumps 8 and the second bumps 9 are made of gold having an excellent plastic deformation function, and are easily pressed by a pressing tool while keeping the temperature of the printed circuit board 5 and the semiconductor chip 1 low. In addition, the first bump 8 and the second bump 9 can have a pressure contact structure. At this time, if the pressing tool is heated, a thermocompression bonding structure can be obtained. For the first bump 8 and the second bump 9, a low melting point metal such as solder or a metal having a eutectic forming composition such as gold and tin is selected. In this way, it is also possible to obtain a joint (high bump) having a fusion contact structure.
【００１３】本実施例においては、半導体チップ１上の
第１バンプ８と配線回路基板５上の第２バンプ９とによ
り接合しているので、導電性接着剤等の接着剤手段を用
いずとも半導体チップを基板に直接実装できる。また半
導体チップ１と配線回路基板５との間には、第１バンプ
８と第２バンプ９とによりハイバンプ１０が形成され、
間隙がバンプ１つの場合に比べて大きいので、封止樹脂
７を半導体チップ１と配線回路基板５との間隙に充填す
る際、粘度の高い封止樹脂７を用いても、間隙に気泡等
の発生を抑えて充分に充填することができる。In this embodiment, since the first bumps 8 on the semiconductor chip 1 and the second bumps 9 on the printed circuit board 5 are joined, it is not necessary to use an adhesive means such as a conductive adhesive. A semiconductor chip can be directly mounted on a substrate. A high bump 10 is formed between the semiconductor chip 1 and the printed circuit board 5 by the first bump 8 and the second bump 9.
Since the gap is larger than in the case of one bump, when the sealing resin 7 is filled in the gap between the semiconductor chip 1 and the wiring circuit board 5, even if the sealing resin 7 having a high viscosity is used, bubbles or the like may be formed in the gap. Generation can be suppressed and sufficient filling can be achieved.
【００１４】次に図３，図４は本発明の第２の実施例を
示す断面図である。図３に示すように、半導体チップ１
の電極パッド２上および配線回路基板５の基板配線６上
にそれぞれ第１の２段バンプ１１および第２の２段バン
プ１２が形成されているが、第１の２段バンプ１１およ
び第２の２段バンプ１２は、ボールボンダーにより金属
細線を使用してボールボンディング法で形成したため、
２段形状の高背型バンプとなっている。Next, FIGS. 3 and 4 are sectional views showing a second embodiment of the present invention. As shown in FIG.
The first two-stage bumps 11 and the second two-stage bumps 12 are formed on the electrode pads 2 and on the substrate wiring 6 of the printed circuit board 5, respectively. Since the two-stage bump 12 was formed by a ball bonding method using a thin metal wire with a ball bonder,
It is a two-stage high-height bump.
【００１５】次に、図４に示すように、配線回路基板５
を適当なステージ上に載せ、半導体チップ１をツールに
より真空吸着し、半導体チップ１上の第１の２段バンプ
１１と配線回路基板５上の第２の２段バンプ１２とをそ
れぞれ当接させて電気的導通を得る。これによって、半
導体チップ１と配線回路基板５との間には、第１の２段
バンプ１１と第２の２段バンプ１２とによりハイバンプ
１３が形成される。この後、半導体チップ１と配線回路
基板５との間隙および周囲に封止樹脂７を塗布して実装
構造を完成する。Next, as shown in FIG.
Is placed on an appropriate stage, the semiconductor chip 1 is vacuum-sucked by a tool, and the first two-stage bumps 11 on the semiconductor chip 1 and the second two-stage bumps 12 on the printed circuit board 5 are brought into contact with each other. To obtain electrical continuity. As a result, a high bump 13 is formed between the semiconductor chip 1 and the printed circuit board 5 by the first two-stage bump 11 and the second two-stage bump 12. Thereafter, a sealing resin 7 is applied to the gap between the semiconductor chip 1 and the printed circuit board 5 and the periphery thereof to complete the mounting structure.
【００１６】図４に示す本実施例の実装構造は、第１の
２段バンプ１１がその電極パッド２上に設けられた半導
体チップ１と、半導体チップ１上の第１の２段バンプ１
１に接合した第２の２段バンプ１２がその基板配線６上
に設けられた配線回路基板５と、半導体チップ１と配線
回路基板５との間隙を充填した封止樹脂７とよりなるも
のであり、半導体チップ１と配線回路基板５との間には
第１の２段バンプ１１と第２の２段バンプ１２とが互い
に当接して接合して中央部が括れた略鼓形状のハイバン
プ１３が設けられているものである。The mounting structure of the present embodiment shown in FIG. 4 includes a semiconductor chip 1 having a first two-stage bump 11 provided on its electrode pad 2 and a first two-stage bump 1 on the semiconductor chip 1.
The second two-stage bumps 12 bonded to the wiring board 1 are composed of a printed circuit board 5 provided on the board wiring 6 and a sealing resin 7 filling a gap between the semiconductor chip 1 and the printed circuit board 5. A first drum 11 and a second bump 12 are brought into contact with and joined to each other between the semiconductor chip 1 and the printed circuit board 5 to form a substantially drum-shaped high bump 13 whose center is constricted. Is provided.
【００１７】なお、第１の２段バンプ１１と第２の２段
バンプ１２を第１の実施例と同様に、塑性変形機能に優
れた金同士として、配線回路基板５、半導体チップ１の
温度を低く保ったままで、押圧ツールにより加圧するこ
とにより、容易に第１の２段バンプ１１と第２の２段バ
ンプ１２とを圧接構造とすることができる。また、この
際押圧ツールを加熱すれば熱圧着構造とすることがで
き、第１の２段バンプ１１、第２の２段バンプ１２を半
田等の低融点金属、または金と錫等の共晶形成組成の金
属を選ぶことで、溶融接構造の接合部を得ることもでき
る。The first two-stage bumps 11 and the second two-stage bumps 12 are made of gold having an excellent plastic deformation function as in the first embodiment, and the temperature of the printed circuit board 5 and the semiconductor chip 1 is reduced. The first two-stage bumps 11 and the second two-stage bumps 12 can be easily brought into a press-contact structure by pressing with a pressing tool while keeping the pressure low. At this time, if the pressing tool is heated, a thermocompression bonding structure can be obtained. The first two-stage bumps 11 and the second two-stage bumps 12 are made of a low melting point metal such as solder or a eutectic such as gold and tin. By selecting a metal having a forming composition, it is also possible to obtain a joint having a fusion contact structure.
【００１８】本実施例においては、半導体チップ１上の
第１の２段バンプ１１と配線回路基板５上の第２の２段
バンプ１２とにより接合しているので、導電性接着剤等
の接着剤手段を用いずとも半導体チップを基板に直接実
装できる。また半導体チップ１と配線回路基板５との間
には、第１の２段バンプ１１と第２の２段バンプ１２と
によりハイバンプ１３が形成され、間隙がバンプ１つの
場合に比べて大きいので、封止樹脂７を半導体チップ１
と配線回路基板５との間隙に充填する際、粘度の高い封
止樹脂７を用いても、間隙に気泡等の発生を抑えて充分
に充填することができる。In the present embodiment, since the first two-stage bumps 11 on the semiconductor chip 1 and the second two-stage bumps 12 on the printed circuit board 5 are joined, bonding with a conductive adhesive or the like is performed. The semiconductor chip can be directly mounted on the substrate without using the agent means. In addition, a high bump 13 is formed between the semiconductor chip 1 and the printed circuit board 5 by the first two-stage bump 11 and the second two-stage bump 12, and the gap is larger than that in the case of one bump. Sealing resin 7 is applied to semiconductor chip 1
When filling the gap between the wiring board and the wiring circuit board 5, even if the sealing resin 7 having high viscosity is used, the gap can be sufficiently filled by suppressing the generation of bubbles and the like.
【００１９】また第１の２段バンプ１１と第２の２段バ
ンプ１２とにより形成されたハイバンプ１３の形状は、
中央部が括れた鼓状に近い形状となり、半導体チップ１
と回路基板５との材料の違いによる熱膨張率の差を吸収
するのに有利な形状となっている。したがって、ハイバ
ンプ１３により、半導体チップと配線回路基板との接合
部分の信頼性を向上させることができる。The shape of the high bump 13 formed by the first two-stage bump 11 and the second two-stage bump 12 is as follows.
The central part is shaped like a drum with a constriction, and the semiconductor chip 1
The shape is advantageous in absorbing the difference in the coefficient of thermal expansion due to the difference in the material between the substrate and the circuit board 5. Therefore, the reliability of the junction between the semiconductor chip and the printed circuit board can be improved by the high bumps 13.
【００２０】以上、本発明の一実施例について述べた
が、たとえば第１バンプ８、第２バンプ９、第１の２段
バンプ１１、第２の２段バンプ１２の材質を金とした場
合に、ツールに超音波を印加して接合性を向上させ、低
温下で融接的構造として強固な接合部を得ることもでき
る。さらに、第２の実施例で２段形状の高背型バンプを
形成する手段として、ボールボンディング法のかわりに
レジストフィルムを複数回使用するメッキ工法によって
形成してもよい。The embodiment of the present invention has been described above. For example, when the material of the first bump 8, the second bump 9, the first two-stage bump 11, and the second two-stage bump 12 is gold. By applying ultrasonic waves to the tool, the joining property can be improved, and a strong joint can be obtained as a fusion-bonded structure at a low temperature. Furthermore, in the second embodiment, as a means for forming a two-step high-profile bump, a plating method using a resist film a plurality of times may be used instead of the ball bonding method.
【００２１】[0021]
【発明の効果】以上のように本発明の半導体装置は、半
導体チップ、配線回路基板の双方に形成したバンプ同士
を接合することにより、半導体チップの直接接合構造を
得ることができ、生産性・信頼性の高いフリップチップ
工法を実現するものである。As described above, according to the semiconductor device of the present invention, by directly joining the bumps formed on both the semiconductor chip and the printed circuit board, a direct joining structure of the semiconductor chip can be obtained, and the productivity and the productivity can be improved. This realizes a highly reliable flip chip method.
【００２２】また製造方法においては、半導体チップ、
配線回路基板の双方に形成したバンプ同士を低温で単に
圧接して接合することができるため、容易に半導体チッ
プを配線回路基板に接合することができる。In the manufacturing method, a semiconductor chip,
Since the bumps formed on both of the printed circuit boards can be simply pressed and joined at a low temperature, the semiconductor chip can be easily joined to the printed circuit board.
【図１】本発明の半導体装置における第１の実施例の断
面図FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
【図２】本発明の半導体装置における第１の実施例の断
面図FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
【図３】本発明の半導体装置における第２の実施例の断
面図FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
【図４】本発明の半導体装置における第２の実施例の断
面図FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
【図５】従来の半導体装置の断面図FIG. 5 is a sectional view of a conventional semiconductor device.
１ 半導体チップ ２ 電極パッド ３ バンプ ４ 導電性接着剤 ５ 配線回路基板 ６ 基板配線 ７ 封止樹脂 ８ 第１バンプ ９ 第２バンプ １０ ハイバンプ １１ 第１の２段バンプ １２ 第２の２段バンプ １３ ハイバンプ Reference Signs List 1 semiconductor chip 2 electrode pad 3 bump 4 conductive adhesive 5 wiring circuit board 6 board wiring 7 sealing resin 8 first bump 9 second bump 10 high bump 11 first two-stage bump 12 second two-stage bump 13 high bump
フロントページの続き (56)参考文献 特開 平４−225542（ＪＰ，Ａ) 特開 平２−206125（ＪＰ，Ａ) 特開 昭62−117346（ＪＰ，Ａ) 特開 平５−47841（ＪＰ，Ａ) 特開 平２−163950（ＪＰ，Ａ) 特開 平４−151843（ＪＰ，Ａ) 特開 平５−235098（ＪＰ，Ａ) 特開 平８−31835（ＪＰ，Ａ) 特開 平８−88249（ＪＰ，Ａ) 特開 平８−222599（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/56 H01L 23/28 Continuation of the front page (56) References JP-A-4-225542 (JP, A) JP-A-2-206125 (JP, A) JP-A-62-117346 (JP, A) JP-A-5-47841 (JP) JP-A-2-163950 (JP, A) JP-A-4-151843 (JP, A) JP-A-5-235098 (JP, A) JP-A-8-31835 (JP, A) 8-88249 (JP, A) JP-A-8-222599 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 H01L 21/56 H01L 23/28
Claims (3)
に設けられた半導体素子と、前記半導体素子上の第１の
２段突起電極に接合した第２の２段突起電極がその基板
配線上に設けられた配線回路基板と、前記半導体素子と
前記配線回路基板との間隙を充填した封止樹脂とよりな
る半導体装置であって、前記半導体素子と配線回路基板
との間には前記第１の２段突起電極と前記第２の２段突
起電極とが互いに当接して接合して中央部が括れた略鼓
形状の高背バンプが設けられていることを特徴とする半
導体装置。1. A semiconductor device having a first two-stage projection electrode provided on an electrode pad thereof, and a second two-stage projection electrode joined to the first two-stage projection electrode on the semiconductor device comprises a substrate. A semiconductor device comprising a printed circuit board provided on a wiring, and a sealing resin filling a gap between the semiconductor element and the printed circuit board, wherein the semiconductor device and the printed circuit board have a gap between the semiconductor element and the printed circuit board. A semiconductor device having a substantially tall drum-shaped tall bump whose central portion is narrowed by contacting and joining a first two-stage projecting electrode and the second two-stage projecting electrode.
けられた第１の２段突起電極および第２の２段突起電極
の材質が共に金であることを特徴とする請求項１に記載
の半導体装置。2. The material according to claim 1, wherein the material of the first two-step projection electrode and the second two-step projection electrode provided on the semiconductor element and the printed circuit board are both gold. Semiconductor device.
金突起電極を形成する工程と、配線回路基板上の基板配
線上であって、前記半導体素子上に形成された第１の２
段金突起電極に対向する位置に第２の２段金突起電極を
形成する工程と、前記半導体素子および前記配線回路基
板の温度を低く保ったままで加圧し、前記半導体素子上
の第１の２段金突起電極と前記配線回路基板上の第２の
２段金突起電極とを圧接接合し、半導体素子と配線回路
基板との間を接続する中央部が括れた略鼓状形状の高背
突起電極を形成する工程と、前記半導体素子と配線回路
基板との間隙に封止樹脂を流し込み、充填する工程とを
有することを特徴とする半導体装置の製造方法。3. A step of forming a first two-stage gold protruding electrode on an electrode pad on a semiconductor element, and a step of forming a first two-stage gold projection electrode on a substrate wiring on a printed circuit board and formed on the semiconductor element.
Forming a second two-stage gold projection electrode at a position facing the step metal projection electrode; and pressing the semiconductor element and the printed circuit board while keeping the temperature of the semiconductor element and the printed circuit board low. A substantially drum-shaped high-profile projection in which a central portion for connecting the semiconductor element and the printed circuit board is press-bonded to the stepped electrode and the second two-step projected electrode on the printed circuit board. A method of manufacturing a semiconductor device, comprising: forming an electrode; and pouring and filling a sealing resin into a gap between the semiconductor element and a printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01683195A JP3243956B2 (en) | 1995-02-03 | 1995-02-03 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01683195A JP3243956B2 (en) | 1995-02-03 | 1995-02-03 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08213425A JPH08213425A (en) | 1996-08-20 |
| JP3243956B2 true JP3243956B2 (en) | 2002-01-07 |
Family
ID=11927150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01683195A Expired - Fee Related JP3243956B2 (en) | 1995-02-03 | 1995-02-03 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3243956B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1138460C (en) * | 1997-10-02 | 2004-02-11 | 松下电器产业株式会社 | Method for mounting semiconductor element to circuit board, and semiconductor device |
| JP2002261262A (en) | 2001-03-01 | 2002-09-13 | Mitsubishi Heavy Ind Ltd | Image sensor and manufacturing method |
| JP4397012B2 (en) * | 2001-11-05 | 2010-01-13 | 独立行政法人 宇宙航空研究開発機構 | Semiconductor image sensor having hole-type electrode and manufacturing method thereof |
| FI20031341A (en) | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Method for manufacturing an electronic module |
| US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
| KR100604334B1 (en) * | 2003-11-25 | 2006-08-08 | (주)케이나인 | Flip Chip Bondig Method for Enhancing the Performance of Connection in Flip Chip Packaging Process |
| FI119714B (en) | 2005-06-16 | 2009-02-13 | Imbera Electronics Oy | Circuit board structure and method for manufacturing a circuit board structure |
| JP4422753B2 (en) * | 2007-12-14 | 2010-02-24 | シャープ株式会社 | Semiconductor device |
| JP4641551B2 (en) * | 2008-06-13 | 2011-03-02 | 富士通株式会社 | Manufacturing method of semiconductor device |
| US8120158B2 (en) * | 2009-11-10 | 2012-02-21 | Infineon Technologies Ag | Laminate electronic device |
| CN104541366A (en) * | 2012-08-08 | 2015-04-22 | 夏普株式会社 | Semiconductor device and method for producing same |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117346A (en) * | 1985-11-18 | 1987-05-28 | Fujitsu Ltd | Semiconductor device |
| JPH0666355B2 (en) * | 1988-12-16 | 1994-08-24 | 松下電器産業株式会社 | Semiconductor device mounting body and mounting method thereof |
| JP2770041B2 (en) * | 1989-02-06 | 1998-06-25 | 新日本製鐵株式会社 | Bump forming method and semiconductor element connecting method |
| JPH04151843A (en) * | 1990-10-16 | 1992-05-25 | Casio Comput Co Ltd | Bonding method of ic chip |
| JPH04225542A (en) * | 1990-12-27 | 1992-08-14 | Tanaka Denshi Kogyo Kk | Semiconductor device |
| JPH0547841A (en) * | 1991-08-20 | 1993-02-26 | Citizen Watch Co Ltd | Mounting method and structure of semiconductor apparatus |
| JPH05235098A (en) * | 1992-02-21 | 1993-09-10 | Fujitsu Ltd | Flip chip bonding method |
| JP3348528B2 (en) * | 1994-07-20 | 2002-11-20 | 富士通株式会社 | Method for manufacturing semiconductor device, method for manufacturing semiconductor device and electronic circuit device, and electronic circuit device |
| JPH0888249A (en) * | 1994-09-19 | 1996-04-02 | Taiyo Yuden Co Ltd | Face-down bonding method |
| JP3160175B2 (en) * | 1995-02-13 | 2001-04-23 | 三菱電機株式会社 | Electronic component mounting method |
-
1995
- 1995-02-03 JP JP01683195A patent/JP3243956B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08213425A (en) | 1996-08-20 |
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