JP3243195B2 - Reflow solder plating material and method of manufacturing the same - Google Patents

Reflow solder plating material and method of manufacturing the same

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Publication number
JP3243195B2
JP3243195B2 JP02837397A JP2837397A JP3243195B2 JP 3243195 B2 JP3243195 B2 JP 3243195B2 JP 02837397 A JP02837397 A JP 02837397A JP 2837397 A JP2837397 A JP 2837397A JP 3243195 B2 JP3243195 B2 JP 3243195B2
Authority
JP
Japan
Prior art keywords
plating layer
reflow
plating
alloy
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP02837397A
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Japanese (ja)
Other versions
JPH111793A (en
Inventor
守正 谷本
智 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THE FURUKAW ELECTRIC CO., LTD.
Original Assignee
THE FURUKAW ELECTRIC CO., LTD.
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Application filed by THE FURUKAW ELECTRIC CO., LTD. filed Critical THE FURUKAW ELECTRIC CO., LTD.
Priority to JP02837397A priority Critical patent/JP3243195B2/en
Publication of JPH111793A publication Critical patent/JPH111793A/en
Application granted granted Critical
Publication of JP3243195B2 publication Critical patent/JP3243195B2/en
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Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品のリード
部や電気接続用コネクタなどに使用されるめっき部材に
関し、特に耐酸化性や半田付性を改善したリフロー半田
めっき材およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plating member used for a lead portion of an electronic component, a connector for electrical connection, and the like, and more particularly to a reflow solder plating material having improved oxidation resistance and solderability, and a method of manufacturing the same. .

【0002】[0002]

【従来の技術】CuまたはCu合金などの導電性基材表
面にSnまたはSn合金をめっきした部材は導電性基材
が具備する導電性と機械的強度、SnまたはSn合金が
具備する耐食性と半田付性とがうまく組合わされた高性
能導体であって、端子、コネクタ、リード線などの電気
電子機器用部品や電線ケーブルなどに多用されている。
2. Description of the Related Art A member in which the surface of a conductive substrate such as Cu or a Cu alloy is plated with Sn or a Sn alloy has the conductivity and mechanical strength of the conductive substrate, the corrosion resistance of the Sn or Sn alloy and the solder. It is a high-performance conductor that has a good combination of stickiness and is widely used for electric and electronic device parts such as terminals, connectors, lead wires, and electric cables.

【0003】従来SnまたはSn合金めっき層はSn−
Pb系合金を電気めっきして形成されていた。また、一
般に、電気めっき材には、短絡事故の原因になるウイス
カー(針状単結晶)が発生し易いという問題があり、こ
の問題は、前記Sn−Pb系合金めっき材では光沢めっ
きまたはめっき層を溶融−凝固させるリフロー処理によ
り解決が図られてきた。近年開発された人体に有害なP
bを含まないSn−Bi系合金めっき材のウイスカー対
策については、光沢めっきによる方法は未解決であり、
リフロー処理法が特開平4−160196号に開示され
ているにすぎない。
Conventionally, a Sn or Sn alloy plating layer is formed of Sn-
It was formed by electroplating a Pb-based alloy. In general, electroplating materials have a problem that whiskers (needle-like single crystals) that cause short circuit accidents are easily generated. This problem is caused by the bright plating or the plating layer in the Sn—Pb alloy plating material. The problem has been solved by a reflow treatment for melting and solidifying the solid. Recently developed P harmful to human body
As for whisker countermeasures for Sn-Bi-based alloy plating materials that do not contain b, the method using bright plating has not been solved.
The reflow processing method is merely disclosed in JP-A-4-160196.

【0004】[0004]

【発明が解決しようとする課題】しかし、前記開示のリ
フロー処理法では、基材成分がめっき層表面に拡散して
半田付性が低下したり、めっき層表面に流れ模様が形成
されて外観不良が起きたり、流れ模様の薄肉部分の半田
付性が低下したりする問題があった。このようなことか
ら、本発明者等は、Sn−Bi系合金めっき材の半田付
性の改善について鋭意研究を行い、リフロー処理を所定
温度に制御して行うことによりめっき層表面への基材の
拡散を防止し得ることを知見し、さらに研究を進めて本
発明を完成させるに至った。本発明は、人体に有害なP
bを含まず、半田付性および外観に優れるSn−Bi系
合金のリフロー半田めっき材およびその製造方法の提供
を目的とする。
However, in the reflow treatment method disclosed above, the base material component is diffused on the surface of the plating layer to deteriorate the solderability, or a flowing pattern is formed on the surface of the plating layer to cause poor appearance. And the solderability of the thin portion of the flow pattern is reduced. From these facts, the present inventors have conducted intensive research on the improvement of the solderability of the Sn—Bi alloy plating material, and performed the reflow treatment at a predetermined temperature to control the base material on the plating layer surface. It has been found that the diffusion of the compound can be prevented, and further research has been made to complete the present invention. The present invention relates to P which is harmful to the human body.
An object of the present invention is to provide a reflow solder plated material of an Sn-Bi-based alloy which does not contain b and has excellent solderability and appearance and a method for producing the same.

【0005】[0005]

【課題を解決するための手段】請求項記載の発明は、
導電性基材上にSn−Bi系合金めっき層が形成された
半田めっき材において、前記Sn−Bi系合金めっき層
がリフロー処理されており、前記めっき層の表面の結晶
粒界にBiリッチ相が連続的に析出した組織からなり、
前記Sn−Bi系合金めっき層のBiの濃度が、めっき
層の表面から内部に向けて漸次減少していることを特徴
とするリフロー半田めっき材である。
According to the first aspect of the present invention,
In a solder plating material in which an Sn-Bi-based alloy plating layer is formed on a conductive base material, the Sn-Bi-based alloy plating layer is subjected to a reflow treatment, and a Bi-rich phase is formed at a crystal grain boundary on a surface of the plating layer. Consists of a continuously precipitated structure,
A reflow solder plating material, characterized in that the concentration of Bi in the Sn-Bi-based alloy plating layer gradually decreases from the surface of the plating layer toward the inside.

【0006】請求項2記載の発明は、導電性基材上に
i濃度が共晶組成以下のSn−Bi系合金めっき層を電
気めっきし、次いでこれを前記Sn−Bi系合金の2相
状態図の(L+β)形成温度領域に加熱して高速でリフ
ロー処理することを特徴とする請求項1記載のリフロー
半田めっき材の製造方法である。
[0006] According to a second aspect of the invention, B on the electrically conductive substrate
An Sn—Bi-based alloy plating layer having an i-concentration equal to or less than the eutectic composition is electroplated, and then heated to the (L + β) forming temperature region of the Sn—Bi-based alloy two-phase phase diagram to rapidly reflow. 2. The method for producing a reflow solder plating material according to claim 1, wherein the reflow solder plating material is subjected to a low-temperature treatment.

【0007】[0007]

【発明の実施の形態】めっき上がり(リフロー処理前)
材の表面組織は図1(ハ) に示すようにBiリッチ相な
どが析出していない。これを従来法によりリフロー処理
するとめっき層の表面は図1(ロ) に示すような、Sn
リッチ相からなる結晶粒内にBiリッチ相40がランダム
に分散した組織になる。このような組織では基材からの
Cuなどの粒界拡散が防止されないばかりか、めっき相
の表面に流れ模様が生じ、表面が平滑でなくなる。これ
はリフロー処理温度が高すぎるためである。本発明のリ
フロー半田めっき材は、そのめっき層の表面が、図1
(イ) に示すようにSnリッチ相からなる結晶粒10の境
界(結晶粒界)20にBiリッチ相30が連続的に析出した
組織からなる。また表面が平滑で外観と半田付性に優れ
る。前記結晶粒界に連続的に析出したBiリッチ相30
は、導電性基材のCuなどの成分が結晶粒界20を通って
半田めっき層の表面に拡散し酸化して半田付性を悪化さ
せるのを防止する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Finishing of plating (before reflow treatment)
In the surface structure of the material, as shown in FIG. 1 (c), no Bi-rich phase or the like was precipitated. When this is subjected to a reflow treatment by a conventional method, the surface of the plating layer becomes Sn as shown in FIG.
A structure in which the Bi-rich phase 40 is randomly dispersed in the crystal grains composed of the rich phase is obtained. With such a structure, not only diffusion of the grain boundary of Cu or the like from the base material is not prevented, but also a flow pattern is generated on the surface of the plating phase, and the surface is not smooth. This is because the reflow temperature is too high. In the reflow solder plating material of the present invention, the surface of the plating layer is as shown in FIG.
As shown in FIG. 2A, the structure is such that the Bi-rich phase 30 is continuously precipitated at the boundary (crystal grain boundary) 20 of the crystal grain 10 composed of the Sn-rich phase. In addition, the surface is smooth and has excellent appearance and solderability. Bi-rich phase 30 continuously precipitated at the crystal grain boundaries
This prevents components such as Cu of the conductive base material from diffusing to the surface of the solder plating layer through the crystal grain boundaries 20 and oxidizing to deteriorate the solderability.

【0008】本発明において、Sn−Bi系合金めっき
層のBiの濃度が、めっき層の表面から内部に向けて漸
次減少していると半田めっき層への導電性基材成分(例
えば、Cu)の拡散がより良好に防止される。これはB
iリッチ相が結晶粒界に高密度に析出して基材の表面へ
の拡散を効率良く抑制するためである。
[0008] In the present invention, the concentration of Bi in the Sn-Bi alloy plating layer, a conductive substrate components to be reduced gradually toward the inside from the surface of the plating layer to Handa plating layer (e.g., Cu ) Is better prevented. This is B
This is because the i-rich phase precipitates at a high density at the crystal grain boundaries and efficiently suppresses diffusion to the surface of the substrate.

【0009】請求項記載の発明は、前記リフロー半田
めっき材の製造方法である。この発明において、リフロ
ー処理温度を、図2に示すSn−Bi系合金の状態図の
(L+β)領域が形成される温度範囲に加熱して行う理
由は、前記温度範囲で加熱すると結晶粒界にBiリッチ
相が連続的に析出した組織が得られるためである。リフ
ロー処理温度が前記温度範囲を低温側に外れると半田め
っき層が溶融(リフロー)せず、リフロー処理温度が前
記温度範囲を高温側に外れるとBiリッチ相が結晶粒内
にランダムに分散し、また表面に流れ模様が生じ、表面
の平滑性が低下する。
The invention according to claim 2 is a method for producing the reflow solder plating material. In the present invention, the reason why the reflow treatment temperature is performed by heating to the temperature range in which the (L + β) region of the phase diagram of the Sn—Bi alloy is formed as shown in FIG. This is because a structure in which a Bi-rich phase is continuously precipitated can be obtained. When the reflow treatment temperature is out of the temperature range on the low temperature side, the solder plating layer does not melt (reflow), and when the reflow treatment temperature is out of the temperature range on the high temperature side, the Bi-rich phase is randomly dispersed in the crystal grains, In addition, a flow pattern is formed on the surface, and the smoothness of the surface is reduced.

【0010】リフロー処理は、導電性基材を、高温に設
定した炉内を高速で通過させて施しても、また低温に設
定した炉内を低速で通過させて施しても良いが、前者の
方がリフロー処理後の冷却が急速になされるため、表面
近傍のBi濃度が高濃度に分布し易い。まためっき層表
面に流れ模様が生じ難い。
The reflow treatment may be performed by passing the conductive substrate through a furnace set at a high temperature at a high speed, or by passing the conductive substrate at a low speed through a furnace set at a low temperature. Since the cooling after the reflow treatment is performed more rapidly, the Bi concentration near the surface tends to be distributed at a higher concentration. In addition, a flow pattern is unlikely to occur on the plating layer surface.

【0011】[0011]

【実施例】以下に、本発明を実施例により詳細に説明す
る。 (実施例1) 0.5mmφの黄銅線上にCuを1μm厚さに下地めっ
きし、次いでSn−Bi系合金を電気めっきし、次いで
これを800℃に設定した炉内を通してリフロー半田め
っき材を製造した。装置には、電解脱脂槽、水洗槽、酸
洗槽、水洗槽、下地Cuめっき槽、水洗槽、半田(Cu
−Bi系合金)めっき槽、水洗槽、熱風乾燥器、リフロ
ー炉(長さ1m)を順に配しためっき装置を用いた。半
田めっき層のBi濃度は種々に変化させた。黄銅線の走
行速度は、半田めっき層が図2に示した状態図の(L+
β)形成温度領域を外れない範囲で種々に変化させた。
The present invention will be described below in detail with reference to examples. (Example 1) Cu was plated on a 0.5 mmφ brass wire to a thickness of 1 μm, then an Sn—Bi alloy was electroplated, and then passed through a furnace set at 800 ° C. to produce a reflow solder plating material. did. The equipment includes an electrolytic degreasing tank, a washing tank, an pickling tank, a washing tank, a base Cu plating tank, a washing tank, a solder (Cu
-Bi-based alloy) A plating apparatus was used in which a plating tank, a washing tank, a hot air dryer, and a reflow furnace (length: 1 m) were sequentially arranged. The Bi concentration of the solder plating layer was changed variously. The traveling speed of the brass wire is represented by (L +
β) The formation temperature range was variously changed without departing from the range.

【0012】(比較例1) 黄銅線の走行速度を、その半田めっき層が図2に示した
状態図のL領域に達する速さに設定した他は、実施例1
と同じ方法によりリフロー半田めっき材を製造した。
Comparative Example 1 Example 1 was repeated except that the traveling speed of the brass wire was set to the speed at which the solder plating layer reached the L region in the state diagram shown in FIG.
A reflow solder plating material was manufactured in the same manner as in the above.

【0013】得られた各々のリフロー半田めっき材につ
いて、めっき層厚さ、めっき層の合金成分の濃度分布、
酸化量、および半田付性を調べた。前記酸化量と半田付
性は加熱後および加湿後について調べた。前記加熱は温
度155℃で8時間保持の条件で、前記加湿は温度10
0℃、相対湿度100%で8時間保持の条件でそれぞれ
行った。まためっき層表面の流れ模様の有無を観察し
た。結果を表1および図3、4に示す。調査方法は下記
の通りである。 〔めっき層厚さ〕 蛍光X線微小膜厚計により測定した。試料長さ30cm
あたり30箇所を測定した。表1には平均値と変動(標
準偏差)を示した。 〔めっき層の合金成分の濃度分布〕 蛍光X線分析計により測定した。試料長さ30cmあた
り30箇所を測定した。表1にはめっき層全体の平均値
とめっき層表面近傍の平均値を示した。 〔濃度分布〕 めっき層、下地層、および基材中のBi、Sn、Cu、
およびZnの厚さ方向の濃度分布をオージェ電子分光計
により測定した。 〔酸化量〕 カソード還元法により測定した。電解液に0.1NのK
Cl溶液を用い、電流密度0.1mA/cm2 の条件で
行った。 〔半田付性〕 メニスコグラフ法により調査した。すなわち、25%ロ
ジン/メタノールフラックスを塗布した試料を230℃
に保持した共晶半田浴に10秒間浸漬(浸漬速度2mm
/秒、浸漬深さ2mm)し、濡れ時間(ゼロクロスタイ
ム)により評価した。なお、濡れ時間は短い程半田付け
性に優れることを示す。
For each of the obtained reflow solder plating materials, the plating layer thickness, the concentration distribution of the alloy component of the plating layer,
The oxidation amount and solderability were examined. The oxidation amount and solderability were examined after heating and after humidification. The heating is performed at a temperature of 155 ° C. for 8 hours, and the humidification is performed at a temperature of 10 ° C.
Each test was carried out at 0 ° C. and 100% relative humidity for 8 hours. Also, the presence or absence of a flow pattern on the plating layer surface was observed. The results are shown in Table 1 and FIGS. The survey method is as follows. [Plating Layer Thickness] The thickness was measured with a fluorescent X-ray fine film thickness meter. Sample length 30cm
30 locations were measured per area. Table 1 shows the average value and the variation (standard deviation). [Concentration distribution of alloy component in plating layer] The concentration was measured by a fluorescent X-ray analyzer. 30 locations were measured per 30 cm of sample length. Table 1 shows the average value of the entire plating layer and the average value near the plating layer surface. [Concentration distribution] Bi, Sn, Cu in the plating layer, the underlayer, and the base material,
And Zn concentration distribution in the thickness direction were measured by an Auger electron spectrometer. [Oxidation amount] It was measured by a cathode reduction method. 0.1N K for electrolyte
The current density was 0.1 mA / cm 2 using a Cl solution. [Solderability] Investigation was performed by the meniscograph method. That is, a sample coated with 25% rosin / methanol flux was heated at 230 ° C.
For 10 seconds in a eutectic solder bath held at a speed of 2 mm
/ Sec, immersion depth 2 mm), and evaluated by the wetting time (zero cross time). The shorter the wetting time, the better the solderability.

【0014】[0014]

【表1】 [Table 1]

【0015】表1より明らかなように、本発明例 (No.1
3)はいずれも、めっき層の結晶粒界にBiリッチ相が
連続的に析出したため酸化量が少なく、また半田付性
(半田濡れ性)に優れた。まためっき層に流れ模様がな
く外観も良好であった。中でもリフロー処理速度が速く
リフロー処理後急速に冷却されたもの(No.1,2)は、図3
から明らかなように、Bi濃度の表面から内部への減少
が急激で、めっき層の表面近傍の所定厚さ内の結晶粒界
にBiリッチ相が非常に高濃度に析出したため、基材成
分の拡散が効率良く抑制され半田付性が特に向上した。
これに対し、比較例のNo.4,5は、リフロー処理速度が遅
いためリフロー処理温度が高くなりすぎて、めっき層表
面が結晶粒内にBiリッチ相がランダムに分散する組織
となり、Biリッチ相による基材成分の拡散防止効果が
得られず、まためっき層が溶融流動してめっき層に薄い
部分が生じ、この薄い部分にCuが大量に拡散して表面
が著しく酸化した。この酸化量の多いことが原因で半田
付性も低下した。まためっき層表面が流れ模様となり外
観不良となった。なお、比較例のNo.5のめっき層のBi
およびSnの濃度分布は、比較的冷却の速い最表面を除
き、厚さ方向にほぼ一定である。
As is clear from Table 1, the examples of the present invention (No. 1)
In all of the cases ( 3) to ( 3) , the Bi-rich phase was continuously precipitated at the crystal grain boundaries of the plating layer, so that the oxidation amount was small and the solderability (solder wettability) was excellent. In addition, the plating layer had no flowing pattern and the appearance was good. Among them, the reflow processing speed was high and those cooled rapidly after reflow processing (Nos. 1 and 2)
As can be seen from the table, the Bi concentration rapidly decreased from the surface to the inside, and the Bi-rich phase was precipitated at a very high concentration at the crystal grain boundaries within a predetermined thickness near the surface of the plating layer. Diffusion was suppressed efficiently and solderability was particularly improved.
On the other hand, in Comparative Examples Nos. 4 and 5 , the reflow treatment temperature was too high due to the slow reflow treatment speed, and the surface of the plating layer became a structure in which Bi-rich phases were randomly dispersed in the crystal grains, and Bi-rich The effect of preventing the diffusion of the base component by the phase was not obtained, and the plating layer melted and flowed to form a thin portion in the plating layer, and a large amount of Cu was diffused into the thin portion to significantly oxidize the surface. Due to the large amount of oxidation, the solderability was also reduced. In addition, the plating layer surface had a flowing pattern, resulting in poor appearance. The Bi of the No. 5 plating layer of the comparative example
The concentration distributions of Sn and Sn are almost constant in the thickness direction except for the outermost surface which is relatively fast to cool.

【0016】以上、導電性基体に黄銅線材を用いた例に
ついて説明したが、本発明は、他の金属材料を用いて
も、また形状が棒、条、板材などであっても同様の効果
が得られる。
Although the example in which the brass wire is used for the conductive substrate has been described above, the present invention can achieve the same effects even when other metal materials are used and the shape is a rod, a strip, a plate, or the like. can get.

【0017】[0017]

【発明の効果】以上に述べたように、本発明のリフロー
半田めっき材は、半田めっき層の結晶組織が基材の構成
元素の表面への拡散が生じ難い組織からなるので表面酸
化が抑制され、したがって半田付性に優れる。また本発
明のリフロー半田めっき材は、リフロー処理を適正な温
度条件で行うことにより容易に製造できる。依って、工
業上顕著な効果を奏する。
As described above, in the reflow solder plating material of the present invention, since the crystal structure of the solder plating layer is a structure in which the constituent elements of the base material hardly diffuse to the surface, surface oxidation is suppressed. Therefore, the solderability is excellent. Further, the reflow solder plating material of the present invention can be easily manufactured by performing the reflow treatment under appropriate temperature conditions. Therefore, an industrially remarkable effect is achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(イ)は本発明材のリフロー処理後の表面結晶組
織図、 (ロ)は従来材のリフロー処理後の表面結晶組織
図、 (ハ)はめっき上がり(リフロー処理前)材の表面
結晶組織図である。
1 (a) is a surface crystallographic structure of a material of the present invention after reflow treatment, (b) is a surface crystallographic structure of a conventional material after reflow treatment, and (c) is a material after plating (before reflow treatment). FIG. 3 is a surface crystal structure diagram.

【図2】Sn−Bi系合金の二元状態図である。FIG. 2 is a binary phase diagram of a Sn—Bi alloy.

【図3】本発明のリフロー半田めっき材のめっき層の表
面から内部へのSn、Bi、Cu、Znの各元素の濃度
分布図である。
FIG. 3 is a concentration distribution diagram of Sn, Bi, Cu, and Zn from the surface to the inside of a plating layer of a reflow solder plating material of the present invention.

【図4】従来のリフロー半田めっき材のめっき層の表面
から内部へのSn、Bi、Cu、Znの各元素の濃度分
布図である。
FIG. 4 is a concentration distribution diagram of each element of Sn, Bi, Cu, and Zn from the surface to the inside of a plating layer of a conventional reflow solder plating material.

【符号の説明】[Explanation of symbols]

10 Snリッチ相からなる結晶粒 20 Snリッチ相からなる結晶粒の境界(結晶粒界) 30 Biリッチ相 40 ランダムに分散したBiリッチ相 10 Crystal grains composed of Sn-rich phase 20 Boundaries (crystal grain boundaries) of crystal grains composed of Sn-rich phase 30 Bi-rich phase 40 Bi-rich phase randomly dispersed

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) C25D 5/50 B23K 35/26 H05K 3/34 Continuation of the front page (58) Field surveyed (Int. Cl. 7 , DB name) C25D 5/50 B23K 35/26 H05K 3/34

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 導電性基材上にSn−Bi系合金めっき
層が形成された半田めっき材において、前記Sn−Bi
系合金めっき層がリフロー処理されており、前記めっき
層の表面の結晶粒界にBiリッチ相が連続的に析出した
組織からなり、前記Sn−Bi系合金めっき層のBiの
濃度が、めっき層の表面から内部に向けて漸次減少して
いることを特徴とするリフロー半田めっき材。
1. A solder plating material in which a Sn—Bi-based alloy plating layer is formed on a conductive base material, wherein the Sn—Bi alloy
The alloy-based plating layer has been subjected to a reflow treatment, and has a structure in which a Bi-rich phase is continuously precipitated at a crystal grain boundary on the surface of the plated layer. A reflow solder plating material characterized by a gradual decrease from the surface to the inside.
【請求項2】 導電性基材上にBi濃度が共晶組成以下
Sn−Bi系合金めっき層を電気めっきし、次いでこ
れを前記Sn−Bi系合金の2相状態図の(L+β)形
成温度領域に加熱して高速でリフロー処理することを特
徴とする請求項1記載のリフロー半田めっき材の製造方
法。
2. The composition according to claim 1, wherein the Bi concentration on the conductive substrate is less than the eutectic composition.
The electroplating of the Sn-Bi-based alloy plating layer is performed, and then this is heated to the (L + β) forming temperature region of the two-phase phase diagram of the Sn-Bi-based alloy and reflowed at a high speed. 2. The method for producing a reflow solder plated material according to 1.
JP02837397A 1997-01-28 1997-01-28 Reflow solder plating material and method of manufacturing the same Expired - Lifetime JP3243195B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02837397A JP3243195B2 (en) 1997-01-28 1997-01-28 Reflow solder plating material and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02837397A JP3243195B2 (en) 1997-01-28 1997-01-28 Reflow solder plating material and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH111793A JPH111793A (en) 1999-01-06
JP3243195B2 true JP3243195B2 (en) 2002-01-07

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Family Applications (1)

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Country Status (1)

Country Link
JP (1) JP3243195B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3622462B2 (en) 1997-12-16 2005-02-23 株式会社日立製作所 Semiconductor device
JP3475910B2 (en) * 2000-05-24 2003-12-10 株式会社村田製作所 Electronic component, method of manufacturing electronic component, and circuit board
JP4535429B2 (en) * 2004-05-28 2010-09-01 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5059292B2 (en) * 2005-03-08 2012-10-24 株式会社神戸製鋼所 Sn alloy plating excellent in suppressing whisker generation
JP4961165B2 (en) * 2006-06-02 2012-06-27 日立協和エンジニアリング株式会社 Electronic component mounting substrate, electronic component and electronic device
JP4535464B2 (en) * 2007-10-26 2010-09-01 ルネサスエレクトロニクス株式会社 Manufacturing method of electronic equipment
JP5061168B2 (en) * 2009-09-17 2012-10-31 ルネサスエレクトロニクス株式会社 Manufacturing method of electronic equipment

Also Published As

Publication number Publication date
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