JP3222207B2 - 半導体デバイスとその製造方法 - Google Patents

半導体デバイスとその製造方法

Info

Publication number
JP3222207B2
JP3222207B2 JP18865292A JP18865292A JP3222207B2 JP 3222207 B2 JP3222207 B2 JP 3222207B2 JP 18865292 A JP18865292 A JP 18865292A JP 18865292 A JP18865292 A JP 18865292A JP 3222207 B2 JP3222207 B2 JP 3222207B2
Authority
JP
Japan
Prior art keywords
semiconductor device
auxiliary body
substrate
layer
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18865292A
Other languages
English (en)
Other versions
JPH05190759A (ja
Inventor
クーネルト ラインホルト
チユルケス ペーター
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH05190759A publication Critical patent/JPH05190759A/ja
Application granted granted Critical
Publication of JP3222207B2 publication Critical patent/JP3222207B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/8383—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Thyristors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】この発明は、下面を金属基板上に
取り付けられた半導体基体を備える半導体デバイス及び
その製造方法に関する。
【０００２】
【従来の技術】この種の半導体デバイスは例えば欧州特
許出願公開第0242626 号公報から知られている。その際
しばしば例えば負荷電流回路中のスイッチとしてこの種
のデバイスを使用する際に生じる短時間の熱負荷を前提
としなければならない。この種のパルス状負荷は、熱負
荷パルスが最大値を短時間でも超えるような半導体デバ
イスの温度をもたらさない限り、デバイスの破壊を招く
ことなく許容定常負荷を超えることができる。
【０００３】
【発明が解決しようとする課題】この発明の課題は、パ
ルス状熱負荷容量がこの種の従来のデバイスの熱負荷容
量を著しく超えるか、又は同等の熱負荷の場合の温度上
昇が従来のデバイスの温度上昇より著しく小さいよう
な、前記の種類の半導体デバイスを提供することにあ
る。
【０００４】
【課題を解決するための手段】この課題はこの発明に基
づき、下面を金属基板上に取り付けられた半導体基体を
備え、該基体の上面上に、熱緩衝体として働き熱伝導率
の大きい材料から成る補助体が取り付けられた半導体デ
バイスにおいて、半導体基体の上面上に、薄い絶縁層に
より覆われた導電性被膜が設けられ、この絶縁層と補助
体の下面との間に位置して、該絶縁層上にこれら部品間
の非常に小さい熱伝達抵抗を保証する結合層が設けられ
ることにより解決される。
【０００５】
【発明の効果】この発明により得られる長所は特に、熱
負荷パルスに基づく半導体デバイスの温度上昇が従来の
デバイスの場合より著しく小さいので、従来のデバイス
に比べて一層大きいパルス状熱負荷又は一層大きい定常
運転温度を許容できるということにある。
【０００６】この発明の有利な実施態様は請求項２ない
し６に記載されている。請求項７ないし１０はこの発明
に基づく半導体デバイスの有利な製造方法を示す。
【０００７】
【実施例】次にこの発明に基づく半導体デバイスの複数
の実施例を示す図面により、この発明を詳細に説明す
る。
【０００８】図１には、半導体デバイスの半導体基体１
が断面図で示されている。これは例えば垂直なｎｐｎｐ
層配列を有するサイリスタである。個々の層はｎ形エミ
ッタ２、ｐ形ベース３、ｎ形ベース４及びｐ形エミッタ
５と呼ばれる。ｐ形ベース３はトリガ電流パルスの供給
のための端子７を有するゲート電極６を備える。ｐ形ベ
ース３をｎ形ベース４から分離するｐｎ接合は符号８で
示されている。半導体基体１の下面９は例えばモリブデ
ンから成り陽極側端子Ａを備える金属基板１０上に取り
付けられている。基体１の上面１１上には、熱伝導率の
大きい金属から成り熱緩衝体として働くブロック形の補
助体１２が取り付けられている。補助体１２は銅、タン
グステン又はモリブデンから作られるのが特に有利であ
る。補助体１２は図１ではｎ形エミッタ２と接触する電
極として構成され、陰極側端子Ｋを備える陰極側リード
線１３と結合されている。
【０００９】半導体基体１の上面１１と補助体１２の下
面との間には結合層１４が設けられ、結合層１４はｎ形
エミッタ２と補助体１２との間の小さい熱伝達抵抗を保
証する。結合層１４は部品１と１２の結合の際に加圧焼
結法により生じる銀層とするのが有利である。他方では
結合層１４は部品１と１２の結合のために拡散溶接法を
用いる場合に、それぞれ相互に結合すべき面上に被着さ
れた接触層から形成することもできる。部品１と１２の
結合のために有利に利用できる加圧焼結法及び拡散溶接
法は後に詳述する。
【００１０】サイリスタが、端子Ａ、Ｋに接続され交流
電圧源のほかに負荷抵抗を備える負荷回路中に置かれ、
端子７に周期的に継続するトリガ電流パルス１５を供給
されると、サイリスタはそれぞれの個々のトリガ電流パ
ルスの発生の際に導通状態に切り換わり、部品１０、
１、１２を負荷電流が貫流する。各トリガ電流パルスに
続く交流電圧のゼロ点通過の際にサイリスタは再び阻止
されるので、一連の負荷電流パルスが生じ、その反復周
波数はトリガ電流パルス１５により決定される。負荷電
流パルスは部品１、１０、１２から成る装置の周期的な
パルス状熱負荷をもたらし、この負荷が装置の一定の基
本温度をもたらす。熱緩衝体である補助体１２によりこ
の装置の熱容量は大きいので、補助的な熱負荷パルスの
発生の際のサイリスタの付加的の温度上昇は部品１、１
０だけから成る同等の従来のサイリスタの場合より著し
く低い。従って図１に示す装置の場合には、所定の最大
デバイス温度を超えることなく従来のサイリスタより大
きいパルス状熱負荷を許容できる。このことは例えば個
々の負荷パルスの期間を従来可能であったより大きくで
きることを意味する。他方では負荷パルスの期間が同じ
場合に、最大デバイス温度を超えることなく内部に放出
される熱を大きくすることができる。
【００１１】大面積の接点としての補助体１２の図１に
示された構成は、端子ＡとＫの間を流れる負荷電流の均
一化に寄与する。更に補助体１２と結合されたリード線
１３を十分に大きい断面により構成できるので、負荷電
流が大きい場合に通常用いられ複数の細いリード線が相
互に並列に一つの同一の電極パターンと結合されるよう
な多重ボンディング法が回避される。
【００１２】図１に示された実施例の場合には、補助体
１２が半導体基体１の上面１１の通電領域に接触する大
面積の電極として構成されているが、図２は、半導体基
体１の上面上に大面積の導電性被膜が設けられ、その結
果補助体の電極としての構成がこの被膜の領域内では考
慮の対象とはならないようなサイリスタを示す。導電性
被膜は詳細には、ｎ形エミッタ２に接触する陰極側電極
１６と、ｐ形ベース３中に挿入されたｎ導電形領域１８
に接触しこの領域１８と共にサイリスタの内部トリガ増
幅部となる補助装置（増幅ゲート）を形成する被膜１７
と、中央に配置されたゲート電極６とから成る。補助体
１２はここでは薄い絶縁層１９上に取り付けられ、絶縁
層１９は導電性被膜６、１６、１７を電気的に絶縁し望
ましくは窒化シリコン（Ｓｉ3 Ｎ4 ）又はアモルファス
炭素から成る。補助体１２と薄い絶縁層１９との間には
更に結合層１４が設けられ、結合層１４は部品１と１２
の結合のために加圧焼結法を利用する場合に特に銀層か
ら形成されるか、又は拡散溶接法の実施の前にそれぞれ
薄い絶縁層１９の上面上及び補助体１２の下面上に塗布
された二つの接触層から生じる。その際結合層１４は部
品１と１２の間の熱伝達抵抗として働き、この抵抗は図
１に示すサイリスタの場合より大きいがしかしなお許容
できる。部品６、１６のためのリード線２０、２１が補
助体１２の前又は後ろに設けられ、このことは破線によ
る表示で示されかつ端子７、Ｋを備える。
【００１３】図３は、図１に示す半導体デバイスの変形
例を示し、この変形例の場合には補助体１２がはめ込ま
れた冷却板２２を備える。それにより半導体デバイスの
直流負荷容量が高められる。
【００１４】図１に示す半導体デバイスでは、部品１と
１２の結合はそれ自体公知の加圧焼結と呼ばれる低温結
合法に基づき行うのが有利であるが、この方法を図４に
より詳細に説明する。補助体１２の少なくとも下面に電
気めっきされた接触層２３が設けられ、接触層２３は約
２〜３μｍの厚さを有し例えば銀から成る。半導体基体
１の上面はｎ形エミッタ２の領域に層配列を被着され、
この層配列は約１μｍの厚さのアルミニウム層、その上
に被着され約１００ｎｍの厚さのチタン層、その上に設
けられ約５００ｎｍの厚さの例えばニッケル又は白金か
ら成る中央層、及び最後にこれを覆う約２００ｎｍの厚
さの銀層から成る。図４では、接触層として働く銀層だ
けが示され符号２４が付けられている。続いて接触層２
４上にペースト２５が層状に、しかも約１０〜１００μ
ｍ望ましくは約２０μｍの層厚で塗布される。ペースト
２５の製造のための出発物質として、溶媒としてのシク
ロヘキサノール中に懸濁した銀粉が用いられる。続いて
乾燥時の空洞発生を避けるために、そのように作られた
ペーストが真空中で脱気される。
【００１５】ペースト２５の乾燥後に補助体１２が接触
層２３と共に、半導体基体１のペースト２５により覆わ
れた接触層２４上に載せられ、部品１と１２から成る装
置が例えば２３０°Ｃの焼結温度にもたらされる。この
温度のもとで装置１、１２上に約１分の焼結時間の間少
なくとも９００Ｎ／ｃｍ2 の圧力が加えられる。しかし
既に数秒の焼結時間で前記部品１、１２の十分な結合が
達成され、また圧力を１〜２ｔ／ｃｍ2 に増加できるこ
とが指摘される。焼結温度は約１５０°Ｃの下限と約２
５０°Ｃの上限を有する範囲内に置くことができる。更
に加圧焼結が通常の雰囲気中で行われ、すなわち保護ガ
スの使用は不必要である。ペースト２５を補助的に又は
専ら接触層２３上に塗布することもできる。
【００１６】部品１と１２の結合のために適した別の低
温結合法は拡散溶接であり、拡散溶接を図５により説明
する。補助体１２の下面は接触層２３を備え、他方では
半導体基体１の上面はｎ形エミッタ２の領域に望ましく
は金又は銀から成る貴金属製接触層２４を設けられる。
接触層２４の下には、例えばＡｌ、Ａｇ、Ｃｕ又はＡｕ
から成り約１０〜２０μｍの層厚を備える金属の中間層
を設けるのが有利である。この中間層は相互に結合すべ
き面の表面粗さを補償するために塑性変形可能である。
中間層が貴金属から成る場合には接触層２４を省略する
こともできる。なぜならば接触層２４はこの場合に中間
層により置き替えられるからである。このようにして被
覆された部品１、１２は、補助体１２の下面が半導体基
体１の接触層２４と接触するように積み上げられる。続
いて部品１、１２は、例えば１５０〜２５０°Ｃの範囲
の温度、従って電力用半導体の運転温度に匹敵する適度
な温度領域にもたらされる。その際これらの部品は約５
００〜２５００ｋｐ／ｃｍ2 の圧力で数分の拡散時間中
押し付けられる。しかし僅か数秒の拡散時間で既に十分
な結果が得られる。他方では圧力を２．５ｔ／ｃｍ2 以
上に高めることができる。拡散溶接は保護ガスを使用せ
ず通常の雰囲気中で行われるので有利である。
【００１７】図６に示すように、図２に示す半導体デバ
イスの製造に際しては、半導体基体１の上面上にまず導
電性被膜６、１６、１７を覆う薄い絶縁層１９が被着さ
れ、そして絶縁層１９が接触層２４で覆われる。続いて
そのように被覆された半導体基体１と接触層２３を備え
る補助体１２との結合が、拡散溶接法によるか又はペー
スト２５を用いて加圧焼結法により行われる。
【００１８】部品１と１２の結合は例えばろう付け法に
より行うこともでき、ろう付け法の場合には鉛／スズろ
うを用いるのが有利である。
【００１９】この発明は、一つの半導体基体上にモノリ
シック集積されたすべての半導体デバイスに、例えばダ
イオード、サイリスタ、パワートランジスタ、パワーＭ
ＯＳＦＥＴ、絶縁ゲートバイポーラトランジスタなどに
用いることができる。半導体基体１がその上に置かれた
ｎ導電形領域をその下に置かれたｐ導電形領域から分離
するそれぞれただ一つのｐｎ接合８を有するときには、
例えばダイオードとして利用することもできる。その際
ゲート電極６及び導電性被膜１６、１７は省略される。
【図面の簡単な説明】
【図１】この発明に基づく半導体デバイスの一実施例の
側面図である。
【図２】半導体デバイスの別の実施例の側面図である。
【図３】半導体デバイスの更に別の実施例の側面図であ
る。
【図４】図１に示す半導体デバイスの製造方法の一実施
例を示す側面図である。
【図５】図１に示す半導体デバイスの製造方法の別の実
施例を示す側面図である。
【図６】図２に示す半導体デバイスの製造方法の一実施
例を示す側面図である。
【符号の説明】
１ 半導体基体 ６、１６、１７ 導電性被膜 ９ 下面 １０ 金属基板 １１ 上面 １２ 補助体 １３ リード線 １４ 結合層 １９ 絶縁層 ２２ 冷却板 ２３、２４ 接触層 ２５ ペースト
フロントページの続き (72)発明者 ペーター チユルケス ドイツ連邦共和国 8025 ウンターハツ ヒング ブサルトシユトラーセ 44 (56)参考文献 ***国特許出願公開3731624（ＤＥ, Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/62

Claims (10)

    (57)【特許請求の範囲】
  1. 【請求項１】 下面（９）を金属基板（１０）上に取り
    付けられた半導体基体（１）を備え、該基体（１）の上
    面（１１）上に、熱緩衝体として働き熱伝導率の大きい
    材料から成る補助体（１２）が取り付けられた半導体デ
    バイスにおいて、 前記基体（１）の上面（１１）上に、薄い絶縁層（１
    ９）により覆われた導電性被膜（６、１６、１７）が設
    けられ、この絶縁層（１９）と前記補助体（１２）の下
    面との間に位置して、前記絶縁層（１９）上にこれら部
    品間の非常に小さい熱伝達抵抗を保証する結合層（１
    ４）が設けられたことを特徴とする半導体デバイス。
  2. 【請求項２】 補助体（１２）が半導体基体（１）の上
    面（１１）の通電領域に接触する電極として構成され、
    一つ以上のリード線（１３）と結合されていることを特
    徴とする請求項１記載の半導体デバイス。
  3. 【請求項３】 補助体（１２）が銅、タングステン及び
    モリブデンを含む金属の群に属する金属から作られてい
    ることを特徴とする請求項１又は２記載の半導体デバイ
    ス。
  4. 【請求項４】 薄い絶縁層（１９）が窒化シリコン層と
    して構成されていることを特徴とする請求項１記載の半
    導体デバイス。
  5. 【請求項５】 薄い絶縁層（１９）がアモルファス炭素
    層として構成されていることを特徴とする請求項１記載
    の半導体デバイス。
  6. 【請求項６】 補助体（１２）が冷却板（２２）を備え
    ることを特徴とする請求項１ないし５の一つに記載の半
    導体デバイス。
  7. 【請求項７】 補助体（１２）が加圧焼結法により半導
    体基体（１）と結合され、その際金属粉及び溶媒から成
    るペースト（２５）が半導体基体（１）の接触層（２
    ４）を備える上面上に及び／又は補助体（１２）の下面
    上に塗布され、塗布されたペースト（２５）が乾燥させ
    られ、そして補助体（１２）の下面が半導体基体（１）
    の上面上に載せられ、そしてこの装置が焼結温度で少な
    くとも９００Ｎ／ｃｍ 2 の圧力により押圧されることを
    特徴とする請求項１ないし６の一つに記載の半導体デバ
    イスの製造方法。
  8. 【請求項８】 ペースト（２５）中に用いられる金属粉
    が銀粉から成ることを特徴とする請求項７記載の方法。
  9. 【請求項９】 補助体（１２）が拡散溶接法により半導
    体基体（１）と結合され、その際半導体基体（１）の上
    面及び補助体（１２）の下面がそれぞれ接触層（２４、
    ２３）を設けられ、次に補助体（１２）の下面が半導体
    基体（１）の上面上に載せられ、この装置が適度の温度
    で少なくとも約５００ｋｐ／ｃｍ 2 により押圧されるこ
    とを特徴とする請求項１ないし６の一つに記載の半導体
    デバイスの製造方法。
  10. 【請求項１０】 半導体基体（１）の上面を覆う接触層
    （２４）が、導電性被膜（６、１６、１７）を覆う薄い
    絶縁層（１９）上に被覆されることを特徴とする請求項
    ３記載の半導体デバイスの製造のための請求項７ないし
    ９の一つに記載の方法。
JP18865292A 1991-06-24 1992-06-22 半導体デバイスとその製造方法 Expired - Lifetime JP3222207B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4120827 1991-06-24
DE4120827.7 1991-06-24

Publications (2)

Publication Number Publication Date
JPH05190759A JPH05190759A (ja) 1993-07-30
JP3222207B2 true JP3222207B2 (ja) 2001-10-22

Family

ID=6434629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18865292A Expired - Lifetime JP3222207B2 (ja) 1991-06-24 1992-06-22 半導体デバイスとその製造方法

Country Status (4)

Country Link
US (2) US5300458A (ja)
EP (1) EP0520294B1 (ja)
JP (1) JP3222207B2 (ja)
DE (1) DE59209470D1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842196B2 (en) 2004-10-08 2010-11-30 Shin-Etsu Polymer Co., Ltd. Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4233073A1 (de) * 1992-10-01 1994-04-07 Siemens Ag Verfahren zum Herstellen eines Halbleiter-Modulaufbaus
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
US5672545A (en) * 1994-08-08 1997-09-30 Santa Barbara Research Center Thermally matched flip-chip detector assembly and method
DE10034262C1 (de) * 2000-07-14 2001-09-20 Infineon Technologies Ag Halbleitervorrichtung mit Temperaturregelung, insb. geeignet für den Kfz-Bereich
FR2847075B1 (fr) * 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
US7635637B2 (en) * 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
JP2007180456A (ja) * 2005-12-28 2007-07-12 Toyota Industries Corp 半田付け方法及び半導体モジュールの製造方法
DE102007022338B4 (de) * 2007-07-26 2013-12-05 Semikron Elektronik Gmbh & Co. Kg Herstellungsverfahren für ein Leistungshalbleiterbauelement mit Metallkontaktschicht
DE102007041124B4 (de) * 2007-08-30 2009-06-04 Infineon Technologies Ag Thyristor mit verbessertem Einschaltverhalten, Thyristoranordnung mit einem Thyristor, Verfahren zur Herstellung eines Thyristors und einer Thyristoranordnung
DE102009001028B4 (de) 2009-02-20 2011-02-17 Infineon Technologies Ag Verfahren zur Herstellung einer Bondverbindung
DE102010062453A1 (de) * 2010-12-06 2012-06-06 Robert Bosch Gmbh Halbleiterbauelement mit erhöhter Stabilität gegenüber thermomechanischen Einflüssen sowie Verfahren zur Kontaktierung eines Halbleiters
DE102011115887A1 (de) * 2011-10-15 2013-04-18 Danfoss Silicon Power Gmbh Leistungshalbleiterchip mit oberseitigen Potentialflächen
DE102011115886B4 (de) * 2011-10-15 2020-06-18 Danfoss Silicon Power Gmbh Verfahren zur Schaffung einer Verbindung eines Leistungshalbleiterchips mit oberseitigen Potentialflächen zu Dickdrähten
DE102014221687B4 (de) 2014-10-24 2019-07-04 Danfoss Silicon Power Gmbh Leistungshalbleitermodul mit kurzschluss-ausfallmodus
DE102015113421B4 (de) 2015-08-14 2019-02-21 Danfoss Silicon Power Gmbh Verfahren zum Herstellen von Halbleiterchips
JP7437582B2 (ja) 2018-04-11 2024-02-26 ヒタチ・エナジー・リミテッド パワー半導体チップ上の材料減少金属板
WO2024128062A1 (ja) * 2022-12-15 2024-06-20 ローム株式会社 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3731624A1 (de) 1987-09-19 1989-03-30 Asea Brown Boveri Ausgleichsronde fuer leistungshalbleitermodule

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343048A (en) * 1964-02-20 1967-09-19 Westinghouse Electric Corp Four layer semiconductor switching devices having a shorted emitter and method of making the same
US3928093A (en) * 1974-06-03 1975-12-23 Northern Electric Co Method for making a bi-directional solid state device
JPS5457976A (en) * 1977-10-18 1979-05-10 Mitsubishi Electric Corp Thyristor
JPS5778173A (en) * 1980-11-04 1982-05-15 Hitachi Ltd Semiconductor device and manufacture thereof
JPS59208758A (ja) * 1983-05-12 1984-11-27 Fuji Electric Co Ltd 複合半導体装置用半導体素子
US4607779A (en) * 1983-08-11 1986-08-26 National Semiconductor Corporation Non-impact thermocompression gang bonding method
FR2571923B1 (fr) * 1984-10-16 1987-02-20 Farco Sa Procede de soudage d'un composant electrique a un ensemble de pattes de connexion ainsi que machine et ruban pour la mise en oeuvre de ce procede
US4764809A (en) * 1985-03-15 1988-08-16 Ampex Corporation Apparatus and method for producing a variety of video wipe borders
JPS6279669A (ja) * 1985-10-03 1987-04-13 Mitsubishi Electric Corp 半導体装置
EP0220469B1 (de) * 1985-10-15 1989-12-06 Siemens Aktiengesellschaft Leistungsthyristor
JPS62194652A (ja) * 1986-02-21 1987-08-27 Hitachi Ltd 半導体装置
IN168174B (ja) * 1986-04-22 1991-02-16 Siemens Ag
EP0330896A3 (de) * 1988-03-03 1991-01-09 Siemens Aktiengesellschaft Verfahren zum Befestigen von Halbleiterbauelementen auf Substraten und Anordnungen zur Durchführung desselben
EP0330895B1 (de) * 1988-03-03 1994-12-14 Siemens Aktiengesellschaft Verfahren zum Befestigen von elektronischen Bauelementen auf Substraten und Anordnung zur Durchführung desselben
GB2222721B (en) * 1988-08-23 1993-07-28 Nobuo Mikoshiba Cooling semiconductor devices
US4848639A (en) * 1988-09-29 1989-07-18 Ag Communication Systems Corporation Compliant pad for use in tape automated bonding process
DE69018846T2 (de) * 1989-02-10 1995-08-24 Fujitsu Ltd Keramische Packung vom Halbleiteranordnungstyp und Verfahren zum Zusammensetzen derselben.
US5073521A (en) * 1989-11-15 1991-12-17 Olin Corporation Method for housing a tape-bonded electronic device and the package employed

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3731624A1 (de) 1987-09-19 1989-03-30 Asea Brown Boveri Ausgleichsronde fuer leistungshalbleitermodule

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842196B2 (en) 2004-10-08 2010-11-30 Shin-Etsu Polymer Co., Ltd. Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof
US8021579B2 (en) 2004-10-08 2011-09-20 Shin-Etsu Polymer Co., Ltd. Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof
US8035952B2 (en) 2004-10-08 2011-10-11 Shin-Etsu Polymer Co., Ltd. Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof

Also Published As

Publication number Publication date
JPH05190759A (ja) 1993-07-30
EP0520294B1 (de) 1998-08-26
US5436502A (en) 1995-07-25
DE59209470D1 (de) 1998-10-01
US5300458A (en) 1994-04-05
EP0520294A1 (de) 1992-12-30

Similar Documents

Publication Publication Date Title
JP3222207B2 (ja) 半導体デバイスとその製造方法
US7915144B2 (en) Methods for forming thermotunnel generators having closely-spaced electrodes
US8975117B2 (en) Semiconductor device using diffusion soldering
US4538170A (en) Power chip package
US7682875B2 (en) Method for fabricating a module including a sintered joint
US5047833A (en) Solderable front metal contact for MOS devices
US8987875B2 (en) Balanced stress assembly for semiconductor devices
US4835119A (en) Semiconductor device and a process of producing same
US3590339A (en) Gate controlled switch transistor drive integrated circuit (thytran)
US4862239A (en) Power semiconductor component
JPH0945891A (ja) 半導体デバイス
US20210028119A1 (en) Power Semiconductor Device and Manufacturing Method
JP2004014599A (ja) 半導体装置およびその製造方法
US3942244A (en) Semiconductor element
US20190295981A1 (en) Silicon Carbide Devices and Methods for Manufacturing the Same
JPS60176281A (ja) ショットキ障壁ダイオードの製造方法
US3702787A (en) Method of forming ohmic contact for semiconducting devices
CN107210280B (zh) 高功率的半导体装置的晶片金属化
JPH09237868A (ja) 半導体モジュール
JP3307145B2 (ja) パワーチップキャリア及びこれを用いたパワー半導体装置
US3979767A (en) Multilayer P-N junction semiconductor switching device having a low resistance path across said P-N junction
JPH01501027A (ja) 半導体構成要素
JPS62229973A (ja) 半導体装置
US11756923B2 (en) High density and durable semiconductor device interconnect
JPS6226582B2 (ja)

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20010712

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080817

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090817

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090817

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100817

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 10

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120817

Year of fee payment: 11

EXPY Cancellation because of completion of term