JP3222207B2 - 半導体デバイスとその製造方法 - Google Patents
半導体デバイスとその製造方法Info
- Publication number
- JP3222207B2 JP3222207B2 JP18865292A JP18865292A JP3222207B2 JP 3222207 B2 JP3222207 B2 JP 3222207B2 JP 18865292 A JP18865292 A JP 18865292A JP 18865292 A JP18865292 A JP 18865292A JP 3222207 B2 JP3222207 B2 JP 3222207B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- auxiliary body
- substrate
- layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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Description
取り付けられた半導体基体を備える半導体デバイス及び
その製造方法に関する。
許出願公開第0242626 号公報から知られている。その際
しばしば例えば負荷電流回路中のスイッチとしてこの種
のデバイスを使用する際に生じる短時間の熱負荷を前提
としなければならない。この種のパルス状負荷は、熱負
荷パルスが最大値を短時間でも超えるような半導体デバ
イスの温度をもたらさない限り、デバイスの破壊を招く
ことなく許容定常負荷を超えることができる。
ルス状熱負荷容量がこの種の従来のデバイスの熱負荷容
量を著しく超えるか、又は同等の熱負荷の場合の温度上
昇が従来のデバイスの温度上昇より著しく小さいよう
な、前記の種類の半導体デバイスを提供することにあ
る。
づき、下面を金属基板上に取り付けられた半導体基体を
備え、該基体の上面上に、熱緩衝体として働き熱伝導率
の大きい材料から成る補助体が取り付けられた半導体デ
バイスにおいて、半導体基体の上面上に、薄い絶縁層に
より覆われた導電性被膜が設けられ、この絶縁層と補助
体の下面との間に位置して、該絶縁層上にこれら部品間
の非常に小さい熱伝達抵抗を保証する結合層が設けられ
ることにより解決される。
負荷パルスに基づく半導体デバイスの温度上昇が従来の
デバイスの場合より著しく小さいので、従来のデバイス
に比べて一層大きいパルス状熱負荷又は一層大きい定常
運転温度を許容できるということにある。
し6に記載されている。請求項7ないし10はこの発明
に基づく半導体デバイスの有利な製造方法を示す。
の実施例を示す図面により、この発明を詳細に説明す
る。
が断面図で示されている。これは例えば垂直なnpnp
層配列を有するサイリスタである。個々の層はn形エミ
ッタ2、p形ベース3、n形ベース4及びp形エミッタ
5と呼ばれる。p形ベース3はトリガ電流パルスの供給
のための端子7を有するゲート電極6を備える。p形ベ
ース3をn形ベース4から分離するpn接合は符号8で
示されている。半導体基体1の下面9は例えばモリブデ
ンから成り陽極側端子Aを備える金属基板10上に取り
付けられている。基体1の上面11上には、熱伝導率の
大きい金属から成り熱緩衝体として働くブロック形の補
助体12が取り付けられている。補助体12は銅、タン
グステン又はモリブデンから作られるのが特に有利であ
る。補助体12は図1ではn形エミッタ2と接触する電
極として構成され、陰極側端子Kを備える陰極側リード
線13と結合されている。
面との間には結合層14が設けられ、結合層14はn形
エミッタ2と補助体12との間の小さい熱伝達抵抗を保
証する。結合層14は部品1と12の結合の際に加圧焼
結法により生じる銀層とするのが有利である。他方では
結合層14は部品1と12の結合のために拡散溶接法を
用いる場合に、それぞれ相互に結合すべき面上に被着さ
れた接触層から形成することもできる。部品1と12の
結合のために有利に利用できる加圧焼結法及び拡散溶接
法は後に詳述する。
電圧源のほかに負荷抵抗を備える負荷回路中に置かれ、
端子7に周期的に継続するトリガ電流パルス15を供給
されると、サイリスタはそれぞれの個々のトリガ電流パ
ルスの発生の際に導通状態に切り換わり、部品10、
1、12を負荷電流が貫流する。各トリガ電流パルスに
続く交流電圧のゼロ点通過の際にサイリスタは再び阻止
されるので、一連の負荷電流パルスが生じ、その反復周
波数はトリガ電流パルス15により決定される。負荷電
流パルスは部品1、10、12から成る装置の周期的な
パルス状熱負荷をもたらし、この負荷が装置の一定の基
本温度をもたらす。熱緩衝体である補助体12によりこ
の装置の熱容量は大きいので、補助的な熱負荷パルスの
発生の際のサイリスタの付加的の温度上昇は部品1、1
0だけから成る同等の従来のサイリスタの場合より著し
く低い。従って図1に示す装置の場合には、所定の最大
デバイス温度を超えることなく従来のサイリスタより大
きいパルス状熱負荷を許容できる。このことは例えば個
々の負荷パルスの期間を従来可能であったより大きくで
きることを意味する。他方では負荷パルスの期間が同じ
場合に、最大デバイス温度を超えることなく内部に放出
される熱を大きくすることができる。
示された構成は、端子AとKの間を流れる負荷電流の均
一化に寄与する。更に補助体12と結合されたリード線
13を十分に大きい断面により構成できるので、負荷電
流が大きい場合に通常用いられ複数の細いリード線が相
互に並列に一つの同一の電極パターンと結合されるよう
な多重ボンディング法が回避される。
12が半導体基体1の上面11の通電領域に接触する大
面積の電極として構成されているが、図2は、半導体基
体1の上面上に大面積の導電性被膜が設けられ、その結
果補助体の電極としての構成がこの被膜の領域内では考
慮の対象とはならないようなサイリスタを示す。導電性
被膜は詳細には、n形エミッタ2に接触する陰極側電極
16と、p形ベース3中に挿入されたn導電形領域18
に接触しこの領域18と共にサイリスタの内部トリガ増
幅部となる補助装置(増幅ゲート)を形成する被膜17
と、中央に配置されたゲート電極6とから成る。補助体
12はここでは薄い絶縁層19上に取り付けられ、絶縁
層19は導電性被膜6、16、17を電気的に絶縁し望
ましくは窒化シリコン(Si3 N4 )又はアモルファス
炭素から成る。補助体12と薄い絶縁層19との間には
更に結合層14が設けられ、結合層14は部品1と12
の結合のために加圧焼結法を利用する場合に特に銀層か
ら形成されるか、又は拡散溶接法の実施の前にそれぞれ
薄い絶縁層19の上面上及び補助体12の下面上に塗布
された二つの接触層から生じる。その際結合層14は部
品1と12の間の熱伝達抵抗として働き、この抵抗は図
1に示すサイリスタの場合より大きいがしかしなお許容
できる。部品6、16のためのリード線20、21が補
助体12の前又は後ろに設けられ、このことは破線によ
る表示で示されかつ端子7、Kを備える。
例を示し、この変形例の場合には補助体12がはめ込ま
れた冷却板22を備える。それにより半導体デバイスの
直流負荷容量が高められる。
12の結合はそれ自体公知の加圧焼結と呼ばれる低温結
合法に基づき行うのが有利であるが、この方法を図4に
より詳細に説明する。補助体12の少なくとも下面に電
気めっきされた接触層23が設けられ、接触層23は約
2〜3μmの厚さを有し例えば銀から成る。半導体基体
1の上面はn形エミッタ2の領域に層配列を被着され、
この層配列は約1μmの厚さのアルミニウム層、その上
に被着され約100nmの厚さのチタン層、その上に設
けられ約500nmの厚さの例えばニッケル又は白金か
ら成る中央層、及び最後にこれを覆う約200nmの厚
さの銀層から成る。図4では、接触層として働く銀層だ
けが示され符号24が付けられている。続いて接触層2
4上にペースト25が層状に、しかも約10〜100μ
m望ましくは約20μmの層厚で塗布される。ペースト
25の製造のための出発物質として、溶媒としてのシク
ロヘキサノール中に懸濁した銀粉が用いられる。続いて
乾燥時の空洞発生を避けるために、そのように作られた
ペーストが真空中で脱気される。
層23と共に、半導体基体1のペースト25により覆わ
れた接触層24上に載せられ、部品1と12から成る装
置が例えば230°Cの焼結温度にもたらされる。この
温度のもとで装置1、12上に約1分の焼結時間の間少
なくとも900N/cm2 の圧力が加えられる。しかし
既に数秒の焼結時間で前記部品1、12の十分な結合が
達成され、また圧力を1〜2t/cm2 に増加できるこ
とが指摘される。焼結温度は約150°Cの下限と約2
50°Cの上限を有する範囲内に置くことができる。更
に加圧焼結が通常の雰囲気中で行われ、すなわち保護ガ
スの使用は不必要である。ペースト25を補助的に又は
専ら接触層23上に塗布することもできる。
温結合法は拡散溶接であり、拡散溶接を図5により説明
する。補助体12の下面は接触層23を備え、他方では
半導体基体1の上面はn形エミッタ2の領域に望ましく
は金又は銀から成る貴金属製接触層24を設けられる。
接触層24の下には、例えばAl、Ag、Cu又はAu
から成り約10〜20μmの層厚を備える金属の中間層
を設けるのが有利である。この中間層は相互に結合すべ
き面の表面粗さを補償するために塑性変形可能である。
中間層が貴金属から成る場合には接触層24を省略する
こともできる。なぜならば接触層24はこの場合に中間
層により置き替えられるからである。このようにして被
覆された部品1、12は、補助体12の下面が半導体基
体1の接触層24と接触するように積み上げられる。続
いて部品1、12は、例えば150〜250°Cの範囲
の温度、従って電力用半導体の運転温度に匹敵する適度
な温度領域にもたらされる。その際これらの部品は約5
00〜2500kp/cm2 の圧力で数分の拡散時間中
押し付けられる。しかし僅か数秒の拡散時間で既に十分
な結果が得られる。他方では圧力を2.5t/cm2 以
上に高めることができる。拡散溶接は保護ガスを使用せ
ず通常の雰囲気中で行われるので有利である。
イスの製造に際しては、半導体基体1の上面上にまず導
電性被膜6、16、17を覆う薄い絶縁層19が被着さ
れ、そして絶縁層19が接触層24で覆われる。続いて
そのように被覆された半導体基体1と接触層23を備え
る補助体12との結合が、拡散溶接法によるか又はペー
スト25を用いて加圧焼結法により行われる。
より行うこともでき、ろう付け法の場合には鉛/スズろ
うを用いるのが有利である。
シック集積されたすべての半導体デバイスに、例えばダ
イオード、サイリスタ、パワートランジスタ、パワーM
OSFET、絶縁ゲートバイポーラトランジスタなどに
用いることができる。半導体基体1がその上に置かれた
n導電形領域をその下に置かれたp導電形領域から分離
するそれぞれただ一つのpn接合8を有するときには、
例えばダイオードとして利用することもできる。その際
ゲート電極6及び導電性被膜16、17は省略される。
側面図である。
る。
例を示す側面図である。
施例を示す側面図である。
例を示す側面図である。
Claims (10)
- 【請求項1】 下面(9)を金属基板(10)上に取り
付けられた半導体基体(1)を備え、該基体(1)の上
面(11)上に、熱緩衝体として働き熱伝導率の大きい
材料から成る補助体(12)が取り付けられた半導体デ
バイスにおいて、 前記基体(1)の上面(11)上に、薄い絶縁層(1
9)により覆われた導電性被膜(6、16、17)が設
けられ、この絶縁層(19)と前記補助体(12)の下
面との間に位置して、前記絶縁層(19)上にこれら部
品間の非常に小さい熱伝達抵抗を保証する結合層(1
4)が設けられたことを特徴とする半導体デバイス。 - 【請求項2】 補助体(12)が半導体基体(1)の上
面(11)の通電領域に接触する電極として構成され、
一つ以上のリード線(13)と結合されていることを特
徴とする請求項1記載の半導体デバイス。 - 【請求項3】 補助体(12)が銅、タングステン及び
モリブデンを含む金属の群に属する金属から作られてい
ることを特徴とする請求項1又は2記載の半導体デバイ
ス。 - 【請求項4】 薄い絶縁層(19)が窒化シリコン層と
して構成されていることを特徴とする請求項1記載の半
導体デバイス。 - 【請求項5】 薄い絶縁層(19)がアモルファス炭素
層として構成されていることを特徴とする請求項1記載
の半導体デバイス。 - 【請求項6】 補助体(12)が冷却板(22)を備え
ることを特徴とする請求項1ないし5の一つに記載の半
導体デバイス。 - 【請求項7】 補助体(12)が加圧焼結法により半導
体基体(1)と結合され、その際金属粉及び溶媒から成
るペースト(25)が半導体基体(1)の接触層(2
4)を備える上面上に及び/又は補助体(12)の下面
上に塗布され、塗布されたペースト(25)が乾燥させ
られ、そして補助体(12)の下面が半導体基体(1)
の上面上に載せられ、そしてこの装置が焼結温度で少な
くとも900N/cm 2 の圧力により押圧されることを
特徴とする請求項1ないし6の一つに記載の半導体デバ
イスの製造方法。 - 【請求項8】 ペースト(25)中に用いられる金属粉
が銀粉から成ることを特徴とする請求項7記載の方法。 - 【請求項9】 補助体(12)が拡散溶接法により半導
体基体(1)と結合され、その際半導体基体(1)の上
面及び補助体(12)の下面がそれぞれ接触層(24、
23)を設けられ、次に補助体(12)の下面が半導体
基体(1)の上面上に載せられ、この装置が適度の温度
で少なくとも約500kp/cm 2 により押圧されるこ
とを特徴とする請求項1ないし6の一つに記載の半導体
デバイスの製造方法。 - 【請求項10】 半導体基体(1)の上面を覆う接触層
(24)が、導電性被膜(6、16、17)を覆う薄い
絶縁層(19)上に被覆されることを特徴とする請求項
3記載の半導体デバイスの製造のための請求項7ないし
9の一つに記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4120827 | 1991-06-24 | ||
DE4120827.7 | 1991-06-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05190759A JPH05190759A (ja) | 1993-07-30 |
JP3222207B2 true JP3222207B2 (ja) | 2001-10-22 |
Family
ID=6434629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18865292A Expired - Lifetime JP3222207B2 (ja) | 1991-06-24 | 1992-06-22 | 半導体デバイスとその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US5300458A (ja) |
EP (1) | EP0520294B1 (ja) |
JP (1) | JP3222207B2 (ja) |
DE (1) | DE59209470D1 (ja) |
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DE102010062453A1 (de) * | 2010-12-06 | 2012-06-06 | Robert Bosch Gmbh | Halbleiterbauelement mit erhöhter Stabilität gegenüber thermomechanischen Einflüssen sowie Verfahren zur Kontaktierung eines Halbleiters |
DE102011115887A1 (de) * | 2011-10-15 | 2013-04-18 | Danfoss Silicon Power Gmbh | Leistungshalbleiterchip mit oberseitigen Potentialflächen |
DE102011115886B4 (de) * | 2011-10-15 | 2020-06-18 | Danfoss Silicon Power Gmbh | Verfahren zur Schaffung einer Verbindung eines Leistungshalbleiterchips mit oberseitigen Potentialflächen zu Dickdrähten |
DE102014221687B4 (de) | 2014-10-24 | 2019-07-04 | Danfoss Silicon Power Gmbh | Leistungshalbleitermodul mit kurzschluss-ausfallmodus |
DE102015113421B4 (de) | 2015-08-14 | 2019-02-21 | Danfoss Silicon Power Gmbh | Verfahren zum Herstellen von Halbleiterchips |
JP7437582B2 (ja) | 2018-04-11 | 2024-02-26 | ヒタチ・エナジー・リミテッド | パワー半導体チップ上の材料減少金属板 |
WO2024128062A1 (ja) * | 2022-12-15 | 2024-06-20 | ローム株式会社 | 半導体装置 |
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- 1992-06-22 JP JP18865292A patent/JP3222207B2/ja not_active Expired - Lifetime
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Cited By (3)
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---|---|---|---|---|
US7842196B2 (en) | 2004-10-08 | 2010-11-30 | Shin-Etsu Polymer Co., Ltd. | Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof |
US8021579B2 (en) | 2004-10-08 | 2011-09-20 | Shin-Etsu Polymer Co., Ltd. | Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof |
US8035952B2 (en) | 2004-10-08 | 2011-10-11 | Shin-Etsu Polymer Co., Ltd. | Conductive composition and production method thereof, antistatic coating material, antistatic coating, antistatic film, optical filter, and optical information recording medium, and capacitors and production method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH05190759A (ja) | 1993-07-30 |
EP0520294B1 (de) | 1998-08-26 |
US5436502A (en) | 1995-07-25 |
DE59209470D1 (de) | 1998-10-01 |
US5300458A (en) | 1994-04-05 |
EP0520294A1 (de) | 1992-12-30 |
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