JP3218294B2 - Logic integrated circuit - Google Patents
Logic integrated circuitInfo
- Publication number
- JP3218294B2 JP3218294B2 JP32408091A JP32408091A JP3218294B2 JP 3218294 B2 JP3218294 B2 JP 3218294B2 JP 32408091 A JP32408091 A JP 32408091A JP 32408091 A JP32408091 A JP 32408091A JP 3218294 B2 JP3218294 B2 JP 3218294B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- input
- signal
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、論理集積回路に関し、
特にスキャンパスを応用して、少ないテストパターンで
高い故障検出率を得ることを可能にした論理集積回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit,
In particular, the present invention relates to a logic integrated circuit that can obtain a high fault detection rate with a small number of test patterns by applying a scan path.
【0002】[0002]
【従来の技術】従来の論理集積回路はテスト(故障検出
テスト)容易化策の一つとして、スキャンパスを設け
て、スキャン動作によってテストパターン数が少なくて
も高い故障検出率を得るようにしていた。2. Description of the Related Art A conventional logic integrated circuit is provided with a scan path as one of the measures for facilitating a test (fault detection test) so that a high fault detection rate can be obtained by a scan operation even if the number of test patterns is small. Was.
【0003】[0003]
【発明が解決しようとする課題】この従来のやり方で
は、テスタ側においてスキャン動作を制御する機能を整
備することが必須であり、またテスタにスキャン動作機
能があっても、使用するテストパターン正当性の検証に
困難があり、有効な手段がないため、しばしばトラブル
が発生し殆んど実用化できていないのが実情と云う課題
があった。In this conventional method, it is essential to provide a function for controlling the scanning operation on the tester side, and even if the tester has a scanning operation function, the test pattern validity to be used is checked. However, there is a problem that the actual situation is that it is difficult to verify and that there is no effective means.
【0004】従って、本発明はスキャンパスの手法を応
用するが、通常のスキャンパス動作とは別の方法を用い
て、テストパターン正当性の検証も容易にでき、故障検
出率の高いテストパターンを容易に作成することのでき
る論理集積回路を提供しようとすることを目的としてい
る。Accordingly, although the present invention applies the scan path method, the validity of the test pattern can be easily verified using a method different from the normal scan path operation, and a test pattern having a high failure detection rate can be obtained. It is an object of the present invention to provide a logic integrated circuit that can be easily manufactured.
【0005】[0005]
【課題を解決するための手段】本発明の論理集積回路は
通常モードとシフトモードとテストモードの3つの実行
モードを選択制御する実行制御信号と、スキャンパス上
前段のF/Fの出力と、外部出力端子のチェックでは故
障検出困難な信号の中から適宜選択された信号とを入力
する排他的論理和回路あるいは外部出力端子のチェック
では故障検出困難な信号の中から適宜選択された2以上
の信号を入力する多入力排他的論理和回路と、前記実行
制御信号により、通常モード時に通常動作のデータ入力
を選択し、シフトモード時にスキャンパス上前段のF/
Fの出力を選択し、テストモード時に前記排他的論理和
回路あるいは多入力排他的論理和回路の出力を選択する
セレクタ回路を有している。According to the present invention, there is provided a logic integrated circuit comprising: an execution control signal for selectively controlling three execution modes of a normal mode, a shift mode, and a test mode; An exclusive OR circuit that inputs a signal appropriately selected from signals that are difficult to detect in the external output terminal or two or more signals that are appropriately selected from signals that are difficult to detect in the external output terminal A data input of a normal operation is selected in a normal mode by a multi-input exclusive-OR circuit for inputting a signal and the execution control signal.
A selector circuit for selecting the output of F and selecting the output of the exclusive OR circuit or the multi-input exclusive OR circuit in the test mode.
【0006】または故障検出が困難でかつ、通常“1”
である頻度の高い信号だけを適宜2以上集めて論理積回
路に入力し、該論理積回路の出力を排他的論理和回路あ
るいは多入力排他的論理和回路に入力する構成となって
いる。[0006] Or, failure detection is difficult and usually "1"
Only two or more frequent signals are appropriately collected and input to an AND circuit, and the output of the AND circuit is input to an exclusive OR circuit or a multi-input exclusive OR circuit.
【0007】または故障検出が困難でかつ、通常“0”
である頻度の高い信号だけを適宜2以上集めて論理和回
路に入力し、該論理和回路の出力を排他的論理和回路あ
るいは多入力排他的論理和回路に入力する構成となって
いる。[0007] Or, it is difficult to detect a failure and usually "0"
Only two or more frequently occurring signals are appropriately collected and input to an OR circuit, and the output of the OR circuit is input to an exclusive OR circuit or a multi-input exclusive OR circuit.
【0008】[0008]
【作用】上記の構成によれば、実行制御信号によってテ
ストモード実行時は、排他的論理和回路には前段のF/
Fの出力と、外部出力端子のチェックでは故障検出困難
な信号の中から適宜選択された信号が入力され、多入力
排他的論理和回路の場合には故障検出が困難な信号の中
から適宜選択された2以上の信号が入力されて、その出
力はセレクタ回路で選択してスキャンパス出力とされ
る。According to the above arrangement, when the test mode is executed by the execution control signal, the exclusive OR circuit has the F / F at the preceding stage.
An output of F and a signal appropriately selected from signals that are difficult to detect in the external output terminal check are input. In the case of a multi-input exclusive OR circuit, a signal is appropriately selected from signals that are difficult to detect in a fault. The received two or more signals are input, and the output is selected by a selector circuit to be a scan path output.
【0009】また、排他的論理和回路あるいは多入力排
他的論理和回路には、故障検出が困難でかつ、通常
“1”である頻度の高い信号だけを、適宜2以上集めて
論理積処理して、あるいは故障検出が困難でかつ、通常
“0”である頻度の高い信号だけを適宜2以上集めて論
理和処理して入力されるので、外部出力端子のチェック
では故障検出困難な内部回路の信号の故障検出が可能と
なる。Further, the exclusive OR circuit or the multi-input exclusive OR circuits, and is difficult to fault detection, only frequent signal is normally "1", and logical processing collected appropriately 2 or more Te or and difficult to fault detection, since the input to the processing logic sum collected by frequent signal is normally "0" as appropriate 2 or more, the check of the external output terminal of the failure detection difficult internal circuit Signal failure detection becomes possible.
【0010】[0010]
【実施例】次に本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0011】図1は本発明の第1の実施例の論理集積回
路図である。FIG. 1 is a logic integrated circuit diagram of a first embodiment of the present invention.
【0012】図においてランダム論理回路1はスキャン
パス回路及び本発明の主要部を除いた残りの回路を示し
ている。フリップフロップ(以下F/Fと呼ぶ)2には
クロック信号3とセレクタ回路4の出力が入力される。
セレクタ回路4は通常モードとシフトモードとテストモ
ードの3つの実行モードを選択する実行制御信号5によ
って、通常モード時データ信号6を選択出力し、シフト
モード時F/F2からの入力信号を選択出力し、テスト
モード時排他的論理和回路7からの入力信号を選択出力
する。In the figure, a random logic circuit 1 shows a scan path circuit and a circuit other than the main part of the present invention. The clock signal 3 and the output of the selector circuit 4 are input to a flip-flop (hereinafter referred to as F / F) 2.
The selector circuit 4 selectively outputs the data signal 6 in the normal mode by the execution control signal 5 for selecting three execution modes of the normal mode, the shift mode and the test mode, and selectively outputs the input signal from the F / F2 in the shift mode. In the test mode, the input signal from the exclusive OR circuit 7 is selectively output.
【0013】排他的論理和回路7はF/F2の出力と、
ランダム論理回路1の内部信号で、外部出力端子9のチ
ェックでは故障検出困難な信号の中から適宜選択された
信号8が入力される。The exclusive OR circuit 7 outputs the output of the F / F2,
A signal 8 which is an internal signal of the random logic circuit 1 and which is appropriately selected from signals whose failure is difficult to detect by checking the external output terminal 9 is input.
【0014】次に本実施例の動作について説明する。通
常モード時(一般の動作を行なう時)F/F2はクロッ
ク信号3のタイミングによって、セレクタ回路4によっ
て選択されたデータ信号6を取込んで本来の機能動作を
している。シフトモード時(F/F2への所望データの
セット、F/F2の内容の取出し等のためのモード)F
/F2はクロック信号3のタイミングによって、セレク
タ回路4によって選択された前段のF/F2の出力信号
を取込む。これをF/F2の数だけ繰返すことにより、
所望のデータを全F/F2にセットでき、あるいは全F
/F2の内容を取出すことができる。テストモード時
(故障の有無をテストするモード)F/F2はクロック
信号3のタイミングによって、セレクタ回路4及び排他
的論理和回路7を通して、前段のF/F2の出力とラン
ダム論理回路1の内部信号で適宜選択された、故障検出
困難な信号8との排他的論理和の結果を取込む。これに
より通常では故障検出困難な信号8の情報も所定のクロ
ックの後にはスキャンパス上に取り出されシフトされて
確実に最終段F/F2から外部端子に取出され、そこで
故障の存在が非常に高い精度でテストされる。Next, the operation of this embodiment will be described. In the normal mode (when performing a general operation), the F / F 2 takes in the data signal 6 selected by the selector circuit 4 at the timing of the clock signal 3 and performs the original functional operation. Shift mode (mode for setting desired data to F / F2, extracting contents of F / F2, etc.) F
/ F2 captures the output signal of the preceding F / F2 selected by the selector circuit 4 according to the timing of the clock signal 3. By repeating this for the number of F / F2,
Desired data can be set in all F / F2 or all F / F2
/ F2 can be extracted. In the test mode (mode for testing for the presence or absence of a failure), the F / F 2 outputs the output of the preceding F / F 2 and the internal signal of the random logic circuit 1 through the selector circuit 4 and the exclusive OR circuit 7 in accordance with the timing of the clock signal 3. The result of the exclusive OR with the signal 8 that is difficult to detect is selected as appropriate. As a result, the information of the signal 8, which is normally difficult to detect a failure, is also taken out on a scan path after a predetermined clock and shifted to be taken out from the final stage F / F2 to an external terminal without fail. Tested for accuracy.
【0015】図2は本発明の第2の実施例の論理集積回
路である。FIG. 2 shows a logic integrated circuit according to a second embodiment of the present invention.
【0016】第2実施例は大部分は前第1の実施例と同
じであるため、特に差異のある部分を中心に説明する。
セレクタ回路4はテストモード時多入力排他的論理和回
路17からの入力信号を選択出力し、その他のモード時
は第1の実施例と同じ動作をする。多入力排他的論理和
回路17は前段のF/F2の出力信号とランダム論理回
路1の内部信号で、適宜選択された2以上の故障検出困
難な信号18とを入力し、その全入力のエラー検出用パ
リティ信号を出力する。信号18の数は特に一定の数で
なくてもよく、場所によっては数が1の所があってもよ
い。Since the second embodiment is almost the same as the first embodiment, the description will focus on the parts that are particularly different.
The selector circuit 4 selects and outputs the input signal from the multi-input exclusive OR circuit 17 in the test mode, and operates the same as in the first embodiment in other modes. The multi-input exclusive-OR circuit 17 inputs the output signal of the previous stage F / F 2 and the internal signal of the random logic circuit 1 and two or more appropriately selected failure-detectable signals 18, and outputs an error of all inputs. A detection parity signal is output. The number of the signals 18 does not need to be a fixed number, and may be one at some places.
【0017】図3は本発明の第3の実施例を示す論理集
積回路図の一部を示す図である。FIG. 3 is a diagram showing a part of a logic integrated circuit diagram showing a third embodiment of the present invention.
【0018】図において、NANDゲート21の出力は
通常“1”である頻度が高く(ゲートへの5入力全ての
“1”“0”の頻度が等しいとすると確率31/32で
“1”出力)、またORゲート22の出力も同じく
“1”の頻度が高い。このようなゲート等の出力で、か
つその出力に故障があっても外部出力端子9では検出困
難な信号を2以上ANDゲート23で集め排他的論理和
回路7に取出し信号8として入力する。この場合、AN
Dゲート23はNANDゲートであっても同じであり、
効果は全く変わらない。In the figure, the output of the NAND gate 21 is normally "1" frequently (assuming that the frequencies of "1" and "0" of all five inputs to the gate are equal, "1" output with a probability of 31/32). ) And the output of the OR gate 22 also has a high frequency of "1". Two or more signals which are output from such gates and are difficult to detect at the external output terminal 9 even if the output has a failure are collected by the AND gate 23 and input to the exclusive OR circuit 7 as a takeout signal 8. In this case, AN
D gate 23 is the same even if it is a NAND gate,
The effect remains the same.
【0019】図4は本発明の第4の実施例を示す論理集
積回路図の一部を示す図である。FIG. 4 is a diagram showing a part of a logic integrated circuit diagram showing a fourth embodiment of the present invention.
【0020】図において、ANDゲート31の出力は通
常“0”である頻度が高く、またNORゲート32の出
力も同じく“0”の頻度が高い。このようなゲート等の
出力で、かつその出力に故障があっても検出困難な信号
を2以上ORゲート33で集め排他的論理和回路7に取
出した信号8を入力する。この場合ORゲート33はN
ORゲートであっても同じであり、効果は全く変わらな
い。なお、図3、図4の第3、4実施例では排他的論理
和回路7に取出した信号8を入力となっているが、これ
が図2の実施例に示した多入力の排他的論理和回路17
に取出し信号18を入力するものであってもよいことは
明らかである。In the figure, the output of the AND gate 31 is normally "0" frequently, and the output of the NOR gate 32 is also frequently "0". An OR gate 33 collects two or more signals output from such gates and the like, which are difficult to detect even if there is a failure in the output, and inputs the signal 8 to the exclusive OR circuit 7. In this case, the OR gate 33 is N
The same applies to the OR gate, and the effect is not changed at all. In the third and fourth embodiments of FIGS. 3 and 4, the signal 8 taken out to the exclusive OR circuit 7 is an input. Circuit 17
It is clear that the extraction signal 18 may be input to the second input terminal.
【0021】[0021]
【発明の効果】以上説明したように本発明は、外部出力
端子では故障検出困難な論理回路内部の信号を、排他的
論理和回路を通してスキャンパス通路内に挿入させ、シ
フト動作を行なわせてスキャンパス最終段のF/F出力
をチェックすることによって、非常に高い確率で故障検
出を可能とする効果がある。As described above, according to the present invention, a signal inside a logic circuit, which is difficult to detect a failure at an external output terminal, is inserted into a scan path path through an exclusive OR circuit to perform a shift operation. Checking the F / F output at the final stage of the campus has the effect of enabling failure detection with a very high probability.
【図1】本発明の第1の実施例による論理集積回路図で
ある。FIG. 1 is a logic integrated circuit diagram according to a first embodiment of the present invention.
【図2】本発明の第2の実施例による論理集積回路図で
ある。FIG. 2 is a logic integrated circuit diagram according to a second embodiment of the present invention.
【図3】本発明の第3の実施例による論理集積回路図で
ある。FIG. 3 is a logic integrated circuit diagram according to a third embodiment of the present invention.
【図4】本発明の第4の実施例による論理集積回路図で
ある。FIG. 4 is a logic integrated circuit diagram according to a fourth embodiment of the present invention.
1 ランダム論理回路 2 フリップフロップ 3 クロック信号 4 セレクタ回路 5 実行制御信号 6 データ信号 7 排他的論理和回路 8,18 故障検出困難な信号 9 外部入力端子 17 多入力排他的論理和回路 21 NANDゲート 22,33 ORゲート 23,31 ANDゲート 32 NORゲート DESCRIPTION OF SYMBOLS 1 Random logic circuit 2 Flip-flop 3 Clock signal 4 Selector circuit 5 Execution control signal 6 Data signal 7 Exclusive-OR circuit 8, 18 Failure-detection difficult signal 9 External input terminal 17 Multiple-input exclusive-OR circuit 21 NAND gate 22 , 33 OR gate 23, 31 AND gate 32 NOR gate
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) G01R 31/28 G06F 11/22 H01L 21/66 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) G01R 31/28 G06F 11/22 H01L 21/66
Claims (3)
シフトモードとテストモードの3つの実行モードを選択
制御する実行制御信号と、スキャンパス上前段のF/F
の出力と外部出力端子のチェックでは故障検出困難な信
号とを入力する排他的論理和回路と、 前記実行制御信号により通常モード時に通常動作のデー
タ入力を選択し、シフトモード時にスキャンパス上前段
のF/Fの出力を選択し、テストモード時に前記排他的
論理和回路の出力を選択するセレクタ回路とを有するこ
とを特徴とする論理集積回路。1. An execution control signal for selectively controlling three execution modes of a normal mode, a shift mode, and a test mode in a synchronous sequential circuit;
Failure detection difficult signal in the output and the external output terminal check
An exclusive-OR circuit for inputting a data signal during normal operation in the normal mode by the execution control signal, selecting an output of the F / F in the previous stage on the scan path in the shift mode, and selecting the output in the test mode. logic integrated circuit, characterized in that a selector circuit for selecting the output of the exclusive OR circuit.
頻度の高い信号だけを2以上集めて論理積回路に入力
し、該論理積回路の出力を前記排他的論理和回路の一方
に入力し、他方の入力をスキャンパス上前段のF/Fの
出力としたことを特徴とする請求項1記載の論理集積回
路。2. A input to the AND circuit by two or more collected frequent signal which is difficult to fault detection and usually "1", the output of the logical product circuit to one of the exclusive OR circuit 2. The logic integrated circuit according to claim 1, wherein the input is the other input and the other input is the output of the F / F at the preceding stage on the scan path.
頻度の高い信号だけを2以上集めて論理和回路に入力
し、該論理和回路の出力を前記排他的論理和回路の一方
に入力し、他方の入力をスキャンパス上前段のF/Fの
出力としたことを特徴とする請求項1記載の論理集積回
路。3. Enter only high failure detection frequent is difficult and usually "0" signal to two or more collected OR circuit, the output of said logical Liwa circuit to one of the exclusive OR circuit 2. The logic integrated circuit according to claim 1, wherein the input is the other input and the other input is the output of the F / F at the preceding stage on the scan path.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32408091A JP3218294B2 (en) | 1991-11-13 | 1991-11-13 | Logic integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32408091A JP3218294B2 (en) | 1991-11-13 | 1991-11-13 | Logic integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05134006A JPH05134006A (en) | 1993-05-28 |
JP3218294B2 true JP3218294B2 (en) | 2001-10-15 |
Family
ID=18161930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32408091A Expired - Fee Related JP3218294B2 (en) | 1991-11-13 | 1991-11-13 | Logic integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3218294B2 (en) |
-
1991
- 1991-11-13 JP JP32408091A patent/JP3218294B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH05134006A (en) | 1993-05-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5422891A (en) | Robust delay fault built-in self-testing method and apparatus | |
KR100265546B1 (en) | Method and system for identifying failure point | |
Ghosh-Dastidar et al. | Adaptive techniques for improving delay fault diagnosis | |
EP0151694B1 (en) | Logic circuit with built-in self-test function | |
JP3218294B2 (en) | Logic integrated circuit | |
US6789219B2 (en) | Arrangement and method of testing an integrated circuit | |
JP2837703B2 (en) | Fault diagnosis device | |
JP3147039B2 (en) | Integrated circuit | |
US5341314A (en) | Method for generating a test to detect differences between integrated circuits | |
JPH0587885A (en) | Generation of inspection series | |
US6691271B1 (en) | Built-in self-test apparatus | |
US6405336B1 (en) | Device and method for testing a semiconductor | |
JP2000304829A (en) | Semiconductor inspection method | |
JP2728793B2 (en) | Logic simulation equipment | |
Cheng | Test generation for delay faults in non-scan and partial scan sequential circuits | |
JP3107061B2 (en) | Test circuit | |
US20080092006A1 (en) | Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage | |
JP2990813B2 (en) | Failure simulation method | |
JPH0777562A (en) | Generation method for short circuit diagnostic data | |
JP3061972B2 (en) | Timing verification model | |
JP3317231B2 (en) | Skew verification method | |
JP2990158B1 (en) | Shift register circuit | |
JPH0540151A (en) | Scan path failure diagnosis method | |
Bareiša et al. | Properties of variable n-detection functional delay fault tests | |
JPH1090368A (en) | Semiconductor integrated circuit and its verifying method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070810 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080810 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080810 Year of fee payment: 7 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080810 Year of fee payment: 7 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |