JP3210094B2 - Capacitor and fluid sensor using the same - Google Patents
Capacitor and fluid sensor using the sameInfo
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- JP3210094B2 JP3210094B2 JP27104592A JP27104592A JP3210094B2 JP 3210094 B2 JP3210094 B2 JP 3210094B2 JP 27104592 A JP27104592 A JP 27104592A JP 27104592 A JP27104592 A JP 27104592A JP 3210094 B2 JP3210094 B2 JP 3210094B2
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- capacitor
- electrode
- electrodes
- insulated gate
- gate fet
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、電極間に注入される流
体による誘電率の変動に基づく静電容量の変化、または
流体圧力の変動による電極間の距離の変化に基づく静電
容量の変化を検知して流体の種類や流量や圧力を検知す
る汎用性を有するキャパシタ及びそれを用いた流体セン
サに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a change in capacitance based on a change in dielectric constant due to a fluid injected between electrodes, or a change in capacitance based on a change in distance between electrodes due to a change in fluid pressure. TECHNICAL FIELD The present invention relates to a versatile capacitor for detecting the type, flow rate, and pressure of a fluid by detecting a fluid, and a fluid sensor using the same.
【０００２】[0002]
【従来の技術】この種の流体センサで特にガスの種類を
検知するのに適したものとして、半導体ガスセンサが知
られている。この半導体ガスセンサは、感応体部と加熱
部とから成り、高温に保持された半導体にガスが触れる
と、そのガスの種類に応じて電気伝導度が変化する等の
原理を応用するものである。2. Description of the Related Art A semiconductor gas sensor is known as a fluid sensor of this type which is particularly suitable for detecting the type of gas. This semiconductor gas sensor is composed of a sensitive part and a heating part, and applies a principle such that when a gas contacts a semiconductor held at a high temperature, the electric conductivity changes according to the kind of the gas.
【０００３】[0003]
【発明が解決しようとする課題】上述した半導体ガスセ
ンサは、感応体部が高温に保持されるため、感応体自身
の劣化や基板との密着性の低下などにより、流体センサ
としての耐久性に問題を有している。そこで常温での電
気抵抗や静電容量等の変化を検知するものも考えられる
が、電気抵抗の変化を検知するものは、測定温度の影響
を受けやすく、静電容量の変化を検知するものは、一般
に検知感度がよくないという問題があり、検知感度をよ
くするには、電極間距離を小さくし、しかもばらつきを
小さくするため電極の製作が極めて困難で実用的ではな
かった。In the semiconductor gas sensor described above, since the sensitive body is maintained at a high temperature, the durability of the fluid sensor is deteriorated due to deterioration of the sensitive body itself and reduced adhesion to the substrate. have. Therefore, one that detects changes in electrical resistance and capacitance at room temperature can be considered, but those that detect changes in electrical resistance are susceptible to the measurement temperature, and those that detect changes in capacitance. However, in general, there is a problem that the detection sensitivity is not good. In order to improve the detection sensitivity, it is extremely difficult to manufacture the electrodes because the distance between the electrodes is reduced and the variation is reduced.
【０００４】本発明は、製作が容易でしかも電極間距離
が小さく且つばらつきの小さいキャパシタとそれを用い
た流体センサの提供を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor which is easy to manufacture, has a small distance between electrodes, and has a small variation, and a fluid sensor using the capacitor.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明のキャパシタ１は、２枚のシリコン基板２，
３の対向位置に異方性エッチングにより形状の等しいＶ
溝８，９，１０，１１を設け、直径の等しい絶縁円柱棒
１２，１３又は絶縁球を前記２枚のシリコン基板２，３
のＶ溝８，９，１０，１１間に介在させて、前記シリコ
ン基板２，３の対向平面部４，６に設けた１対の電極
５，７間の間隙を所定値ｇとしたものである。In order to achieve the above object, the capacitor 1 of the present invention comprises two silicon substrates 2,
3 having the same shape by anisotropic etching
Grooves 8, 9, 10, 11 are provided, and insulating cylinder rods 12, 13 or insulating spheres having the same diameter are attached to the two silicon substrates 2, 3, respectively.
The gap between the pair of electrodes 5 and 7 provided in the opposed flat portions 4 and 6 of the silicon substrates 2 and 3 is set to a predetermined value g by being interposed between the V-grooves 8, 9, 10 and 11. is there.
【０００６】また本発明の流体センサは、上記キャパシ
タ１と、絶縁ゲートＦＥＴ２０と、直流電源２１と、電
流計２２とを備え、キャパシタ１の電極５又は７と絶縁
ゲートＦＥＴ２０のゲート電極Ｇを接続し、キャパシタ
１の他方の電極７又は５と絶縁ゲートＦＥＴ２０のソー
ス電極Ｓとの間及び絶縁ゲートＦＥＴ２０のドレイン電
極Ｄとソース電極Ｓとの間に直流電源２１により直流電
圧を印加し、電流計２２によりドレイン電流を測定する
よう接続して成るものである。The fluid sensor of the present invention includes the above-mentioned capacitor 1, an insulated gate FET 20, a DC power supply 21, and an ammeter 22, and connects the electrode 5 or 7 of the capacitor 1 to the gate electrode G of the insulated gate FET 20. Then, a DC voltage is applied by the DC power supply 21 between the other electrode 7 or 5 of the capacitor 1 and the source electrode S of the insulated gate FET 20 and between the drain electrode D and the source electrode S of the insulated gate FET 20, and the ammeter is applied. 22 is connected to measure the drain current.
【０００７】[0007]
【作用】本発明のキャパシタ１は、２枚のシリコン基板
２，３の対向位置にＶ溝を異方性エッチングにより形成
するので、マスキングの位置、形状（正方形又は長方
形）、面積等を設定すれば、Ｖ溝の位置及び深さが決ま
る。また、前記２枚のシリコン基板２，３のＶ溝間に直
径の等しい絶縁円柱棒１２，１３又は絶縁球を介在させ
るので、電極の間隙設定が極めて正確で且つ容易であ
る。In the capacitor 1 of the present invention, V-grooves are formed by anisotropic etching at positions facing two silicon substrates 2 and 3, so that the masking position, shape (square or rectangular), area, etc. can be set. For example, the position and depth of the V-groove are determined. In addition, since the insulating cylindrical rods 12, 13 or insulating balls having the same diameter are interposed between the V grooves of the two silicon substrates 2, 3, the electrode gap setting is extremely accurate and easy.
【０００８】また前記電極を用いたセンサは、電極間容
量の変化により絶縁ゲートＦＥＴのゲート電極の電位が
変化し、そのためドレイン電流が鋭敏に変化する。Further, in the sensor using the electrodes, the potential of the gate electrode of the insulated gate FET changes due to the change in the capacitance between the electrodes, and therefore the drain current changes sharply.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面を参照しつつ説
明する。図１は本発明のキャパシタの側面断面図、図２
は図１のＡ−Ａ断面図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a side sectional view of a capacitor of the present invention, and FIG.
FIG. 2 is a sectional view taken along line AA of FIG.
【００１０】図１及び図２において、キャパシタ１は２
枚のシリコン基板２，３を対向させ、シリコン基板２，
３の対向平面部４，６に一対の電極５，７を設けて所定
間隔ｇで対向させたものである。ここで、所定間隔ｇは
例えば１０μｍ程度と微小間隔であり、正確な所定間隔
ｇの確保のために、シリコン基板２，３の対向位置に異
方性エッチングにより平行で深さの等しい２条のＶ溝
８，９，１０，１１を設け、直径の等しい絶縁円柱棒１
２，１３をＶ溝８，９，１０，１１間に介在させてい
る。In FIG. 1 and FIG.
Silicon substrates 2 and 3 are opposed to each other,
A pair of electrodes 5 and 7 are provided on the opposing flat portions 4 and 6 so as to oppose each other at a predetermined interval g. Here, the predetermined interval g is a minute interval of, for example, about 10 μm. In order to secure an accurate predetermined interval g, two rows of parallel and equal depths are anisotropically etched at opposing positions of the silicon substrates 2 and 3. V-grooves 8, 9, 10 and 11 are provided, and insulated cylindrical rod 1 having the same diameter.
2 and 13 are interposed between the V-grooves 8, 9, 10 and 11.
【００１１】シリコン基板２，３は断面Ｖ字型で平行な
２条のＶ溝８，９，１０，１１を対向平面部４，６の両
側に周知の異方性エッチングにより形成し、その後全体
を加熱して表面に二酸化シリコン被膜２ａ，３ａが形成
されたものである。そして、対向平面部４，６にアルミ
ニウムを蒸着後、パターニングにより一対の電極５，７
を設ける。電極５，７の端子５ａ，７ａも設けられる。
異方性エッチングはＶ溝８，９，１０，１１の開口に相
当する部分以外に二酸化シリコン被膜のパターンを形成
してマスキングし、ＥＤＰと呼ばれるエチレンジアミン
−ピロカテコール−水の混合液、それにさらにピラジン
を加えた混合液、ＣｓＯＨ等のアルカリ金属の水酸化物
又はヒドラジン等をエッチャントとするシリコンの異方
性エッチング技術でＶ溝８，９，１０，１１の部分をエ
ッチングで彫り込むものである。エッチャントとして
は、ＥＤＰにピラジンを加えた混合液が好ましく、混合
比率は、例えば次のようにするのが好ましい。 エチレンジアミン７．５ミリリットル、 ピロカ
テコール１．２グラム、 水１ミリリットル、 ピ
ラジン エチレンジアミン１リットルに対して６グラ
ム。 異方性エッチングにおいては、シリコン結晶体の性質上
｛１１１｝面が殆どエッチングされないので、Ｖ溝の開
口部の位置、形状（正方形又は長方形）、面積は、｛１
００｝面でのマスキングの位置、形状、面積を設定すれ
ば正確且つ簡単に設定できる。シリコン結晶体は、前記
マスキングの正方形又は矩形の各辺から｛１００｝面で
ある対向平面部４又は６に対して５４．７４度の角度で
腐食され、エッチングがＶ字状の底部に達した後は、そ
れ以上腐食されないので、Ｖ溝の深さは自ずから定ま
る。エッチング時間はこのＶ溝形成に必要な最低時間以
上であればよく、厳密な制御を必要としない。In the silicon substrates 2 and 3, two parallel V-shaped grooves 8, 9, 10, and 11 having a V-shaped cross section are formed on both sides of the opposing flat portions 4 and 6 by well-known anisotropic etching. Is heated to form silicon dioxide coatings 2a and 3a on the surfaces. Then, after vapor deposition of aluminum on the opposing flat portions 4, 6, a pair of electrodes 5, 7 is formed by patterning.
Is provided. Terminals 5a and 7a for the electrodes 5 and 7 are also provided.
In the anisotropic etching, a pattern of a silicon dioxide film is formed and masked at portions other than the portions corresponding to the openings of the V-grooves 8, 9, 10, and 11, and a mixed solution of ethylenediamine-pyrocatechol-water called EDP and further pyrazine The V-grooves 8, 9, 10, and 11 are etched by anisotropic etching technology of silicon using a mixed solution to which is added, an alkali metal hydroxide such as CsOH or hydrazine as an etchant. As the etchant, a mixed solution obtained by adding pyrazine to EDP is preferable, and the mixing ratio is preferably, for example, as follows. 7.5 ml of ethylenediamine, 1.2 g of pyrocatechol, 1 ml of water, pyrazine 6 g per liter of ethylenediamine. In the anisotropic etching, since the {111} plane is hardly etched due to the nature of the silicon crystal, the position, shape (square or rectangular), and area of the opening of the V-groove are {1}
If the position, shape and area of the masking on the 00 ° plane are set, it can be set accurately and easily. The silicon crystal was eroded at an angle of 54.74 degrees from each side of the masking square or rectangle to the opposing plane portion 4 or 6, which is the {100} plane, and the etching reached the V-shaped bottom. Thereafter, the depth of the V-groove is determined by itself because it is not corroded any more. The etching time may be longer than the minimum time required for forming the V-groove, and strict control is not required.
【００１２】シリコン基板２，３のＶ溝８，９，１０，
１１にスペーサとして介在させる絶縁円柱棒１２，１３
は直径が小さく均一なものでなければならないので、光
ファイバを用いることが好ましい。光ファイバとして
は、例えば汎用されている直径１２５μｍのものを流用
し、Ｖ溝８，９，１０，１１の深さを調整することによ
り、電極５，７間を例えば１０μｍとすることができ
る。また、絶縁円柱棒１２，１３に代わり、絶縁球を用
いることもできる。この絶縁球として液晶スペーサに用
いられるジビニルベンゼン系の真球状ポリマー粒子を流
用できる。この時、Ｖ溝８，９，１０，１１に絶縁球を
列設してもよく、２条の平行なＶ溝に代わって四角錐の
Ｖ溝とし電極５，７の周囲に３か所以上配設し絶縁球を
一個ずつスペーサとして用いるものでもよい。V-grooves 8, 9, 10 in silicon substrates 2, 3
Insulated cylindrical rods 12, 13 interposed as spacers in 11
It is preferable to use an optical fiber because the diameter must be small and uniform. For example, a commonly used optical fiber having a diameter of 125 μm can be used and the depth between the V-grooves 8, 9, 10, and 11 can be adjusted to make the distance between the electrodes 5 and 7 at 10 μm, for example. Further, insulating balls can be used instead of the insulating cylindrical rods 12 and 13. As the insulating sphere, divinylbenzene-based spherical polymer particles used for a liquid crystal spacer can be used. At this time, insulating spheres may be arranged in the V-grooves 8, 9, 10, and 11, and instead of two parallel V-grooves, V-shaped square pyramids may be used at three or more places around the electrodes 5, 7. It is also possible to dispose the insulating balls one by one as a spacer.
【００１３】つぎに、上述したキャパシタ１の作動を図
１及び図４により説明する。シリコン基板２，３のＶ溝
８，９，１０，１１にスペーサとしての絶縁円柱棒１
２，１３が介在されることにより水平方向の位置決めが
なされる。また、Ｖ溝８，９，１０，１１の深さＨと絶
縁円柱棒１２，１３の直径が厳密な寸法であるため、電
極５，７の間隙ｇは例えば１０μｍの如き微小間隙を確
保できる。図４において、Ｖ溝の横断面をＡＣＡ、これ
に載置した光ファイバ断面の中心をＯ、直線ＯＣと直線
ＡＡの交点をＢとし、光ファイバ断面の中心ＯからＶ溝
の辺ＡＣに下ろした垂線の足をＰとすると、∠ＣＯＰは
∠ＣＡＢ＝αに等しい。角αは、｛１００｝面である対
向平面部６と｛１１１｝面であるＡＣ面とのなす角度で
あり、５４．７４度となる。したがって、光ファイバの
半径をＲ、ＯＣの長さをＸ、Ｖ溝の深さをＨ、Ｖ溝の幅
をＷとすると、電極間ギャップｇは下記の数式４によっ
て得られる。Next, the operation of the above-described capacitor 1 will be described with reference to FIGS. Insulating cylindrical rods 1 as spacers in V-grooves 8, 9, 10, 11 of silicon substrates 2, 3
The positioning in the horizontal direction is performed by the interposition of 2 and 13. Also, since the depth H of the V-grooves 8, 9, 10, 11 and the diameter of the insulating cylindrical rods 12, 13 are strict dimensions, the gap g between the electrodes 5, 7 can secure a minute gap of, for example, 10 μm. In FIG. 4, the cross section of the V-groove is ACA, the center of the cross-section of the optical fiber placed thereon is O, the intersection of the straight line OC and the straight line A is B, and the center O of the cross-section of the optical fiber is lowered to the side AC of the V-groove. Assuming that the leg of the vertical line is P, ∠COP is equal to ∠CAB = α. The angle α is an angle formed between the opposing plane portion 6 that is the {100} plane and the AC plane that is the {111} plane, and is 54.74 degrees. Therefore, assuming that the radius of the optical fiber is R, the length of the OC is X, the depth of the V groove is H, and the width of the V groove is W, the gap g between the electrodes is obtained by the following equation (4).
【００１４】 Ｘ＝Ｒ／ｃｏｓα ・・・数式１ Ｈ＝（Ｗｔａｎα）／２ ・・・数式２ ｇ＝２（Ｘ−Ｈ−δ） ・・・数式３ 数式３に数式１，２を代入すると、 ｇ＝２（Ｒ／ｃｏｓα−Ｗｔａｎα／２−δ） ・・・数式４ となる。X = R / cos α Equation 1 H = (Wtanα) / 2 Equation 2 g = 2 (X−H−δ) Equation 3 Substituting Equations 1 and 2 into Equation 3. , G = 2 (R / cos α−Wtan α / 2−δ) Expression 4
【００１５】電極間ギャップｇは、上記数式から明らか
なように、光ファイバ半径Ｒ、Ｖ溝深さＨ又はＶ溝幅
Ｗ、電極厚さδを適宜選択することにより、所望の値と
することができる。さらに、シリコン基板２，３の二酸
化シリコン被膜は流体によって腐食されにくいものであ
り、電極５，７も流体によって腐食されにくい金属電極
を使用すると、キャパシタ１の耐久性が向上する。As is clear from the above equation, the gap g between the electrodes is set to a desired value by appropriately selecting the radius R of the optical fiber, the depth H of the V-groove or the width W of the V-groove, and the electrode thickness δ. Can be. Furthermore, the silicon dioxide films on the silicon substrates 2 and 3 are hardly corroded by a fluid, and the use of metal electrodes that are hardly corroded by the fluid for the electrodes 5 and 7 improves the durability of the capacitor 1.
【００１６】図３は本発明のキャパシタを用いた流体セ
ンサのブロック図である。図において、１はキャパシ
タ、２０は絶縁ゲートＦＥＴ、２１は直流電源、２２は
電流計である。そして、流体センサは、絶縁ゲートＦＥ
Ｔ２０のゲート電極Ｇをキャパシタ１の一方の電極７ａ
に接続し、絶縁ゲートＦＥＴ２０のソース電極Ｓを直流
電源２１ａを介してキャパシタ１の他方の電極５ａに接
続し、絶縁ゲートＦＥＴ２０のドレイン電極Ｄとソース
電極Ｓとの間に電流計２２及び直流電源２１ｂを接続す
る構成である。絶縁ゲートＦＥＴとしては、一般にＭＯ
ＳＦＥＴが用いられる。FIG. 3 is a block diagram of a fluid sensor using the capacitor of the present invention. In the figure, 1 is a capacitor, 20 is an insulated gate FET, 21 is a DC power supply, and 22 is an ammeter. The fluid sensor is an insulated gate FE
The gate electrode G of T20 is connected to one electrode 7a of the capacitor 1.
The source electrode S of the insulated gate FET 20 is connected to the other electrode 5a of the capacitor 1 via the DC power supply 21a, and the ammeter 22 and the DC power supply are connected between the drain electrode D and the source electrode S of the insulated gate FET 20. 21b is connected. Insulated gate FETs are generally MO
An SFET is used.
【００１７】このような構成の流体センサにおいて、直
流電源２１ａによって印加される電圧は、キャパシタ１
の第１，第２電極５，７間の静電容量と絶縁ゲートＦＥ
Ｔ２０の絶縁ゲートの静電容量とによって分圧され、絶
縁ゲートＦＥＴ２０のゲート電極Ｇに特定電圧が印加さ
れる。ゲート電極Ｇに印加される特定電圧に対応し、絶
縁ゲートＦＥＴ２０のドレイン電極Ｄからソース電極Ｓ
へと電流が流れ、その電流値が電流計２２で計測され
る。ここで、キャパシタ１の電極間に誘電率の異なる流
体が流れると、電極間の静電容量が変化し、絶縁ゲート
ＦＥＴ２０のゲート電極Ｇに印加される電圧も変化し、
電流計２２で計測される電流値も変わって特定流体の存
在が検出される。また、キャパシタ１に作用する流体圧
で電極の間隙が変わっても同様に電流計２２で検出で
き、流体圧センサとしても使用できる。図３において、
絶縁ゲートＦＥＴ２０はｎチャネル型のＭＯＳＦＥＴと
したが、ｐチャネル型のものを用いてもよい。また、直
流電源２１ａ，２１ｂが同じ電圧のものでよい場合は、
１個にまとめてもよい。さらに、ドレイン電流検出手段
２２としては電流計のほか、キャパシタ１の静電容量の
変化に対応する充放電時間を測定するものなど種々の回
路が考えられる。In the fluid sensor having such a configuration, the voltage applied by the DC power supply 21a
Between the first and second electrodes 5 and 7 and the insulating gate FE
The voltage is divided by the capacitance of the insulated gate of T20, and a specific voltage is applied to the gate electrode G of the insulated gate FET20. Corresponding to a specific voltage applied to the gate electrode G, the drain electrode D to the source electrode S
, And the current value is measured by the ammeter 22. Here, when fluids having different dielectric constants flow between the electrodes of the capacitor 1, the capacitance between the electrodes changes, and the voltage applied to the gate electrode G of the insulated gate FET 20 also changes.
The current value measured by the ammeter 22 also changes, and the presence of the specific fluid is detected. Further, even if the gap between the electrodes changes due to the fluid pressure acting on the capacitor 1, it can be similarly detected by the ammeter 22 and used as a fluid pressure sensor. In FIG.
Although the insulated gate FET 20 is an n-channel MOSFET, a p-channel MOSFET may be used. When the DC power supplies 21a and 21b may be of the same voltage,
They may be combined into one. Furthermore, as the drain current detecting means 22, various circuits such as an ammeter and a circuit for measuring a charging / discharging time corresponding to a change in the capacitance of the capacitor 1 can be considered.
【００１８】[0018]
【発明の効果】本発明のキャパシタは、２枚のシリコン
基板２，３のＶ溝８，９，１０，１１を異方性エッチン
グにより形成するので、マスキングの位置、形状（正方
形又は長方形）、面積等を設定すれば、Ｖ溝の位置及び
深さが定まり、エッチング時間も一定時間以上であれば
よく、厳密な制御を必要としない。また、前記２枚のシ
リコン基板２，３のＶ溝間に直径の等しい絶縁円柱棒１
２，１３又は絶縁球を介在させるだけで電極の間隙設定
ができるので、製作が容易でしかも電極間距離が小さく
且つバラツキの小さいものを量産できる。According to the capacitor of the present invention, the V-grooves 8, 9, 10, 11 of the two silicon substrates 2, 3 are formed by anisotropic etching, so that the masking position, shape (square or rectangular), If the area and the like are set, the position and the depth of the V-groove are determined, and the etching time only needs to be a certain time or longer, and strict control is not required. An insulating cylindrical rod 1 having the same diameter between the V grooves of the two silicon substrates 2 and 3.
Since the gap between the electrodes can be set only by interposing the insulating balls 2 and 13 or insulating balls, it is possible to mass-produce products that are easy to manufacture and have a small distance between the electrodes and small variations.
【００１９】また、上記キャパシタを用いた流体センサ
は、電極間容量の変化により絶縁ゲートＦＥＴ２０のゲ
ート電極Ｇの電位が変化し、そのためドレイン電流が鋭
敏に変化するので、流体の種類や流量や圧力を高い精度
で検出できる。In the fluid sensor using the above-described capacitor, the potential of the gate electrode G of the insulated gate FET 20 changes due to the change in the interelectrode capacitance, and the drain current changes sharply. Can be detected with high accuracy.
【図１】本発明のキャパシタの側面断面図である。FIG. 1 is a side sectional view of a capacitor of the present invention.
【図２】図１のＡ−Ａ断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明のキャパシタを用いた流体センサのブロ
ック図である。FIG. 3 is a block diagram of a fluid sensor using the capacitor of the present invention.
【図４】本発明のキャパシタの電極間間隙ｇの算出方法
説明図である。FIG. 4 is a diagram illustrating a method for calculating a gap g between electrodes of a capacitor according to the present invention.
１ キャパシタ ２，３ シリコン基板 ４，６ 対向平面部 ５，７ 電極 ８，９，１０，１１ Ｖ溝 １２，１３ 絶縁円柱棒 ２０ 絶縁ゲートＦＥＴ ２１ 直流電源 ２２ ドレイン電流検出手段 DESCRIPTION OF SYMBOLS 1 Capacitor 2,3 Silicon substrate 4,6 Opposing plane part 5,7 Electrode 8,9,10,11 V groove 12,13 Insulated cylindrical rod 20 Insulated gate FET 21 DC power supply 22 Drain current detecting means
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小川 倉一 兵庫県神戸市垂水区狩口台７丁目18番７ 号 (72)発明者 柴原 庸介 大阪府東大阪市岩田町２丁目３番１号 タツタ電線株式会社内 (56)参考文献 特開 平２−249936（ＪＰ，Ａ) 特開 平３−134570（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) G01N 27/00 - 27/24 G01L 9/12 ＪＩＣＳＴファイル（ＪＯＩＳ)──────────────────────────────────────────────────続 き Continuing on the front page (72) Kuraichi Ogawa 7-18-7, Kariguchidai, Tarumi-ku, Kobe City, Hyogo Prefecture (72) Yosuke Shibahara 2-3-1, Iwatacho, Higashiosaka City, Osaka Tatsuta Electric Wire (56) References JP-A-2-249936 (JP, A) JP-A-3-134570 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) G01N 27/00 -27/24 G01L 9/12 JICST file (JOIS)
Claims (2)
置に異方性エッチングにより形状の等しいＶ溝（８，
９，１０，１１）を設け、直径の等しい絶縁円柱棒（１
２，１３）又は絶縁球を前記２枚のシリコン基板（２，
３）のＶ溝（８，９，１０，１１）間に介在させて、前
記シリコン基板（２，３）の対向平面部（４，６）に設
けた１対の電極（５，７）間の間隙を所定値（ｇ）とし
たキャパシタ。A V-groove (8, 8) having the same shape is formed by anisotropic etching at a position facing two silicon substrates (2, 3).
9, 10, 11), and insulated cylindrical rods (1
2, 13) or insulating spheres on the two silicon substrates (2, 13).
3) between the pair of electrodes (5, 7) provided on the opposed plane portions (4, 6) of the silicon substrate (2, 3), interposed between the V grooves (8, 9, 10, 11) of A capacitor having a predetermined gap (g).
絶縁ゲートＦＥＴ（２０）と、直流電源（２１）と、電
流計（２２）とを備え、キャパシタ（１）の一方の電極
（５又は７）と絶縁ゲートＦＥＴ（２０）のゲート電極
（Ｇ）を接続し、キャパシタ（１）の他方の電極（７又
は５）と絶縁ゲートＦＥＴ（２０）のソース電極（Ｓ）
との間及び絶縁ゲートＦＥＴ（２０）のドレイン電極
（Ｄ）とソース電極（Ｓ）との間に直流電源（２１）に
より直流電圧を印加し、電流計（２２）によりドレイン
電流を測定するよう接続して成る流体センサ。2. A capacitor (1) according to claim 1,
An insulated gate FET (20), a DC power supply (21), and an ammeter (22) are provided. One electrode ( 5 or 7 ) of the capacitor (1) and a gate electrode (G) of the insulated gate FET (20) are provided. And the other electrode of the capacitor (1) ( 7 or
5 ) and the source electrode (S) of the insulated gate FET (20)
And a drain voltage is applied between the drain electrode (D) and the source electrode (S) of the insulated gate FET (20) by the DC power supply (21), and the drain current is measured by the ammeter (22). Fluid sensor connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27104592A JP3210094B2 (en) | 1992-09-14 | 1992-09-14 | Capacitor and fluid sensor using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27104592A JP3210094B2 (en) | 1992-09-14 | 1992-09-14 | Capacitor and fluid sensor using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0694665A JPH0694665A (en) | 1994-04-08 |
| JP3210094B2 true JP3210094B2 (en) | 2001-09-17 |
Family
ID=17494639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27104592A Expired - Fee Related JP3210094B2 (en) | 1992-09-14 | 1992-09-14 | Capacitor and fluid sensor using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3210094B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5076364B2 (en) * | 2006-06-01 | 2012-11-21 | カシオ計算機株式会社 | Semiconductor sensor and identification method |
-
1992
- 1992-09-14 JP JP27104592A patent/JP3210094B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0694665A (en) | 1994-04-08 |
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