JP3205272B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3205272B2 JP3205272B2 JP28303396A JP28303396A JP3205272B2 JP 3205272 B2 JP3205272 B2 JP 3205272B2 JP 28303396 A JP28303396 A JP 28303396A JP 28303396 A JP28303396 A JP 28303396A JP 3205272 B2 JP3205272 B2 JP 3205272B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- layer
- conductive
- integrated circuit
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、Ｔ・ＢＧＡ型の半
導体装置に係り、特に集積回路素子の複数の電極パッド
と外部配線基板の接続パッドとを接続するインターポー
ザとして、導体回路パターン層、導電プレーン層から成
る２層構造の導体回路パターン層を備えた集積回路素子
搭載基板を構成部材とする半導体装置の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a T.BGA type semiconductor device, and more particularly, to a semiconductor circuit pattern layer, a conductive circuit pattern layer, and an interposer for connecting a plurality of electrode pads of an integrated circuit element to connection pads of an external wiring board. The present invention relates to a structure of a semiconductor device including an integrated circuit element mounting board provided with a conductor circuit pattern layer having a two-layer structure composed of a plane layer.
【０００２】[0002]
【従来の技術】ＩＣ、ＬＳＩ等の半導体装置は、外部配
線基板上の配線パッドに半田などを用いて接続されてい
る。近来、集積回路素子の微細化、高集積化及び小型化
に対応して、ＳＢＣ法と指称される、半田ボールを用い
て配線基板上の配線パッドに半導体装置を面実装する方
法が提案されている。この方法によれば、配線基板上に
半導体装置を位置決め載置した後、これを加熱して半田
ボールをリフロー固着すればよく、実装が容易なことか
ら、注目されている。2. Description of the Related Art Semiconductor devices such as ICs and LSIs are connected to wiring pads on an external wiring board using solder or the like. Recently, in response to miniaturization, high integration, and miniaturization of integrated circuit elements, there has been proposed a method called SBC method, in which a semiconductor device is surface-mounted on a wiring pad on a wiring board using a solder ball. I have. According to this method, after positioning and mounting the semiconductor device on the wiring board, it is only necessary to heat the semiconductor device to reflow-fix the solder ball, which has attracted attention because it is easy to mount.
【０００３】ところが、近年、情報処理機器の高速化に
伴い、半導体装置の作動に超高周波を用いるようになっ
てきている。しかしながら、ポリイミド基板に微細な間
隔で形成された導体回路パターンの複数の電送路（導体
リード）を超高周波信号が電送される際に、隣接する前
記導体リードに信号が漏れてしまうクロストーク現象を
生じるという問題があった。このような問題点を解決す
るために、ポリイミドテープ基板の前記導体回路パター
ンの反対面に、別体に形成された導電性部材の支持基板
（導電プレーン）を固着し、この導体回路パターンの所
定のリードと支持基板とを貫通孔を介して接続し、放熱
及び接地用導電プレーンとするものが提案されている。However, in recent years, with the increase in the speed of information processing equipment, ultra-high frequencies have been used for the operation of semiconductor devices. However, when a super-high-frequency signal is transmitted through a plurality of transmission paths (conductor leads) of a conductor circuit pattern formed at fine intervals on a polyimide substrate, a crosstalk phenomenon in which a signal leaks to the adjacent conductor lead may occur. There was a problem that would occur. In order to solve such a problem, a support substrate (conductive plane) of a conductive member formed separately is fixed to the opposite side of the conductive circuit pattern of the polyimide tape substrate, and a predetermined portion of the conductive circuit pattern is fixed. The lead and the support substrate are connected through a through hole to provide a conductive plane for heat dissipation and grounding.
【０００４】この方式の半導体装置では、プレス加工に
より、図６に示すように、別体に形成された略四辺形の
凹部１０１を設けた支持基板１０２の片面に導体回路パ
ターン１０３が形成されたポリイミドテープ基板１０４
を前記導体回路パターン１０３の終端部（ワイヤボンデ
ングエリア）１０８が前記集積回路素子搭載部１０５の
周縁沿って配列された状態で固着された構成の集積回路
素子搭載基板１０５ａと、この集積回路素子搭載基板１
０５ａに固着された集積回路素子１０６と、これを被覆
保護する樹脂封止部１０７を備えた構成のものが一般的
である。In a semiconductor device of this type, as shown in FIG. 6, a conductor circuit pattern 103 is formed on one surface of a support substrate 102 provided with a substantially quadrangular recess 101 by press working, as shown in FIG. Polyimide tape substrate 104
An integrated circuit element mounting board 105a having a configuration in which terminal portions (wire bonding areas) 108 of the conductor circuit pattern 103 are fixed along the periphery of the integrated circuit element mounting section 105; Mounting board 1
In general, an integrated circuit element 106 is provided with an integrated circuit element 106 fixed to 05a and a resin sealing portion 107 for covering and protecting the integrated circuit element 106.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら上記の半
導体装置にあっては、集積回路素子搭載基板の支持基板
とポリイミドテープ基板が別体に形成されているので、
接合の際に位置ずれを生じ集積回路素子搭載の歩留まり
が低下すると言う問題があった。However, in the above-described semiconductor device, since the support substrate of the integrated circuit element mounting substrate and the polyimide tape substrate are formed separately,
There has been a problem that displacement occurs at the time of bonding, and the yield of mounting integrated circuit elements is reduced.
【０００６】更に、集積回路素子搭載キャビティ部を略
四辺形に形成しているので、その角部分に応力が集中し
部材内部に内部残留応力が滞有し、半導体装置の組立工
程や実装後の加熱処理などによって内部残留応力解放さ
れ、ねじれ等の変形が生じ実装不良が発生するという問
題があった。Further, since the cavity for mounting the integrated circuit element is formed in a substantially quadrangular shape, stress concentrates at the corners, and internal residual stress stays inside the member. There has been a problem that internal residual stress is released by heat treatment or the like, and deformation such as twisting is caused, resulting in mounting failure.
【０００７】また、集積回路素子搭載キャビティ部を略
四辺形にディプレス形成しているので、導体回路パター
ン層の導体リードを斜め方向の横断線（図７参照）に沿
って絞り込む（デイプレス）ことになり、微細な幅の導
体リードに切断、ズレなどが発生するという問題があっ
た。Further, since the cavity for mounting the integrated circuit element is depressed in a substantially quadrilateral shape, the conductor leads of the conductor circuit pattern layer are narrowed down along oblique transverse lines (see FIG. 7) (depressing). As a result, there is a problem that the conductor lead having a fine width is cut or shifted.
【０００８】また、支持基板（導電プレーン）への接地
導通回路の形成は、前記導体回路パターンの導体リード
の微細な幅に形成された貫通孔を介して接続形成するの
で、信号回路の設置スペースが減少すると共に、前記導
体リード間の短絡や切断などが生じるという問題があっ
た。In addition, since the formation of the ground conductive circuit on the supporting substrate (conductive plane) is performed by connecting the conductor leads of the conductive circuit pattern through through holes formed in a fine width, the signal circuit installation space is provided. And there is a problem that short-circuiting and disconnection between the conductor leads occur.
【０００９】本発明は、上記の実情に鑑みてなされたも
ので、集積回路素子搭載キャビティをディプレス加工し
て形成する際に生じる前記キャビティのコーナ部分に滞
有する内部残留応力の分散化を図り、内部残留応力によ
って生じる問題点を解消して長期信頼性の高い高品質の
半導体装置の構造を提供することを目的とする。さら
に、半導体装置の多ピン化や放熱性、電気特性（寄生電
流の拡散）の向上及び小型化に対応することのできる半
導体装置を提供することを目的とする。さらに、製造が
容易であって且つ、高集積化、高精度化にあっても、実
装が容易で信頼性の高い半導体を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and aims to disperse internal residual stress that is retained in a corner portion of an integrated circuit element mounting cavity formed when the cavity is formed by depressing. It is another object of the present invention to provide a high-quality semiconductor device with high long-term reliability by eliminating the problems caused by internal residual stress. Further, it is another object of the present invention to provide a semiconductor device capable of coping with an increase in the number of pins, heat dissipation, improvement of electric characteristics (diffusion of parasitic current), and miniaturization of the semiconductor device. It is still another object of the present invention to provide a semiconductor which is easy to manufacture, has high integration, and has high accuracy, and can be easily mounted and has high reliability.
【００１０】[0010]
【課題を解決するための手段】本発明は上記の目的を達
成する請求項１記載の半導体装置は、第１の絶縁体層
（ポリイミドテープ）の表面に、信号、電源用回路パタ
ーン層と接地用回路パターン層とから成る導体回路パタ
ーン層を、前記第１の絶縁体層の裏面に、放熱用導電プ
レーン層を具備し、さらに前記導体回路パターン層を被
覆し、集積回路素子搭載用開口部とエリア・アレイ状に
配列された複数のヴィアとを設けた第２の絶縁体層とを
有するポリイミド基板が用いられており、前記ポリイミ
ド基板に形成された導体回路パターン層及び前記導電プ
レーン層を円形皿状にディプレスした前記信号、電源用
回路パターン層及び接地用回路パターン層の一端部側を
第１の導体回路パターンとする第１の平坦部と、前記信
号、電源用回路パターン層及び接地用回路パターン層の
他端部側を第２の導体回路パターンとする第２の平坦部
と、第１の導体回路パターンと第２の導体回路パターン
とを連接する導体回路パターン層を第３の導体回路パタ
ーンとする斜面部とから成る集積回路素子搭載用キャビ
ティ部を設けた集積回路素子搭載基板と、前記集積回路
搭載基板の集積回路素子搭載キャビティ部に導電性接着
剤層を介して搭載され、前記第１の導体回路パターンと
電気的に接続された集積回路素子と、前記集積回路素子
及び前記第１の導体回路パターンの一端部を含む前記キ
ャビティ内をポッティング樹脂で覆う片面樹脂封止部
と、前記第２の絶縁体層側に突出した複数の外部接続端
子及び複数の接地端子とを含む構成とされて成ることを
特徴とするものである。According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein a signal and power supply circuit pattern layer and a ground are provided on a surface of a first insulator layer (polyimide tape). A heat dissipation conductive plane layer on the back surface of the first insulator layer, and further covering the conductor circuit pattern layer, and an opening for mounting an integrated circuit element. A polyimide substrate having a second insulator layer provided with a plurality of vias arranged in an area array is used, and a conductive circuit pattern layer and the conductive plane layer formed on the polyimide substrate are used. A first flat portion having one end side of the signal, the power supply circuit pattern layer and the grounding circuit pattern layer depressed in a circular dish shape as a first conductor circuit pattern, and the signal and power supply circuit pattern; A second flat portion having the other end side of the connection layer and the grounding circuit pattern layer as a second conductor circuit pattern, and a conductor circuit pattern layer connecting the first conductor circuit pattern and the second conductor circuit pattern. An integrated circuit element mounting substrate provided with an integrated circuit element mounting cavity portion comprising a slope portion having a third conductor circuit pattern, and a conductive adhesive layer in the integrated circuit element mounting cavity portion of the integrated circuit mounting substrate. An integrated circuit element mounted via the first conductive circuit pattern and electrically connected to the first conductive circuit pattern; and a single surface covering the cavity including the integrated circuit element and one end of the first conductive circuit pattern with a potting resin. It is characterized by comprising a resin sealing portion, a plurality of external connection terminals and a plurality of ground terminals protruding toward the second insulator layer side.
【００１１】また、請求項２記載の半導体装置は、請求
項１記載の半導体装置において、前記第３の導体回路パ
ターンは、集積回路素子搭載キャビティ部の中心から放
射状に延びる線状に配設された複数の導体リードから成
る導体回路パターンであることを特徴とするものであ
る。According to a second aspect of the present invention, in the semiconductor device of the first aspect, the third conductive circuit pattern is disposed in a linear shape extending radially from the center of the cavity for mounting the integrated circuit element. And a conductor circuit pattern including a plurality of conductor leads.
【００１２】さらにまた、請求項３記載の半導体装置
は、請求項１及び２記載の半導体装置において、前記集
積回路素子搭載用キャビティ部は、前記第３の導体回路
パターンの中間部分でディプレスして円形皿状に形成さ
れて成るたことを特徴とするものである。Further, in the semiconductor device according to a third aspect, in the semiconductor device according to the first and second aspects, the cavity for mounting the integrated circuit element is depressed at an intermediate portion of the third conductive circuit pattern. In a circular dish shape.
【００１３】さらに、請求項４記載の半導体装置は、請
求項１記載の半導体装置において、前記導電プレーン層
及び導体回路パターン層を形成する金属部材として、Ｃ
ｕ又はアルミなどの電気的、熱的導伝性の良好な金属薄
板材が用いられていることを特徴とするものである。Further, in the semiconductor device according to a fourth aspect, in the semiconductor device according to the first aspect, the metal member for forming the conductive plane layer and the conductive circuit pattern layer may include C
The present invention is characterized in that a metal sheet material having good electrical and thermal conductivity such as u or aluminum is used.
【００１４】さらに、請求項５記載の半導体装置は、請
求項１記載の半導体装置において、前記接地用回路パタ
ーン層は、集積回路素子搭載部とこれから延在する接地
リードとこれに接続する枠体とから成ることを特徴とす
るもである。According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the grounding circuit pattern layer includes an integrated circuit element mounting portion, a grounding lead extending therefrom, and a frame body connected to the grounding lead. And characterized by the following.
【００１５】さらに、請求項６記載の半導体装置は、請
求項１記載の半導体装置において、前記接地端子は、前
記接地用回路パターン層の接地リードの終端部に位置
し、前記接地回路パターン及び第１の絶縁体層を貫通す
る導電路を介して前記導電プレーン層に接続する電気的
導通路を形成したことを特徴とするものである。Furthermore, in the semiconductor device according to the present invention, the ground terminal is located at a terminal end of a ground lead of the ground circuit pattern layer, and the ground terminal and the ground circuit pattern are connected to each other. An electrical conduction path connected to the conductive plane layer via a conductive path penetrating the first insulator layer is formed.
【００１６】さらに、請求項７記載の半導体装置は、請
求項１記載の半導体装置において、前記導電プレーン層
は、放熱プレーンとして機能すると共に、接地プレーン
（グランドプレーン）としても機能する構成としたこと
を特徴とするものである。Further, the semiconductor device according to the present invention is configured such that the conductive plane layer functions as a heat dissipation plane and also functions as a ground plane (ground plane). It is characterized by the following.
【００１７】したがって、本発明の構造を有する半導体
装置によれば、導体回路パターン層及び前記導電プレー
ン層の一端部側を円形状にディプレスされた集積回路素
子搭載用キャビティ部を備えた構成とされているので、
従来技術の略四辺形にディプレスされた集積回路素子搭
載用キャビティ部に生じるコーナー部分を無くすことに
よって、前記コーナー部分に滞有したていた内部残留応
力を分散することができる。 これによって、薄型の半
導体装置に生じていた捻れ、反りなどの変形がなくな
り、それによる外部接続端子のコプラナリティの発生を
防止することができる。Therefore, according to the semiconductor device having the structure of the present invention, there is provided a structure including the integrated circuit element mounting cavity in which one end side of the conductive circuit pattern layer and the conductive plane layer is depressed in a circular shape. Has been
By eliminating the corners generated in the cavity for mounting the integrated circuit element which is depressed into a substantially quadrangular shape in the prior art, the internal residual stress that has been accumulated in the corners can be dispersed. As a result, deformation such as torsion or warping that has occurred in the thin semiconductor device can be eliminated, and coplanarity of the external connection terminal due to the deformation can be prevented.
【００１８】また、集積回路素子搭載基板（インターポ
ーザ）としてポリイミドテープ基板を用い、外部接続端
子にはソルダボール又はソルダバンプをエリア・アレイ
状に配置した片面樹脂封止した構成とされているので、
半導体装置の面実装が容易になると共に、多ピン化に対
応した薄型の半導体装置を形成することができる。Further, since a polyimide tape substrate is used as an integrated circuit element mounting substrate (interposer) and solder balls or solder bumps are externally connected to the external connection terminals in a one-side resin-sealed arrangement in an area array.
The surface mounting of the semiconductor device becomes easy, and a thin semiconductor device corresponding to the increase in the number of pins can be formed.
【００１９】また、前記集積回路素子搭載用キャビティ
部は、集積回路素子搭載部の中心から放射状に延びる線
状に配設された複数の導体リード有する前記第３の導体
回路パターン層の中間部分で円形状にディプレスして形
成されているので、従来技術の略四辺形にディプレスす
る際に、導体リードを斜めの横断線上（図７参照）でデ
ィプレスするのに比べて、導体リードに直交する横断線
上（図５参照）でディプレスされるから導体リードに生
じるストレスが導体リードの幅方向に直角に作用し、導
体リードに滞有する内部残留応力が均一化する。その結
果として、導体リードの剥離、切断、変形などを無くす
ことができる。The integrated circuit element mounting cavity is an intermediate portion of the third conductive circuit pattern layer having a plurality of linearly arranged conductive leads extending radially from the center of the integrated circuit element mounting section. Since it is formed by depressing in a circular shape, when depressing into a substantially quadrilateral of the prior art, the conductor lead is more depressed than on a diagonal transverse line (see FIG. 7). Since the conductor is depressed on the orthogonal transverse line (see FIG. 5), the stress generated in the conductor lead acts at right angles in the width direction of the conductor lead, and the internal residual stress retained in the conductor lead becomes uniform. As a result, peeling, cutting, deformation and the like of the conductor lead can be eliminated.
【００２０】また、前記導電層及び導体回路層を形成す
る部材にＣｕ又はアルミなどの金属薄板材を用いている
ので、電気的、熱的導伝性を向上させることができる。Further, since a thin metal plate such as Cu or aluminum is used as a member for forming the conductive layer and the conductive circuit layer, electrical and thermal conductivity can be improved.
【００２１】さらにまた、集積回路素子搭載部とこれか
ら延在する接地リードとこれに接続する枠体とから成る
接地回路パターン層を設ると共に、その接地リードと枠
体の交点に位置し、前記接地回路パターン及び第１の絶
縁体層を貫通する導電路を介して前記導電プレーン層に
接続する電気的導通路を備えた外部接続端子を設けた構
成としているので、信号、電源用導体リードを増設する
ことができると共に、前記接地回路パターンが接地用の
共通回路として機能させることができる。Further, a ground circuit pattern layer comprising an integrated circuit element mounting portion, a ground lead extending therefrom and a frame connected thereto is provided, and the ground circuit pattern layer is located at the intersection of the ground lead and the frame. An external connection terminal having an electrical conduction path connected to the conductive plane layer via a conductive path penetrating the ground circuit pattern and the first insulator layer is provided, so that signal and power supply conductor leads are provided. The ground circuit pattern can function as a common circuit for grounding.
【００２２】[0022]
【発明の実施の形態】続いて、添付した図面に基づき本
発明の実施の態様の一例について詳細に説明する。ここ
で、図１は本発明の実施の態様の一例に係るポリイミド
テープ基板部材の構成を示す断面図、図２は本発明の実
施の態様の一例に係るポリイミドテープ基板を示す第２
絶縁体層側の平面図、図３は本発明の実施の態様の一例
に係るポリイミドテープ基板の中央部分を円形状にディ
プレスした状態を示す平面図、図４は本発明の実施の態
様の一例に係る半導体装置を示す平面図、図５は本発明
の実施の態様の一例に係る第３の導体回路パターンを円
形皿状にデイプレス状態を示す部分拡大平面図、図６は
従来の半導体装置を示す平面図、図７は従来の四辺形に
ディプレスした状態を示す一部拡大平面図である。Next, an example of an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, FIG. 1 is a cross-sectional view showing a configuration of a polyimide tape substrate member according to an example of the embodiment of the present invention, and FIG. 2 is a second view showing a polyimide tape substrate according to an example of the embodiment of the present invention.
FIG. 3 is a plan view showing a state in which a central portion of a polyimide tape substrate according to an embodiment of the present invention is depressed in a circular shape, and FIG. 4 is a plan view showing an embodiment of the present invention. FIG. 5 is a plan view showing a semiconductor device according to an example, FIG. 5 is a partially enlarged plan view showing a third conductor circuit pattern according to an example of the embodiment of the present invention in a circular dish shape, and FIG. FIG. 7 is a plan view showing the apparatus, and FIG. 7 is a partially enlarged plan view showing a state where the apparatus is depressed into a conventional quadrilateral.
【００２３】本発明の実施の形態に係る半導体装置は、
第１の絶縁体層の片面に導電プレーン層を、他面には導
体回路パターンを備え、その中央部に円形皿状の集積回
路素子搭載キャビテイを設けた集積回路素子搭載基板を
構成部材とされており、これに集積回路素子を搭載し、
該集積回路素子を封止する樹脂封止部から成る構成とさ
れている。以下、半導体装置の構成部材について説明す
る。The semiconductor device according to the embodiment of the present invention
An integrated circuit element mounting substrate having a conductive plane layer on one side of the first insulator layer and a conductive circuit pattern on the other side, and a circular dish-shaped integrated circuit element mounting cavity provided at the center thereof is a constituent member. On which integrated circuit elements are mounted,
It is configured to include a resin sealing portion for sealing the integrated circuit element. Hereinafter, components of the semiconductor device will be described.
【００２４】まず、図１に示すように、前記集積回路素
子搭載基板の構成部材であるポリイミドテープ基板部材
２００は、第１の絶縁体層の一例であるポリイミドテー
プ２０１の両面に導電性部材の一例であるアルミ（Ａ
ｌ）の薄板材２０２を圧着して形成された（Ａｌ／ポリ
イミド／Ａｌ）の２層構造の導電性部材を備えた構成と
されている。ここで、前記ポリイミドテープ基板部材は
前記導電性部材としてＣｕ、Ｎｉなどの導電性、熱伝導
性の良好な部材をＣｕ／ポリイミド／Ｃｕ、Ｎｉ／ポリ
イミド／Ｃｕ、Ｎｉ／ポリイミド／Ｎｉなどの組合せ構
成とすることもできる。First, as shown in FIG. 1, a polyimide tape substrate member 200 which is a constituent member of the integrated circuit element mounting substrate has conductive members on both sides of a polyimide tape 201 which is an example of a first insulator layer. An example of aluminum (A
1) A structure having a (Al / polyimide / Al) two-layer conductive member formed by pressing the thin plate member 202 of (1). Here, the polyimide tape substrate member is a combination of a member having good conductivity and thermal conductivity such as Cu and Ni as the conductive member, such as Cu / polyimide / Cu, Ni / polyimide / Cu, and Ni / polyimide / Ni. It can also be configured.
【００２５】そして、図２に示すように、前記集積回路
素子搭載基板３０（図３参照）の構成部材であるポリイ
ミドテーブ基板２２は、前記ポリイミドテープ基板部材
２００から、慣用のエッチング加工法により、その片面
を放熱プレーン及び接地プレーンとして機能する導電プ
レーン層１１、その他面を信号・電源となる導体回路パ
ターン層１２及び集積回路素子搭載部１３と集積回路素
子搭載部１３からのびる接地リード１４とこれに接続し
た枠体１５を備えた接地回路パターン層１６を設けた導
体回路層１７、さらに、前記導体回路層１７を被覆し、
集積回路素子搭載部１３及びワイヤボンディングエリア
１８を露出する開口部１９とヴィアホール２０を設けた
第２の絶縁体層２１の一例である感光性レジスト皮膜層
から成る構成（導電プレーン層／ポリイミド／導体回路
パターン／第２の絶縁体層）とされている。As shown in FIG. 2, the polyimide tape substrate 22, which is a component of the integrated circuit element mounting substrate 30 (see FIG. 3), is formed from the polyimide tape substrate member 200 by a conventional etching method. One surface thereof is a conductive plane layer 11 functioning as a heat dissipation plane and a ground plane, and the other surface is a conductor circuit pattern layer 12 serving as a signal / power supply, an integrated circuit element mounting portion 13, and a ground lead 14 extending from the integrated circuit element mounting portion 13. A conductor circuit layer 17 provided with a ground circuit pattern layer 16 having a frame 15 connected to the
A structure composed of a photosensitive resist film layer which is an example of a second insulator layer 21 provided with an opening 19 for exposing the integrated circuit element mounting portion 13 and the wire bonding area 18 and a via hole 20 (conductive plane layer / polyimide / Conductive circuit pattern / second insulator layer).
【００２６】そして、図３に示すように、集積回路素子
搭載基板３０は、前記ポリイミドテーブ基板２２の中央
部分に、前記導体回路パターン層１２及び接地回路パタ
ーン層１６の一端部側を第１の導体回路パターン２３と
する第１の平坦部２４と、他端部側を第２の導体回路パ
ターン２５とする第２の平坦部２６と、前記第１の導体
回路パターン２３と前記第２の導体回路パターン２５と
を連接する回路層を第３の導体回路パターン２７とする
斜面部２８とから成る円形皿状にディプレスされた集積
回路素子搭載用キャビティ部２９を備えた構成とされて
いる。ここで、少なくとも前記導体回路層１７の表面に
図示していないＡｕメッキの保護皮膜層を形成してもよ
い。これによつて導体回路層１７及び導電プレン層１１
の耐食性を向上させると共に、内部接続端子及び外部接
続端子の形成が容易になる。As shown in FIG. 3, the integrated circuit element mounting board 30 has a first end portion of the conductive circuit pattern layer 12 and the ground circuit pattern layer 16 at the center of the polyimide tape substrate 22. A first flat portion 24 serving as a conductive circuit pattern 23, a second flat portion 26 serving as a second conductive circuit pattern 25 on the other end side, the first conductive circuit pattern 23 and the second conductor The circuit board has a cavity 29 for mounting an integrated circuit element, which is depressed in a circular dish shape and includes a sloped portion 28 having a circuit layer connected to the circuit pattern 25 as a third conductor circuit pattern 27. Here, a protective coating layer of Au plating (not shown) may be formed on at least the surface of the conductor circuit layer 17. Thereby, the conductive circuit layer 17 and the conductive plane layer 11 are formed.
And the formation of internal connection terminals and external connection terminals is facilitated.
【００２７】そして、図４に示すように、半導体装置１
００は、前記集積回路搭載基板３０の集積回路素子搭載
キャビティ部２９に設けた集積回路素子搭載部１３に、
集積回路素子３１が導電性接着剤層を介してフェイスダ
ウン方式で搭載され、ボンデングワイヤ３２を介して前
記集積回路素子の複数の電極パッド３３と前記第１の導
体回路パターン２３の複数のワイヤボンディングエリア
１８とが一対一で電気的に接続されている。そして、前
記集積回路素子３１、前記ボンデングワイヤ３２及び前
記導体回路パターン１２の一端部を含む前記キャビティ
部２９内をポッティング樹脂３４で覆う片面樹脂封止さ
れている。そしてさらに、前記集積回路素子搭載キャビ
ティ部２９に隣接した第２の平坦部２６に、前記第２の
絶縁体層２１側に突出し、エリア・アレイ状に配列され
た複数の外部接続端子３５及び複数の接地端子３６とな
るソルダボール又はソルダバンプを具備する構成とされ
ている。Then, as shown in FIG.
00 denotes an integrated circuit element mounting portion 13 provided in the integrated circuit element mounting cavity portion 29 of the integrated circuit mounting substrate 30,
An integrated circuit element 31 is mounted in a face-down manner via a conductive adhesive layer, and a plurality of electrode pads 33 of the integrated circuit element and a plurality of wires of the first conductive circuit pattern 23 via bonding wires 32. The bonding areas 18 are electrically connected one to one. Then, the inside of the cavity portion 29 including the integrated circuit element 31, the bonding wire 32, and one end of the conductive circuit pattern 12 is sealed with a single-sided resin to cover with a potting resin. Further, a plurality of external connection terminals 35 and a plurality of external connection terminals 35 protruding toward the second insulator layer 21 and arranged in an area array shape are formed on a second flat portion 26 adjacent to the integrated circuit element mounting cavity portion 29. , A solder ball or a solder bump serving as the ground terminal 36 is provided.
【００２８】また、図５に示すように、第１の導体回路
パターン２３備えた第１の平坦部２４と、第２の導体回
路パターン２５備えた第２の平坦部２６と、前記第１の
導体回路パターン２３と前記第２の導体回路パターン２
５とを連接する第３の導体回路パターン２７を備えた斜
面部２８とから成る集積回路素子搭載用キャビティ部２
９は該集積回路素子搭載キャビティ部の中心（円形状の
デイプレスの中心点）から放射状に延びる線状に配設さ
れた第３の導体回路パターン２７の複数の導体リード２
７ａの中間部分で円形皿状にディプレスされて形成され
た構成とされている。As shown in FIG. 5, a first flat portion 24 provided with a first conductor circuit pattern 23, a second flat portion 26 provided with a second conductor circuit pattern 25, and Conductor circuit pattern 23 and second conductor circuit pattern 2
And a slope portion 28 provided with a third conductive circuit pattern 27 that connects the integrated circuit element 5 to the integrated circuit element mounting cavity 2.
Reference numeral 9 denotes a plurality of conductor leads 2 of a third conductor circuit pattern 27 linearly extending from the center of the cavity for mounting the integrated circuit element (the center point of the circular depress).
The intermediate portion 7a is formed by depressing in a circular dish shape.
【００２９】[0029]
【発明の効果】以上説明したように、集積回路素子搭載
キャビティをディプレス加工して形成する際に、円形皿
状のディプレス構造とされているので、従来技術で前記
キャビティのコーナ部分に滞有していた内部残留応力を
分散化し、後工程や実装後の加熱処理などで生じていた
捻れ、曲がりなどの変形を防止することができ長期信頼
性の高い半導体装置の構造を提供することができる。さ
らに、半導体装置の多ピン化や放熱性、電気特性（寄生
電流の拡散）の向上及び小型化に対応することのできる
半導体装置を提供することができる。As described above, when a cavity for mounting an integrated circuit element is formed by depressing, the cavity is formed in a circular dish-shaped depressed structure. It is possible to provide a structure of a semiconductor device having high long-term reliability by dispersing the internal residual stress that it has and preventing deformation such as torsion and bending caused by a post-process or a heat treatment after mounting. it can. Further, it is possible to provide a semiconductor device capable of responding to increase in the number of pins, heat dissipation, improvement of electric characteristics (diffusion of parasitic current), and downsizing of the semiconductor device.
【図１】本発明の実施の態様の一例に係るポリイミドテ
ープ基板部材の構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a configuration of a polyimide tape substrate member according to an example of an embodiment of the present invention.
【図２】本発明の実施の態様の一例に係るポリイミドテ
ープ基板を示す第２絶縁体層側の平面図である。FIG. 2 is a plan view of a polyimide tape substrate according to an example of an embodiment of the present invention, on a second insulator layer side.
【図３】本発明の実施の態様の一例に係るポリイミドテ
ープ基板の中央部分を円形状にディプレスした状態を示
す平面図である。FIG. 3 is a plan view showing a state in which a central portion of a polyimide tape substrate according to an embodiment of the present invention is depressed in a circular shape.
【図４】本発明の実施の態様の一例に係る半導体装置を
示す平面図である。FIG. 4 is a plan view showing a semiconductor device according to an example of an embodiment of the present invention.
【図５】本発明の実施の態様の一例に係る第３の導体回
路パターンを円形皿状にデイプレス状態を示す部分拡大
平面図である。FIG. 5 is a partially enlarged plan view showing a third conductor circuit pattern according to an embodiment of the present invention in a circular dish shape in a pressed state.
【図６】従来の半導体装置を示す平面図である。FIG. 6 is a plan view showing a conventional semiconductor device.
【図７】従来の四辺形にディプレスした状態を示す一部
拡大平面図である。FIG. 7 is a partially enlarged plan view showing a state where a conventional quadrilateral is depressed.
１００ 半導体装置 １０１ 凹部 １０２ 支持基板 １０３ 導体回路パターン １０４ ポリイミドテープ基板 １０５ 集積回路素子搭載部 １０５ａ 集積回路素子搭載基板 １０６ 集積回路素子 １０７ 樹脂封止部 １０８ ワイヤボンディングエリア ２００ ポリイミドテープ基板部材 ２０１ ポリイミドテープ ２０２ アルミの薄板材 １０ 第１の絶縁体層 １１ 導電プレーン層 １２ 導体回路パターン層 １３ 集積回路素子搭載部 １４ 接地リード １５ 枠体 １６ 接地回路パターン層 １７ 導体回路層 １８ ワイヤボンディングエリア １９ 開口部 ２０ ヴィアホール ２１ 第２の絶縁体層 ２２ ポリイミドテーブ基板 ２３ 第１の導体回路パターン ２４ 第１の平坦部 ２５ 第２の導体回路パターン ２６ 第２の平坦部 ２７ 第３の導体回路パターン ２７ａ 導体リード ２８ 斜面部 ２９ 集積回路素子搭載用キャビティ部 ３０ 集積回路搭載基板 ３１ 集積回路素子 ３２ ボンデングワイヤ ３３ 電極パッド ３４ ポッティング樹脂 ３５ 外部接続端子 ３６ 接地端子 REFERENCE SIGNS LIST 100 semiconductor device 101 concave portion 102 support substrate 103 conductive circuit pattern 104 polyimide tape substrate 105 integrated circuit element mounting portion 105 a integrated circuit element mounting substrate 106 integrated circuit element 107 resin sealing portion 108 wire bonding area 200 polyimide tape substrate member 201 polyimide tape 202 Aluminum sheet material 10 First insulator layer 11 Conductive plane layer 12 Conductive circuit pattern layer 13 Integrated circuit element mounting portion 14 Ground lead 15 Frame 16 Ground circuit pattern layer 17 Conductor circuit layer 18 Wire bonding area 19 Opening 20 Via Hole 21 Second insulator layer 22 Polyimide tape substrate 23 First conductive circuit pattern 24 First flat portion 25 Second conductive circuit pattern 26 Second flat portion 27 Third conductive circuit pattern 27 Conductor leads 28 slope portion 29 integrated circuit element mounting cavity 30 integrated circuit mounting substrate 31 integrated circuit element 32 carbon dengue wire 33 electrode pads 34 potting resin 35 external connection terminal 36 ground terminal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 23/12 ５０１ Ｈ０１Ｌ 23/12 ５０１Ｓ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI H01L 23/12 501 H01L 23/12 501S
Claims (7)
表面に、信号、電源用回路パターン層と接地用回路パタ
ーン層とから成る導体回路パターン層を、前記第１の絶
縁体層の裏面に、放熱用導電プレーン層を具備し、さら
に前記導体回路パターン層を被覆し、集積回路素子搭載
用開口部とエリア・アレイ状に配列された複数のヴィア
とを設けた第２の絶縁体層とを有するポリイミド基板が
用いられており、 前記ポリイミド基板に形成された導体回路パターン層及
び前記導電プレーン層を円形皿状にディプレスした前記
信号、電源用回路パターン層及び接地用回路パターン層
の一端部側を第１の導体回路パターンとする第１の平坦
部と、前記信号、電源用回路パターン層及び接地用回路
パターン層の他端部側を第２の導体回路パターンとする
第２の平坦部と、第１の導体回路パターンと第２の導体
回路パターンとを連接する導体回路パターン層を第３の
導体回路パターンとする斜面部とから成る集積回路素子
搭載用キャビティ部を設けた集積回路素子搭載基板と、 前記集積回路搭載基板の集積回路素子搭載キャビティ部
に導電性接着剤層を介して搭載され、前記第１の導体回
路パターンと電気的に接続された集積回路素子と、 前記集積回路素子及び前記第１の導体回路パターンの一
端部を含む前記キャビティ内をポッティング樹脂で覆う
片面樹脂封止部と、 前記第２の絶縁体層側に突出した複数の外部接続端子及
び複数の接地端子とを含む構成とされて成ることを特徴
とする半導体装置。1. A conductor circuit pattern layer comprising a signal and power supply circuit pattern layer and a ground circuit pattern layer on a surface of a first insulator layer (polyimide tape), and a back surface of the first insulator layer. A second insulator layer provided with a heat-dissipating conductive plane layer, further covering the conductive circuit pattern layer, and provided with an opening for mounting an integrated circuit element and a plurality of vias arranged in an area array. The polyimide substrate having the following is used: The signal obtained by depressing the conductive circuit pattern layer and the conductive plane layer formed on the polyimide substrate into a circular dish shape, a circuit pattern layer for power supply and a circuit pattern layer for grounding. A first flat portion having one end as a first conductive circuit pattern, and a second conductive circuit pattern at the other end of the signal, power supply circuit pattern layer and grounding circuit pattern layer. 2 and a cavity portion for mounting an integrated circuit element, comprising a slope portion having a third conductor circuit pattern as a conductor circuit pattern layer connecting the first conductor circuit pattern and the second conductor circuit pattern. An integrated circuit element mounting substrate, and an integrated circuit element mounted on the integrated circuit element mounting cavity of the integrated circuit mounting substrate via a conductive adhesive layer and electrically connected to the first conductive circuit pattern. A single-sided resin sealing portion that covers the inside of the cavity including a potting resin including one end of the integrated circuit element and the first conductive circuit pattern; a plurality of external connection terminals protruding toward the second insulator layer; A semiconductor device having a configuration including a plurality of ground terminals.
路素子搭載キャビティ部の中心から放射状に延びる線状
に配設された複数の導体リードから成る導体回路パター
ンであることを特徴とする請求項１記載の半導体装置。2. The conductor circuit pattern according to claim 1, wherein the third conductor circuit pattern is a conductor circuit pattern including a plurality of conductor leads arranged in a line extending radially from the center of the integrated circuit element mounting cavity. Item 2. The semiconductor device according to item 1.
は、前記第３の導体回路パターンの中間部分でディプレ
スして円形皿状に形成されて成るたことを特徴とする請
求項１及び２記載の半導体装置。3. The integrated circuit element mounting cavity portion is formed in a circular dish shape by depressing an intermediate portion of the third conductive circuit pattern. Semiconductor device.
ン層を形成する金属部材として、Ｃｕ又はアルミなどの
電気的、熱的導伝性の良好な金属薄板材が用いられてい
ることを特徴とする請求項１記載の半導体装置。4. A metal sheet material having good electrical and thermal conductivity, such as Cu or aluminum, is used as a metal member for forming the conductive plane layer and the conductive circuit pattern layer. The semiconductor device according to claim 1.
素子搭載部とこれから延在する接地リードとこれに接続
する枠体とから成ることを特徴とする請求項１記載の半
導体装置。5. The semiconductor device according to claim 1, wherein the ground circuit pattern layer comprises an integrated circuit element mounting portion, a ground lead extending therefrom, and a frame connected to the ground lead.
ン層の接地リードの終端部に位置し、前記接地回路パタ
ーン及び第１の絶縁体層を貫通する導電路を介して前記
導電プレーン層に接続する電気的導通路を形成したこと
を特徴とする請求項１記載の半導体装置。6. The ground terminal is located at a terminal end of a ground lead of the ground circuit pattern layer, and is connected to the conductive plane layer via a conductive path penetrating the ground circuit pattern and a first insulator layer. 2. The semiconductor device according to claim 1, wherein an electrical conduction path for connection is formed.
して機能すると共に、接地プレーン（グランドプレー
ン）としても機能する構成としたことを特徴とする請求
項１記載の半導体装置。7. The semiconductor device according to claim 1, wherein the conductive plane layer functions as a heat radiation plane and also functions as a ground plane (ground plane).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28303396A JP3205272B2 (en) | 1996-10-04 | 1996-10-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28303396A JP3205272B2 (en) | 1996-10-04 | 1996-10-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10112524A JPH10112524A (en) | 1998-04-28 |
| JP3205272B2 true JP3205272B2 (en) | 2001-09-04 |
Family
ID=17660357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28303396A Expired - Fee Related JP3205272B2 (en) | 1996-10-04 | 1996-10-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3205272B2 (en) |
-
1996
- 1996-10-04 JP JP28303396A patent/JP3205272B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10112524A (en) | 1998-04-28 |
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