JP3174409B2 - Semiconductor manufacturing apparatus and substrate processing method in semiconductor manufacturing apparatus - Google Patents
Semiconductor manufacturing apparatus and substrate processing method in semiconductor manufacturing apparatusInfo
- Publication number
- JP3174409B2 JP3174409B2 JP26551392A JP26551392A JP3174409B2 JP 3174409 B2 JP3174409 B2 JP 3174409B2 JP 26551392 A JP26551392 A JP 26551392A JP 26551392 A JP26551392 A JP 26551392A JP 3174409 B2 JP3174409 B2 JP 3174409B2
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- JP
- Japan
- Prior art keywords
- substrate
- processing
- time
- film forming
- chamber
- Prior art date
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Description
【０００１】[0001]
【産業上の利用分野】本発明はＬＣＤ（Ｌｉｑｕｉｄ
Ｃｒｙｓｔａｌ Ｄｉｓｐｌａｙ）等、半導体素子の製
造装置、特に１枚ずつ処理を行う枚葉式半導体製造装置
に於ける基板処理方法に関するものである。BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display (LCD).
The present invention relates to a substrate processing method in a semiconductor device manufacturing apparatus, such as a crystal display, and in particular, in a single-wafer semiconductor manufacturing apparatus that performs processing one by one.
【０００２】[0002]
【従来の技術】従来のＬＣＤ半導体製造装置を、図１３
に於いて説明する。2. Description of the Related Art A conventional LCD semiconductor manufacturing apparatus is shown in FIG.
It will be described in.
【０００３】該従来のＬＣＤ半導体製造装置は、所謂イ
ンライン方式の搬送形態を有し、垂直な基板保持プレー
ト１の両面にＬＣＤ用の基板２をそれぞれ４枚、計８枚
の基板を保持させ、前記基板保持プレート１をローダ部
３、予熱槽４、成膜槽５、冷却槽６を経てアンローダ部
７迄移動させ、前記成膜槽５に於いて基板２に単層膜を
積層するものである。The conventional LCD semiconductor manufacturing apparatus has a so-called in-line transfer mode, in which a vertical substrate holding plate 1 holds four LCD substrates 2 on both sides, that is, a total of eight substrates. The substrate holding plate 1 is moved to an unloader section 7 through a loader section 3, a preheating tank 4, a film forming tank 5, and a cooling tank 6, and a single layer film is laminated on the substrate 2 in the film forming tank 5. is there.
【０００４】斯かる従来例の半導体製造装置は、基板保
持プレート１がＬＣＤ半導体製造装置を一方向に通過す
る構成であり、その為占有床面積が大きくなり、又基板
２を垂直姿勢で２段に保持するので、装置の高さが高く
なり、この為作業者による基板の交換作業は容易でな
く、作業者の負担は大きかった。In such a conventional semiconductor manufacturing apparatus, the substrate holding plate 1 passes through the LCD semiconductor manufacturing apparatus in one direction, so that the occupied floor area becomes large, and the substrate 2 is placed vertically in two steps. , The height of the apparatus is increased, and thus the replacement work of the substrate by the operator is not easy, and the burden on the operator is large.
【０００５】更に、上記従来例では単層膜生成装置であ
るので、複数層の膜を生成する場合は、成膜条件を変え
複数回の成膜を必要とした。更に、装置外での基板の運
搬は人手に頼っていたので、パーティクルにより基板が
汚染されるという問題があった。Furthermore, since the above-described conventional example is a single-layer film forming apparatus, when forming a film of a plurality of layers, the film forming conditions are changed and a plurality of film formings are required. Further, since the substrate is transported outside the apparatus by hand, there is a problem that the substrate is contaminated by particles.
【０００６】更に、近年では顧客要求が多様化している
が、複数枚を同時に成膜し且単層膜を生成している従来
の装置では、多様化した顧客要求への対応が難しいとい
う不具合があった。Further, in recent years, customer requirements have been diversified. However, the conventional apparatus, which simultaneously forms a plurality of films and generates a single-layer film, has a disadvantage that it is difficult to respond to diversified customer requirements. there were.
【０００７】[0007]
【発明が解決しようとする課題】前記多様化した顧客要
求への対応に適合するものとして枚葉式の半導体製造装
置が具体化されているが、この枚葉式の半導体製造装置
では基板を１枚ずつ処理する為、処理内容の自由度が大
幅に増すが、一方で基板の搬送が複雑化するので搬送の
能率が装置の稼働率に大きく影響し、或いは１枚の基板
に対して複数の処理工程を連続して行う場合は、或る処
理工程で事故が発生した場合の対策が稼働率に大きく影
響することになる。A single-wafer type semiconductor manufacturing apparatus has been embodied to meet the diversified customer requirements. In this single-wafer type semiconductor manufacturing apparatus, one substrate is used. Since the processing is performed one by one, the degree of freedom of the processing content is greatly increased. On the other hand, the transfer of the substrate is complicated, so the transfer efficiency greatly affects the operation rate of the apparatus. When processing steps are performed continuously, measures to be taken when an accident occurs in a certain processing step greatly affect the operation rate.
【０００８】本発明は斯かる実情に鑑み、搬送能率、稼
働率を大幅に向上させた基板処理方法を提供しようとす
るものである。The present invention has been made in view of the above circumstances, and has as its object to provide a substrate processing method in which the transport efficiency and the operation rate are greatly improved.
【０００９】[0009]
【課題を解決するための手段】本発明は、複数の処理工
程を有する半導体製造装置に於いて、前記複数の処理工
程の内、最も長いプロセスタイムを基にタクトタイムを
設定し、前記各処理工程に対する基板投入間隔を前記タ
クトタイムとし、前記複数の処理工程の内、いずれか１
つに異常が発生した場合に、異常が前記タクトタイム以
内に回復しない場合は新しい基板の投入を停止する半導
体製造装置に於ける基板処理方法に係り、更に複数の処
理工程のそれぞれの処理時間を監視し、それぞれの基準
時間との比較で各処理工程に異常が発生したかどうかを
監視する半導体製造装置に於ける基板処理方法に係るも
のであり、又複数の処理工程を有する半導体製造装置に
於いて、前記複数の処理工程の内、最も長いプロセスタ
イムを基にタクトタイムを設定し、前記各処理工程に対
する基板投入間隔を前記タクトタイムとし、前記複数の
処理工程の内、いずれか１つに異常が発生した場合に、
異常が前記タクトタイム以内に回復しない場合は新しい
基板の投入を停止する様にした半導体製造装置に係るも
のである。 SUMMARY OF THE INVENTION According to the present invention, in a semiconductor manufacturing apparatus having a plurality of processing steps, a tact time is set based on the longest process time among the plurality of processing steps. A substrate loading interval for a process is defined as the tact time, and any one of the plurality of process steps
In the event that an abnormality occurs, the abnormality
In the semiconductor manufacturing apparatus according to the present invention, the input of a new substrate is stopped when the recovery time does not recover.In addition , the processing time of each of a plurality of processing steps is monitored, and the reference time and also abnormality in the processing step in comparison of Ru engaged in in the substrate processing method in a semiconductor manufacturing apparatus for monitoring whether generated
And a semiconductor manufacturing apparatus having a plurality of processing steps.
Out of the plurality of processing steps,
Tact time is set based on the
The substrate loading interval to be set is the tact time, and the plurality of
If any one of the processing steps becomes abnormal,
If the abnormality does not recover within the takt time,
According to a semiconductor manufacturing apparatus in which the loading of the substrate is stopped.
It is.
【００１０】[0010]
【作用】各基板の投入から処理後の搬出迄の時間が一定
になり、各基板の熱履歴を一定にすることができると共
に装置の未稼働状態が極力少なくなり、処理品質の均一
が図れると共に稼働率の向上が図れる。[Function] The time from the loading of each substrate to the unloading after the processing is constant, the heat history of each substrate can be kept constant, the non-operating state of the apparatus is reduced as much as possible, and the processing quality can be uniform. The operation rate can be improved.
【００１１】[0011]
【実施例】以下、図面を参照しつつ本発明の一実施例を
説明する。An embodiment of the present invention will be described below with reference to the drawings.
【００１２】先ず、図１に於いて本発明が実施される枚
葉式半導体製造装置について説明する。First, a single-wafer type semiconductor manufacturing apparatus in which the present invention is implemented will be described with reference to FIG.
【００１３】ロード側カセットスタンド８に第１搬送機
９が連設され、該第１搬送機９にはゲートバルブ１０を
介してロード側基板予備室１１が連設され、更にロード
側基板予備室１１にはゲートバルブ１２を介して第２搬
送機１３が連設されている。又、該第２搬送機１３には
ゲートバルブ１４を介して予備加熱室１５が連設されて
いる。A first transfer unit 9 is connected to the load-side cassette stand 8, and a load-side substrate preparatory chamber 11 is connected to the first transfer unit 9 via a gate valve 10. A second transfer device 13 is connected to 11 via a gate valve 12. Further, a preheating chamber 15 is connected to the second transporter 13 via a gate valve 14.
【００１４】前記第２搬送機１３には第１成膜室１７、
第３搬送機１８、第２成膜室１９、第４搬送機２０、更
に第３成膜室２１が順次ゲートバルブ１６，２２，２
３，２４，２５を介して連設され、前記第４搬送機２０
にはゲートバルブ３５を介して基板冷却室を兼ねるアン
ロード側基板予備室２６が連設され、更にゲートバルブ
２７を介して第５搬送機２８、該第５搬送機２８にアン
ロード側カセットスタンド２９を連設する。The second transfer unit 13 includes a first film forming chamber 17,
The third transfer device 18, the second film formation chamber 19, the fourth transfer device 20, and the third film formation chamber 21 are sequentially provided with gate valves 16, 22, 2.
3, 24, 25, and the fourth transfer device 20
An unloading-side substrate pre-chamber 26 also serving as a substrate cooling chamber is provided continuously through a gate valve 35, and a fifth transfer unit 28 is further connected to the fifth transfer unit 28 through a gate valve 27. 29 are connected in series.
【００１５】前記カセットスタンド８，２９は基板が装
填された基板カセットを授受可能であり、前記第１搬送
機９との協働により、基板を１枚ずつ前記ロード側基板
予備室１１に搬送可能となっており、又前記第２搬送機
１３は前記ロード側基板予備室１１の基板を前記予備加
熱室１５に搬送し、又該予備加熱室１５の基板を前記第
１成膜室１７に搬送する。更に、前記第３搬送機１８は
前記第１成膜室１７から前記第２成膜室１９へ基板を搬
送し、前記第４搬送機２０は前記第２成膜室１９から第
３成膜室２１へ、或いは前記第３成膜室２１から前記ア
ンロード側基板予備室２６へ基板を搬送し、前記第５搬
送機２８は前記アンロード側基板予備室２６から前記ア
ンロード側カセットスタンド２９へ基板を搬送する様に
なっている。The cassette stands 8 and 29 can transfer a substrate cassette loaded with substrates, and can transfer substrates one by one to the load-side substrate spare chamber 11 in cooperation with the first transfer device 9. The second transfer device 13 transfers the substrate in the load-side substrate pre-chamber 11 to the pre-heating chamber 15 and transfers the substrate in the pre-heating chamber 15 to the first film formation chamber 17. I do. Further, the third transfer device 18 transfers the substrate from the first film formation chamber 17 to the second film formation chamber 19, and the fourth transfer device 20 transfers the substrate from the second film formation chamber 19 to the third film formation chamber. 21 or the substrate is transferred from the third film forming chamber 21 to the unloading-side substrate preparatory chamber 26, and the fifth transfer device 28 is transferred from the unloading-side substrate preparatory chamber 26 to the unloading-side cassette stand 29. The substrate is transported.
【００１６】又、前記第１搬送機９、第２搬送機１３、
第３搬送機１８、第４搬送機２０、第５搬送機２８はそ
れぞれ独立して基板を搬送可能となっている。Further, the first transporter 9, the second transporter 13,
The third transporter 18, the fourth transporter 20, and the fifth transporter 28 can transport a substrate independently of each other.
【００１７】先ず、本装置搬送系のタクトタイム（或る
プロセス工程の始まりから次の工程の始り迄の所要時間
間隔）を前記予備加熱室１５、第１成膜室１７、第２成
膜室１９、第３成膜室２１の各処理時間の内最大値を基
に設定する。First, the tact time (the required time interval from the start of a certain process step to the start of the next step) of the transfer system of the present apparatus is determined by the preheating chamber 15, the first film forming chamber 17, and the second film forming chamber. It is set based on the maximum value among the processing times of the chamber 19 and the third film forming chamber 21.
【００１８】前記第２搬送機１３による前記ロード側基
板予備室１１から前記予備加熱室１５への基板投入間隔
は、前記設定したタクトタイムの間隔で行い、更に前記
予備加熱室１５、第１成膜室１７、第２成膜室１９、第
３成膜室２１の搬送時間を含む基板処理サイクルをそれ
ぞれ前記タクトタイムとする。The interval between the loading of the substrate from the substrate prechamber 11 on the loading side to the preheating chamber 15 by the second transfer device 13 is performed at the interval of the set tact time. The substrate processing cycle including the transport time in the film chamber 17, the second film forming chamber 19, and the third film forming chamber 21 is defined as the tact time.
【００１９】更に、図２、図３により基板処理の流れに
ついて説明する。尚、図４は図３及び以下に示されるタ
イムチャートに於ける記号の意味を示す。Further, the flow of substrate processing will be described with reference to FIGS. FIG. 4 shows the meaning of the symbols in FIG. 3 and the time chart shown below.
【００２０】１枚の基板の処理の流れは、ロード側カセ
ットスタンド８から前記ロード側基板予備室１１への基
板搬入タスク３０、予備加熱室１５の処理タスク３１、
第１成膜室１７の処理タスク３２、第２成膜室１９の処
理タスク３３、第３成膜室２１の処理タスク３４、アン
ロード側基板予備室２６からの搬出処理タスク３５と進
行し、前記予備加熱室１５の処理タスク３１ではロード
側基板予備室１１から前記予備加熱室１５への基板搬送
３１ａと成膜処理を行うに必要な余熱３１ｂが行われ、
又、前記第１成膜室１７の処理タスク３２では前記予備
加熱室１５から第１成膜室１７への基板搬送３２ａと前
記第１成膜室１７での成膜処理３２ｂが行われ、前記第
２成膜室１９の処理タスク３３では前記第１成膜室１７
から前記第２成膜室１９への基板搬送３３ａと前記第２
成膜室１９での成膜処理３３ｂが行われ、前記第３成膜
室２１の処理タスク３４では前記第２成膜室１９から前
記第３成膜室２１への基板搬送３４ａと前記第３成膜室
２１での成膜処理３４ｂ、更に該第３成膜室２１から前
記アンロード側基板予備室２６への基板搬送３４ｃが行
われ、前記アンロード側基板予備室２６からの搬出処理
タスク３５では前記アンロード側基板予備室２６から前
記アンロード側カセットスタンド２９への基板搬送が行
われる。The processing flow of one substrate includes a task 30 for loading a substrate from the cassette stand 8 on the loading side to the substrate holding chamber 11 on the loading side, a processing task 31 for the preheating chamber 15,
A processing task 32 of the first film forming chamber 17, a processing task 33 of the second film forming chamber 19, a processing task 34 of the third film forming chamber 21, and a carrying out processing task 35 from the unloading-side substrate preliminary chamber 26. In the processing task 31 of the preliminary heating chamber 15, a substrate transfer 31a from the load-side substrate preliminary chamber 11 to the preliminary heating chamber 15 and residual heat 31b necessary for performing a film forming process are performed.
In the processing task 32 of the first film forming chamber 17, a substrate transfer 32a from the preheating chamber 15 to the first film forming chamber 17 and a film forming process 32b in the first film forming chamber 17 are performed. In the processing task 33 of the second film forming chamber 19,
From the substrate transfer 33a to the second film forming chamber 19 and the second
A film forming process 33b is performed in the film forming chamber 19, and in a processing task 34 of the third film forming chamber 21, the substrate transfer 34a from the second film forming chamber 19 to the third film forming chamber 21 and the third A film forming process 34b in the film forming chamber 21 and a substrate transfer 34c from the third film forming chamber 21 to the unloading-side substrate preliminary chamber 26 are performed, and a carry-out processing task from the unloading-side substrate preliminary chamber 26 is performed. At 35, the substrate is transferred from the unloading-side substrate preliminary chamber 26 to the unloading-side cassette stand 29.
【００２１】而して、各タスクは複数の基板に対して同
時に並列的に実行される。Thus, each task is simultaneously executed in parallel on a plurality of substrates.
【００２２】タクトタイム制御タスク３６は、前記処理
タスク３１、処理タスク３２、処理タスク３３、処理タ
スク３４それぞれが、それぞれの基準処理時間で完了す
るかどうかを監視し、前記処理タスク３１、処理タスク
３２、処理タスク３３、処理タスク３４がそれぞれの基
準処理時間で完了された場合は、更に次の基板を処理す
べく前記予備加熱室１５への基板投入を指示する。これ
は正常時の基板処理の流れである。The tact time control task 36 monitors whether or not each of the processing tasks 31, 32, 33, and 34 is completed in the respective reference processing time. When the processing tasks 32, 33, and 34 are completed within the respective reference processing times, an instruction is given to put the substrates into the preheating chamber 15 to process the next substrate. This is a flow of the substrate processing in a normal state.
【００２３】而して、或る処理室で搬送系、排気系等の
トラブルが発生したと判断した場合、或いは前記タスク
の内いずれかがそれぞれの基準時間内に完了しなかった
場合、前記タクトタイム制御タスク３６の指示により、
前記タクトタイムのカウントダウンは一時中止され、障
害発生箇所より下流側は正常処理が続行され、上流側は
障害回復待ちとなり、処理室内に止まる。[0023] In Thus, if the transfer system in one processing chamber, trouble of the exhaust system or the like is determined to have occurred, or the task
Is not completed within the respective reference time, the instruction of the tact time control task 36,
The countdown of the takt time is temporarily stopped, normal processing is continued on the downstream side from the failure occurrence point, and the upstream side waits for failure recovery, and stops in the processing chamber.
【００２４】又、障害が他の処理室の基板に影響なく回
復した場合、即ちタクトタイム内に回復した場合、下流
側は勿論、上流側についても、基板の正常処理が続行さ
れる。When the fault is recovered without affecting the substrates in the other processing chambers, that is, when the fault is recovered within the tact time, normal processing of the substrates is continued not only on the downstream side but also on the upstream side.
【００２５】以下、図５〜図１２に於いて具体的に説明
する。Hereinafter, a specific description will be given with reference to FIGS.
【００２６】先ず、図５〜図８は、前記予備加熱室１
５、第１成膜室１７、第２成膜室１９、第３成膜室２１
でそれぞれプロセスタイムが異なる場合に、半導体製造
装置としてのタクトタイムの選択、又処理の流れを示し
ている。First, FIG. 5 to FIG.
5, first film forming chamber 17, second film forming chamber 19, third film forming chamber 21
2 shows the selection of the tact time as a semiconductor manufacturing apparatus and the flow of processing when the process times are different.
【００２７】図５は、予備加熱室１５のプロセスタイム
が最大である場合を示しており、この場合ロード側基板
予備室１１から予備加熱室１５への基板搬送時間と、予
備加熱室１５のプロセスタイムと、予備加熱室１５から
第１成膜室１７への基板搬送時間とを加えたものがタク
トタイムとなる。FIG. 5 shows a case where the process time of the preheating chamber 15 is the maximum. In this case, the substrate transfer time from the load-side substrate prechamber 11 to the preheating chamber 15 and the process time of the preheating chamber 15 are shown. The tact time is obtained by adding the time and the substrate transfer time from the preheating chamber 15 to the first film forming chamber 17.
【００２８】又、図中、、、、…は処理される
基板が何番目であるかを示すものである。而して、１枚
の基板が処理される為に必要なトータルの処理時間は図
中Ｔで示され、又各処理室でのプロセスタイムが相違す
ることから、第１成膜室１７に関してはｔ1 、第２成膜
室１９に関してはｔ2 、第３成膜室２１に関してはｔ3
のそれぞれ休止時間が生ずる。In the drawing,... Indicate the order of the substrate to be processed. Thus, the total processing time required to process one substrate is indicated by T in the figure, and the process time in each processing chamber is different. t1, t2 for the second film forming chamber 19, and t3 for the third film forming chamber 21.
Each of the downtime occurs.
【００２９】図６は第１成膜室１７のプロセスタイムが
最大である場合を示し、この場合半導体製造装置として
のタクトタイムは、この場合予備加熱室１５から第１成
膜室１７への基板搬送時間と、第１成膜室１７のプロセ
スタイムと、第１成膜室１７から第２成膜室１９への基
板搬送時間とを加えたものがタクトタイムとなる。FIG. 6 shows a case where the process time of the first film forming chamber 17 is the maximum. In this case, the tact time as the semiconductor manufacturing apparatus is such that the substrate from the preheating chamber 15 to the first film forming chamber 17 The tact time is the sum of the transfer time, the process time of the first film forming chamber 17, and the time of substrate transfer from the first film forming chamber 17 to the second film forming chamber 19.
【００３０】更に、この場合第１成膜室１７に関して
は、休止時間がなくなるが前記予備加熱室１５に関して
はｔh の休止時間が生じる。Further, in this case, the downtime of the first film forming chamber 17 is eliminated, but the downtime of the preheating chamber 15 is th.
【００３１】図７は第２成膜室１９のプロセスタイムが
最大である場合のタクトタイム及び他処理との関連を示
し、図８は第３成膜室２１のプロセスタイムが最大であ
る場合のタクトタイム及び他処理との関連を示してい
る。FIG. 7 shows the relationship between the tact time when the process time of the second film forming chamber 19 is the maximum and the other processing, and FIG. 8 shows the case where the process time of the third film forming chamber 21 is the maximum. It shows the relationship between tact time and other processing.
【００３２】而して、複数の膜生成を人手を介さないで
処理し得、高スループットの実現が可能となり、更に連
続搬送に伴い、タクトタイムを設定して処理を行うの
で、基板処理で重要な熱履歴を一定に保ち基板間の品質
のバラツキを防止することができる。Since a plurality of film formations can be processed without human intervention, a high throughput can be realized, and the processing is performed by setting the tact time with the continuous transfer. It is possible to maintain a constant heat history and prevent quality variations between substrates.
【００３３】次に、図９、図１０はタクトタイムが前記
第１成膜室１７のプロセスタイムを基に設定された場合
で、２枚目の基板が前記第２成膜室１９で処理中に異常
が発生した場合を示している。Next, FIGS. 9 and 10 show the case where the tact time is set based on the process time of the first film forming chamber 17 and the second substrate is being processed in the second film forming chamber 19. Shows a case where an abnormality has occurred.
【００３４】図９は、前記第２成膜室１９での異常によ
りタクトタイムが一時停止した場合に、異常の回復が３
枚目の前記第１成膜室１７からの基板搬送予定時刻より
早かった場合、３枚目以降の基板処理には影響なく、異
常がない場合と同様に処理が進行していく。FIG. 9 shows that when the tact time is temporarily stopped due to an abnormality in the second film forming chamber 19, the recovery from the abnormality is three times.
If it is earlier than the scheduled substrate transfer time from the first film deposition chamber 17 of the first sheet, the processing of the third and subsequent substrates is not affected, and the processing proceeds as in the case where there is no abnormality.
【００３５】図１０は、前記第２成膜室１９での異常に
よりタクトタイムが一時停止した場合に、異常の回復が
３枚目の前記第１成膜室１７からの基板搬送予定時刻を
越えた場合、３枚目の基板処理に影響する。FIG. 10 shows that when the tact time is temporarily stopped due to an abnormality in the second film forming chamber 19, the recovery of the abnormality exceeds the scheduled transfer time of the substrate from the first film forming chamber 17 for the third sheet. In this case, processing of the third substrate is affected.
【００３６】図１１は、基板が第１成膜室１７から第２
成膜室１９へ搬送される場合に、搬送系第３搬送機１８
に異常が発生した場合で、第３搬送機１８の異常が回復
した場合、２枚目の基板は不良基板となると共に３枚目
の基板も保温処理となって不良基板となる。FIG. 11 shows that the substrate is moved from the first film forming chamber 17 to the second film forming chamber 17.
When transported to the film forming chamber 19, the transport system third transporter 18
When the abnormality occurs in the third transfer device 18 and the abnormality is recovered, the second substrate becomes a defective substrate, and the third substrate is also subjected to a heat retention process and becomes a defective substrate.
【００３７】図１２は所要の位置、例えば第２成膜室１
９で異常が発生した場合で、異常が回復しなかった時に
は、予備加熱室１５、第１成膜室１７、第２成膜室１９
に装入されている基板は不良基板となる。図１２では予
備加熱室１５に４枚目の基板が装入されていない状態で
あるので、２枚目、３枚目の基板が不良となる。FIG. 12 shows a required position, for example, the second film forming chamber 1.
9, when the abnormality has not been recovered, the preheating chamber 15, the first film forming chamber 17, and the second film forming chamber 19
The substrate loaded in the device becomes a defective substrate. In FIG. 12, since the fourth substrate is not loaded in the preheating chamber 15, the second and third substrates are defective.
【００３８】而して、異常が発生した箇所より下流につ
いては、正常処理が続行され、異常が発生した箇所より
上流については、新たな基板投入は異常回復の状態に応
じてなされ、又異常回復後直ちに処理が続行されるの
で、不良基板の発生は最小限に押さえられると共に搬送
効率の低下を防止する。The normal processing is continued downstream of the location where the abnormality has occurred, and a new substrate is loaded upstream of the location where the abnormality has occurred in accordance with the state of the recovery. Since the processing is continued immediately afterward, the occurrence of defective substrates is minimized, and a decrease in transport efficiency is prevented.
【００３９】尚、上記実施例は成膜室が３組であった
が、２組でも、或いは４組以上であっても同様に実施可
能であることは言う迄もなく、成膜室等のユニットの配
列も上記実施例に限定されるものではないことも勿論で
ある。In the above embodiment, the number of the film forming chambers is three. However, it is needless to say that the number of the film forming chambers can be reduced to two or four or more. Needless to say, the arrangement of the units is not limited to the above embodiment.
【００４０】[0040]
【発明の効果】以上述べた如く本発明によれば、タクト
タイムを設定して各工程を設定したタクトタイムを基準
に行う様にすると共に各工程での処理が所定時間に完了
するかどうかを監視し、異常が発生した場合に、タクト
タイムを一時停止し、下流側基板に関しては正常処理、
上流側は異常回復待ちを行わせる等するので、各基板の
熱履歴を一定にすることができると共に装置の未稼働状
態を極力少なくし、稼働率の向上を図り、異常が発生し
た場合でも不良基板の発生を最小限に押さえることが可
能となる。As described above, according to the present invention, the tact time is set and each step is performed based on the set tact time, and it is determined whether the processing in each step is completed in a predetermined time. Monitors and suspends the tact time when an abnormality occurs, normal processing is performed for the downstream side board,
Since the upstream side waits for an abnormal recovery, etc., it is possible to keep the thermal history of each substrate constant, minimize the non-operational status of the device, improve the operation rate, and improve the failure even if an abnormality occurs. The generation of the substrate can be minimized.
【図１】本発明を実施する場合の半導体製造装置の一例
を示す配置図である。FIG. 1 is a layout view showing an example of a semiconductor manufacturing apparatus when implementing the present invention.
【図２】基板の処理系統を示すブロック図である。FIG. 2 is a block diagram illustrating a processing system of a substrate.
【図３】基本的な基板処理の流れを示すタイムチャート
である。FIG. 3 is a time chart showing a flow of basic substrate processing.
【図４】図３、図５〜図１２で示される記号の説明図で
ある。FIG. 4 is an explanatory diagram of symbols shown in FIGS. 3 and 5 to 12;
【図５】各処理工程に於けるプロセスタイムが異なる場
合の基板処理の流れとタクトタイム設定の一例を示すタ
イムチャートである。FIG. 5 is a time chart showing an example of a substrate processing flow and a tact time setting when the process time in each processing step is different.
【図６】各処理工程に於けるプロセスタイムが異なる場
合の基板処理の流れとタクトタイム設定の一例を示すタ
イムチャートである。FIG. 6 is a time chart showing an example of a substrate processing flow and a tact time setting when the process time in each processing step is different.
【図７】各処理工程に於けるプロセスタイムが異なる場
合の基板処理の流れとタクトタイム設定の一例を示すタ
イムチャートである。FIG. 7 is a time chart showing an example of a substrate processing flow and a tact time setting when the process time in each processing step is different.
【図８】各処理工程に於けるプロセスタイムが異なる場
合の基板処理の流れとタクトタイム設定の一例を示すタ
イムチャートである。FIG. 8 is a time chart showing an example of a flow of a substrate processing and a tact time setting when a process time in each processing step is different.
【図９】異常が発生した場合の基板処理の流れを示すタ
イムチャートである。FIG. 9 is a time chart showing a flow of substrate processing when an abnormality occurs.
【図１０】異常が発生した場合の基板処理の流れを示す
タイムチャートである。FIG. 10 is a time chart showing a flow of substrate processing when an abnormality occurs.
【図１１】異常が発生した場合の基板処理の流れを示す
タイムチャートである。FIG. 11 is a time chart showing a flow of substrate processing when an abnormality occurs.
【図１２】異常が発生した場合の基板処理の流れを示す
タイムチャートである。FIG. 12 is a time chart showing a flow of substrate processing when an abnormality occurs.
【図１３】従来の半導体製造装置の一例を示す説明図で
ある。FIG. 13 is an explanatory view showing an example of a conventional semiconductor manufacturing apparatus.
１５ 予備加熱室 １７ 第１成膜室 １９ 第２成膜室 ２１ 第３成膜室 15 Preheating chamber 17 First film forming chamber 19 Second film forming chamber 21 Third film forming chamber
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−113612（ＪＰ，Ａ) 特開 平２−267847（ＪＰ，Ａ) 特開 平４−127555（ＪＰ，Ａ) 特開 平５−108114（ＪＰ，Ａ) 特開 平６−20898（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/68 H01L 21/02 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-113612 (JP, A) JP-A-2-267847 (JP, A) JP-A-4-127555 (JP, A) JP-A-5-127555 108114 (JP, A) JP-A-6-20898 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/68 H01L 21/02
Claims (3)
に於いて、前記複数の処理工程の内、最も長いプロセス
タイムを基にタクトタイムを設定し、前記各処理工程に
対する基板投入間隔を前記タクトタイムとし、前記複数
の処理工程の内、いずれか１つに異常が発生した場合
に、異常が前記タクトタイム以内に回復しない場合は新
しい基板の投入を停止することを特徴とする半導体製造
装置に於ける基板処理方法。In a semiconductor manufacturing apparatus having a plurality of processing steps, a tact time is set based on a longest process time among the plurality of processing steps, and a substrate input interval for each of the processing steps is set to the tact time. Time and the plural
If an error occurs in any one of the processing steps
If the abnormality does not recover within the takt time,
A method of processing a substrate in a semiconductor manufacturing apparatus, comprising: stopping the loading of a new substrate.
監視し、それぞれの基準時間との比較で各処理工程に異
常が発生したかどうかを監視する請求項１の半導体製造
装置に於ける基板処理方法。2. A substrate in a semiconductor manufacturing apparatus according to claim 1, wherein each processing time of each of the plurality of processing steps is monitored, and whether or not an abnormality has occurred in each of the processing steps is monitored by comparing with each reference time. Processing method.
に於いて、前記複数の処理工程の内、最も長いプロセス
タイムを基にタクトタイムを設定し、前記各処理工程に
対する基板投入間隔を前記タクトタイムとし、前記複数
の処理工程の内、いずれか１つに異常が発生した場合
に、異常が前記タクトタイム以内に回復しない場合は新
しい基板の投入を停止する様にしたことを特徴とする半
導体製造装置。 3. A semiconductor manufacturing apparatus having a plurality of processing steps.
, The longest of the plurality of processing steps
Set the takt time based on the time, and
The substrate loading interval with respect to the
If an error occurs in any one of the processing steps
If the abnormality does not recover within the takt time,
Characterized in that the loading of a new substrate is stopped.
Conductor manufacturing equipment.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26551392A JP3174409B2 (en) | 1992-09-08 | 1992-09-08 | Semiconductor manufacturing apparatus and substrate processing method in semiconductor manufacturing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26551392A JP3174409B2 (en) | 1992-09-08 | 1992-09-08 | Semiconductor manufacturing apparatus and substrate processing method in semiconductor manufacturing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0689934A JPH0689934A (en) | 1994-03-29 |
| JP3174409B2 true JP3174409B2 (en) | 2001-06-11 |
Family
ID=17418206
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26551392A Expired - Fee Related JP3174409B2 (en) | 1992-09-08 | 1992-09-08 | Semiconductor manufacturing apparatus and substrate processing method in semiconductor manufacturing apparatus |
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| Country | Link |
|---|---|
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Cited By (1)
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| KR101336420B1 (en) * | 2010-07-13 | 2013-12-04 | 도쿄엘렉트론가부시키가이샤 | Vacuum processing apparatus |
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| JP4093462B2 (en) | 2002-10-09 | 2008-06-04 | 東京エレクトロン株式会社 | Substrate processing method and substrate processing apparatus |
| JP4566632B2 (en) * | 2004-07-01 | 2010-10-20 | 大日本スクリーン製造株式会社 | Calculation device, setting device, substrate processing device |
| JP4557986B2 (en) * | 2004-11-24 | 2010-10-06 | 株式会社日立国際電気 | Substrate processing apparatus and semiconductor device manufacturing method |
| JP5006122B2 (en) | 2007-06-29 | 2012-08-22 | 株式会社Ｓｏｋｕｄｏ | Substrate processing equipment |
| JP5128918B2 (en) | 2007-11-30 | 2013-01-23 | 株式会社Ｓｏｋｕｄｏ | Substrate processing equipment |
| JP5344734B2 (en) * | 2007-12-28 | 2013-11-20 | 株式会社Ｓｏｋｕｄｏ | Substrate processing equipment |
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| JP6241913B2 (en) * | 2013-04-25 | 2017-12-06 | 東レエンジニアリング株式会社 | Substrate heat treatment equipment |
| JP6213443B2 (en) * | 2014-10-29 | 2017-10-18 | Ｊｆｅスチール株式会社 | How to stop linked equipment when abnormal hot rolling |
| JP7149748B2 (en) * | 2018-07-04 | 2022-10-07 | 東京エレクトロン株式会社 | SUBSTRATE PROCESSING SYSTEM, SUBSTRATE TRANSFER METHOD, AND CONTROL PROGRAM |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101336420B1 (en) * | 2010-07-13 | 2013-12-04 | 도쿄엘렉트론가부시키가이샤 | Vacuum processing apparatus |
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| Publication number | Publication date |
|---|---|
| JPH0689934A (en) | 1994-03-29 |
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