JP3169726B2 - Arithmetic unit with load circuit - Google Patents
Arithmetic unit with load circuitInfo
- Publication number
- JP3169726B2 JP3169726B2 JP01680693A JP1680693A JP3169726B2 JP 3169726 B2 JP3169726 B2 JP 3169726B2 JP 01680693 A JP01680693 A JP 01680693A JP 1680693 A JP1680693 A JP 1680693A JP 3169726 B2 JP3169726 B2 JP 3169726B2
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- power supply
- capacitor
- load circuit
- arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Direct Current Feeding And Distribution (AREA)
- Safety Devices In Control Systems (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、比較的消費電流を要
する負荷回路を備えた、負荷回路付き演算装置に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit with a load circuit having a load circuit requiring a relatively large current consumption.
【０００２】[0002]
【従来の技術】図４は従来の負荷回路付き演算装置の構
成図である。また図５は従来の負荷回路付き演算装置の
信号図である。図４において、１は測定する流体を加熱
するヒータ（電気素子）、２はセンサ等を含む演算処理
装置、３は例えば電池等の内部抵抗を含む電源であり、
ヒータ１および演算処理装置２に接続される。２１はヒ
ータ１を駆動するヒータ駆動回路、２２はヒータ１によ
る熱分布が流体の速度によって変わることにより流量を
測定するセンサブリッジであり、上流側センサ２２１と
下流側センサ２２２が直列に接続され、またそれと並列
に基準用抵抗２つを直列に接続して構成されている。2. Description of the Related Art FIG. 4 is a block diagram of a conventional arithmetic unit with a load circuit. FIG. 5 is a signal diagram of a conventional arithmetic device with a load circuit. In FIG. 4, 1 is a heater (electric element) for heating a fluid to be measured, 2 is an arithmetic processing unit including a sensor and the like, 3 is a power supply including an internal resistance such as a battery, for example,
It is connected to the heater 1 and the processing unit 2. 21 is a heater drive circuit for driving the heater 1, 22 is a sensor bridge for measuring the flow rate by changing the heat distribution by the heater 1 according to the speed of the fluid, and an upstream sensor 221 and a downstream sensor 222 are connected in series. Also, two reference resistors are connected in series in parallel with the reference resistor.
【０００３】また２３はセンサブリッジ２２の各々の中
点の電位を増幅する差動増幅器、２４は差動増幅器２３
の出力する電位をＡ／Ｄ変換するＡ／Ｄ変換器、２５は
演算処理装置２内のヒータ駆動回路２１、センサブリッ
ジ２２等に安定した電圧を供給する定電圧回路、２６は
スタート信号（図５の７）と同期して供給されるクロッ
ク信号（図５の８）により動作する、ヒータ１をオンオ
フさせるタイミング、センサブリッジ２２をオンオフさ
せるタイミング、Ａ／Ｄ変換器２４をヒータオフ時とヒ
ータオン時の２回動作させるタイミング、ヒータオン時
のＡ／Ｄ変換終了時に定電圧回路２５をオフさせるタイ
ミング等の各種タイミングを生成するシーケンス回路、
２７はヒータ駆動回路２１のヒータ温度上昇、センサブ
リッジ２２のブリッジバランスを調整し、流量がないと
きのヒータオフ時とヒータオン時のＡ／Ｄ出力差を０に
し、差動増幅器２３のゲインをＤ／Ａ変換で調整し、Ｅ
ＥＰＲＯＭに調整データを保持し、スタート信号７の終
了時にＥＥＰＲＯＭからＤ／Ａ変換器にデータをリフレ
ッシュする調整回路である。[0003] 23 differential amplifier for amplifying the potential of each of the midpoint of the sensor bridge 22, 24 is a differential amplifier 23
A / D converter for A / D-converting the potential output from the A / D converter 25, a constant voltage circuit for supplying a stable voltage to the heater drive circuit 21, the sensor bridge 22, etc. in the arithmetic processing unit 2, and a start signal 26 5) The timing of turning on / off the heater 1, the timing of turning on / off the sensor bridge 22, and the timing of turning on / off the A / D converter 24 by the clock signal (8 in FIG. 5) supplied in synchronization with 7). A sequence circuit for generating various timings such as a timing for operating twice, a timing for turning off the constant voltage circuit 25 when A / D conversion is completed when the heater is turned on,
Reference numeral 27 denotes an adjustment of the heater temperature rise of the heater drive circuit 21 and the bridge balance of the sensor bridge 22, the A / D output difference between the heater off and the heater on when there is no flow rate is set to 0, and the gain of the differential amplifier 23 is set to D / D. Adjust by A conversion, E
The adjustment circuit holds adjustment data in the EPROM and refreshes the data from the EEPROM to the D / A converter when the start signal 7 ends.
【０００４】また図５において、９は演算処理装置２の
駆動電流、１０はヒータ１の駆動電流、１１は電源３が
供給する電源電圧、１２は演算処理装置２の最低動作電
圧、１３は定電圧回路２５が供給する定電圧回路電圧、
１４は無負荷時の電源電圧である。In FIG. 5, reference numeral 9 denotes a drive current of the arithmetic processing unit 2, 10 denotes a drive current of the heater 1, 11 denotes a power supply voltage supplied by the power supply 3, 12 denotes a minimum operating voltage of the arithmetic processing unit 2, and 13 denotes a constant. A constant voltage circuit voltage supplied by the voltage circuit 25,
Reference numeral 14 denotes a power supply voltage when no load is applied.
【０００５】次に動作について説明する。従来のマイク
ロダイヤフラム型流量計等の負荷回路付き演算装置にお
いては、ヒータ１をある一定時間毎に間欠駆動すること
により、ヒータ１の両脇に設けられた上流側センサ２２
１と下流側センサ２２２の抵抗値の違いにより、測定対
象流体の流量を測定する。マイクロダイヤフラム型流量
計はその特性上非常に小型のため発熱応答性が高いの
で、常時作動させておく必要がなく、間欠駆動でよい。
従って、ヒータ１の駆動時にはヒータ１の駆動電流１０
＋演算処理装置２の駆動電流９が必要であり比較的大き
な消費電力が必要であるが、その他の時は演算処理装置
２の駆動電流９のみでよい。Next, the operation will be described. In a conventional computing device with a load circuit such as a micro-diaphragm flow meter, the upstream sensor 22 provided on both sides of the heater 1 is driven by intermittently driving the heater 1 at a certain time interval.
The flow rate of the fluid to be measured is measured based on the difference between the resistance value of 1 and the resistance value of the downstream sensor 222. Since the micro-diaphragm flow meter is very small in its characteristics and has a high heat generation responsiveness, it is not necessary to keep the micro-diaphragm flow meter operating at all times.
Therefore, when the heater 1 is driven, the driving current 10
+ The drive current 9 of the processing unit 2 is required, and relatively large power consumption is required. At other times, only the drive current 9 of the processing unit 2 is sufficient.
【０００６】[0006]
【発明が解決しようとする課題】従来の負荷回路付き演
算装置は以上のように構成されているので、図４の回路
構成において、内部抵抗を含む電源３を接続した場合、
演算処理装置２の電流９およびセンサ１の電流１０が流
れ、この電流と内部抵抗の積の電圧分だけ電源電圧１１
が低下し、演算処理装置２の最低動作電圧１２を下回る
ことがままある。この場合は、定電圧回路２５は定電圧
化できなくなり、この定電圧回路を電源とする演算処理
装置の構成要素が正常に作動しなくなる。これを解決す
るには、演算処理装置２の最低動作電圧１２を下げた
り、電流を減少したり、内部抵抗の小さな電源を選んだ
りする必要があるが、技術的困難があり、自ずと限界が
ある。また別の方法としてコンデンサ４を電源３と並列
に接続する方法もあるが、電流値とその動作時間の積で
決まるコンデンサ４の容量値が大きくなり、そのもれ電
流も大きくなるという問題点があった。Since the conventional arithmetic unit with a load circuit is configured as described above, when the power supply 3 including the internal resistance is connected in the circuit configuration of FIG.
The current 9 of the arithmetic processing unit 2 and the current 10 of the sensor 1 flow, and the power supply voltage 11 corresponds to the product of this current and the internal resistance.
Is lower than the minimum operating voltage 12 of the arithmetic processing unit 2. In this case, the constant voltage circuit 25
Operation using this constant voltage circuit as a power supply
The components of the device do not work properly. To solve this, it is necessary to lower the minimum operating voltage 12 of the arithmetic processing unit 2, reduce the current, or select a power supply with a small internal resistance, but there are technical difficulties, and there is a limit naturally. . As another method, there is a method of connecting the capacitor 4 in parallel with the power supply 3. However, there is a problem that the capacitance value of the capacitor 4 determined by the product of the current value and the operation time becomes large, and the leakage current also becomes large. there were.
【０００７】また、電池などの内部抵抗が大きく、低温
などで電源電圧が低くなり、内部抵抗も変化する温度特
性を持つ電源３では、演算処理装置２の最低動作電圧１
２だけ考慮しただけでは不具合が生じ、電流と内部抵抗
の積の電圧降下も加味して設計しなければならず、必然
的に演算処理装置２の最低動作電圧１２をさらに低く設
計しなければならないという問題点もあった。Further, in the power supply 3 having a temperature characteristic in which the internal resistance of a battery or the like is large and the power supply voltage is low at a low temperature and the internal resistance is changed, the minimum operating voltage 1
Considering only 2 causes a problem, and the design must be made taking into account the voltage drop of the product of the current and the internal resistance. Inevitably, the minimum operating voltage 12 of the arithmetic processing unit 2 must be further reduced. There was also a problem.
【０００８】この発明は上記のような問題点を解消する
ためになされたもので、電源３の内部抵抗をあまり意識
せずとも、無負荷時の電源電圧１４を考慮すれば、演算
処理装置２の最低動作電圧１２を高く設計できる負荷回
路付き演算装置を得ることを目的とする。The present invention has been made in order to solve the above-mentioned problem. Even if the internal resistance of the power supply 3 is not so much taken into consideration, the power supply voltage 14 at the time of no load is taken into consideration, and the arithmetic processing unit 2 is provided. It is an object of the present invention to obtain an arithmetic unit with a load circuit that can design the minimum operating voltage 12 higher.
【０００９】[0009]
【課題を解決するための手段】この発明に係る負荷回路
付き演算装置は、第１の開閉スイッチを介して電源に接
続された比較的消費電流を要する電気素子と、第２の開
閉スイッチを介して上記電源に接続されたコンデンサ
と、このコンデンサと並列に接続された各種信号処理を
行なう演算処理装置と、上記第２のスイッチが開路され
た時、上記コンデンサの充電電荷を入力し電源として上
記演算処理装置を作動させる定電圧回路とを備え、上記
第２のスイッチの開路から所定時間後に所定時間のみの
上記演算処理装置から出力信号で上記第１の電気素子を
導通させるものである。An arithmetic unit with a load circuit according to the present invention is connected to a power supply via a first open / close switch.
Electrical elements that require relatively high current consumption and a second
Capacitor connected to the power supply via a close switch
And the various signal processing connected in parallel with this capacitor
An arithmetic processing unit for performing the operation and the second switch being opened
Input the charge of the above capacitor and
A constant voltage circuit for operating the arithmetic processing unit.
Only a predetermined time after a predetermined time from the opening of the second switch.
The first electric element is output by the output signal from the arithmetic processing unit.
This is to make it conductive .
【００１０】[0010]
【作用】この発明における負荷回路付き演算装置は、各
種信号処理を行なう比較的消費電流が小さい演算処理装
置と、間欠的に動作する比較的消費電流が大きい電気素
子を分離させ、上記電気素子に間欠的に電流を流す際、
演算処理装置の電源としてコンデンサの充電電荷を電源
とするものである。The arithmetic unit with a load circuit according to the present invention separates an arithmetic processing unit for performing various signal processing with relatively small current consumption from an electric element which operates intermittently and has relatively large current consumption. When passing current intermittently,
Power supply of capacitor charge as power supply for arithmetic processing unit
It is assumed that .
【００１１】[0011]
実施例１．以下、この発明の一実施例を図について説明
する。図１は請求項１の発明による負荷回路付き演算装
置の一実施例を示す構成図、図２は信号図である。図に
おいて、６１はスタート信号７を反転させるインバー
タ、６はインバータ６１の出力によりコントロールされ
るスイッチとしてのＰＭＯＳトランジスタ、５は演算処
理装置２と並列に接続されるコンデンサ、１５はＰＭＯ
Ｓトランジスタ６がオフのときの演算処理装置２の電圧
である。Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an arithmetic unit with a load circuit according to the present invention, and FIG. 2 is a signal diagram. In the figure, 61 is an inverter for inverting a start signal 7, 6 is a PMOS transistor as a switch controlled by the output of the inverter 61, 5 is a capacitor connected in parallel with the arithmetic processing unit 2, and 15 is a PMO.
This is the voltage of the arithmetic processing unit 2 when the S transistor 6 is off.
【００１２】次に動作について説明する。スタート信号
７が’Ｈ’期間中はＰＭＯＳトランジスタ６がオンし、
このとき演算処理装置２は動作していないので無負荷時
の電源電圧１４でコンデンサ５は充電される。スタート
信号７が’Ｌ’期間中はＰＭＯＳトランジスタ６がオフ
し、この時演算処理装置２が動作し、コンデンサ５で保
持された電圧１５から演算処理装置２に漏れる電流によ
って決まる放電カーブで電圧１５が減少していくがコン
デンサ５の容量を十分に設計しておけば最低動作電圧１
２は確保され、ヒータ１がオンしたときの電源電圧１１
が下がっても定電圧回路２５の電圧１３に影響を及ぼす
ことなく、演算処理装置２の動作は保証される。Next, the operation will be described. While the start signal 7 is “H”, the PMOS transistor 6 is turned on,
At this time, since the arithmetic processing unit 2 is not operating, the capacitor 5 is charged with the power supply voltage 14 at the time of no load. While the start signal 7 is in the "L" period, the PMOS transistor 6 is turned off. At this time, the arithmetic processing device 2 operates, and the voltage 15 has a discharge curve determined by the current leaking from the voltage 15 held by the capacitor 5 to the arithmetic processing device 2. However, if the capacity of the capacitor 5 is sufficiently designed, the minimum operating voltage 1
2 is secured and the power supply voltage 11 when the heater 1 is turned on.
Does not affect the voltage 13 of the constant voltage circuit 25, the operation of the arithmetic processing unit 2 is guaranteed.
【００１３】実施例２．図３は請求項１の発明による負
荷回路付き演算装置の他の実施例を示す構成図である。
図において１７は遮断弁（電気素子）、１６は演算処理
装置２の信号により遮断弁１７を動作させるようなコン
トロール回路、１８はコントロール回路１６により出力
される遮断弁１７を制御する信号である。Embodiment 2 FIG. FIG. 3 is a block diagram showing another embodiment of the arithmetic unit with a load circuit according to the first aspect of the present invention.
In the figure, reference numeral 17 denotes a shutoff valve (electric element), 16 denotes a control circuit for operating the shutoff valve 17 based on a signal from the arithmetic processing unit 2, and 18 denotes a signal output from the control circuit 16 for controlling the shutoff valve 17.
【００１４】次に動作について説明する。遮断弁１７も
ヒータ１と同様に比較的大きな駆動電流を必要とするの
で、スタート信号７と遮断弁信号１８のＯＲをとってＰ
ＭＯＳトランジスタ６をオンオフさせれば、実施例１と
同様に小さな容量のコンデンサ５で演算処理装置２とコ
ントロール回路１６の動作電圧を確保できることがわか
る。しかも演算処理装置２とコントロール回路１６のＩ
／Ｆのレベルも同じところからとっているので整合も容
易である。Next, the operation will be described. Since the shut-off valve 17 also requires a relatively large drive current as in the case of the heater 1, the OR of the start signal 7 and the shut-off valve signal 18 results in P
It can be seen that if the MOS transistor 6 is turned on and off, the operating voltage of the arithmetic processing unit 2 and the control circuit 16 can be secured by the small-capacity capacitor 5 as in the first embodiment. Moreover, the I and I of the arithmetic processing unit 2 and the control circuit 16
Since the / F level is also taken from the same place, matching is easy.
【００１５】[0015]
【発明の効果】以上のように、請求項１の発明によれば
負荷回路付き演算装置を、各種信号処理を行なう比較的
消費電流が小さい演算処理装置と、間欠的に動作する比
較的消費電流が大きい電気素子に分離させ、上記電気素
子に間欠的に電流を流す際、演算処理装置の電源として
コンデンサの充電電荷を電源とするように構成したの
で、演算処理装置の動作電流と動作時間に見合うコンデ
ンサ容量を決定すれば、電源の内部抵抗の影響により電
源電圧が演算処理装置の最低動作電圧より低くなって
も、演算処理装置の最低動作電圧は確保され、その分演
算処理装置の動作の余裕度が上がりコンデンサの容量を
小さくでき小型化が計れ、またコンデンサ容量が小さい
と漏れ電流も小さいため、電池などを電源とする場合に
は電池寿命を長く設計できる負荷回路付き演算装置が得
られる。この場合、コンデンサの充電電荷を入力とする
定電圧回路は常に安定した定電圧を出力し、この定電圧
回路を電源とする演算処理装置を正常に作動させること
ができるという効果がある。As described above, according to the first aspect of the present invention, an arithmetic unit with a load circuit can be used to perform various signal processing.
An arithmetic processing unit with low current consumption and a ratio of intermittent operation
Separation into electrical elements with relatively large current consumption
When a current is intermittently applied to the
Since the charge of the capacitor is used as the power supply, if the capacitor capacity that matches the operating current and operating time of the processing unit is determined, the power supply voltage will be lower than the minimum operating voltage of the processing unit due to the internal resistance of the power supply. Even if it becomes lower, the minimum operating voltage of the processing unit is ensured, the operating margin of the processing unit is increased accordingly, the capacity of the capacitor can be reduced and the size can be reduced, and if the capacitor capacity is small, the leakage current is small. When a battery or the like is used as a power source, an arithmetic unit with a load circuit that can design a long battery life can be obtained . In this case, input the charge of the capacitor
The constant voltage circuit always outputs a stable constant voltage.
Normal operation of the processing unit powered by the circuit
There is an effect that can be .
【図１】この発明による負荷回路付き演算装置の一実施
例を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of an arithmetic unit with a load circuit according to the present invention.
【図２】この発明による負荷回路付き演算装置の一実施
例の信号図である。FIG. 2 is a signal diagram of one embodiment of an arithmetic unit with a load circuit according to the present invention.
【図３】この発明による負荷回路付き演算装置の他の実
施例を示す構成図である。FIG. 3 is a configuration diagram showing another embodiment of an arithmetic unit with a load circuit according to the present invention.
【図４】従来の負荷回路付き演算装置の構成図である。FIG. 4 is a configuration diagram of a conventional arithmetic device with a load circuit.
【図５】従来の負荷回路付き演算装置の信号図である。FIG. 5 is a signal diagram of a conventional arithmetic device with a load circuit.
１ ヒータ（電気素子） ２ 演算処理装置 ３ 電源 ５ コンデンサ ６ ＰＭＯＳトランジスタ Reference Signs List 1 heater (electric element) 2 arithmetic processing unit 3 power supply 5 capacitor 6 PMOS transistor
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H02J 1/00 G05B 9/02 G06F 1/26 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H02J 1/00 G05B 9/02 G06F 1/26
Claims (1)
された比較的消費電流を要する電気素子と、第２の開閉
スイッチを介して上記電源に接続されたコンデンサと、
このコンデンサと並列に接続された各種信号処理を行な
う演算処理装置と、上記第２のスイッチが開路された
時、上記コンデンサの充電電荷を入力し電源として上記
演算処理装置を作動させる定電圧回路とを備え、上記第
２のスイッチの開路から所定時間後に所定時間のみ上記
演算処理装置からの出力信号で上記第１の電気素子を導
通させることを特徴とする負荷回路付き演算装置。 1. A power supply connected via a first open / close switch.
Electrical element that requires relatively high current consumption and a second opening and closing
A capacitor connected to the power supply through a switch,
Performs various signal processing connected in parallel with this capacitor.
And the second switch is opened.
When the charge of the capacitor is input,
A constant voltage circuit for operating the arithmetic processing unit.
After a predetermined time from the opening of the switch No. 2, only for a predetermined time
An output signal from the processing unit guides the first electric element.
An arithmetic unit with a load circuit, characterized by passing through .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01680693A JP3169726B2 (en) | 1993-01-08 | 1993-01-08 | Arithmetic unit with load circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01680693A JP3169726B2 (en) | 1993-01-08 | 1993-01-08 | Arithmetic unit with load circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06209522A JPH06209522A (en) | 1994-07-26 |
| JP3169726B2 true JP3169726B2 (en) | 2001-05-28 |
Family
ID=11926399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01680693A Expired - Lifetime JP3169726B2 (en) | 1993-01-08 | 1993-01-08 | Arithmetic unit with load circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3169726B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100391752C (en) * | 2003-03-03 | 2008-06-04 | 米其林技术公司 | Tire with a reinforced sidewall and fabrication process |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4778258B2 (en) * | 2005-04-15 | 2011-09-21 | コニカミノルタビジネステクノロジーズ株式会社 | Power supply circuit device |
-
1993
- 1993-01-08 JP JP01680693A patent/JP3169726B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100391752C (en) * | 2003-03-03 | 2008-06-04 | 米其林技术公司 | Tire with a reinforced sidewall and fabrication process |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06209522A (en) | 1994-07-26 |
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